KR20140044445A - Method for fabricating a semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device comprising a step for etching the central part of active areas and forming a bit line contact area which is positioned less than the flat upper surface of a substrate; a step for forming a bit line structure on the bit line contact area; a step for forming a column silicon oxide film pattern which is touched to the upper surface of the edge part of the active area and the upper surface of a device separation film pattern; a step for filling both sides of the column silicon oxide film pattern and forming an interlayer insulating film by using an insulating material having the silicon oxide film pattern and an etching selective ratio; a step for forming a preparative contact hole by selectively removing the silicon oxide film pattern; a step for forming a contact hole which exposes the upper surface and a side of the edge part of the both sides of the active area by removing the device separation film pattern of the preparative contact hole; and a step for forming contact by filling a conductive material inside the contact hole. The present invention is provided to manufacture the semiconductor device comprising the contact having low resistance by increasing a contact area.

Description

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE [0002]

The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a highly integrated DRAM device.

Recent semiconductor devices such as DRAM have been highly integrated. Due to this increase in the degree of integration, the contact area of the contact is reduced and the contact resistance is increasing. Due to such an increase in contact resistance, it is difficult for a semiconductor device to have excellent electrical characteristics desired by a user. Therefore, there is a need for a method of manufacturing a semiconductor device having high integration and excellent electrical characteristics.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a structure in which the contact contact area is increased.

In a method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object, an isolation pattern is formed in a substrate to form active regions having an isolated shape. The center portion of the active regions is etched to form a bit line contact region located below the flat top surface of the substrate. A bit line structure is formed on the bit line contact region. A pillar-shaped silicon oxide film pattern is formed to contact the upper surface of the edge of the active region and the upper surface of the device isolation layer pattern adjacent thereto. An interlayer insulating layer is formed using an insulating material having a shape surrounding the silicon oxide layer pattern while filling both side portions of the pillar-shaped silicon oxide layer pattern, and having an etching selectivity with the silicon oxide layer pattern. The silicon oxide pattern may be selectively removed to form a preliminary contact hole. The device isolation layer pattern under the preliminary contact hole is removed to form a contact hole exposing both side edge top surfaces and sidewalls of the active region together. In addition, a conductive material is filled in the contact hole to form a contact.

In an embodiment of the present invention, in order to form an isolation pattern in the substrate, an isolation trench is formed in the substrate. A silicon oxide layer is formed to fill the trench for device isolation between the active regions. The silicon oxide film is planarized to form a device isolation pattern including silicon oxide.

In an embodiment of the present disclosure, a process of forming an etch stop layer including silicon nitride on the surface of the substrate on which the device isolation layer pattern is formed may be further performed.

In order to form the preliminary contact hole, the insulating layer pattern may be removed to expose the etch stop layer. In addition, the etch stop layer may be removed through a dry etching process.

In one embodiment of the present invention, the interlayer insulating film may include silicon nitride.

In an embodiment of the present disclosure, the process of removing the insulating layer pattern may include a wet etching process.

In an embodiment of the present disclosure, the process of removing the device isolation layer pattern under the preliminary contact hole may include an isotropic etching process.

In example embodiments, the device isolation layer pattern on the bottom surface of the preliminary contact hole may be removed such that the contact hole lower surface is located at least 100 kHz higher than the upper surface of the substrate of the bit line region.

In an embodiment of the present disclosure, a process of forming a buried gate structure having a line shape extending perpendicular to the bit line structure may be performed in the substrate and the device isolation pattern of the active region.

The pillar-shaped silicon oxide layer pattern may be formed on an upper surface of the active region and the device isolation layer pattern positioned between the bit line structure and the buried gate structure.

As described, according to the method of manufacturing a semiconductor device according to the present invention, a contact hole exposing both side edge top surfaces and sidewalls of an active region together is formed, and a contact is formed inside the contact hole. Therefore, the contact area of the contact is increased to reduce the resistance of the contact. Therefore, a semiconductor device having high performance can be manufactured.

1A to 1N are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
2A to 2G are process plan views corresponding to the respective step cross-sectional views.
3 is a block diagram illustrating a schematic configuration of a computing system in accordance with example embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the drawings of the present invention, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the following description. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

1A to 1N are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 2A to 2G are process plan views corresponding to the respective step cross-sectional views.

The process cross-sectional views in FIGS. 1A to 1N are cut out portions II ′, II-II ′, and III-III ′ of FIG. 2A, respectively. In the following description, the length direction in which the active regions extend is referred to as a first direction, the direction in which the buried gate structure extends as a second direction, and the direction perpendicular to the second direction is described as a third direction.

Referring to FIGS. 1A and 2A, a first mask pattern (not shown) for forming a device isolation trench 108 is formed in a substrate 100 including single crystal silicon. The first mask pattern may include silicon nitride.

Using the first mask pattern as an etching mask, the substrate 100 is anisotropically etched to form a trench 108 for device isolation. The substrate 100 in a portion where the device isolation trench 108 is not formed may have a relatively protruding shape. Therefore, the flat surface of the substrate 100 of the protruding portion is provided to the active region 100a.

As shown, the active region 100a may have an isolated island shape in which the first direction is the longitudinal direction. In addition, each of the active regions 100a may be arranged in a line in the first direction. The first direction may be a direction that is not perpendicular to a second direction that is an extension direction of the buried gate structure. That is, the first direction may be a diagonal direction with respect to the extension direction of the buried gate structure.

In each of the process cross-sectional views, a cross-sectional view of the I_I 'region (hereinafter referred to as a first process cross-sectional view) is cut in the second direction such that the bit line contact and the storage node contact region respectively appear in the active region 100a. A cross-sectional view of the II_II 'portion (hereinafter referred to as a second process cross-sectional view) is cut in the second direction so that a portion where the buried gate structure is formed in the active region 100a appears.

A silicon oxide film is formed to fill the inside of the device isolation trench 108. As shown in the cross-sectional view of the first process, the device isolation trench 108 may be filled with only a silicon oxide layer, and silicon nitride or another kind of insulating layer may not be formed. In particular, in the cell region of the substrate, only the silicon oxide layer may be filled in the device isolation trench positioned between the active regions 100a having a tight spacing.

Thereafter, the silicon oxide film is planarized to form the device isolation layer pattern 110. When the planarization process is performed, most of the first mask patterns may be removed from the active area substrate 100 to have a flat surface.

As described above, in the present embodiment, the inside of the device isolation trench is filled only with silicon oxide, and an insulating material other than silicon oxide is not formed. That is, no nitride film liner is formed on the sidewalls of the device isolation trench. The silicon oxide may include an oxide film such as a high density plasma oxide film (HDP oxide) and a spin-on insulating film (SOD).

Although not shown, the substrate 100 is doped with impurities to form an impurity region below the surface of the substrate. The impurity region may be provided to the source and drain regions of the buried transistor.

1B and 2B, a mask pattern (not shown) for forming a gate trench 112 is formed on the substrate 100. The mask pattern may have a line shape extending in the second direction.

The mask pattern selectively exposes a portion where the gate trench 112 is to be formed. Therefore, the mask pattern exposes a portion of the active region 100a and a portion of the device isolation layer pattern 110.

Using the mask pattern as an etching mask, the gate trench 112 is formed by etching the exposed substrate 100 and the device isolation layer pattern 110 of the active region 100a. When the etching process is performed, the gate trenches 112 having the same depth are not formed in each region because the etching ratio between the substrate 100 and the device isolation layer pattern 110 is different from each other. That is, since the device isolation layer pattern 110 is etched relatively faster, the region where the device isolation layer pattern 110 is located below may have a deeper depth of the gate trench 112.

As illustrated in FIG. 2B, two gate trenches 112 may be disposed in parallel with each other in the one isolated active region 100a while being spaced apart from each other. In addition, one trench may be disposed spaced apart from both edge portions of the isolated active region 100a.

A gate insulating layer 116 is formed along sidewalls and bottom surfaces of the gate trench 112. The gate insulating layer 116 may be formed through a thermal oxidation process or a chemical vapor deposition process. A conductive film is formed on the gate insulating layer 116 to fill the gate trench 112. The conductive film may be formed by sequentially depositing a barrier metal film and a metal film. Examples of materials that can be used as the barrier metal film include titanium and titanium nitride. In addition, examples of the material that may be used as the metal film may include tungsten. The conductive layer is planarized through a chemical mechanical polishing process, and then an etch back process is performed to form a buried gate electrode 118 that fills a portion of the gate trench 112.

An insulating layer is formed on the buried gate electrode 118 while filling the inside of the gate trench 112. Thereafter, the insulating film is planarized to form an insulating film pattern 120. The insulating layer pattern 120 may include a silicon nitride layer.

By performing the above process, a buried gate structure 122 having a line shape extending in the second direction is formed in the substrate and the device isolation pattern of the active region. The buried gate structure 122 may include a gate insulating layer 116, a buried gate electrode 118, and an insulating layer pattern 120.

Referring to FIG. 1C, a pad oxide layer 124 and a first etch stop layer 126 are sequentially formed on the surface of the substrate 100. The pad oxide layer 124 may include silicon oxide. The first etch stop layer 126 may include an insulating material having silicon oxide and an etch selectivity. For example, the first etch stop layer 126 may be formed of silicon nitride.

A first conductive layer 128 is formed on the first etch stop layer 126. The first conductive layer 128 may include a polysilicon layer.

A first hard mask layer 130 that is used as a mask for forming bit line contact holes is formed on the first conductive layer 128. The first hard mask layer 130 may be formed using silicon oxide.

An etching mask 132 for forming a bit line contact hole is formed on the first hard mask layer 130. The hole portion exposed in the etching mask may be formed larger than the size of the bit line contact hole to be finally formed. The etching mask 132 may include a photoresist pattern.

1D and 2C, the first hard mask layer 130, the first conductive layer 128, the device isolation layer pattern 110, and the substrate 100 in the active region are formed by using the etching mask 132. The bit is anisotropically etched to form the bit line contact hole 134. In the etching process, an exposed surface of the insulating layer pattern 120 included in the buried gate structure 122 may be partially etched.

A portion of the substrate 100 of the active region exposed to the bottom portion of the bit line contact hole 134 is provided to the bit line contact region A. FIG. The bit line contact region A should be positioned lower than the flat top surface of the active region 100a between the bit line contact regions A. FIG. As such, the bottom surface of the bit line contact hole 134 and the top surface of the flat active area therebetween are located on different planes, thereby reducing bridge failure between the bit line contact and the storage node contact formed in a subsequent process. have.

When the bit line contact area A has a step d1 of 350 dB or less from the upper surface of the adjacent flat active area, a bridge failure between the bit line contact and the storage node contact may occur. Therefore, in the present embodiment, the bit line contact region A is preferably formed to be located at least 350 kHz or lower from the upper surface of the neighboring flat active region.

In addition, in the case where the design rule forms an ultrafine semiconductor device of 30 nm or less, when the bit line contact region A has a step of 1000 m or more from the upper surface of the adjacent flat active region, the bit line patterning is performed. It may not be easy. In addition, since the etch depth of the layers for forming the bit line contact hole 134 is deepened, the buried gate electrode 118 may be exposed, which is not preferable.

Therefore, when the design rule forms an ultrafine semiconductor device of 30 nm or less, the bit line contact region A has a step d1 of 350 to 1000 microseconds with an upper surface of an adjacent flat active region. .

After forming the bit line contact hole 134, the etch mask 132 and the hard mask pattern are removed.

Referring to FIG. 1E, a second conductive layer 136 is formed on the first conductive layer 128 while filling the bit line contact hole 134. For example, the first and second conductive layers 128 and 136 may be formed of the same material. That is, the second conductive layer 136 may include polysilicon.

Thereafter, the upper surface of the second conductive film 136 is planarized to form the first bit line conductive film 140. The first bit line conductive layer 140 may include a first portion having a shape in contact with the bit line contact region A and a second portion disposed on an upper surface of the etch stop layer.

A second bit line conductive film 142 is formed on the first bit line conductive film 140. The second bit line conductive layer 142 may include a conductive material having a lower resistance than the first bit line conductive layer 140. The second bit line conductive film may include a barrier metal film and a metal film. Examples of the material that can be used as the barrier metal film include titanium, titanium nitride, and the like. These may be formed alone or in a stack. In addition, examples of the material that may be used as the metal film may include tungsten.

A second hard mask layer 144 to be used as an etching mask is formed on the second bit line conductive layer 142. The second hard mask layer 144 may include silicon nitride.

1F and 2D, the second hard mask layer 144 is patterned to form a hard mask pattern 144a. The hard mask pattern 144a has a shape extending in the third direction. The hard mask pattern 144a has a shape covering the bit line contact regions A positioned at the center of each of the active regions. The line width of the portion masked by the hard mask pattern 144a may be smaller than the diameter of the bit line contact hole 134.

The first and second bit lines conductive layers 140 and 142 are anisotropically etched using the hard mask pattern 144a as an etching mask. Through the anisotropic etching process, a bit line structure 146 having a structure in which the bit line contacts 136a, the bit lines 136b and 142a, and the hard mask pattern 144a are stacked is formed.

As described above, since the line width of the portion masked by the hard mask pattern 144a is smaller than the diameter of the bit line contact hole 134, the second conductive layer formed inside the bit line contact hole 134. 136 may be partially removed.

Although not shown, in the etching process, an area of the bit line contact 136a below the bit line structure 134 may have a lower etch rate than other areas. Therefore, the bit line contact 136a portion of the bit line structure 146 may have a relatively wide width.

Insulating spacers 148 are formed on both sidewalls of the bit line structure 146. The insulating spacer 148 may have a structure in which silicon oxide and silicon nitride are stacked. Alternatively, the insulating spacer 148 may have a structure including an air spacer.

A second etch stop layer 150 is formed on surfaces of the insulating spacer 148, the first etch stop layer 126, and the device isolation layer pattern 110. The second etch stop layer 150 is formed of a material having a high etching selectivity with silicon oxide. The second etch stop layer 150 may include silicon nitride.

1G and 2E, a silicon oxide layer is formed to cover the bit line structure 146. Thereafter, the silicon oxide layer is planarized to expose the top surface of the second etch stop layer 150 to form a preliminary silicon oxide layer pattern 152. The planarization may comprise a chemical mechanical polishing or etch back process. The preliminary silicon oxide layer pattern 152 has a shape of filling a portion between the bit line structures.

When the structure after the process is performed in plan view, the preliminary silicon oxide layer pattern 152 and the second etch stop layer 150 extending in the second direction may be repeatedly arranged. That is, silicon oxide and silicon nitride having an etching selectivity are repeatedly arranged while having a line shape. Silicon nitride is positioned at a portion where the bit line structure 146 is formed.

1H and 2F, a photoresist pattern 154 is formed on the second etch stop layer 150 and the preliminary silicon oxide layer pattern 152. The gap region 156 between the photoresist patterns 154 may have a line shape that selectively exposes an upper portion of the buried gate structure 122. That is, the photoresist pattern 154 has a shape covering a portion between the buried gate structures 122.

The photoresist pattern 154 extends in the second direction, and the second etch stop layer 150 extends in the third direction. Therefore, a portion is isolated by the photoresist pattern 154 and the second etch stop layer 150. The preliminary silicon oxide layer pattern 152 is exposed to the isolated portion.

Referring to FIG. 1I, the preliminary silicon oxide layer pattern 152 of the portion isolated by the photoresist pattern 154 and the second etch stop layer 150 is selectively etched. When the above process is performed, only the masked preliminary silicon oxide layer pattern 152 remains, thereby forming the silicon oxide layer pattern 152a. Subsequently, the exposed first etch stop layer 126 and the pad oxide layer 124 are etched. The silicon oxide layer patterns 152a formed by the etching process may have a columnar shape. In addition, the silicon oxide pattern 152a is positioned on a position where a storage node contact hole is to be formed.

An interlayer insulating layer 160 is formed to sufficiently fill gaps between the silicon oxide layer patterns. The interlayer insulating layer 160 is formed of an insulating material having an etch selectivity with the silicon oxide layer pattern. The interlayer insulating layer 160 may be formed of silicon nitride.

In the present embodiment, the device isolation layer pattern 110 is formed of only silicon oxide. Therefore, the interlayer insulating layer 160 has an etching selectivity with the device isolation layer pattern 110 in the portion.

Thereafter, the interlayer insulating layer 160 is planarized so that the top surface of the silicon oxide layer pattern 152a is exposed. When the process is performed, the interlayer insulating layer 160 formed of the silicon nitrides has a shape completely surrounding the sidewall portion of the pillar-shaped silicon oxide layer pattern 152a.

Referring to FIG. 1J, the silicon oxide film pattern 152a is removed. The process of removing the silicon oxide layer pattern 152a may include a wet etching process. Since the silicon oxide pattern 152a is removed through the wet etching process, damage by plasma is reduced. Therefore, damage to the substrate 100 in the active region by the etching process can be reduced.

Thereafter, the first etch stop layer 126 and the pad oxide layer 124 are exposed to the portions where the silicon oxide layer pattern 152a is removed. The etching process includes a dry etching process. When the above processes are performed, a preliminary contact hole 162 is formed to expose an upper portion of the active region 100a of the storage node contact region and a portion of the device isolation layer pattern 110 adjacent thereto.

Only a very narrow top surface of the edge of the active region 100a is exposed on the bottom surface of the preliminary contact hole 162. This is because the area of the upper surface of the active region 100a exposed between the buried gate structure 122 and the bit line structure 134 is very narrow.

Meanwhile, as shown in FIG. 1K, when the bit line structure 146 is misaligned, the active region may not be exposed inside the preliminary contact hole 162.

1L and 2G, the device isolation layer pattern 110 exposed on the bottom surface of the preliminary contact hole 162 is removed through an isotropic etching process to form the storage node contact hole 164.

When the isotropic etching process is performed, a portion of the device isolation layer pattern 110 covering the sidewalls of the active region 100a is partially removed to expose sidewall portions of the edge portion of the active region 100a. That is, the storage node contact hole 164 exposes not only an upper surface of the active region 100a which becomes the storage node contact region, but also a sidewall of the active region 100a adjacent to the storage node contact region. Therefore, the area of the active region 100a exposed by the storage node contact hole 164 is increased.

The isotropic etching may include a wet etching process. By performing the isotropic etching process, damage to the substrate of the active region due to the etching process may be reduced.

When the bottom portion of the storage node contact hole 164 completed through the isotropic etching process is equal to or lower than the bottom portion of the bit line structure 146, the bit line structure is formed on the sidewall of the storage node contact hole 164. A defect in which 146 is exposed may occur. Therefore, the bottom of the storage node contact hole 164 should be located higher than the bottom of the bit line structure 146.

In order to reduce the bridge failure between the bit line structure 146 and the storage node contact, the bottom portion of the storage node contact hole 164 completed through the isotropic etching process is at least 100 Å over the bottom portion of the bit line structure 146. It is preferable to make it higher than this. That is, the height difference d2 between the bottom portions of the storage node contact holes 164 may be at least 100 μs. To this end, the thickness of the device isolation layer pattern 110 to be etched by the isotropic etching process should be controlled.

Meanwhile, since the interlayer insulating layer 160 is formed of silicon nitride, the interlayer insulating layer 160 is hardly etched during the wet etching process. That is, the sidewall portion of the preliminary contact hole 162 is hardly etched. In addition, only the bottom of the preliminary contact hole 162 may be etched to deepen only the depth of the storage node contact hole 164. Therefore, even when the wet etching process is performed, the inner width of the upper portion of the preliminary contact hole 162 is hardly extended. Therefore, a defect such as the storage node contact holes 164 contacting each other at the top is hardly generated.

Unlike the present exemplary embodiment, when the wet etching process is performed in the general structure in which the interlayer insulating layer 160 is formed of silicon oxide, the preliminary contact hole also extends to the upper side, thereby increasing the internal width of the storage node contact hole. do. Therefore, the spacing between the storage node contact holes is further reduced. In addition, in the case of highly integrated semiconductor devices in which the storage node contact holes are densely arranged, a problem may arise in that the storage node contact holes are connected to neighboring storage node contact holes as the internal width of the storage node contact holes increases. Thus, bridge failure of storage node contacts may occur.

Meanwhile, as shown in FIG. 1M, even when the active region is not exposed inside the preliminary contact hole 164, storage node contact holes are formed in which sidewall portions of the active region are exposed by the isotropic etching process. Can be. Therefore, even if the bit line structure is misaligned, the storage node contact holes may be normally formed without a sick open failure.

Referring to FIG. 1N, a conductive layer is formed in the storage node contact hole 164, and the storage layer is polished to form a storage node contact 166. The conductive film may include polysilicon.

The storage node contact 166 is in contact with the sidewall portion of the active region 100a as well as the upper surface of the edge of the active region 100a. Thus, the contact area of the storage node contact 166 may be increased. As the contact area of the storage node contact 166 increases, the resistance of the storage node contact 166 may decrease.

Although not shown, a capacitor 150 may be formed on an upper surface of the storage node contact 166. Alternatively, a contact pad may be further formed on the storage node contact 166, and then a capacitor may be formed in contact with the contact pad. The capacitor may be formed as a cylindrical capacitor or may be formed as a stacked capacitor.

By performing the above processes, the DRAM device is completed.

The semiconductor device according to the exemplary embodiments of the present invention described above may be mounted in various types of semiconductor packages. In addition, the semiconductor device or the semiconductor package including the same according to the exemplary embodiments may be applied to various types of systems such as a computing system.

3 is a block diagram illustrating a schematic configuration of a computing system in accordance with example embodiments.

Referring to FIG. 3, the computing system 300 may include a microprocessor (CPU) 420, a RAM 430, a user interface 440, and a baseband chipset electrically connected to a system bus. a modem (MODEM) 450 such as chipset) and a memory system 410. The memory system 410 may include a memory device 412 and a memory controller 411. The memory device 412 may include a semiconductor device or a DRAM device according to the above-described exemplary embodiments. The memory controller 411 is configured to control the memory device 412. By combining the memory device 412 and the memory controller 411, the memory system 410 may be provided as a memory card or a solid state disk (SSD). When the computing system 400 is a mobile device, a battery for supplying an operating voltage of the computing system 400 may be additionally provided. Although not shown, the computing system 400 according to the exemplary embodiments may further include an application chipset, a camera image processor (CIS), a mobile DRAM, and the like.

As described above, according to the present invention, a semiconductor element with reduced contact resistance is provided. The semiconductor device may be used in a memory device such as a DRAM device.

100: substrate 100a: active region
108: trench for device isolation 110: device isolation film pattern
112: trench for gate 122: buried gate structure
124: pad oxide film 126: first etch stop film
130: first hard mask film 132: etching mask
134: bit line contact hole 146: bit line structure
152a: silicon oxide film pattern 162: preliminary contact hole
164: storage node contact hole 166: storage node contact

Claims (10)

Forming an isolation pattern in the substrate to form active regions having an isolated shape;
Etching a central portion of the active regions to form a bit line contact region located below the flat top surface of the substrate;
Forming a bit line structure on the bit line contact region;
Forming a pillar-shaped silicon oxide film pattern in contact with the upper surface of the edge of the active region and the upper surface of the device isolation layer pattern adjacent thereto;
Forming an interlayer insulating film using an insulating material having a shape surrounding the silicon oxide film pattern while filling both side portions of the pillar-shaped silicon oxide film pattern and having an etching selectivity with the silicon oxide film pattern;
Selectively removing the silicon oxide layer pattern to form a preliminary contact hole;
Removing the device isolation layer pattern under the preliminary contact hole to form a contact hole exposing both side edge top surfaces and sidewalls of the active region together; And
And forming a contact by filling a conductive material in the contact hole. The method of claim 1, wherein the forming of the device isolation layer pattern in the substrate comprises:
Forming a device isolation trench in the substrate;
Forming a silicon oxide layer to fill an inside of the isolation trench between the active regions; And
Planarizing the silicon oxide layer to form a device isolation layer pattern including silicon oxide. The method of claim 1, further comprising forming an etch stop layer including silicon nitride on a surface of the substrate on which the device isolation layer pattern is formed. The method of claim 3, wherein the forming of the preliminary contact hole comprises:
Removing the insulating layer pattern to expose the etch stop layer; And
And removing the etch stop layer under the insulating layer pattern through a dry etching process. The method of claim 1, wherein the interlayer insulating layer comprises silicon nitride. The method of claim 1, wherein removing the insulating layer pattern comprises a wet etching process. The method of claim 1, wherein removing the device isolation layer pattern under the preliminary contact hole comprises an isotropic etching process. The method of claim 1, wherein the device isolation layer pattern on the bottom surface of the preliminary contact hole is removed so that the contact hole lower surface is located at least 100 kHz higher than the substrate upper surface of the bit line region. The method of claim 1, further comprising forming a buried gate structure having a line shape extending perpendicular to the bit line structure in the substrate and the device isolation pattern of the active region. 10. The method of claim 9, wherein the pillar-shaped silicon oxide pattern is the bit line structure
And forming an active region between the buried gate structure forming portions and an upper surface of the device isolation layer pattern.

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