US20150280122A1 - Resistive random access memory and method for fabricating the same - Google Patents

Resistive random access memory and method for fabricating the same Download PDF

Info

Publication number
US20150280122A1
US20150280122A1 US14/735,063 US201514735063A US2015280122A1 US 20150280122 A1 US20150280122 A1 US 20150280122A1 US 201514735063 A US201514735063 A US 201514735063A US 2015280122 A1 US2015280122 A1 US 2015280122A1
Authority
US
United States
Prior art keywords
layer
metal oxide
oxygen atom
oxide layer
oxygen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/735,063
Inventor
Heng-Yuan Lee
Pang-Shiu Chen
Tai-Yuan Wu
Ching-Chiun Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute ITRI
Original Assignee
Industrial Technology Research Institute ITRI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Industrial Technology Research Institute ITRI filed Critical Industrial Technology Research Institute ITRI
Priority to US14/735,063 priority Critical patent/US20150280122A1/en
Assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE reassignment INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, PANG-SHIU, LEE, HENG-YUAN, WANG, CHING-CHIUN, WU, TAI-YUAN
Publication of US20150280122A1 publication Critical patent/US20150280122A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H01L45/1641—
    • H01L45/08—
    • H01L45/1233—
    • H01L45/1253—
    • H01L45/146—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H10N70/046—Modification of switching materials after formation, e.g. doping by diffusion, e.g. photo-dissolution
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the invention relates to a memory element, and more particularly to a resistive random access memory element.
  • RRAM Resistive random access memory
  • the resistive random access memory 10 includes a Pt bottom electrode 14 , a dielectric layer 16 of nickel oxide, and a Pt top electrode 18 sequentially formed on a substrate 12 .
  • the structure of the conventional resistive random access memory 10 can be represented as below: Pt/NiO/Pt.
  • the conventional resistive random access memory 10 exhibits extremely unstable operating voltage (in particular SET voltage) after repeated and continuous conversion of resistance, resulting in loss of endurance.
  • U.S. Pat. Publication No. 20070215977 discloses a resistive random access memory 20 with two adjacent oxide layers, as shown in FIG. 2 .
  • the resistive random access memory 20 includes a lower electrode 22 , a first oxide layer 23 , a second oxide layer 24 doped with transition metals (serving as current control layer), and an upper electrode 25 sequentially formed on a substrate 21 .
  • the resistive random access memory 20 has lower on-current. Even so, the resistive random access memory 20 does not improve upon endurance.
  • An exemplary embodiment of a method for fabricating a resistive random access memory includes: forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.
  • Another exemplary embodiment of a method for fabricating a resistive random access memory includes: forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a top electrode on the oxygen atom gettering layer; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with a part of the oxygen atom gettering layer, resulting in that a plurality of oxygen vacancies within the metal oxide layer, wherein a part of the oxygen atom gettering layer which is not reacted with the migrated oxygen atoms of the metal oxide layer is defined as a first sub-layer, and the part of the oxygen atom gettering layer reacted with the migrated oxygen atoms of the metal oxide layer is defined as a second sub-layer
  • the disclosure also provides a resistive random access memory fabricated by the aforementioned method.
  • the resistive random access memory includes: a bottom electrode disposed on a substrate; a metal oxide layer with oxygen vacancies disposed on the bottom electrode and directly contacted to the bottom electrode; an oxygen atom gettering layer, oxidized by migrated oxygen atoms of the metal oxide layer, directly contacted to the metal oxide layer, wherein a material of the metal oxide layer is different from a material of the oxygen atom gettering layer; and a top electrode formed on the oxygen atom gettering layer.
  • FIG. 1 is a cross section of a conventional resistive random access memory.
  • FIG. 2 is a cross section of a conventional resistive random access memory with two adjacent oxide layers.
  • FIGS. 3 a to 3 e are cross sections of a method for fabricating a resistive random access memory according to an embodiment of the invention.
  • FIG. 4 is a cross section of a resistive random access memory having a top composite electrode according to another embodiment of the invention.
  • FIG. 5 is a cross section of a resistive random access memory with an oxygen atom gettering layer having a non-oxidized sub-layer according to still another embodiment of the invention.
  • FIG. 6 is a cross section of a resistive random access memory with gradient distribution according to yet another embodiment of the invention.
  • FIG. 7 is a graph plotting intensity of oxygen of each layer of the RRAM element A as disclosed in Example 1 before and after annealing.
  • FIG. 8 is a graph plotting current against voltage of the RRAM element A as disclosed in Example 1.
  • FIG. 9 is a graph plotting a resistance against read/write cycles of the RRAM element A as disclosed in Example 1.
  • the method for fabricating a resistive random access memory of the invention includes subjecting a metal oxide layer and an oxygen atom gettering layer (adjacent to the oxide layer) to a thermal treatment, and forcing the oxygen atoms of oxide layer to migrate into the oxygen atom gettering layer to leave oxygen vacancies within the oxide layer. Since the oxygen vacancies of the resistive random access memory can optionally capture or release electric charges, the resistive random access memory of the invention exhibits stable binary resistance switching characteristics.
  • the substrate 102 can be a substrate employed in a semiconductor process, such as silicon substrate.
  • the substrate 102 can be a substrate including a complementary metal oxide semiconductor (CMOS) circuit, isolation structure, diode, or capacitor.
  • CMOS complementary metal oxide semiconductor
  • the accompanying drawings show the substrate 100 in a plain rectangle in order to simplify the illustration.
  • the bottom electrode 104 can be electrically connected to a drain electrode of a transistor (not shown).
  • the bottom electrode 104 can further include an oxygen barrier layer formed thereon.
  • Suitable material for the bottom electrode 104 can be TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof, and thickness of the bottom electrode can be between 5-500 nm.
  • the metal oxide layer can consist of a binary oxide, such as binary metal oxide with oxides containing Al, Hf, Ti, Nb, Ta, La, or Zr. It should be noted that since the oxide layer must be formed directly on the bottom electrode and a subsequent oxygen atom gettering layer must be formed on the oxide layer, the binary oxide layer can achieve the expected characteristics of a resistive random access memory (RRAM). Therefore, a ternary oxide layer is not required to be used as the oxide layer of the invention, resulting in reduction of process complexity. The method for forming the metal oxide layer is unlimited.
  • the thickness of the metal oxide layer 106 can be between 1-100 nm.
  • an oxygen atom gettering layer 108 is formed on the metal oxide layer 106 and directly contacts to the metal oxide layer 106 .
  • the of the oxygen atom gettering layer can be between 1-50 nm.
  • the oxygen atom gettering layer can be metal, such as Mg, Al, Zn, Ti, Hf, La, Ta, Zr, Cu, laminations thereof, or combinations thereof (for example AlCu).
  • the oxygen atom gettering layer 108 includes partially oxidized metallic oxide or a mixture of metal and metallic oxide.
  • the oxygen atom gettering layer 108 can include partially oxidized metallic oxides containing Mg, Al, Zn, Ti, Hf, La, Ta, Zr, Cu, or combinations thereof.
  • the oxygen atom gettering layer can include TiO, TaO, or AlO. It should be noted that the oxygen atom gettering layer must include materials which have lower oxidation chemical formation energy than that of the metal oxide layer 106 . As a result, after a subsequent thermal treatment, the oxygen atoms of the metal oxide layer 106 would migrate into and react with the oxygen atom gettering layer 108 .
  • a top electrode 110 is formed on the oxygen atom gettering layer 108 .
  • the top electrode includes TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof.
  • FIG. 3 e wherein the structure shown in FIG. 3 d (the metal oxide layer 106 and the oxygen atom gettering layer 108 ) is subjected to a thermal treatment 114 , thereby driving the oxygen atoms 116 of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies 118 within the metal oxide layer.
  • the thermal treatment can be an annealing treatment, a microwave heating treatment, or electro-migration of oxygen atoms and the temperature of the thermal treatment can be between 200-800° C.
  • the atmosphere for annealing can be gas or N2.
  • a key aspect for the resistive random access memory of the invention is that the oxygen atom gettering layer have a higher tendency to react with oxygen than that of the contained metal of the metal oxide layer, so that the oxygen atom gettering layer 108 would be oxidized after performing the thermal treatment and a great amount of oxygen vacancies would be produced in the original metal oxide layer 106 .
  • the resistive random access memory of the invention exhibits stable binary resistance switching characteristics.
  • the top electrode can be a composite electrode including at least two metal layers such as two metal layer (first top electrode sub-layer 111 and second top electrode sub-layer 112 as shown in FIG. 4 ), wherein the at least two metal layers are made of different materials and respectively include TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof.
  • the composite top electrode can prevent oxide atoms from further diffusing thereinto.
  • the oxygen atom gettering layer may not be completely oxidized by migrated oxygen atoms and can be defined as a first sub-layer 107 directly contacted the top electrode 110 and a second sub-layer 109 directly contacted the metal oxide layer 106 , as shown in FIG. 5 .
  • the first sub-layer 107 is not oxidized by migrated oxygen atoms (i.e. the second sub-layer 109 is made of oxidized metal).
  • the element has the structure “TiN/Ti/HfO 2 /TiN” before annealing.
  • the oxygen atoms are incapable for completely diffusing among all Ti layer and the element would have the structure “TiN/Ti/TiOx/HfO 2 /TiN” after annealing.
  • the oxidized oxygen atom gettering layer 108 can have a gradient distribution of migrated oxygen atoms 116 and the metal oxide layer 106 can have a gradient distribution of oxygen vacancies 118 , when the atom gettering layer 108 has a specific thickness which less than 30 nm, as shown in FIG. 6 .
  • the gradient direction of the oxidized oxygen atom gettering layer is the same as that of the metal oxide layer.
  • a silicon substrate was provided.
  • a TiN layer with a thickness of 50 nm serving as bottom electrode was formed on the substrate.
  • an HfO layer with a thickness of 20 nm was formed on the bottom electrode, serving as a metal oxide layer.
  • a Ti layer with a thickness of 10 nm was formed on the HfO layer.
  • a TiN layer with a thickness of 50 nm was formed on the Ti layer.
  • the content of the oxygen atoms of the aforementioned structure was measured by an Auger Electron Spectroscopy (AES) before and after annealing, and the results are shown in FIG. 7 .
  • the content of the oxygen atoms of the HfO layer was reduced and that of the Ti layer was increased after annealing. Further, the content of the oxygen atoms of the TiN layer was almost the same before and after annealing. Therefore, a great amount of oxygen atoms migrated from the HfO layer into the Ti layer, resulting in production of a great amount of oxygen vacancies.
  • FIG. 8 is a graph showing the resistance switching property of the RRAM element A.
  • the endurance test of 105 switching cycles is shown in FIG. 9 . Accordingly, the resistive random access memory of the invention exhibits characteristics of superior stability and endurance.
  • a silicon substrate was provided.
  • a TiN layer with a thickness of 50 nm serving as a bottom electrode was formed on the substrate.
  • an HfO layer with a thickness of 20 nm was formed on the bottom electrode, serving as a metal oxide layer.
  • an Al layer with a thickness of 10 nm was formed on the HfO layer.
  • a TiN layer with a thickness of 50 nm was formed on the Al layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A resistive random access memory and a method for fabricating the same are provided. The method includes providing a structure comprising a substrate, a bottom electrode disposed on the substrate, a metal oxide layer disposed on the bottom electrode, and an oxygen atom gettering layer disposed on the metal oxide layer; and subjecting the structure to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional application of pending U.S. patent application Ser. No. 13/723,009, which is a continuation application of issued U.S. Pat. No. 8,362,454, filed Dec. 12, 2008 and entitled “Resistive random access memory and method for fabricating the same”, which claims priority of Taiwan Patent Application No. 97130654, filed on Aug. 12, 2008.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to a memory element, and more particularly to a resistive random access memory element.
  • 2. Description of the Related Art
  • For IC (integrated circuit) designers, the ideal semiconductor memory includes random accessibility, non-volatile characteristics, increased capacity, increased speed, reduced power consumption, and unlimited reading and writing functions. Resistive random access memory (RRAM) technology has been gradually recognized as having exhibited the aforementioned semiconductor memory advantages.
  • Please refer to FIG. 1, a conventional single-pole operation resistive random access memory 10 with a single oxide layer is shown. The resistive random access memory 10 includes a Pt bottom electrode 14, a dielectric layer 16 of nickel oxide, and a Pt top electrode 18 sequentially formed on a substrate 12. The structure of the conventional resistive random access memory 10 can be represented as below: Pt/NiO/Pt. The conventional resistive random access memory 10, however, exhibits extremely unstable operating voltage (in particular SET voltage) after repeated and continuous conversion of resistance, resulting in loss of endurance.
  • U.S. Pat. Publication No. 20070215977 discloses a resistive random access memory 20 with two adjacent oxide layers, as shown in FIG. 2. The resistive random access memory 20 includes a lower electrode 22, a first oxide layer 23, a second oxide layer 24 doped with transition metals (serving as current control layer), and an upper electrode 25 sequentially formed on a substrate 21. In comparison with the conventional single-pole operation resistive random access memory 10, the resistive random access memory 20 has lower on-current. Even so, the resistive random access memory 20 does not improve upon endurance.
  • Therefore, it is necessary to develop a resistive random access memory with superior endurance and reduced on-current.
    • BRIEF SUMMARY OF THE INVENTION
  • An exemplary embodiment of a method for fabricating a resistive random access memory includes: forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.
  • Another exemplary embodiment of a method for fabricating a resistive random access memory includes: forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a top electrode on the oxygen atom gettering layer; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with a part of the oxygen atom gettering layer, resulting in that a plurality of oxygen vacancies within the metal oxide layer, wherein a part of the oxygen atom gettering layer which is not reacted with the migrated oxygen atoms of the metal oxide layer is defined as a first sub-layer, and the part of the oxygen atom gettering layer reacted with the migrated oxygen atoms of the metal oxide layer is defined as a second sub-layer
  • The disclosure also provides a resistive random access memory fabricated by the aforementioned method. The resistive random access memory includes: a bottom electrode disposed on a substrate; a metal oxide layer with oxygen vacancies disposed on the bottom electrode and directly contacted to the bottom electrode; an oxygen atom gettering layer, oxidized by migrated oxygen atoms of the metal oxide layer, directly contacted to the metal oxide layer, wherein a material of the metal oxide layer is different from a material of the oxygen atom gettering layer; and a top electrode formed on the oxygen atom gettering layer.
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1 is a cross section of a conventional resistive random access memory.
  • FIG. 2 is a cross section of a conventional resistive random access memory with two adjacent oxide layers.
  • FIGS. 3 a to 3 e are cross sections of a method for fabricating a resistive random access memory according to an embodiment of the invention.
  • FIG. 4 is a cross section of a resistive random access memory having a top composite electrode according to another embodiment of the invention.
  • FIG. 5 is a cross section of a resistive random access memory with an oxygen atom gettering layer having a non-oxidized sub-layer according to still another embodiment of the invention.
  • FIG. 6 is a cross section of a resistive random access memory with gradient distribution according to yet another embodiment of the invention.
  • FIG. 7 is a graph plotting intensity of oxygen of each layer of the RRAM element A as disclosed in Example 1 before and after annealing.
  • FIG. 8 is a graph plotting current against voltage of the RRAM element A as disclosed in Example 1.
  • FIG. 9 is a graph plotting a resistance against read/write cycles of the RRAM element A as disclosed in Example 1.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The method for fabricating a resistive random access memory of the invention includes subjecting a metal oxide layer and an oxygen atom gettering layer (adjacent to the oxide layer) to a thermal treatment, and forcing the oxygen atoms of oxide layer to migrate into the oxygen atom gettering layer to leave oxygen vacancies within the oxide layer. Since the oxygen vacancies of the resistive random access memory can optionally capture or release electric charges, the resistive random access memory of the invention exhibits stable binary resistance switching characteristics.
  • The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
  • First, referring to FIG. 3 a, a substrate 102 with a bottom electrode 104 formed thereon is provided. Particularly, the substrate 102 can be a substrate employed in a semiconductor process, such as silicon substrate. The substrate 102 can be a substrate including a complementary metal oxide semiconductor (CMOS) circuit, isolation structure, diode, or capacitor. The accompanying drawings show the substrate 100 in a plain rectangle in order to simplify the illustration. Further, the bottom electrode 104 can be electrically connected to a drain electrode of a transistor (not shown). The bottom electrode 104 can further include an oxygen barrier layer formed thereon. Suitable material for the bottom electrode 104 can be TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof, and thickness of the bottom electrode can be between 5-500 nm.
  • Next, please refer to FIG. 3 b, wherein a metal oxide layer 106 is formed on the bottom electrode 104 and directly contacts to the bottom electrode 104. Herein, the metal oxide layer can consist of a binary oxide, such as binary metal oxide with oxides containing Al, Hf, Ti, Nb, Ta, La, or Zr. It should be noted that since the oxide layer must be formed directly on the bottom electrode and a subsequent oxygen atom gettering layer must be formed on the oxide layer, the binary oxide layer can achieve the expected characteristics of a resistive random access memory (RRAM). Therefore, a ternary oxide layer is not required to be used as the oxide layer of the invention, resulting in reduction of process complexity. The method for forming the metal oxide layer is unlimited. The thickness of the metal oxide layer 106 can be between 1-100 nm.
  • Next, please refer to FIG. 3 c, wherein an oxygen atom gettering layer 108 is formed on the metal oxide layer 106 and directly contacts to the metal oxide layer 106. The of the oxygen atom gettering layer can be between 1-50 nm. In an embodiment of the invention, the oxygen atom gettering layer can be metal, such as Mg, Al, Zn, Ti, Hf, La, Ta, Zr, Cu, laminations thereof, or combinations thereof (for example AlCu). Further, according to another embodiment of the invention, the oxygen atom gettering layer 108 includes partially oxidized metallic oxide or a mixture of metal and metallic oxide. The oxygen atom gettering layer 108 can include partially oxidized metallic oxides containing Mg, Al, Zn, Ti, Hf, La, Ta, Zr, Cu, or combinations thereof. For example, the oxygen atom gettering layer can include TiO, TaO, or AlO. It should be noted that the oxygen atom gettering layer must include materials which have lower oxidation chemical formation energy than that of the metal oxide layer 106. As a result, after a subsequent thermal treatment, the oxygen atoms of the metal oxide layer 106 would migrate into and react with the oxygen atom gettering layer 108.
  • Next, please refer to FIG. 3 d, wherein a top electrode 110 is formed on the oxygen atom gettering layer 108. The top electrode includes TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof.
  • Finally, please refer to FIG. 3 e, wherein the structure shown in FIG. 3 d (the metal oxide layer 106 and the oxygen atom gettering layer 108) is subjected to a thermal treatment 114, thereby driving the oxygen atoms 116 of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies 118 within the metal oxide layer. Thus, completing the process for forming a resistive random access memory. The thermal treatment can be an annealing treatment, a microwave heating treatment, or electro-migration of oxygen atoms and the temperature of the thermal treatment can be between 200-800° C. When the thermal treatment is an annealing treatment, the atmosphere for annealing can be gas or N2. A key aspect for the resistive random access memory of the invention is that the oxygen atom gettering layer have a higher tendency to react with oxygen than that of the contained metal of the metal oxide layer, so that the oxygen atom gettering layer 108 would be oxidized after performing the thermal treatment and a great amount of oxygen vacancies would be produced in the original metal oxide layer 106.
  • Since the oxygen vacancies of the resistive random access memory can optionally capture or release electric charges, the resistive random access memory of the invention exhibits stable binary resistance switching characteristics.
  • Please refer to FIG. 4, in embodiments of the invention, the top electrode can be a composite electrode including at least two metal layers such as two metal layer (first top electrode sub-layer 111 and second top electrode sub-layer 112 as shown in FIG. 4), wherein the at least two metal layers are made of different materials and respectively include TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof. The composite top electrode can prevent oxide atoms from further diffusing thereinto.
  • According to another embodiment of the invention, the oxygen atom gettering layer may not be completely oxidized by migrated oxygen atoms and can be defined as a first sub-layer 107 directly contacted the top electrode 110 and a second sub-layer 109 directly contacted the metal oxide layer 106, as shown in FIG. 5. The first sub-layer 107 is not oxidized by migrated oxygen atoms (i.e. the second sub-layer 109 is made of oxidized metal). For example, the element has the structure “TiN/Ti/HfO2/TiN” before annealing. When the thickness of Ti layer is not less than 30 nm, the oxygen atoms are incapable for completely diffusing among all Ti layer and the element would have the structure “TiN/Ti/TiOx/HfO2/TiN” after annealing.
  • In still another embodiment of the invention, the oxidized oxygen atom gettering layer 108 can have a gradient distribution of migrated oxygen atoms 116 and the metal oxide layer 106 can have a gradient distribution of oxygen vacancies 118, when the atom gettering layer 108 has a specific thickness which less than 30 nm, as shown in FIG. 6. Particularly, the gradient direction of the oxidized oxygen atom gettering layer is the same as that of the metal oxide layer.
  • The following examples are intended to illustrate the invention more fully without limiting its scope, since numerous modifications and variations will be apparent to those skilled in this art.
    • Example 1
  • A silicon substrate was provided. A TiN layer with a thickness of 50 nm serving as bottom electrode was formed on the substrate. Next, an HfO layer with a thickness of 20 nm was formed on the bottom electrode, serving as a metal oxide layer. Next, a Ti layer with a thickness of 10 nm was formed on the HfO layer. Next, a TiN layer with a thickness of 50 nm was formed on the Ti layer. Finally, the above structure was subjected to an annealing treatment, thereby forcing the oxygen atoms of the HfO to migrate into the Ti to form TiO. Thus, obtaining a RRAM element A.
  • The content of the oxygen atoms of the aforementioned structure was measured by an Auger Electron Spectroscopy (AES) before and after annealing, and the results are shown in FIG. 7. The content of the oxygen atoms of the HfO layer was reduced and that of the Ti layer was increased after annealing. Further, the content of the oxygen atoms of the TiN layer was almost the same before and after annealing. Therefore, a great amount of oxygen atoms migrated from the HfO layer into the Ti layer, resulting in production of a great amount of oxygen vacancies.
  • FIG. 8 is a graph showing the resistance switching property of the RRAM element A. The endurance test of 105 switching cycles is shown in FIG. 9. Accordingly, the resistive random access memory of the invention exhibits characteristics of superior stability and endurance.
    • Example 2
  • A silicon substrate was provided. A TiN layer with a thickness of 50 nm serving as a bottom electrode was formed on the substrate. Next, an HfO layer with a thickness of 20 nm was formed on the bottom electrode, serving as a metal oxide layer. Next, an Al layer with a thickness of 10 nm was formed on the HfO layer. Next, a TiN layer with a thickness of 50 nm was formed on the Al layer. Finally, the above structure was subjected to an annealing treatment, thereby forcing the oxygen atoms of the HfO to migrate into the Al to form the AlO layer. Thus, obtaining a RRAM element B.
  • While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (21)

What is claimed is:
1. A method for fabricating a resistive random access memory, comprising:
providing a structure comprising a substrate, a bottom electrode disposed on the substrate, a metal oxide layer disposed on the bottom electrode, and an oxygen atom gettering layer disposed on the metal oxide layer; and
subjecting the structure to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.
2. The method as claimed in claim 1, wherein the bottom electrode comprises an oxygen barrier layer.
3. The method as claimed in claim 1, wherein the bottom electrode comprises TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof.
4. The method as claimed in claim 1, wherein the thickness of the bottom electrode is between 5-500 nm.
5. The method as claimed in claim 1, wherein the metal oxide layer comprises a binary oxide.
6. The method as claimed in claim 1, wherein the metal oxide layer comprises oxides containing Al, Hf, Ti, Nb, Ta, La, or Zr.
7. The method as claimed in claim 1, wherein the thickness of the metal oxide layer is between 1-100 nm.
8. The method as claimed in claim 1, wherein the thickness of the oxygen atom gettering layer is between 1-50 nm.
9. The method as claimed in claim 1, wherein the oxygen atom gettering layer comprises metal.
10. The method as claimed in claim 1, wherein the oxygen atom gettering layer comprises Mg, Al, Zn, Ti, Hf, La, Ta, Zr, Cu, laminations thereof, or combinations thereof.
11. The method as claimed in claim 1, wherein the oxygen atom gettering layer comprises partially oxidized metallic oxide.
12. The method as claimed in claim 11, wherein the oxygen atom gettering layer comprises partially oxidized metallic oxides containing Mg, Al, Zn, Ti, Hf, La, Ta, Zr, Cu, or combinations thereof.
13. The method as claimed in claim 11, wherein the oxygen atom gettering layer comprises TiO, TaO, or AlO.
14. The method as claimed in claim 1, wherein the top electrode comprises TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof.
15. The method as claimed in claim 1, wherein the thickness of the top electrode is between 5-500 nm.
16. The method as claimed in claim 1, wherein the thermal treatment comprises an annealing treatment.
17. The method as claimed in claim 16, wherein the temperature of the annealing treatment is between 200-800° C.
18. The method as claimed in claim 1, wherein the thermal treatment comprises a microwave heating treatment.
19. The method as claimed in claim 18, wherein the temperature of the microwave heating treatment is between 200-800° C.
20. The method as claimed in claim 1, wherein the thermal treatment comprises electro-migration of oxygen atoms.
21. A resistive random access memory, comprising:
a bottom electrode disposed on a substrate;
a metal oxide layer with oxygen vacancies disposed on the bottom electrode and directly contacted to the bottom electrode;
an oxygen atom gettering layer, oxidized by migrated oxygen atoms of the metal oxide layer, directly contacted to the metal oxide layer, wherein the oxygen atom gettering layer has a concentration gradient of migrated oxygen atoms; and
a top electrode formed on the oxygen atom gettering layer.
US14/735,063 2008-08-12 2015-06-09 Resistive random access memory and method for fabricating the same Abandoned US20150280122A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/735,063 US20150280122A1 (en) 2008-08-12 2015-06-09 Resistive random access memory and method for fabricating the same

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
TW97130654 2008-08-12
TW97130654 2008-08-12
US12/334,203 US8362454B2 (en) 2008-08-12 2008-12-12 Resistive random access memory having metal oxide layer with oxygen vacancies and method for fabricating the same
US13/723,009 US9142776B2 (en) 2008-08-12 2012-12-20 Resistive random access memory and method for fabricating the same
US14/735,063 US20150280122A1 (en) 2008-08-12 2015-06-09 Resistive random access memory and method for fabricating the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/723,009 Division US9142776B2 (en) 2008-08-12 2012-12-20 Resistive random access memory and method for fabricating the same

Publications (1)

Publication Number Publication Date
US20150280122A1 true US20150280122A1 (en) 2015-10-01

Family

ID=41680748

Family Applications (4)

Application Number Title Priority Date Filing Date
US12/334,203 Active 2030-07-07 US8362454B2 (en) 2008-08-12 2008-12-12 Resistive random access memory having metal oxide layer with oxygen vacancies and method for fabricating the same
US13/723,009 Active 2029-08-25 US9142776B2 (en) 2008-08-12 2012-12-20 Resistive random access memory and method for fabricating the same
US14/521,422 Active US9373789B2 (en) 2008-08-12 2014-10-22 Resistive random access memory and method for fabricating the same
US14/735,063 Abandoned US20150280122A1 (en) 2008-08-12 2015-06-09 Resistive random access memory and method for fabricating the same

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US12/334,203 Active 2030-07-07 US8362454B2 (en) 2008-08-12 2008-12-12 Resistive random access memory having metal oxide layer with oxygen vacancies and method for fabricating the same
US13/723,009 Active 2029-08-25 US9142776B2 (en) 2008-08-12 2012-12-20 Resistive random access memory and method for fabricating the same
US14/521,422 Active US9373789B2 (en) 2008-08-12 2014-10-22 Resistive random access memory and method for fabricating the same

Country Status (2)

Country Link
US (4) US8362454B2 (en)
TW (1) TWI469338B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112331768A (en) * 2020-11-13 2021-02-05 上海华力集成电路制造有限公司 Method for manufacturing RRAM device and method for preparing gradient insulating layer structure

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8343813B2 (en) * 2009-04-10 2013-01-01 Intermolecular, Inc. Resistive-switching memory elements having improved switching characteristics
US8362454B2 (en) * 2008-08-12 2013-01-29 Industrial Technology Research Institute Resistive random access memory having metal oxide layer with oxygen vacancies and method for fabricating the same
US9385314B2 (en) 2008-08-12 2016-07-05 Industrial Technology Research Institute Memory cell of resistive random access memory and manufacturing method thereof
US9000411B2 (en) * 2009-01-06 2015-04-07 Hewlett-Packard Development Company, L.P. Memristor devices configured to control bubble formation
WO2010085226A1 (en) * 2009-01-26 2010-07-29 Hewlett-Packard Development Company, L.P. Using alloy electrodes to dope memristors
JPWO2011043448A1 (en) * 2009-10-09 2013-03-04 日本電気株式会社 Semiconductor device and manufacturing method thereof
US8216862B2 (en) * 2010-03-16 2012-07-10 Sandisk 3D Llc Forming and training processes for resistance-change memory cell
US8354660B2 (en) * 2010-03-16 2013-01-15 Sandisk 3D Llc Bottom electrodes for use with metal oxide resistivity switching layers
TWI399852B (en) * 2010-05-26 2013-06-21 Ind Tech Res Inst Resistance random access memory and method of fabricating the same
US8946046B1 (en) 2012-05-02 2015-02-03 Crossbar, Inc. Guided path for forming a conductive filament in RRAM
US9570678B1 (en) 2010-06-08 2017-02-14 Crossbar, Inc. Resistive RAM with preferental filament formation region and methods
US9601692B1 (en) 2010-07-13 2017-03-21 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US8737111B2 (en) 2010-06-18 2014-05-27 Sandisk 3D Llc Memory cell with resistance-switching layers
US8520425B2 (en) 2010-06-18 2013-08-27 Sandisk 3D Llc Resistive random access memory with low current operation
US8724369B2 (en) 2010-06-18 2014-05-13 Sandisk 3D Llc Composition of memory cell with resistance-switching layers
US8569172B1 (en) 2012-08-14 2013-10-29 Crossbar, Inc. Noble metal/non-noble metal electrode for RRAM applications
US8884261B2 (en) 2010-08-23 2014-11-11 Crossbar, Inc. Device switching using layered device structure
KR20120021539A (en) * 2010-08-06 2012-03-09 삼성전자주식회사 Nonvolatile memory element and memory device including the same
KR101744758B1 (en) 2010-08-31 2017-06-09 삼성전자 주식회사 Nonvolatile memory element and memory device including the same
US8325507B2 (en) * 2010-09-29 2012-12-04 Hewlett-Packard Development Company, L.P. Memristors with an electrode metal reservoir for dopants
US8389971B2 (en) 2010-10-14 2013-03-05 Sandisk 3D Llc Memory cells having storage elements that share material layers with steering elements and methods of forming the same
US8841648B2 (en) * 2010-10-14 2014-09-23 Sandisk 3D Llc Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same
US20120091418A1 (en) * 2010-10-14 2012-04-19 Yung-Tin Chen Bipolar storage elements for use in memory cells and methods of forming the same
USRE46335E1 (en) 2010-11-04 2017-03-07 Crossbar, Inc. Switching device having a non-linear element
US8502185B2 (en) 2011-05-31 2013-08-06 Crossbar, Inc. Switching device having a non-linear element
KR101166227B1 (en) 2011-04-12 2012-08-03 연세대학교 산학협력단 Nonvolatile resistive-switching random access memory device and method for fabricating the same
US9620206B2 (en) 2011-05-31 2017-04-11 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US8619459B1 (en) 2011-06-23 2013-12-31 Crossbar, Inc. High operating speed resistive random access memory
US8946669B1 (en) 2012-04-05 2015-02-03 Crossbar, Inc. Resistive memory device and fabrication methods
US9627443B2 (en) 2011-06-30 2017-04-18 Crossbar, Inc. Three-dimensional oblique two-terminal memory with enhanced electric field
US9166163B2 (en) 2011-06-30 2015-10-20 Crossbar, Inc. Sub-oxide interface layer for two-terminal memory
US9564587B1 (en) 2011-06-30 2017-02-07 Crossbar, Inc. Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
US20130247935A1 (en) * 2011-10-31 2013-09-26 Seh-Jin Park Getter reticle
US8637413B2 (en) * 2011-12-02 2014-01-28 Sandisk 3D Llc Nonvolatile resistive memory element with a passivated switching layer
TWI483394B (en) * 2011-12-27 2015-05-01 Ind Tech Res Inst A resistive random access memory and its fabrication method
US8581224B2 (en) * 2012-01-20 2013-11-12 Micron Technology, Inc. Memory cells
US9093636B2 (en) 2012-01-30 2015-07-28 Micron Technology, Inc. Incorporation of oxygen into memory cells
US8633118B2 (en) * 2012-02-01 2014-01-21 Tokyo Electron Limited Method of forming thin metal and semi-metal layers by thermal remote oxygen scavenging
US9685608B2 (en) * 2012-04-13 2017-06-20 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US8658476B1 (en) 2012-04-20 2014-02-25 Crossbar, Inc. Low temperature P+ polycrystalline silicon material for non-volatile memory device
US8536558B1 (en) * 2012-07-31 2013-09-17 Globalfoundries Singapore Pte. Ltd. RRAM structure with improved memory margin
US9583701B1 (en) 2012-08-14 2017-02-28 Crossbar, Inc. Methods for fabricating resistive memory device switching material using ion implantation
US10096653B2 (en) 2012-08-14 2018-10-09 Crossbar, Inc. Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
JP5696260B2 (en) * 2012-09-05 2015-04-08 株式会社アルバック Resistance change element and manufacturing method thereof
US20140077149A1 (en) * 2012-09-14 2014-03-20 Industrial Technology Research Institute Resistance memory cell, resistance memory array and method of forming the same
US9129894B2 (en) 2012-09-17 2015-09-08 Intermolecular, Inc. Embedded nonvolatile memory elements having resistive switching characteristics
US9576616B2 (en) 2012-10-10 2017-02-21 Crossbar, Inc. Non-volatile memory with overwrite capability and low write amplification
US8872152B2 (en) 2012-12-13 2014-10-28 Intermolecular, Inc. IL-free MIM stack for clean RRAM devices
CN103117359B (en) 2013-02-07 2015-04-15 北京大学 High-reliability nonvolatile memory and preparation method thereof
US20140241031A1 (en) 2013-02-28 2014-08-28 Sandisk 3D Llc Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same
US8981332B2 (en) * 2013-03-15 2015-03-17 Intermolecular, Inc. Nonvolatile resistive memory element with an oxygen-gettering layer
CN103280405A (en) * 2013-05-28 2013-09-04 清华大学 Method of forming stacking structure of ultrathin mixed oxide layer
GB2515568B (en) 2013-06-28 2016-05-18 Ibm Resistive random-access memory cells
US9203022B2 (en) 2013-07-23 2015-12-01 Globalfoundries Inc. Resistive random access memory devices with extremely reactive contacts
CN104617218B (en) * 2013-11-04 2018-12-11 华邦电子股份有限公司 Resistive memory device and preparation method thereof
CN103594622B (en) * 2013-11-28 2016-10-05 北京大学 High conforming resistance variation memory structure and preparation method thereof
US10290801B2 (en) 2014-02-07 2019-05-14 Crossbar, Inc. Scalable silicon based resistive memory device
CN103915565B (en) * 2014-04-03 2017-06-13 电子科技大学 A kind of multistage random access memory unit and preparation method thereof
KR101562932B1 (en) * 2014-11-28 2015-10-26 연세대학교 산학협력단 Oxide semiconductor device and method for fabricating the same
US10516109B2 (en) * 2014-12-24 2019-12-24 Intel Corporation Resistive memory cells and precursors thereof, methods of making the same, and devices including the same
TWI563502B (en) * 2015-04-27 2016-12-21 Winbond Electronics Corp Resistive random access memory
KR102469834B1 (en) * 2015-06-26 2022-11-23 타호 리서치 리미티드 Perpendicular magnetic memory with filamentary conduction path
CN106410024A (en) * 2015-08-03 2017-02-15 华邦电子股份有限公司 Resistance-type random access memory
US10230047B2 (en) * 2015-10-22 2019-03-12 Winbond Electronics Corp. RRAM device and method for manufacturing the same
US20170133588A1 (en) * 2015-11-06 2017-05-11 HGST Netherlands B.V. Resistive ram cell with focused electric field
US20170287555A1 (en) * 2016-03-31 2017-10-05 Intel Corporation Resistive random access memory cell having bottom-side oel layer and/or optimized access signaling
US11063209B2 (en) 2017-05-30 2021-07-13 Samsung Electronics Co., Ltd. Method and system for providing magnetic junctions utilizing oxygen blocking, oxygen adsorber and tuning layer(s)
US10340449B2 (en) * 2017-06-01 2019-07-02 Sandisk Technologies Llc Resistive memory device containing carbon barrier and method of making thereof
US10516106B2 (en) 2017-06-26 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Electrode structure to improve RRAM performance
US10361366B2 (en) 2017-08-03 2019-07-23 Tokyo Electron Limited Resistive random accress memory containing a conformal titanium aluminum carbide film and method of making
US10490739B2 (en) * 2018-01-10 2019-11-26 Winbond Electronics Corp. One-time-programmable resistive random access memory and method for forming the same
US11437573B2 (en) * 2018-03-29 2022-09-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
US11476416B2 (en) 2018-03-29 2022-10-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
WO2020024221A1 (en) 2018-08-02 2020-02-06 深圳市为通博科技有限责任公司 Preparation method and preparation device for memristor electrode material, and memristor electrode material
US10985316B2 (en) * 2018-09-27 2021-04-20 Taiwan Semiconductor Manufacturing Co., Ltd. Bottom electrode structure in memory device
TWI676170B (en) * 2018-12-22 2019-11-01 國立中山大學 Selector and method for manufacturing the same
TWI696179B (en) 2019-07-09 2020-06-11 華邦電子股份有限公司 Resistive random access memory and resetting method thereof
KR102638493B1 (en) * 2019-09-03 2024-02-19 에스케이하이닉스 주식회사 Nonvolatile memory device and method of fabricating the same
US11042432B1 (en) 2019-12-20 2021-06-22 Western Digital Technologies, Inc. Data storage device with dynamic stripe length manager
CN112018237B (en) * 2020-07-31 2021-11-23 厦门半导体工业技术研发有限公司 Semiconductor device and method for manufacturing semiconductor device
CN112928210B (en) * 2021-02-03 2022-04-15 长鑫存储技术有限公司 Capacitor structure and preparation method thereof
CN112909167B (en) * 2021-03-10 2023-04-07 中国科学院微电子研究所 Resistive random access memory and preparation method thereof
CN115117236A (en) * 2021-03-17 2022-09-27 华邦电子股份有限公司 Resistive random access memory and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150044851A1 (en) * 2008-08-12 2015-02-12 Industrial Technology Research Institute Resistive random access memory and method for fabricating the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2703206B2 (en) * 1994-09-30 1998-01-26 三星電子株式会社 Ferroelectric capacitor and method of manufacturing the same
JP4376490B2 (en) 2002-07-19 2009-12-02 富士通マイクロエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6831854B2 (en) * 2002-08-02 2004-12-14 Unity Semiconductor Corporation Cross point memory array using distinct voltages
KR100576369B1 (en) 2004-11-23 2006-05-03 삼성전자주식회사 Method for programming a non-volatile memory device employing a transition metal oxide layer as a data storage material layer
US20070048990A1 (en) 2005-08-30 2007-03-01 Sharp Laboratories Of America, Inc. Method of buffer layer formation for RRAM thin film deposition
US7666526B2 (en) 2005-11-30 2010-02-23 The Trustees Of The University Of Pennsylvania Non-volatile resistance-switching oxide thin film devices
KR100723420B1 (en) 2006-02-20 2007-05-30 삼성전자주식회사 Non volatile memory device comprising amorphous alloy metal oxide layer
KR100718155B1 (en) 2006-02-27 2007-05-14 삼성전자주식회사 Non-volatile memory device using two oxide layer
KR101176543B1 (en) 2006-03-10 2012-08-28 삼성전자주식회사 Resistance Random Memory Device
KR101239962B1 (en) 2006-05-04 2013-03-06 삼성전자주식회사 Variable resistive memory device comprising buffer layer on lower electrode
KR101159075B1 (en) 2006-06-27 2012-06-25 삼성전자주식회사 Variable resistance random access memory device comprising n+ interfacial layer
JP2009164580A (en) * 2007-11-07 2009-07-23 Interuniv Micro Electronica Centrum Vzw METHOD FOR MANUFACTURING MEMORY ELEMENT COMPRISING RESISTIVITY-SWITCHING NiO LAYER AND DEVICES OBTAINED THEREOF
US20090189159A1 (en) 2008-01-28 2009-07-30 Atmel Corporation Gettering layer on substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150044851A1 (en) * 2008-08-12 2015-02-12 Industrial Technology Research Institute Resistive random access memory and method for fabricating the same
US9142776B2 (en) * 2008-08-12 2015-09-22 Industrial Technology Research Institute Resistive random access memory and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112331768A (en) * 2020-11-13 2021-02-05 上海华力集成电路制造有限公司 Method for manufacturing RRAM device and method for preparing gradient insulating layer structure

Also Published As

Publication number Publication date
US9373789B2 (en) 2016-06-21
TW201007939A (en) 2010-02-16
US20100038791A1 (en) 2010-02-18
US8362454B2 (en) 2013-01-29
US20130119343A1 (en) 2013-05-16
TWI469338B (en) 2015-01-11
US20150044851A1 (en) 2015-02-12
US9142776B2 (en) 2015-09-22

Similar Documents

Publication Publication Date Title
US9373789B2 (en) Resistive random access memory and method for fabricating the same
US9397292B2 (en) Methods for forming resistive switching memory elements by heating deposited layers
KR101054321B1 (en) Semiconductor device and manufacturing method thereof
US9112144B2 (en) Method of fabricating a resistive non-volatile memory device
US20120292587A1 (en) Nonvolatile memory device
CN103907192A (en) Resistive switching devices having alloyed electrodes and methods of formation thereof
CN102449763B (en) Nonvolatile memory element and method for manufacturing same
WO2008075471A1 (en) Resistance change element and method for manufacturing the same
US20090230391A1 (en) Resistance Storage Element and Method for Manufacturing the Same
TWI497693B (en) Memory cell and process for manufacturing the same
JP5572749B2 (en) Nonvolatile memory element and manufacturing method thereof
KR101570742B1 (en) Resistive random access memory and method of fabricating the same
US11770985B2 (en) Resistive random access memory and method of fabricating the same
US20080247215A1 (en) Resistive switching element
US20110031468A1 (en) Nonvolatile memory device and method for manufacturing the same
US8907314B2 (en) MoOx-based resistance switching materials
KR20110014518A (en) Semiconductor memory device and a method of menufacturing the same
KR20170089726A (en) switching device and method of fabricating the same, and resistive random access memory having the switching device as selection device
CN101577307B (en) Storage unit of resistance storage and manufacture method thereof
US9385314B2 (en) Memory cell of resistive random access memory and manufacturing method thereof
TWI497492B (en) Memory cell of resistive random access memory and manufacturing method thereof
US20130105758A1 (en) Memory cell of resistive random access memory and manufacturing method thereof
KR102614117B1 (en) Capacitor for semiconductor device, method of manufacturing capacitor for semiconductor device, and dram device
CN114005851A (en) Resistive random access memory and manufacturing method thereof
CN113764578A (en) Memory device and method of forming a memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, HENG-YUAN;CHEN, PANG-SHIU;WU, TAI-YUAN;AND OTHERS;REEL/FRAME:035822/0053

Effective date: 20150528

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION