US20150270223A1 - Method for applying a final metal layer for wafer level packaging and associated device - Google Patents

Method for applying a final metal layer for wafer level packaging and associated device Download PDF

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US20150270223A1
US20150270223A1 US14/577,544 US201414577544A US2015270223A1 US 20150270223 A1 US20150270223 A1 US 20150270223A1 US 201414577544 A US201414577544 A US 201414577544A US 2015270223 A1 US2015270223 A1 US 2015270223A1
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metal layer
alloys
backside
layer
titanium
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Guy F. Burgess
Anthony P. Curtis
Douglas M. Scott
Shannon D. Buzard
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials

Definitions

  • the present disclosure generally relates to a structure and method for semiconductor devices, and more particularly to a structure and method for electronic wafer-level chip-scale packaging and flip-chip packaging and assembly.
  • Backside metallization depositions/coatings can be applied to the semiconductor chips or other microelectronic devices via sputtering, evaporation, electroplating, electroless plating etc. which are deposition technologies that are known to those familiar with the art.
  • metallizations are placed on the backside of the semiconductor substrate in the semiconductor industry. They can be used on integrated circuits to help dissipate heat buildup during operation of the device. They can also be used to modify the electrical properties of the semiconductor substrate. They can also be used to increase the mechanical strength or reliability of a thinned substrate following a backgrind process.
  • Backside metallization layer(s) are generally placed on the backside of thinly ground or full thickness chips/devices while the chips/devices are still in wafer form.
  • Backside metallization requires suitable adhesion between the semiconductor substrate material and the initial backside metallization layer. Subsequent metal layers can then be applied dependent on the intended application provided the added metal depositions/coatings have a suitable level of adhesion between layers for long term reliability.
  • Copper and its alloys are highly used backside metallization layers due to their high electrical conductivity and thermal heat transfer; however Cu and its alloys can become corroded or oxidized in subsequent processing steps, during assembly, and/or subjected to high humidity environments.
  • a corroded or oxidized backside metal surface presents a variety of problems which could include but are not limited to: a discolored backside surface that will interfere with automated assembly vision requirements (especially if a laser marking is present), increased risk of extended corrosion shortening the life of the part, increased risk of extended corrosion inhibiting the overall performance of the device.
  • This disclosure provides a cost effective corrosion/oxidation resistant backside protective metal layer atop any layer of Copper and its alloys and any other previously applied backside metal layer that is susceptible to the problems described above. This will thereby provide a surface that is chemically and mechanically viable through subsequent processing steps, assembly, and throughout the life of the assembled part.
  • a reliable and manufacturable method for applying a corrosion and oxidation resistant metal layer atop previously applied backside metal layer(s) for thinned and full thickness semiconductor substrates has been invented.
  • the deposition of this metal layer can be accomplished through sputtering, evaporation, immersion plating, electroless plating, or other deposition/coating techniques.
  • the method in accordance with this disclosure includes providing a semiconductor device such as a Wafer-Level Chip-Scale package (WLCSP) device that has at least an outer backside metal layer that is susceptible to corrosion or discoloration; and applying a protective metal layer to the outer backside metal layer wherein the protective metal is selected from the group consisting of Titanium, Titanium Alloys, Nickel, Nickel Alloys, Chromium, Chromium Alloys, Cobalt and Cobalt Alloys, Palladium and Palladium Alloys.
  • WLCSP Wafer-Level Chip-Scale package
  • the device in accordance with this disclosure include a semiconductor wafer substrate having a backside and a conductive prior metallization layer on the backside, and a protective metal layer over the metallization layer wherein the protective metal is selected from the group consisting of Titanium, Titanium alloys, Nickel, Nickel alloys, Chromium, Chromium alloys, Cobalt, Cobalt alloys, Palladium and Palladium alloys.
  • FIG. 1 illustrates a cross-sectional view of a portion of a semiconductor wafer substrate with 1/0 bond pads. This view also shows the deposited backside metal layers.
  • FIG. 2 illustrates a closer cross-sectional view of the semiconductor wafer substrate and the backside metal layers.
  • FIG. 3 illustrates a backside view of the semiconductor substrate with backside metallization and with a laser marking.
  • FIG. 4 illustrates the cross-sectional view of a portion of an assembled WLCSP device with backside metallization attached to a corresponding board or other board side substrate.
  • One embodiment of a method in accordance with this disclosure includes providing a semiconductor device such as a Wafer-Level Chip-Scale package (WLCSP) device that has at least an outer backside metal layer that is susceptible to corrosion or discoloration; and applying a protective metal layer of titanium to the outer backside metal layer.
  • WLCSP Wafer-Level Chip-Scale package
  • This titanium layer may be applied by any conventional means such as vapor deposition, sputtering, and chemical plating.
  • the corrosion/oxidation resistant metals for this invention include: titanium and its alloys, nickel and its alloys, chromium and its alloys, and cobalt and its alloys. This disclosure provides a means for the finished surface to remain uniformly colored throughout the life of the part, even in higher humidity conditions for both non-laser mark applications, as well as laser marked surfaces.
  • This method applies to any semiconductor substrate with previously applied backside metallization that can be corroded, oxidized, and/or discolored and includes but is not limited to: copper and its alloys, aluminum and its alloys, silver and its alloys, tungsten and its alloys, etc.
  • the resulting corrosion/oxidation resistant metal layer can be deposited with a range between 10 Angstroms and 40,000 Angstroms.
  • the underlying metal layer is a copper plated metallization that is also subsequently processed through laser marking, which produces a laser marked backside plated copper layer, followed by the deposition of a corrosion/oxidation resistant titanium layer.
  • the resulting backside metallization is uniformly colorized for clear legibility of the laser marking and it is highly resistant to corrosion or oxidation.
  • FIG. 1 shows a cross sectional view of an assembled WLCSP device substrate 100 that includes one or more backside metal layers 102 .
  • FIG. 2 is an enlarged view of the device substrate 100 in accordance with the present disclosure showing an adhesion metal layer 104 applied first to the wafer substrate 106 , followed by a primary backside metal layer 108 , and finally application of a protective corrosion resistant metal layer 110 in accordance with the present disclosure.
  • This protective outer corrosion resistant metal layer 110 may be applied either before or after laser etching of an identification mark 112 as shown in FIG. 3 .
  • FIG. 4 is a cross sectional view of a completely assembled device 200 in accordance with an embodiment of the present disclosure.
  • the backside metal layers 202 comprise at least a primary layer 108 and an outer corrosion resistant layer 110 as described above with reference to FIG. 2 .
  • This disclosure includes a new method of using a final backside metallization layer 110 that is corrosion/oxidation resistant atop previously deposited/coated metal layers.
  • This corrosion/oxidation resistant layer can be deposited through the means of sputtering, evaporation, immersion plating, electroless plating or other deposition/coating techniques.
  • Titanium and its alloys are an ideal metal for this final resistant backside metallization layer provided its adhesion to the previously deposited metallization layer is suitable for reliability.
  • This new method can be used in conjunction with or without laser marking, with the laser marking occurring either before or after the deposition of this final protective metallization layer.
  • the method involves using a final backside metallization layer that is corrosion/oxidation resistant atop a previously deposited copper or one of its alloys as the prior metallization layers.
  • the final metallization layer is comprised of titanium atop a previously electroplated copper or one of its alloys as the prior metallization layer.
  • One specific embodiment of this invention includes deposition of copper or one of its alloys as a first backside metallization, producing a laser marking on the first backside metallization layer, followed by deposition of an additional metallization layer of titanium atop the previously deposited copper backside metallization or one of its alloys.
  • An alternate embodiment of this invention includes deposition of copper or one of its alloys as a first backside metallization, followed by deposition of an additional metallization layer of titanium atop a previously deposited copper or one of its alloys, and finally creation of a laser marking on the previously deposited layer.
  • additional metallization layers may be applied beyond the two layers above specifically described.
  • the corrosion/oxidation resistant layer can be deposited in a range between 10 Angstroms and 40,000 Angstroms.
  • backside metallization layers have incorporated gold, silver, platinum, palladium, and nickel as a final deposited layer in a stack of metals
  • the specific benefit of this new method is that it can be applied later, such as after multiple steps of sputtering/plating processes or sputter/plating/laser marking processes, etc.
  • it can preferably be applied after the laser marking process.

Abstract

A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substitute having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt, cobalt alloys, palladium, and palladium alloys.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This divisional application claims the benefit of priority of U.S. Non-Provisional patent application Ser. No. 13/789,411, filed Mar. 7, 2013, entitled Method For Applying A Corrosion Resistant Final Metal Layer Atop Previous Backside Metal Layer(s) For Wafer Level Packaging, which claims priority from Provisional Patent Application Ser. No. 61/658,788, filed Jun. 12, 2012, entitled Method For Applying A Corrosion Resistant Final Metal Layer Atop Previous Backside Metal Layer(s) For Wafer Level Packaging. The disclosure of both applications is hereby incorporated by reference in its entirety.
    • FIELD
  • The present disclosure generally relates to a structure and method for semiconductor devices, and more particularly to a structure and method for electronic wafer-level chip-scale packaging and flip-chip packaging and assembly.
    • BACKGROUND
  • Backside metallization depositions/coatings can be applied to the semiconductor chips or other microelectronic devices via sputtering, evaporation, electroplating, electroless plating etc. which are deposition technologies that are known to those familiar with the art. There are a variety of reasons metallizations are placed on the backside of the semiconductor substrate in the semiconductor industry. They can be used on integrated circuits to help dissipate heat buildup during operation of the device. They can also be used to modify the electrical properties of the semiconductor substrate. They can also be used to increase the mechanical strength or reliability of a thinned substrate following a backgrind process.
  • Backside metallization layer(s) are generally placed on the backside of thinly ground or full thickness chips/devices while the chips/devices are still in wafer form.
  • Backside metallization requires suitable adhesion between the semiconductor substrate material and the initial backside metallization layer. Subsequent metal layers can then be applied dependent on the intended application provided the added metal depositions/coatings have a suitable level of adhesion between layers for long term reliability.
  • Copper and its alloys are highly used backside metallization layers due to their high electrical conductivity and thermal heat transfer; however Cu and its alloys can become corroded or oxidized in subsequent processing steps, during assembly, and/or subjected to high humidity environments.
  • A corroded or oxidized backside metal surface presents a variety of problems which could include but are not limited to: a discolored backside surface that will interfere with automated assembly vision requirements (especially if a laser marking is present), increased risk of extended corrosion shortening the life of the part, increased risk of extended corrosion inhibiting the overall performance of the device.
  • One known solution is to apply an outer corrosion resistant metallization layer of gold, platinum, silver, platinum or palladium. However, the cost of each of these metals is prohibitively high. Therefore a more cost effective solution is needed.
    • SUMMARY OF THE DISCLOSURE
  • This disclosure provides a cost effective corrosion/oxidation resistant backside protective metal layer atop any layer of Copper and its alloys and any other previously applied backside metal layer that is susceptible to the problems described above. This will thereby provide a surface that is chemically and mechanically viable through subsequent processing steps, assembly, and throughout the life of the assembled part.
  • A reliable and manufacturable method for applying a corrosion and oxidation resistant metal layer atop previously applied backside metal layer(s) for thinned and full thickness semiconductor substrates has been invented. The deposition of this metal layer can be accomplished through sputtering, evaporation, immersion plating, electroless plating, or other deposition/coating techniques.
  • The method in accordance with this disclosure includes providing a semiconductor device such as a Wafer-Level Chip-Scale package (WLCSP) device that has at least an outer backside metal layer that is susceptible to corrosion or discoloration; and applying a protective metal layer to the outer backside metal layer wherein the protective metal is selected from the group consisting of Titanium, Titanium Alloys, Nickel, Nickel Alloys, Chromium, Chromium Alloys, Cobalt and Cobalt Alloys, Palladium and Palladium Alloys.
  • The device in accordance with this disclosure include a semiconductor wafer substrate having a backside and a conductive prior metallization layer on the backside, and a protective metal layer over the metallization layer wherein the protective metal is selected from the group consisting of Titanium, Titanium alloys, Nickel, Nickel alloys, Chromium, Chromium alloys, Cobalt, Cobalt alloys, Palladium and Palladium alloys.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present disclosure, reference is now made to the following figures:
  • FIG. 1 illustrates a cross-sectional view of a portion of a semiconductor wafer substrate with 1/0 bond pads. This view also shows the deposited backside metal layers.
  • FIG. 2 illustrates a closer cross-sectional view of the semiconductor wafer substrate and the backside metal layers.
  • FIG. 3 illustrates a backside view of the semiconductor substrate with backside metallization and with a laser marking.
  • FIG. 4 illustrates the cross-sectional view of a portion of an assembled WLCSP device with backside metallization attached to a corresponding board or other board side substrate.
  • The exemplification set out herein illustrates particular embodiments, and such exemplification is not intended to be construed as limiting in any manner,
    •  DETAILED DESCRIPTION
  • One embodiment of a method in accordance with this disclosure includes providing a semiconductor device such as a Wafer-Level Chip-Scale package (WLCSP) device that has at least an outer backside metal layer that is susceptible to corrosion or discoloration; and applying a protective metal layer of titanium to the outer backside metal layer. This titanium layer may be applied by any conventional means such as vapor deposition, sputtering, and chemical plating.
  • The corrosion/oxidation resistant metals for this invention include: titanium and its alloys, nickel and its alloys, chromium and its alloys, and cobalt and its alloys. This disclosure provides a means for the finished surface to remain uniformly colored throughout the life of the part, even in higher humidity conditions for both non-laser mark applications, as well as laser marked surfaces.
  • This method applies to any semiconductor substrate with previously applied backside metallization that can be corroded, oxidized, and/or discolored and includes but is not limited to: copper and its alloys, aluminum and its alloys, silver and its alloys, tungsten and its alloys, etc. The resulting corrosion/oxidation resistant metal layer can be deposited with a range between 10 Angstroms and 40,000 Angstroms.
  • In one particular embodiment of this invention the underlying metal layer is a copper plated metallization that is also subsequently processed through laser marking, which produces a laser marked backside plated copper layer, followed by the deposition of a corrosion/oxidation resistant titanium layer. The resulting backside metallization is uniformly colorized for clear legibility of the laser marking and it is highly resistant to corrosion or oxidation.
  • FIG. 1 shows a cross sectional view of an assembled WLCSP device substrate 100 that includes one or more backside metal layers 102. FIG. 2 is an enlarged view of the device substrate 100 in accordance with the present disclosure showing an adhesion metal layer 104 applied first to the wafer substrate 106, followed by a primary backside metal layer 108, and finally application of a protective corrosion resistant metal layer 110 in accordance with the present disclosure. This protective outer corrosion resistant metal layer 110 may be applied either before or after laser etching of an identification mark 112 as shown in FIG. 3.
  • FIG. 4 is a cross sectional view of a completely assembled device 200 in accordance with an embodiment of the present disclosure. The backside metal layers 202 comprise at least a primary layer 108 and an outer corrosion resistant layer 110 as described above with reference to FIG. 2.
  • This disclosure includes a new method of using a final backside metallization layer 110 that is corrosion/oxidation resistant atop previously deposited/coated metal layers.
  • This corrosion/oxidation resistant layer can be deposited through the means of sputtering, evaporation, immersion plating, electroless plating or other deposition/coating techniques.
  • Titanium and its alloys are an ideal metal for this final resistant backside metallization layer provided its adhesion to the previously deposited metallization layer is suitable for reliability.
  • Other corrosive/oxidation resistant metals such as nickel and its alloys, chromium and its alloys, cobalt and its alloys, Tungsten and its alloys, as well as Palladium and its alloys are also good candidates for forming this final deposited layer provided their adhesion to the previously deposited metallization layer is suitable for reliability. By using this final backside metallization layer, the backside surface of the semiconductor substrate will remain uniform in appearance through subsequent processing of the semiconductor substrate and throughout the life of the part.
  • This new method can be used in conjunction with or without laser marking, with the laser marking occurring either before or after the deposition of this final protective metallization layer. Preferably the method involves using a final backside metallization layer that is corrosion/oxidation resistant atop a previously deposited copper or one of its alloys as the prior metallization layers. In particular, the final metallization layer is comprised of titanium atop a previously electroplated copper or one of its alloys as the prior metallization layer.
  • One specific embodiment of this invention includes deposition of copper or one of its alloys as a first backside metallization, producing a laser marking on the first backside metallization layer, followed by deposition of an additional metallization layer of titanium atop the previously deposited copper backside metallization or one of its alloys. An alternate embodiment of this invention includes deposition of copper or one of its alloys as a first backside metallization, followed by deposition of an additional metallization layer of titanium atop a previously deposited copper or one of its alloys, and finally creation of a laser marking on the previously deposited layer. Preferably there is also a liquid etch step after the laser marking to remove any copper oxide before deposition of the corrosion resistant metallization layer of titanium. Furthermore, additional metallization layers may be applied beyond the two layers above specifically described. Preferably the corrosion/oxidation resistant layer can be deposited in a range between 10 Angstroms and 40,000 Angstroms.
  • Although it is known that backside metallization layers have incorporated gold, silver, platinum, palladium, and nickel as a final deposited layer in a stack of metals, the specific benefit of this new method is that it can be applied later, such as after multiple steps of sputtering/plating processes or sputter/plating/laser marking processes, etc. In addition, it can preferably be applied after the laser marking process.
  • Many variations will become apparent to a person of ordinary skill in the art from a reading of this disclosure. For example, additional metallization layers may be applied to the backside without departing from the scope of the present disclosure. All such modifications and variations are encompassed within the scope of the present disclosure. The examples cited here are to be regarded in an illustrative rather than a restrictive sense.

Claims (7)

1. A wafer level device comprising:
a semiconductor wafer substrate having a backside and a laser marked metal layer on the back side; and
a protective metal layer over the laser marked metal layer wherein the protective metal layer is comprised of a metal selected from the group consisting of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt and cobalt alloys, palladium and palladium alloys.
2. The device of claim 1 wherein the protective metal layer has a thickness between about 10 Angstroms and about 40,000 Angstroms.
3. The device of claim 1 wherein the protective metal layer is made of titanium.
4. The device of claim 1 wherein the primary metal layer is one of copper and a copper alloy.
5. The method of claim 1 wherein the backside of the semiconductor device wafer substrate consists of only a single metal layer comprising a single metal or metal alloy that is susceptible to corrosion and a single corrosion resistant metal layer comprising a single metal or metal alloy overlying the single backside metal layer.
6. A wafer level device comprising:
a semiconductor wafer substrate having a backside and a metal layer on the back side; and
a protective metal layer over the backside metal layer wherein the protective metal layer is comprised of a metal selected from the group consisting of chromium, chromium alloys, cobalt and cobalt alloys, palladium and palladium alloys.
7. The wafer level device of claim 6, further comprising an adhesion layer between the backside and the backside metal layer.
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CN111710613A (en) * 2020-06-18 2020-09-25 宁波芯健半导体有限公司 Wafer-level chip packaging method

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Publication number Priority date Publication date Assignee Title
CN104851850A (en) * 2014-02-14 2015-08-19 飞思卡尔半导体公司 Back side metallized figure of integrated circuit
JP6955931B2 (en) * 2017-08-22 2021-10-27 株式会社ディスコ Inspection wafer and energy distribution inspection method
US11935753B2 (en) 2021-12-09 2024-03-19 Nxp B.V Backside and sidewall metallization of semiconductor devices

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4793041A (en) * 1979-05-03 1988-12-27 Jerome D. Jenkins Transfer roll with ceramic-fluorocarbon coating containing cylindrical ink holes with round, beveled entrances
US4790922A (en) * 1987-07-13 1988-12-13 Viracon, Inc. Temperable low emissivity and reflective windows
TW552678B (en) 2001-05-29 2003-09-11 Sharp Kk Semiconductor apparatus and process for producing the same, and process for making via hole
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
US7230292B2 (en) * 2003-08-05 2007-06-12 Micron Technology, Inc. Stud electrode and process for making same
EP1893791A2 (en) 2005-06-22 2008-03-05 Henkel Kommanditgesellschaft Auf Aktien ELECTRODEPOSITION MATERIAL, PROCESS FOR PROVIDING A CORROSION-PROTECTIVE LAYER OF TiO2 ON AN ELECTRICALLY CONDUCTIVE SUBSTRATE AND METAL SUBSTRATE COATED WITH A LAYER OF TiO2
US20080166837A1 (en) * 2007-01-10 2008-07-10 Tao Feng Power MOSFET wafer level chip-scale package
US20080242003A1 (en) * 2007-03-26 2008-10-02 National Semiconductor Corporation Integrated circuit devices with integral heat sinks
WO2010075998A2 (en) 2008-12-29 2010-07-08 Hille & Müller GMBH Coated product for use in an electrochemical device and a method for producing such a product
US7842543B2 (en) * 2009-02-17 2010-11-30 Alpha And Omega Semiconductor Incorporated Wafer level chip scale package and method of laser marking the same
US8449995B2 (en) 2009-03-31 2013-05-28 Seagate Technology Llc Corrosion resistant coating for copper substrate
US20100276701A1 (en) * 2009-04-29 2010-11-04 Hebert Francois Low thermal resistance and robust chip-scale-package (csp), structure and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111710613A (en) * 2020-06-18 2020-09-25 宁波芯健半导体有限公司 Wafer-level chip packaging method

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