US20150170905A1 - Methods for device fabrication using pitch reduction and related devices - Google Patents
Methods for device fabrication using pitch reduction and related devices Download PDFInfo
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- US20150170905A1 US20150170905A1 US14/635,023 US201514635023A US2015170905A1 US 20150170905 A1 US20150170905 A1 US 20150170905A1 US 201514635023 A US201514635023 A US 201514635023A US 2015170905 A1 US2015170905 A1 US 2015170905A1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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Definitions
- Embodiments of the invention relate generally to integrated circuit device fabrication and, more particularly, to patterning techniques utilizing pitch reduction to fabricate a portion of the device, and associated structures.
- DRAM dynamic random access memories
- SRAM static random access memories
- FE ferroelectric
- DRAM may comprise thousands to billions of identical device components in the form of memory cells.
- pitch can be used to describe the sizes of these features.
- Pitch may be defined as the distance between identical points in two neighboring features. These features are typically defined by spaces between adjacent features, which spaces are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature.
- photolithography techniques each have a minimum achievable pitch, below which a particular photolithographic technique cannot reliably form features.
- the minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction.
- Pitch doubling” or “pitch multiplication” is one method for extending the capabilities of photolithographic techniques beyond their minimum pitch.
- One pitch multiplication method is illustrated in FIGS. 1A-1F hereof and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference.
- a pattern of lines 10 is photolithographically formed in a photo definable layer, such as a photoresist, which overlies a layer 20 of an expendable material, which in turn overlies a substrate 30 .
- a photo definable layer such as a photoresist
- the pattern is then transferred using an anisotropic etch to the layer 20 to form placeholders, or mandrels, 40 .
- the photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40 , as shown in FIG. 1C .
- a layer 50 of spacer material is subsequently deposited over the mandrels 40 , as shown in FIG. 1D .
- Spacers 60 i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels 40 .
- the spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown in FIG. 1E .
- the remaining mandrels 40 are then removed, leaving behind only the spacers 60 , which together act as a mask for patterning, as shown in FIG. 1F .
- the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers 60 .
- the smallest feature size possible with a photolithographic technique is effectively decreased.
- pitch doubling this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.”
- pitch “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor.
- the conventional terminology is retained herein.
- the layer 50 of spacer material typically has a single thickness 90 (see FIGS. 1D and 1E ) and because the sizes of the features formed by the spacers 60 usually correspond to that thickness 90 , pitch doubling typically produces features of only one width.
- Devices generally employ features of different sizes.
- random access memory devices typically contain arrays of memory cells located in one, more central region of the active surface of the devices and logic devices located in the outer, so-called “peripheral” regions. In the arrays, the memory cells are connected by conductive lines and, in the periphery, the conductive lines contact landing pads for connecting arrays to logic. Peripheral features such as landing pads, however, may be larger than the conductive lines.
- periphery electrical devices including peripheral transistors, may be larger than the electrical devices in the array.
- peripheral features can be formed with the same pitch as features in the array, because mask patterns formed by pitch multiplication may be limited to those that are formed along the sidewalls of patterned photoresist, pitch multiplication by itself typically does not offer the flexibility, e.g., geometric flexibility, required to define some features, particularly when features vary in size above and below the pitch resolution of the photolithographic technique used.
- some proposed methods for forming patterns at the periphery and in the array involve separately etching patterns into the array region and then peripheral region of a substrate.
- a pattern in the array region is first formed and transferred to the substrate or intermediate hard mask layer using one mask and then another pattern in the periphery region is formed and separately transferred to the substrate using another mask.
- such methods require forming the pattern in the array region first before forming the other pattern in the periphery region in order to thereafter transfer the patterns to the same level to be subsequently transferred to a substrate, such methods are limited in their ability to form equivalent or higher quality patterns suitable for forming the conductive lines of the array without additional masking and etching steps required for forming the pattern for the periphery features if the array pattern is to be adequately protected.
- defects may be caused, for example, by the photoresist material deposited between spacers so that features of a larger size may be formed in the periphery.
- the process conventionally used to form smaller, dimensionally critical, spacers in the pattern of the array while the other larger features in the pattern of the periphery are formed adds expense to the process flow without reducing defect potential in the array.
- a layer of material overlaid on the spacers while the features in the peripheral region are formed may leave residual material between adjacent spacers which may potentially cause defects or shorts therein which are subsequently transferred to one or more underlying layers.
- FIGS. 1A-1F show cross-sectional side views of a sequence of masking patterns for forming conductive lines in accordance with a conventional pitch doubling method.
- FIG. 2 shows a schematic top view of a partially formed semiconductor device, in accordance with embodiments of the invention.
- FIG. 3 shows a cross-sectional side view of a portion of the partially formed semiconductor device of FIG. 2 , in accordance with embodiments of the invention.
- FIG. 4 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after forming a pattern of features in a selectively definable layer in the periphery of the device in accordance with embodiments of the invention.
- FIG. 5 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after transferring the pattern of features into a first hard mask layer in accordance with embodiments of the invention.
- FIG. 6 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after stripping off the material of the selectively definable layer in accordance with embodiments of the invention.
- FIG. 7 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after layering on another selectively definable layer over the pattern of features and upon a second hard mask layer in accordance with embodiments of the invention.
- FIG. 8 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after forming a pattern of lines in the another selectively definable layer in the array of the device in accordance with embodiments of the invention.
- FIG. 9 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after widening spaces between lines in the another selectively definable layer in accordance with embodiments of the invention.
- FIG. 10 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after depositing a layer of spacer material over the patterns in accordance with embodiments of the invention.
- FIG. 11 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after etching the layer of spacer material in accordance with embodiments of the invention.
- FIG. 12 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after etching the layer of spacer material and stripping the lines of the another selectively definable layer in accordance with embodiments of the invention.
- FIG. 13 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after depositing a protective layer of material over the patterns in accordance with embodiments of the invention.
- FIG. 14 shows a top view of the portion of partially formed semiconductor device of FIG. 2 after forming a protective mask in the protective layer of material over the patterns in accordance with embodiments of the invention.
- FIG. 15A shows a top view of the portion of partially formed semiconductor device of FIG. 2 after forming a “loop chop” etch of a pattern exposed by the protective mask in accordance with embodiments of the invention.
- FIG. 15B shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after stripping the material of the protective mask and the lines from the device providing a modified pattern in accordance with embodiments of the invention.
- FIG. 16 shows a cross-sectional side view of the portion of partially formed semiconductor device of FIG. 2 after transferring the modified pattern to a primary hard mask layer ready for transferring into the substrate of the partially formed device.
- a method for semiconductor device fabrication by what may be termed “reverse pitch reduction flow” includes patterning a first pattern of features above a substrate and patterning a second pattern of pitch-multiplied spacers subsequent to patterning the first pattern of features.
- the first pattern of features may be formed using conventional lithography and the second pattern of pitch-multiplied spacers may be formed by a pitch multiplication technique.
- Embodiments of the invention also encompass structures associated with the methods disclosed.
- Embodiments of the invention may have particular utility in fabrication of NAND Flash devices, wherein the first pattern of features may comprise gates in a peripheral region of the device and the second pattern of features may comprise word lines in a central region thereof.
- Embodiments of the invention may also be employed in fabrication of DRAM memory, phase change memory and programmable gate array (PGA) devices.
- PGA programmable gate array
- a sequence of material layers is formed that allows formation of a mask for processing a substrate.
- FIG. 2 shows a top view of a portion of a partially formed integrated circuit device 100 .
- the embodiments of the invention may be used to form any device, they are particularly advantageously applied to form devices having arrays of electrical devices, including memory cell arrays for volatile and non-volatile memory devices such as DRAM, ROM, phase change, or Flash memory, including NAND Flash memory, or integrated devices having logic or gate arrays.
- the logic array may be a field programmable gate array (FPGA) having a core array similar to a memory array and a periphery with supporting logics.
- the array may be a fine pitch repetitive logic circuitry or embedded memory on a processor, as additional examples. Consequently, the integrated circuit device 100 may be, e.g., a memory chip or a processor, which may include both a logic array and embedded memory, or any other integrated device having a logic or a gate array.
- the integrated circuit device 100 includes a central region 102 , which may be termed the “array,” at least partially bounded by a peripheral region 104 , which may be termed the “periphery.”
- the array 102 will typically be densely populated with conducting lines and electrical devices such as transistors and capacitors.
- the electrical devices form a plurality of memory cells, which are conventionally arranged in a regular grid pattern at the intersections of word lines and bit lines. Desirably, pitch multiplication may be used to form features in the array 102 , as discussed below.
- the periphery 104 typically comprises features larger than those in the array 102 .
- FIG. 3 shows a cross-sectional side view of the partially formed integrated circuit device 100 .
- Various layers 120 - 150 are provided for masking above a substrate 110 comprising a layer of semiconductor material.
- the substrate 110 may comprise a conventional polysilicon/WSi x /oxide gate stack or metal gate stack array.
- the layers 120 - 150 will be etched to form a mask for patterning the substrate 110 , as discussed below.
- the materials for the layers 120 - 150 overlying the substrate 110 are selectively chosen based upon consideration of the chemistry and process conditions for the pattern forming and pattern transferring steps discussed herein. Because the layers 120 - 150 between a topmost selectively definable layer 150 and the substrate 110 function to transfer a pattern derived from the selectively definable layer 150 to the substrate 110 , the layers 120 - 140 between the selectively definable layer 150 and the substrate 110 are chosen so that they may be selectively etched relative to other exposed materials.
- a material is considered selectively, or preferentially, etched when the etch rate for that material upon exposure to a given etchant is substantially greater, on the order of at least about 2-3 times greater to at least about 40 times greater than the etch rate for adjacent materials exposed to the same etchant. Because a function of the layers 130 - 150 overlying the primary hard mask layer 120 is to allow well-defined patterns to be formed in layer 120 , it will be appreciated that one or more of the layers 130 - 150 may be omitted or substituted if suitable other materials, chemistries and/or process conditions are used.
- the selectively definable layer 150 which may comprise an optically or mechanically patternable layer overlies a hard mask, or etch stop, layer 140 , which overlies a hard mask layer 130 , which overlies the mask layer 120 , which overlies the substrate 110 to be processed (e.g., etched) through a mask.
- the mask through which the substrate 110 is processed is formed in the hard mask layer 130 and/or in the mask layer 120 .
- the selectively definable layer 150 is photodefinable, e.g., formed of a photoresist, including any photoresist known in the art.
- the photoresist may be any photoresist compatible with 157 nm, 193 nm, 248 nm or 365 nm wavelength systems, 193 nm wavelength immersion systems, extreme ultraviolet systems (including 13.7 nm wavelength systems) or electron beam lithographic systems.
- maskless lithography, or maskless photolithography may be used to define the selectively definable layer 150 .
- photoresist materials include argon fluoride (ArF) sensitive photoresist, i.e., photoresist suitable for use with an ArF light source, and krypton fluoride (KrF) sensitive photoresist, i.e., photoresist suitable for use with a KrF light source.
- ArF photoresists are typically used with photolithography systems utilizing relatively short wavelength light, e.g., 193 nm.
- KrF photoresists are used with longer wavelength photolithography systems, such as 248 nm systems.
- the layer 120 and any subsequent resist layers may be formed of a resist that may be patterned by nano-imprint lithography, e.g., by using a mold or mechanical force to pattern the resist.
- the selectively definable layer 150 will allow a first feature having a first size to be formed in the periphery 104 . It will be appreciated that light reflections may decrease the precision with which photolithography may define the edges of a pattern.
- a bottom anti-reflective coating (BARC) (not shown) may similarly be used in addition to the first hard mask layer 140 to control light reflections.
- the material for the hard mask layer 130 which functions as an etch stop and exhibits anti-reflective properties, comprises an inorganic material.
- Suitable materials for hard mask layer 130 include silicon oxide (SiO 2 ) or a deep ultra-violet (DUV) dielectric anti-reflective coating (DARC), such as a silicon-rich silicon oxynitride.
- the hard mask layer 130 is a dielectric anti-reflective coating (DARC).
- DARC dielectric anti-reflective coating
- Using a DARC for the hard mask layer 130 may be particularly advantageous for forming patterns having pitches near the resolution limits of a particular photolithographic technique.
- the DARC may enhance resolution by minimizing light reflections, thus increasing the precision with which photolithography may define the edges of a pattern.
- the DARC layer may comprise a DUV DARC of about 200-400 ⁇ (20-40 nm) thickness.
- Other suitable materials that exhibit adequate etch stop and anti-reflective properties may be used for the hard mask layer 130 .
- the hard mask or etch stop layer 140 is formed of silicon, e.g., poly amorphous silicon, or a film of another material that exhibits good etch selectivity to oxide.
- suitable materials for the first hard mask layer 140 may include a silicon oxide, e.g., a low silane oxide (LSO), low temperature nitride, and a thin layer of aluminum oxide, such as Al 2 O 3 .
- LSO low silane oxide
- the LSO is formed by chemical vapor deposition using a relatively low silane flow and a relatively high N 2 O precursor flow.
- such a deposition can be performed at relatively low temperatures, e.g., less than about 550° C., for example, less than about 400° C., to prevent damage to the underlying primary mask layer 120 , when the layer 120 is formed of a temperature-sensitive material.
- oxides may typically be etched with greater selectivity relative to silicon than nitrides.
- conventional etch chemistries for oxides may remove the oxides at a rate more than 10 times faster than amorphous silicon
- conventional etch chemistries for nitrides typically only remove the nitrides at a rate of about three times faster than poly amorphous silicon.
- both the spacers (discussed below) and the second hard mask layer are preferably formed of the same material, in the form of an oxide, when the first hard mask layer is formed of poly amorphous silicon.
- the mask layer 120 may be formed of amorphous carbon due to the excellent etch selectivity of this material relative to many other materials, including a very high etch selectivity relative to the hard mask materials.
- the transparent carbon is a form of amorphous carbon that is highly transparent to light and that offers further improvements for photo alignment by being transparent to the wavelengths of light used for such alignment. Deposition techniques for forming such transparent carbon are known to those of ordinary skill in the art and, so, need not be further described.
- the amorphous carbon is particularly advantageous for transferring patterns to difficult-to-etch substrates, such as the substrate 110 comprising multiple materials or multiple layers of materials, or for forming small and high aspect ratio features therein.
- the combination of materials for the hard mask layers 130 and 140 are selectably chosen based upon the material used to form a first feature in the periphery 104 in combination with providing the material used to form the spacers in the array 102 allowing transfer of the pattern or mask formed by the layers, as discussed below, into the underlying mask layer 120 .
- the mask layer 120 of the current embodiment is formed of amorphous carbon and layer 150 is formed of photoresist.
- oxide/amorphous silicon/oxide oxide/amorphous silicon/oxide; nitride/amorphous silicon/oxide; nitride/oxide/amorphous silicon; amorphous silicon/oxide/amorphous silicon; carbon/amorphous silicon/oxide; and carbon/oxide/amorphous silicon.
- oxide may be a form of silicon oxide and the nitride may be silicon nitride.
- the associated hard mask layer 120 is a material that is preferentially etchable relative to the oxide.
- the hard mask layer 120 may be formed of a silicon-containing material.
- examples of other materials include amorphous carbon and etchable high dielectric materials.
- the thicknesses of the layers 120 - 150 are selectively chosen depending upon compatibility with the etch chemistries and process conditions described herein. As discussed above, when transferring a pattern from an overlying layer to an underlying layer by selectively etching the underlying layer, materials from both layers are removed to some degree. Thus, the upper layer is sufficiently thick so that it is not removed over the course of the pattern transfer to the underlying layer but no so thick as to create an undesirable topography.
- the selectively definable layer 150 is about 2000 angstroms (“ ⁇ ”) (200 nm) in thickness and, in other embodiments, may range in thickness from 500-3000 ⁇ (50-300 nm). It is also recognized that the thickness of the selectively definable layer 150 may be to a greater or lesser extent than the 2000 ⁇ illustrated. It will be appreciated that, in cases where the layer 150 is a photoresist, the thickness of the layer 150 may vary depending upon the wavelength of light used to pattern the layer 120 . A thickness of about 500-3000 ⁇ (50-300 nm) thick and, more specifically, a thickness of about 2000-2500 ⁇ (200-250 nm), is particularly advantageous for 248 nm wavelength systems.
- the hard mask layer 140 has a thickness of about 150-200 ⁇ (20 nm) and, in other embodiments, may range in thickness to a greater or lesser extent than the 200 ⁇ illustrated. One particularly suitable thickness is 100 ⁇ .
- the hard mask layer 140 may have a thickness ranging from about 100 ⁇ (10 nm) to about 400 ⁇ (40 nm).
- the hard mask layer 130 is about 200-600 ⁇ (20-60 nm) thick and, in other embodiments, may range in thickness to a greater or lesser extent.
- the layer 130 may have a thickness of about 300-500 ⁇ (30-50 nm).
- the thickness of the mask layer 120 is chosen based upon the selectivity of the etch chemistry for etching the substrate and based upon the materials and complexity of the substrate.
- a thickness for mask layer 120 of about 3000 ⁇ (300 nm) and, in other embodiments a thickness between 1000-5000 ⁇ (100-500 nm) is particularly effective for transferring patterns to a variety of substrates, including substrates having a plurality of different materials to be etched during the transfer.
- the illustrated substrate 110 comprising a plurality of layers (not shown) may be etched to form word lines over an array of gate stacks.
- the layers of the substrate 110 may include a tungsten silicide layer overlying a polysilicon layer, which overlies an oxide-nitride-oxide (ONO) composite layer, which overlies a polysilicon layer, the layers in combination and as previously processed comprising an array of gate stacks.
- ONO oxide-nitride-oxide
- the various layers discussed herein may be formed by various conventional methods. For example, spin-on-coating processes may be used to form photoresist, selectively definable layers. Various vapor deposition processes, such as chemical vapor deposition, may be used to form hard mask layers. Depositing each layer of materials may include depositing a material by coating, layering, or spinning, for example.
- a low temperature chemical vapor deposition (CVD) process may be used to deposit the hard mask layers or any other materials, e.g., spacer material described herein, over the mask layer 120 , especially in cases where the mask layer 120 is formed of amorphous carbon.
- CVD chemical vapor deposition
- the hard mask layers 140 and 130 may be deposited at relatively low temperatures of less than about 550° C., lower than about 450° C., and even lower than about 400° C.
- Such low temperature deposition processes advantageously prevent chemical or physical disruption of a mask layer 120 made of amorphous carbon material.
- Various methods for forming these layers are known to those of ordinary skill in the art and are described in U.S. Pat. No. 7,115,525, U.S. Pat. No. 6,573,030, and U.S. Pat. Pub. No. 2006/0211260, the entire disclosures of each of which documents are incorporated herein by reference.
- a first pattern of features is formed according to an embodiment of the invention.
- a second pattern of spacers may be formed by pitch multiplication, followed by subjecting the patterns to a so-called “loop chop” process to eliminate closed loops formed in the mask.
- the pattern of features and the pattern of spacers at this point are consolidated for transferring into the substrate.
- the quality of the final structure formed within the substrate is improved by forming of the first pattern of features before forming the second pattern of spacers during a masking process.
- this process flow enables quality improvement in the second pattern of spacers by first subjecting the less dimensionally sensitive structures of the first pattern to the forming process.
- a first pattern of features is formed principally in the periphery of the device.
- Each feature of the first pattern includes, particularly at minimum or larger critical dimensions that are directly formable in the photodefinable material of the selectively definable layer, and do not require a pitch reduction or multiplication technique as is required to obtain smaller critical dimensions of the spacers of the second pattern, as will be discussed below.
- a first pattern 106 of features 105 is formed in the selectively definable layer 150 .
- the selectively definable layer 150 may be patterned by, e.g., photolithography, in which the layer 150 is exposed to radiation through a reticle and then developed. After being developed, the remaining photodefinable material, photoresist in this embodiment, comprises features 105 (only one feature shown for clarity).
- Each feature 105 of the first pattern 106 may form various landing pads, transistors and local interconnects, for example and without limitation, and generally may have a size larger than the smaller critical dimensions obtained with the spacers of the second pattern, as discussed below.
- the hard mask layer 140 is etched to transfer the first pattern 106 formed in layer 150 down to the hard mask layer 140 as shown in FIG. 5 .
- the hard mask layer 140 formed of amorphous silicon, is anisotropically etched using, for example, an HBr and Cl 2 -containing plasma, and stopping the etch at the hard mask layer 130 . This so called “dry” etch of the HBr and Cl 2 -containing plasma etches the amorphous silicon at a rate greater than about five times, and even as great as ten times, the rate at which the photoresist material of the features 105 may be etched.
- etching hard mask layer 140 may consume some of the DARC material of the hard mask layer 130 , for example, between 20-30 A (4-5 nm), which may leave the surface of layer 130 slightly nonuniform in topography.
- the uniformity of the hard mask layer 130 is addressed below when forming the second pattern of spacers.
- HBr and Cl 2 chemistry-based etchants exhibit good selectivity to oxide.
- Other suitable etchants may include C 2 F 6 /Cl 2 /O 2 , SF 6 , and CF 4 for example and without limitation.
- the first pattern 106 is cleaned while stripping the selectively definable layer 150 .
- the carbon material fanning the photoresist layer 150 and DARC hard mask layer 130 may polymerize upon contact with etchants.
- the HBr/Cl 2 etch of the hard mask layer 140 may cause parts of the layers 150 and 130 to polymerize and leave a residue around features 105 in the hard mask layer 140 , causing a pattern having undesirably non-uniform features.
- the first pattern 106 is cleaned by stripping off organic material.
- the strip may be accomplished using, for example, an isotropic etch with O 2 plasma or other etch processes recognized as suitable by a person of ordinary skill in the art for preserving the features 105 in the hard mask layer 140 .
- a second pattern of spacers is formed by pitch multiplication over the first pattern 106 of features 105 .
- the second pattern comprises spacers having smaller critical dimensions than the first pattern 106 of features 105 as formed.
- the second pattern may be formed completely, partially, or not overlapping the first pattern 106 .
- a selectively definable layer 160 is formed on, and overlies, the hard mask layer 130 and first pattern 106 of features now formed in the first hard mask layer 140 to allow for patterning of the second pattern in the array 102 .
- the selectively definable layer 160 may be photodefinable, e.g., formed of a photoresist, including any suitable photoresist known in the art, such as a trimmable mandrel material.
- the selectively definable layer 160 may be formed of a resist suitable for patterning by nano-imprint lithography.
- a planar surface may be formed prior to depositing the layer 160 by depositing a planarizing material (not shown) around the features 105 and upon the second hard mask layer 130 when required for improving the planarity of structure of the to-be-patterned array for forming spacers.
- the planarizing layer may be employed where the resolution of the spacers to be formed in the second pattern may not be adequately defined without first providing a planarized surface.
- a spin-on antireflective coating may be used for planarization purposes.
- the selectively definable layer 160 is patterned using, e.g., the same photolithographic technique used to pattern the selectively definable layer 150 .
- a second pattern 108 is formed in the selectively definable layer 160 .
- the area in the selectively definable layer 160 in the periphery 104 is preferably open, as illustrated.
- the second pattern 108 may partially or completely overlap the first pattern 106 or be completely separated from the first pattern 106 .
- the use of different reference numerals ( 106 and 108 ) for these respective patterns indicates that they were originally formed in different acts.
- the process flow as described below results in the second pattern 108 that includes a pitch or feature size smaller than the minimum pitch or resolution of the photolithographic technique used in forming it, unlike the first pattern 106 that includes pitch or feature size equal to or greater than the minimum pitch or resolution of the photolithographic technique used to form the first pattern 106 .
- the second pattern 108 in the array 102 may be used to form arrays of conductive feeds, contacts and other semiconductor components when transferred into the substrate 110 , for example and without limitation.
- the second pattern 108 includes spaces or trenches 162 , which are delimited by photodefinable material features, or lines, 164 formed in the photodefinable layer 160 .
- the trenches 162 may be formed by, for example, photolithography with 248 nm or 193 nm wavelengths light, in which the layer 160 is exposed to radiation through a reticle and then developed as is known by a person of ordinary skill in the art. After being developed, the remaining photodefinable material, photoresist in the illustrated embodiment, forms mask features such as the array of lines 164 (shown in cross-section only) as illustrated.
- the resulting pitch of the lines 164 is equal to the sum of the width of a line 164 and the width of a neighboring space 162 .
- the pitch may be at or near the limits of the photolithographic technique used to pattern the photodefinable layer 160 .
- the pitch of the lines 164 can be about 1000 ⁇ (100 nm).
- the pitch may be at the minimum pitch of the photolithographic technique and the spacer formed in the pattern as discussed below may advantageously have a pitch below the minimum pitch of the photolithographic technique.
- the spaces 162 may be widened by etching the photoresist material of the lines 164 , to form modified spaces 162 a and lines 164 a.
- the photoresist lines 164 are etched using an isotropic etch to “shrink” those features. Suitable etches include etches using an oxygen-containing plasma, e.g., a SO 2 /O 2 /N 2 /Ar plasma, a Cl 2 /O 2 /He plasma or an HBr/O 2 /N 2 plasma.
- the extent of the etch is selected so that the widths of the lines 164 a are substantially equal to the desired spacing between the later-formed spacers ( 172 in FIG.
- the width of the lines 164 may be reduced to 800-1200 ⁇ (80-120 nm) or even further reduced to about 400-700 ⁇ (40-70 nm).
- the width-reducing etch allows the lines 164 a to be narrower than would otherwise be possible using the photolithographic technique used to pattern the selectively definable layer 160 .
- the etch may smooth the edges by removing material of the resist lines 164 a, thus improving the line edge roughness uniformity of those lines.
- a layer 170 of spacer material is preferably blanket deposited conformally over exposed surfaces, including the hard mask layer 130 and the top and sidewalls of the patterned, modified definable layer 160 a.
- the spacer material may be any material that can act as a mask for transferring a pattern to the underlying hard mask layer 130 .
- the spacer material is selected for deposition with good step coverage, at a temperature compatible with the modified definable layer 160 a, and suitability for etching relative to the modified definable layer 160 a and the underlying hard mask layer 130 .
- Materials for the layer 170 may include silicon, silicon oxides and silicon nitrides.
- the spacer material is a silicon oxide deposited at a relatively low temperature, such as 75° C., which provides particular advantages in combination with other selected materials of the masking stack.
- Methods for depositing the material of the spacer layer 170 may include chemical vapor deposition, e.g., using O 3 and TEOS to form silicon oxide, and atomic layer deposition, e.g., using a silicon precursor with an oxygen or nitrogen precursor to form silicon oxides and nitrides, respectively.
- the thickness of the spacer layer 170 is preferentially determined based upon the desired width of the spacers 172 ( FIG. 11 ). For example, in this embodiment, the layer 170 is deposited to a thickness of about 200-800 ⁇ (20-80 nm). In other embodiments, the layer 170 may be deposited to a thickness ranging between 400-600 ⁇ (40-60 nm).
- the layer may range between about 100-300 ⁇ (10-30 nm) or to a greater or lesser extent than illustrated.
- the spacer layer 170 formed over the first pattern 106 of features 105 in the periphery 104 of the device 100 may see uneven steps ranging about 250 ⁇ (25 nm) in size, which will be stripped away when forming the spacers 172 as shown in FIG. 11 without substantial alteration of the features 105 as formed.
- the spacers 172 are now formed in the second pattern 108 by exposing the silicon oxide material of the spacer layer 170 to an anisotropic etch to remove spacer material from horizontal surfaces 180 of the partially formed device 100 while stopping on the surface of the first hard mask layer 140 and the second hard mask layer 130 .
- an etch also known as “spacer etch,” may be performed using a fluorocarbon plasma containing, for example and without limitation, CF 4 /CHF 3 , C 4 F 8 /CH 2 F 2 or CHF 3 /Ar plasma.
- the material of the modified definable layer 160 a may be selectively retained between adjacent spacers 172 while further processing to remove portions of the spacer material is performed in accordance with embodiments of the invention as described below.
- retaining the material used to form the lines 164 a of the modified definable layer 160 a between adjacent spacers 172 enhances the quality of a portion of the spacers 172 by not subjecting the material to extra processing or cleaning steps that may undesirably erode or otherwise damage or displace the spacers prior to their ultimate pattern transfer to the underlying substrate 110 .
- the modified definable layer 160 a may be removed to leave the spacers 172 in freestanding alignment.
- the modified definable layer 160 a may be selectively removed using an organic strip process as described above.
- Optional etch chemistries may include an oxygen-containing plasma etch, such as etching using an O 2 plasma strip.
- the pitch of the spacers 172 is roughly half that of the photoresist lines 164 and spaces 162 ( FIG. 8 ) originally formed by photolithography. Where the photoresist lines 164 had a pitch of about 2000 ⁇ (200 nm), spacers 172 having a pitch of about 1000 ⁇ (100 nm) or less may be formed.
- the spacers 172 are formed on opposing sidewalls of each of the features or lines 164 a, the spacers 172 generally follow the outline of the pattern of features or lines 164 a in the modified photodefinable layer 160 a and, so, form a closed loop around the ends of the lines 164 a.
- the spacers 172 form relatively smaller features of the second pattern 108 that may be transferred to the underlying substrate 110 together with the relatively larger features 105 forming the first pattern 106 .
- the first pattern 106 and the second pattern 108 may now be subjected to so-called “loop chop” process to eliminate undesirable closed loops or other portions of pattern material before transferring the mask to the substrate 110 .
- a second pattern of spacers may be formed after the first pattern of features is formed by utilizing other methods of pitch multiplication.
- Other methods of pitch multiplication may require layering different or select layers of material above the substrate in addition to the layers mentioned herein.
- a method of forming a pattern of spacers by pitch multiplication is described in paragraphs [0056]-[0092] and FIGS. 2A-10 of U.S. Pub. No. 2006/0046422 to Tran et al., dated Mar. 2, 2006, the entire disclosure of which is incorporated by reference herein.
- spacer material in the form of loops of spacer material connecting adjacent spacers 172 is etched to remove the loops and isolate the spacers 172 .
- This etch may be used to form two separate lines of spacers 172 initially connected at their adjacent ends by a loop of spacer material extending around the end of a line 164 a corresponding to two separate conductive paths to be formed in the substrate 110 . It will be appreciated that more than two lines may be formed, if desired, by etching the spacers 172 at more than two locations.
- Other suitable method for cutting off the ends of the loops is disclosed in U.S. Pub. No. 2006/0046422 to Tran et al., dated Mar. 2, 2006, the entire disclosure of which is incorporated by reference herein.
- a protective mask is formed over parts of the lines to be retained and the exposed, unprotected part of the loop of spacer material connecting the spacer lines are then etched. The protective mask is then removed to leave a plurality of physically separated and electrically isolated lines comprised of spacers 172 .
- a protective material forming a protective layer 181 is selectively deposited around and over the spacers 172 and the parts of the layers 130 and 160 forming the pattern 108 , and, in this embodiment, is selectively deposited around and over the features 105 forming the pattern 106 .
- the material of the protective layer 181 may be a photodefinable material such as photoresist as described above and is sufficiently thick to protect the underlying mask during the etch.
- an anti-reflective coating (“ARC”) (not shown) may be provided under the protective layer 181 , e.g., above the patterns 106 and 108 , to improve photolithography results as understood by a person of ordinary skill in the art.
- the photoresist and the optional anti-reflective coating may be deposited using various methods known in the art, including spin-on-coating processes.
- a protective mask 182 is subsequently patterned in the protective layer 181 , e.g., by photolithography, to protect desired portions of the underlying patterns 106 and 108 from a subsequent etch. It is recognized that the pattern 106 forming the features 105 may be entirely, partially or not covered depending upon the relative resistance to etching during the etch.
- portions of the loops are exposed for etching in at least two separate locations. To simplify processing, the exposed portions of the loops are generally the ends of the loops formed by the spacers 172 , as illustrated.
- the protective layer 181 may be formed of any material that may be selectively removed, e.g., relative to the spacers 172 , the layers 130 , 140 , 160 a, and 170 .
- the protective mask 182 may be formed in another material, e.g., photoresist, overlying the protective layer 181 .
- the length and simple geometry of the straight lines may minimize the precision required for forming the protective mask 182 ; that is, the protective mask need only be formed so that it leaves the ends of the spacers 172 exposed.
- a misaligned mask may cause slightly more or less of the spacers 172 to be exposed, but may still accomplish the objective of leaving the ends adequately exposed.
- the margin of error for aligning the protective mask 182 is larger than if the protective mask 182 were required to form a geometrically complex shape, it is recognized that other shapes may be formed in the protective mask 182 different from the rectangular shape of the protective mask 182 as illustrated. See, for example, U.S. Pub. No. 2006/0046422 to Tran et al., the disclosure of which is incorporated herein in its entirety by reference.
- the exposed portions of the spacers 172 are etched away leaving the exposed portions of the photoresist lines 164 a and the features 105 of pattern 106 .
- suitable etch chemistries may include a fluorocarbon etch or in the case of spacers 172 formed of an oxide, such as silicon oxide, the exposed loops of the spacers 172 may be isotropically etched using a wet chemistry, for example, a buffered oxide etch.
- a suitable etchant for a silicon dioxide spacer material is an HF/H 2 O wet etch at a 500:1 dilution ratio.
- FIG. 15B shows a side view of the resulting structure, taken along the vertical plane as indicated in FIG. 15A with the material of the lines 164 a removed.
- the exposed portions of the photoresist lines 164 a may be descummed or etched away in order to facilitate etching the exposed portions of the spacers 172 .
- an O 2 /N 2 reactive ion etch, an O 2 etch, or a CF 4 and/or CHF 3 plasma etch may be employed.
- the exposed surface of the partially fabricated device 100 i.e., the portion not protected by the protective mask 182 , may be cleaned prior to the etching the exposed portions of the spacers 172 .
- the materials of the protective mask 182 and of the lines 164 a are selectively removed.
- etch chemistries include anisotropic etches, such as with an SO 2 -containing plasma.
- the mask of the partially formed device 100 may be subjected to an ashing process to remove the material of layers 181 and 160 where the material of the modified pattern 109 is compatible with the ashing process. It will be appreciated that the spacers 172 and the features 105 are not attacked during this removal act and that the primary hard mask layer 120 is protected by the second hard mask layer 130 .
- the inner portions of the spacers 172 are subjected to less processing than would be if the material of the lines 164 a was removed prior to the “loop chop” process, beneficially enhancing resolution and reducing variations and defects when the pattern 109 is transferred to the underlying substrate 110 .
- the modified pattern 109 comprising the spacers 172 and the features 105 of the patterns 108 and 106 , respectively, may be simultaneously transferred to the substrate 110 .
- the second hard mask layer 130 and primary hard mask layer 120 are etched to transfer the modified pattern 109 down to the mask layer 120 , to form a pattern of components of mixed feature size in the mask layer 120 .
- the modified pattern 109 is cleaned.
- the carbon material forming the layers 130 and 181 may polymerize upon contact with etchants, leaving a residue around features or spacers on the hard mask layer 130 , causing a modified pattern 109 having undesirably non-uniform feature sizes.
- the modified pattern 109 is cleaned by stripping off an organic material.
- the cleaning may be accomplished using, e.g., an isotropic etch with O 2 plasma and may be done simultaneously while stripping of the protective mask 182 .
- the modified pattern 109 is transferred to the mask layer 120 .
- the transfer is accomplished by anisotropically etching the second hard mask layer 130 and the primary mask layer 120 , using an SO 2 -containing plasma.
- suitable etch chemistries include a Cl 2 /O 2 , HBr/O 2 /N 2 or SiCl 4 /O 2 N 2 /HBr or SiCl 4 /O 2 -containing plasma.
- the SO 2 -containing plasma is particularly suitable as it has been found to have excellent selectivity for the amorphous carbon of the mask layer 120 and the DARC of the hard mask layer 130 relative to the material of the spacers 172 and the features 105 .
- a thick enough mask may be formed in the primary mask layer 120 to later effectively transfer the mask pattern to the substrate 110 , particularly through multiple materials of the substrate using selective etch chemistries and without wearing away the mask layer 120 before the pattern transfer is complete.
- the pattern 109 is transferred to the substrate 110 using the patterned mask layer 120 as a mask.
- the pattern transfer can be readily accomplished using conventional etch chemistries appropriate for etching the material or materials of the substrate 110 to form the final structures therein.
- the process used to transfer the modified pattern 109 from the mask layer 120 and into the substrate 110 may include any suitable process known to a person of ordinary skill in the art.
- the spacers 172 and the features 105 of the modified pattern 109 may be employed to respectively form interconnect lines such as word lines and associated integrated device features, such as landing pads as transferred into the substrate.
- Methods for forming interconnects and landing pads are disclosed in U.S. Pub. No. 2006/0046422 to Tran et al., dated Mar. 2, 2006, the entire disclosure of which was previously incorporated herein by reference.
- Other methods for forming interconnects and landing pad are disclosed in U.S. Pat. No. 7,115,525 to Abatchev et al., dated Oct. 3, 2006, and U.S. Pub. No. 2006/0211260 to Tran et al., dated Sep. 21, 2006, the entire disclosures of which are incorporated herein by reference.
- the pitch of the pattern 108 may be more than doubled as is shown in the drawing figures herein, particularly before the modified pattern 109 is transferred to the substrate.
- the pattern 108 may be further pitch multiplied by forming spacers around the spacers 172 , then removing the spacers 172 , then forming spacers around the spacers that were formerly around the spacers 172 , and so on.
- a method for further pitch multiplication is discussed in U.S. Pat. No. 5,328,810 to Lowrey et al., the entire disclosure of which is incorporated herein by reference.
- embodiments of the invention may advantageously be applied to form a modified pattern 109 having both pitch multiplied and conventionally photolithographically defined features, the patterns 106 and 108 may both be pitch multiplied or may have different degrees of pitch multiplication.
- the embodiments of the invention may be employed multiple times throughout an integrated device fabrication process to form pitch multiplied features and conventional features in a plurality of layers or vertical levels, which may be vertically contiguous or non-contiguous and vertically separated.
- each of the individual levels to be patterned would constitute a substrate 110 and the various layers 120 - 181 may be formed over the individual level to be patterned.
- the particular composition and height of the various layers 120 - 181 discussed above may be varied depending upon a particular application.
- the layer 120 may be sufficiently thin in order to provide structural stability to the mask, to protect the substrate material throughout fabrication, and to allow the mask to be transferred into the substrate 110 without complete removal of the material of layer 120 before the final etch is finished.
- the thickness of the layer 120 may be varied depending upon the identity of the substrate 110 , e.g., the chemical composition of the substrate, whether the substrate comprises single or multiple layers of material, the depth of features to be formed, for example, and the available etch chemistries, without limitation.
- one or more layers of layers 120 - 181 may be omitted or more layers may be added.
- the layer 120 may be omitted in cases where the hard mask layer 130 is sufficiently durable to adequately transfer a modified pattern 109 to the substrate 110 .
- processing through the mask layers may involve subjecting layers underlying the mask layers to any semiconductor fabrication process.
- processing may involve ion implantation, diffusion doping, depositing, or wet etching, without limitation, through the mask layers and onto underlying layers.
- the mask layers may be used as a stop or barrier for chemical mechanical polishing (CMP) or CMP may be performed on any of the layers to allow for both planarization and etching of the underlying layers, as disclosed in U.S. Provisional Patent Application No. 60/666,031, filed Mar. 28, 2005, the entire disclosure of which is incorporated by reference herein.
- the “substrate” to which patterns are transferred may include a layer of a single material, a plurality of layers of different materials, a layer or layers having regions of different materials or structures in them, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof.
- the substrate may comprise doped polysilicon, an electrical device active area, a silicide, or a metal layer, such as a tungsten, aluminum or copper layer, or combinations thereof.
- the mask features discussed herein may directly correspond to the desired placement of conductive features, such as interconnects, in the substrate.
- the substrate may be an insulator and the location of mask features may correspond to the desired location of insulators, such as in damascene metallization. Examples of structures formed in the substrate include gate stacks and shallow trench isolation structures.
- transferring a pattern from an overlying level to an underlying level involves forming features or spacers in the underlying level that generally correspond to features or spacers in the overlying level.
- the path of lines in the underlying level will generally follow the path of lines in the overlying level and the location of other features in the underlying level will correspond to the location of similar features or spacers in the overlying level.
- the precise shapes and sizes of features and spacers may vary from the overlying level to the underlying level, however.
- the sizes of and relative spacing between the features and spacers forming the transferred patterns may be enlarged or diminished relative to the pattern on the overlying level, while still resembling the same initial “pattern,” as are seen from the example of shrinking the lines in the embodiments described above.
- the transferred pattern, or patterns is still considered to be the same pattern, or patterns, as the initial pattern.
- forming spacers around mask features, e.g., the lines may change the pattern.
- Embodiments of the invention provide reverse pitch reduction flow enabling improved pattern transfer and the formation of differently sized features in conjunction with the use of pitch multiplication.
- a sequence of layers of materials is formed that allow formation of a mask for processing a substrate to fabricate, for example, a memory chip or other integrated circuit device incorporating at least two regions on the active surface thereof having structural elements of substantially differing feature size.
- a first pattern of features is formed where conventional photolithography may be used to form the first pattern defining features in the mask, the features being generally formed in one region of the device, e.g., the peripheral region of the memory chip.
- a second pattern of spacers is formed using pitch multiplication.
- the second pattern of spacers form an element array in another region of the device, e.g., the memory array of the memory chip, advantageously eliminating acts conventionally required to form the spacers when subsequent features of various sizes are required to be formed therewith.
- the quality of the pattern of spacers may be improved and enhanced for subsequent transfer to the underlying substrate while potentially eliminating additional layering, cleaning, and etching acts otherwise conventionally required in order to form a device having respective features of diverse dimensions in the region of the memory array and in the peripheral region.
- the second pattern may completely or partially overlap the first pattern, or, in some embodiments, may be completely formed in different regions of the device, e.g., the periphery of the memory chip.
- the first pattern and the second pattern may be selectively covered by a protective mask and subjected to a so-called “loop chop” process to eliminate undesirable closed loops in order to obtain a modified pattern for transfer to the substrate.
- a “loop chop” may be omitted during fabrication for a particular polarity of a level, thus saving an additional masking step.
- Embodiments of the invention facilitate combining the patterns forming the differently sized spacers and features and successfully transferring the spacer and feature sizes and configurations to the underlying substrate while subjecting the spacers, with their size below the minimum pitch of the photolithographic technique used for patterning them, to fewer process acts which might compromise the quality of the transfer.
- the pattern of pitch-multiplied resolution spacers may be configured as an array.
Abstract
Description
- This application is a divisional of U.S. patent application Ser. No. 11/830,449, filed Jul. 30, 2007, pending, the disclosure of which is hereby incorporated herein in its entirety by this reference.
- Embodiments of the invention relate generally to integrated circuit device fabrication and, more particularly, to patterning techniques utilizing pitch reduction to fabricate a portion of the device, and associated structures.
- As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, electronic devices such as integrated devices, are continuously being reduced in size. The sizes of the constituent features that form the devices, e.g., electrical elements and interconnect lines, are also constantly being decreased to facilitate this size reduction.
- The trend of decreasing feature size is evident, for example, in memory devices or devices such as dynamic random access memories (DRAM), Flash memory, static random access memories (SRAM), ferroelectric (FE) memories, etc. To take one example, DRAM may comprise thousands to billions of identical device components in the form of memory cells. By decreasing the sizes of the electrical device structures that comprise a memory cell and the widths and lengths of the conducting lines to access the memory cells, the memory devices can be made smaller. Additionally, storage capacities can be increased by fitting more memory cells on a given area in the memory devices.
- The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to pattern features, such as conductive lines and pads. The concept of pitch can be used to describe the sizes of these features. Pitch may be defined as the distance between identical points in two neighboring features. These features are typically defined by spaces between adjacent features, which spaces are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature. However, due to factors such as limitations of optics and usable light or other radiation wavelengths, photolithography techniques each have a minimum achievable pitch, below which a particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction.
- “Pitch doubling” or “pitch multiplication” is one method for extending the capabilities of photolithographic techniques beyond their minimum pitch. One pitch multiplication method is illustrated in
FIGS. 1A-1F hereof and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference toFIG. 1A , a pattern oflines 10 is photolithographically formed in a photo definable layer, such as a photoresist, which overlies alayer 20 of an expendable material, which in turn overlies asubstrate 30. As shown inFIG. 1B , the pattern is then transferred using an anisotropic etch to thelayer 20 to form placeholders, or mandrels, 40. Thephotoresist lines 10 can be stripped and themandrels 40 can be isotropically etched to increase the distance between neighboringmandrels 40, as shown inFIG. 1C . Alayer 50 of spacer material is subsequently deposited over themandrels 40, as shown inFIG. 1D . Spacers 60, i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of themandrels 40. The spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown inFIG. 1E . Theremaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown inFIG. 1F . Thus, where a given pitch previously included a pattern defining one feature and one space, the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers 60. As a result, the smallest feature size possible with a photolithographic technique is effectively decreased. - While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein.
- Because the
layer 50 of spacer material typically has a single thickness 90 (seeFIGS. 1D and 1E ) and because the sizes of the features formed by the spacers 60 usually correspond to thatthickness 90, pitch doubling typically produces features of only one width. Devices, however, generally employ features of different sizes. For example, random access memory devices typically contain arrays of memory cells located in one, more central region of the active surface of the devices and logic devices located in the outer, so-called “peripheral” regions. In the arrays, the memory cells are connected by conductive lines and, in the periphery, the conductive lines contact landing pads for connecting arrays to logic. Peripheral features such as landing pads, however, may be larger than the conductive lines. In addition, periphery electrical devices, including peripheral transistors, may be larger than the electrical devices in the array. Moreover, even if peripheral features can be formed with the same pitch as features in the array, because mask patterns formed by pitch multiplication may be limited to those that are formed along the sidewalls of patterned photoresist, pitch multiplication by itself typically does not offer the flexibility, e.g., geometric flexibility, required to define some features, particularly when features vary in size above and below the pitch resolution of the photolithographic technique used. - To overcome such limitations, some proposed methods for forming patterns at the periphery and in the array involve separately etching patterns into the array region and then peripheral region of a substrate. A pattern in the array region is first formed and transferred to the substrate or intermediate hard mask layer using one mask and then another pattern in the periphery region is formed and separately transferred to the substrate using another mask. Because such methods require forming the pattern in the array region first before forming the other pattern in the periphery region in order to thereafter transfer the patterns to the same level to be subsequently transferred to a substrate, such methods are limited in their ability to form equivalent or higher quality patterns suitable for forming the conductive lines of the array without additional masking and etching steps required for forming the pattern for the periphery features if the array pattern is to be adequately protected. One limitation affecting the quality of the array pattern is defects. Defects may be caused, for example, by the photoresist material deposited between spacers so that features of a larger size may be formed in the periphery. Undesirably, the process conventionally used to form smaller, dimensionally critical, spacers in the pattern of the array while the other larger features in the pattern of the periphery are formed adds expense to the process flow without reducing defect potential in the array.
- In addition to problems encountered in forming differently sized features on an integrated circuit device, it has been found that conventional pitch-doubling techniques may experience difficulty transferring a pattern of spacers to a substrate. In conventional methods of transferring the pattern, both the spacers and the underlying substrate layer or layers are exposed to an etchant. The etchants, however, may also etch the material of the spacers, albeit at a slower rate. Thus, over the course of subsequently forming another pattern of features in a peripheral region of the same substrate and then transferring the patterns to an underlying material, the etchant used to form the pattern of features in the peripheral region may remove an unacceptable amount of the material of the spacers before the pattern transfer is completed in both central and peripheral regions.
- Also, a layer of material overlaid on the spacers while the features in the peripheral region are formed may leave residual material between adjacent spacers which may potentially cause defects or shorts therein which are subsequently transferred to one or more underlying layers. These difficulties are exacerbated by the trend towards decreasing feature size, which, for example, leads to the need to form trenches which have increasingly higher depth to width, or “aspect” ratios, increasing the potential for defects when subjected to additional steps in the process flow in order to obtain features of various sizes. Thus, in conjunction with difficulties in producing structures having different feature sizes, pattern transfer limitations make the application of pitch multiplication principles to integrated circuit device manufacture even more difficult.
- Accordingly, it would be desirable to provide enhanced methods of forming features of different sizes on semiconductor device structures, especially where some features are formed below the minimum size achievable using photolithographic and other conventional lithography techniques, and in conjunction with pitch multiplication.
-
FIGS. 1A-1F show cross-sectional side views of a sequence of masking patterns for forming conductive lines in accordance with a conventional pitch doubling method. -
FIG. 2 shows a schematic top view of a partially formed semiconductor device, in accordance with embodiments of the invention. -
FIG. 3 shows a cross-sectional side view of a portion of the partially formed semiconductor device ofFIG. 2 , in accordance with embodiments of the invention. -
FIG. 4 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after forming a pattern of features in a selectively definable layer in the periphery of the device in accordance with embodiments of the invention. -
FIG. 5 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after transferring the pattern of features into a first hard mask layer in accordance with embodiments of the invention. -
FIG. 6 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after stripping off the material of the selectively definable layer in accordance with embodiments of the invention. -
FIG. 7 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after layering on another selectively definable layer over the pattern of features and upon a second hard mask layer in accordance with embodiments of the invention. -
FIG. 8 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after forming a pattern of lines in the another selectively definable layer in the array of the device in accordance with embodiments of the invention. -
FIG. 9 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after widening spaces between lines in the another selectively definable layer in accordance with embodiments of the invention. -
FIG. 10 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after depositing a layer of spacer material over the patterns in accordance with embodiments of the invention. -
FIG. 11 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after etching the layer of spacer material in accordance with embodiments of the invention. -
FIG. 12 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after etching the layer of spacer material and stripping the lines of the another selectively definable layer in accordance with embodiments of the invention. -
FIG. 13 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after depositing a protective layer of material over the patterns in accordance with embodiments of the invention. -
FIG. 14 shows a top view of the portion of partially formed semiconductor device ofFIG. 2 after forming a protective mask in the protective layer of material over the patterns in accordance with embodiments of the invention. -
FIG. 15A shows a top view of the portion of partially formed semiconductor device ofFIG. 2 after forming a “loop chop” etch of a pattern exposed by the protective mask in accordance with embodiments of the invention. -
FIG. 15B shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after stripping the material of the protective mask and the lines from the device providing a modified pattern in accordance with embodiments of the invention. -
FIG. 16 shows a cross-sectional side view of the portion of partially formed semiconductor device ofFIG. 2 after transferring the modified pattern to a primary hard mask layer ready for transferring into the substrate of the partially formed device. - According to an embodiment of the invention, a method for semiconductor device fabrication by what may be termed “reverse pitch reduction flow” includes patterning a first pattern of features above a substrate and patterning a second pattern of pitch-multiplied spacers subsequent to patterning the first pattern of features. In embodiments of the invention, the first pattern of features may be formed using conventional lithography and the second pattern of pitch-multiplied spacers may be formed by a pitch multiplication technique. Embodiments of the invention also encompass structures associated with the methods disclosed.
- Embodiments of the invention may have particular utility in fabrication of NAND Flash devices, wherein the first pattern of features may comprise gates in a peripheral region of the device and the second pattern of features may comprise word lines in a central region thereof. Embodiments of the invention may also be employed in fabrication of DRAM memory, phase change memory and programmable gate array (PGA) devices.
- Reference will now be made to the Figures, wherein like numerals refer to like features and elements throughout. It will be appreciated that these Figures are not necessarily drawn to scale.
- In embodiments of the invention, a sequence of material layers is formed that allows formation of a mask for processing a substrate.
-
FIG. 2 shows a top view of a portion of a partially formedintegrated circuit device 100. While the embodiments of the invention may be used to form any device, they are particularly advantageously applied to form devices having arrays of electrical devices, including memory cell arrays for volatile and non-volatile memory devices such as DRAM, ROM, phase change, or Flash memory, including NAND Flash memory, or integrated devices having logic or gate arrays. For example, the logic array may be a field programmable gate array (FPGA) having a core array similar to a memory array and a periphery with supporting logics. Also, the array may be a fine pitch repetitive logic circuitry or embedded memory on a processor, as additional examples. Consequently, theintegrated circuit device 100 may be, e.g., a memory chip or a processor, which may include both a logic array and embedded memory, or any other integrated device having a logic or a gate array. - The
integrated circuit device 100 includes acentral region 102, which may be termed the “array,” at least partially bounded by aperipheral region 104, which may be termed the “periphery.” It will be appreciated that, in a completed integrated circuit device, thearray 102 will typically be densely populated with conducting lines and electrical devices such as transistors and capacitors. In a memory device, the electrical devices form a plurality of memory cells, which are conventionally arranged in a regular grid pattern at the intersections of word lines and bit lines. Desirably, pitch multiplication may be used to form features in thearray 102, as discussed below. On the other hand, theperiphery 104 typically comprises features larger than those in thearray 102. Conventional photolithography, rather than pitch multiplication techniques, is generally used to pattern features, such as logic circuitry, in theperiphery 104, because the geometric complexity of logic circuits located in theperiphery 104 makes using pitch multiplication difficult, whereas the regular grid typical of element patterns in thearray 102 is conducive to pitch multiplication. In addition, some devices in the periphery require larger geometries due to electrical constraints, making pitch multiplication less advantageous than conventional photolithography for such devices. In addition to possible differences in relative scale, it will be appreciated by one of ordinary skill in the art that the relative positions, and the number, ofperiphery 104 andarray 102 regions in theintegrated circuit device 100 may vary from that depicted. -
FIG. 3 shows a cross-sectional side view of the partially formedintegrated circuit device 100. Various layers 120-150 are provided for masking above asubstrate 110 comprising a layer of semiconductor material. In one NAND Flash embodiment, thesubstrate 110 may comprise a conventional polysilicon/WSix/oxide gate stack or metal gate stack array. The layers 120-150 will be etched to form a mask for patterning thesubstrate 110, as discussed below. - The materials for the layers 120-150 overlying the
substrate 110 are selectively chosen based upon consideration of the chemistry and process conditions for the pattern forming and pattern transferring steps discussed herein. Because the layers 120-150 between a topmost selectivelydefinable layer 150 and thesubstrate 110 function to transfer a pattern derived from the selectivelydefinable layer 150 to thesubstrate 110, the layers 120-140 between the selectivelydefinable layer 150 and thesubstrate 110 are chosen so that they may be selectively etched relative to other exposed materials. It will be appreciated that a material is considered selectively, or preferentially, etched when the etch rate for that material upon exposure to a given etchant is substantially greater, on the order of at least about 2-3 times greater to at least about 40 times greater than the etch rate for adjacent materials exposed to the same etchant. Because a function of the layers 130-150 overlying the primaryhard mask layer 120 is to allow well-defined patterns to be formed inlayer 120, it will be appreciated that one or more of the layers 130-150 may be omitted or substituted if suitable other materials, chemistries and/or process conditions are used. - In the illustrated embodiment, the selectively
definable layer 150, which may comprise an optically or mechanically patternable layer overlies a hard mask, or etch stop,layer 140, which overlies ahard mask layer 130, which overlies themask layer 120, which overlies thesubstrate 110 to be processed (e.g., etched) through a mask. Beneficially, the mask through which thesubstrate 110 is processed is formed in thehard mask layer 130 and/or in themask layer 120. - With continued reference to
FIG. 3 , the selectivelydefinable layer 150 is photodefinable, e.g., formed of a photoresist, including any photoresist known in the art. For example, the photoresist may be any photoresist compatible with 157 nm, 193 nm, 248 nm or 365 nm wavelength systems, 193 nm wavelength immersion systems, extreme ultraviolet systems (including 13.7 nm wavelength systems) or electron beam lithographic systems. In addition, maskless lithography, or maskless photolithography, may be used to define the selectivelydefinable layer 150. Examples of photoresist materials include argon fluoride (ArF) sensitive photoresist, i.e., photoresist suitable for use with an ArF light source, and krypton fluoride (KrF) sensitive photoresist, i.e., photoresist suitable for use with a KrF light source. ArF photoresists are typically used with photolithography systems utilizing relatively short wavelength light, e.g., 193 nm. KrF photoresists are used with longer wavelength photolithography systems, such as 248 nm systems. In other embodiments, thelayer 120 and any subsequent resist layers may be formed of a resist that may be patterned by nano-imprint lithography, e.g., by using a mold or mechanical force to pattern the resist. The selectivelydefinable layer 150 will allow a first feature having a first size to be formed in theperiphery 104. It will be appreciated that light reflections may decrease the precision with which photolithography may define the edges of a pattern. Optionally, a bottom anti-reflective coating (BARC) (not shown) may similarly be used in addition to the firsthard mask layer 140 to control light reflections. - The material for the
hard mask layer 130, which functions as an etch stop and exhibits anti-reflective properties, comprises an inorganic material. Suitable materials forhard mask layer 130 include silicon oxide (SiO2) or a deep ultra-violet (DUV) dielectric anti-reflective coating (DARC), such as a silicon-rich silicon oxynitride. In this embodiment of the invention, thehard mask layer 130 is a dielectric anti-reflective coating (DARC). Using a DARC for thehard mask layer 130 may be particularly advantageous for forming patterns having pitches near the resolution limits of a particular photolithographic technique. The DARC may enhance resolution by minimizing light reflections, thus increasing the precision with which photolithography may define the edges of a pattern. By way of nonlimiting example, the DARC layer may comprise a DUV DARC of about 200-400 Å (20-40 nm) thickness. Other suitable materials that exhibit adequate etch stop and anti-reflective properties may be used for thehard mask layer 130. - In the illustrated embodiment, the hard mask or
etch stop layer 140 is formed of silicon, e.g., poly amorphous silicon, or a film of another material that exhibits good etch selectivity to oxide. Other suitable materials for the firsthard mask layer 140 may include a silicon oxide, e.g., a low silane oxide (LSO), low temperature nitride, and a thin layer of aluminum oxide, such as Al2O3. The LSO is formed by chemical vapor deposition using a relatively low silane flow and a relatively high N2O precursor flow. Advantageously, such a deposition can be performed at relatively low temperatures, e.g., less than about 550° C., for example, less than about 400° C., to prevent damage to the underlyingprimary mask layer 120, when thelayer 120 is formed of a temperature-sensitive material. It will be appreciated that oxides may typically be etched with greater selectivity relative to silicon than nitrides. For example, conventional etch chemistries for oxides may remove the oxides at a rate more than 10 times faster than amorphous silicon, while conventional etch chemistries for nitrides typically only remove the nitrides at a rate of about three times faster than poly amorphous silicon. As a result, both the spacers (discussed below) and the second hard mask layer are preferably formed of the same material, in the form of an oxide, when the first hard mask layer is formed of poly amorphous silicon. - The
mask layer 120 may be formed of amorphous carbon due to the excellent etch selectivity of this material relative to many other materials, including a very high etch selectivity relative to the hard mask materials. Further, the transparent carbon is a form of amorphous carbon that is highly transparent to light and that offers further improvements for photo alignment by being transparent to the wavelengths of light used for such alignment. Deposition techniques for forming such transparent carbon are known to those of ordinary skill in the art and, so, need not be further described. The amorphous carbon is particularly advantageous for transferring patterns to difficult-to-etch substrates, such as thesubstrate 110 comprising multiple materials or multiple layers of materials, or for forming small and high aspect ratio features therein. - The combination of materials for the hard mask layers 130 and 140 are selectably chosen based upon the material used to form a first feature in the
periphery 104 in combination with providing the material used to form the spacers in thearray 102 allowing transfer of the pattern or mask formed by the layers, as discussed below, into theunderlying mask layer 120. As previously mentioned, themask layer 120 of the current embodiment is formed of amorphous carbon andlayer 150 is formed of photoresist. Optionally, other combinations of materials may be utilized to advantage, for example and without limitation, including (spacer material/first hard mask material/second hard mask material): oxide/amorphous silicon/oxide; nitride/amorphous silicon/oxide; nitride/oxide/amorphous silicon; amorphous silicon/oxide/amorphous silicon; carbon/amorphous silicon/oxide; and carbon/oxide/amorphous silicon. It will be appreciated that the oxide may be a form of silicon oxide and the nitride may be silicon nitride. Where the spacer material is oxide, as discussed below, the associatedhard mask layer 120 is a material that is preferentially etchable relative to the oxide. For example, thehard mask layer 120 may be formed of a silicon-containing material. Depending on the selection of appropriate etch chemistries and neighboring materials; examples of other materials include amorphous carbon and etchable high dielectric materials. - In addition to selecting appropriate materials for the various layers, the thicknesses of the layers 120-150 are selectively chosen depending upon compatibility with the etch chemistries and process conditions described herein. As discussed above, when transferring a pattern from an overlying layer to an underlying layer by selectively etching the underlying layer, materials from both layers are removed to some degree. Thus, the upper layer is sufficiently thick so that it is not removed over the course of the pattern transfer to the underlying layer but no so thick as to create an undesirable topography.
- In the illustrated embodiment, the selectively
definable layer 150 is about 2000 angstroms (“Å”) (200 nm) in thickness and, in other embodiments, may range in thickness from 500-3000 Å (50-300 nm). It is also recognized that the thickness of the selectivelydefinable layer 150 may be to a greater or lesser extent than the 2000 Å illustrated. It will be appreciated that, in cases where thelayer 150 is a photoresist, the thickness of thelayer 150 may vary depending upon the wavelength of light used to pattern thelayer 120. A thickness of about 500-3000 Å (50-300 nm) thick and, more specifically, a thickness of about 2000-2500 Å (200-250 nm), is particularly advantageous for 248 nm wavelength systems. - The
hard mask layer 140 has a thickness of about 150-200 Å (20 nm) and, in other embodiments, may range in thickness to a greater or lesser extent than the 200 Å illustrated. One particularly suitable thickness is 100 Å. Thehard mask layer 140 may have a thickness ranging from about 100 Å (10 nm) to about 400 Å (40 nm). Thehard mask layer 130 is about 200-600 Å (20-60 nm) thick and, in other embodiments, may range in thickness to a greater or lesser extent. For example, thelayer 130 may have a thickness of about 300-500 Å (30-50 nm). - As discussed above, the thickness of the
mask layer 120 is chosen based upon the selectivity of the etch chemistry for etching the substrate and based upon the materials and complexity of the substrate. Advantageously, a thickness formask layer 120 of about 3000 Å (300 nm) and, in other embodiments a thickness between 1000-5000 Å (100-500 nm) is particularly effective for transferring patterns to a variety of substrates, including substrates having a plurality of different materials to be etched during the transfer. - Transferring patterns into a variety of substrates is accommodated readily when utilizing a
mask layer 120 of sufficient thickness. For example, the illustratedsubstrate 110 comprising a plurality of layers (not shown) may be etched to form word lines over an array of gate stacks. The layers of thesubstrate 110 may include a tungsten silicide layer overlying a polysilicon layer, which overlies an oxide-nitride-oxide (ONO) composite layer, which overlies a polysilicon layer, the layers in combination and as previously processed comprising an array of gate stacks. - The various layers discussed herein may be formed by various conventional methods. For example, spin-on-coating processes may be used to form photoresist, selectively definable layers. Various vapor deposition processes, such as chemical vapor deposition, may be used to form hard mask layers. Depositing each layer of materials may include depositing a material by coating, layering, or spinning, for example.
- A low temperature chemical vapor deposition (CVD) process may be used to deposit the hard mask layers or any other materials, e.g., spacer material described herein, over the
mask layer 120, especially in cases where themask layer 120 is formed of amorphous carbon. Advantageously, it is known to those of ordinary skill in the art that the hard mask layers 140 and 130 may be deposited at relatively low temperatures of less than about 550° C., lower than about 450° C., and even lower than about 400° C. Such low temperature deposition processes advantageously prevent chemical or physical disruption of amask layer 120 made of amorphous carbon material. Various methods for forming these layers are known to those of ordinary skill in the art and are described in U.S. Pat. No. 7,115,525, U.S. Pat. No. 6,573,030, and U.S. Pat. Pub. No. 2006/0211260, the entire disclosures of each of which documents are incorporated herein by reference. - After formation of the various layers 120-150 as described above, to improve and enhance the quality of a pattern of spacers formed by pitch multiplication, a first pattern of features is formed according to an embodiment of the invention. Then, a second pattern of spacers may be formed by pitch multiplication, followed by subjecting the patterns to a so-called “loop chop” process to eliminate closed loops formed in the mask. The pattern of features and the pattern of spacers at this point are consolidated for transferring into the substrate. The quality of the final structure formed within the substrate is improved by forming of the first pattern of features before forming the second pattern of spacers during a masking process. Specifically, as the second pattern of spacers is more sensitive to masking-related sensitivities and transferring processes than the first pattern of features, this process flow according to embodiments of the invention enables quality improvement in the second pattern of spacers by first subjecting the less dimensionally sensitive structures of the first pattern to the forming process.
- In accordance with an embodiment of the invention, a first pattern of features is formed principally in the periphery of the device. Each feature of the first pattern includes, particularly at minimum or larger critical dimensions that are directly formable in the photodefinable material of the selectively definable layer, and do not require a pitch reduction or multiplication technique as is required to obtain smaller critical dimensions of the spacers of the second pattern, as will be discussed below.
- With reference to
FIG. 4 , afirst pattern 106 offeatures 105 is formed in the selectivelydefinable layer 150. The selectivelydefinable layer 150 may be patterned by, e.g., photolithography, in which thelayer 150 is exposed to radiation through a reticle and then developed. After being developed, the remaining photodefinable material, photoresist in this embodiment, comprises features 105 (only one feature shown for clarity). Eachfeature 105 of thefirst pattern 106 may form various landing pads, transistors and local interconnects, for example and without limitation, and generally may have a size larger than the smaller critical dimensions obtained with the spacers of the second pattern, as discussed below. - After forming the
first pattern 106, thehard mask layer 140 is etched to transfer thefirst pattern 106 formed inlayer 150 down to thehard mask layer 140 as shown inFIG. 5 . Thehard mask layer 140, formed of amorphous silicon, is anisotropically etched using, for example, an HBr and Cl2-containing plasma, and stopping the etch at thehard mask layer 130. This so called “dry” etch of the HBr and Cl2-containing plasma etches the amorphous silicon at a rate greater than about five times, and even as great as ten times, the rate at which the photoresist material of thefeatures 105 may be etched. It is recognized that etchinghard mask layer 140 may consume some of the DARC material of thehard mask layer 130, for example, between 20-30 A (4-5 nm), which may leave the surface oflayer 130 slightly nonuniform in topography. The uniformity of thehard mask layer 130 is addressed below when forming the second pattern of spacers. HBr and Cl2 chemistry-based etchants exhibit good selectivity to oxide. Other suitable etchants may include C2F6/Cl2/O2, SF6, and CF4 for example and without limitation. - With reference to
FIG. 6 , thefirst pattern 106 is cleaned while stripping the selectivelydefinable layer 150. The carbon material fanning thephotoresist layer 150 and DARChard mask layer 130 may polymerize upon contact with etchants. For example, the HBr/Cl2 etch of thehard mask layer 140 may cause parts of thelayers hard mask layer 140, causing a pattern having undesirably non-uniform features. Thus, thefirst pattern 106 is cleaned by stripping off organic material. The strip may be accomplished using, for example, an isotropic etch with O2 plasma or other etch processes recognized as suitable by a person of ordinary skill in the art for preserving thefeatures 105 in thehard mask layer 140. - Next, a second pattern of spacers is formed by pitch multiplication over the
first pattern 106 offeatures 105. The second pattern comprises spacers having smaller critical dimensions than thefirst pattern 106 offeatures 105 as formed. In addition, the second pattern may be formed completely, partially, or not overlapping thefirst pattern 106. - Turning to
FIG. 7 , to allow the second pattern to be formed, a selectivelydefinable layer 160 is formed on, and overlies, thehard mask layer 130 andfirst pattern 106 of features now formed in the firsthard mask layer 140 to allow for patterning of the second pattern in thearray 102. - As with the selectively
definable layer 150, the selectivelydefinable layer 160 may be photodefinable, e.g., formed of a photoresist, including any suitable photoresist known in the art, such as a trimmable mandrel material. In addition, in other embodiments, the selectivelydefinable layer 160 may be formed of a resist suitable for patterning by nano-imprint lithography. - Optionally, while not necessarily required, a planar surface (not shown) may be formed prior to depositing the
layer 160 by depositing a planarizing material (not shown) around thefeatures 105 and upon the secondhard mask layer 130 when required for improving the planarity of structure of the to-be-patterned array for forming spacers. Specifically, the planarizing layer may be employed where the resolution of the spacers to be formed in the second pattern may not be adequately defined without first providing a planarized surface. For example, a spin-on antireflective coating may be used for planarization purposes. - With reference to
FIG. 8 , the selectivelydefinable layer 160 is patterned using, e.g., the same photolithographic technique used to pattern the selectivelydefinable layer 150. Thus, asecond pattern 108 is formed in the selectivelydefinable layer 160. Where thesecond pattern 108 is used to mask features in thearray 102, the area in the selectivelydefinable layer 160 in theperiphery 104 is preferably open, as illustrated. As noted above, however, while illustrated laterally adjacent thefirst pattern 106, thesecond pattern 108 may partially or completely overlap thefirst pattern 106 or be completely separated from thefirst pattern 106. Thus, the use of different reference numerals (106 and 108) for these respective patterns indicates that they were originally formed in different acts. - The process flow as described below results in the
second pattern 108 that includes a pitch or feature size smaller than the minimum pitch or resolution of the photolithographic technique used in forming it, unlike thefirst pattern 106 that includes pitch or feature size equal to or greater than the minimum pitch or resolution of the photolithographic technique used to form thefirst pattern 106. It will be appreciated that thesecond pattern 108 in thearray 102 may be used to form arrays of conductive feeds, contacts and other semiconductor components when transferred into thesubstrate 110, for example and without limitation. - The
second pattern 108 includes spaces ortrenches 162, which are delimited by photodefinable material features, or lines, 164 formed in thephotodefinable layer 160. Thetrenches 162 may be formed by, for example, photolithography with 248 nm or 193 nm wavelengths light, in which thelayer 160 is exposed to radiation through a reticle and then developed as is known by a person of ordinary skill in the art. After being developed, the remaining photodefinable material, photoresist in the illustrated embodiment, forms mask features such as the array of lines 164 (shown in cross-section only) as illustrated. - The resulting pitch of the
lines 164 is equal to the sum of the width of aline 164 and the width of a neighboringspace 162. To minimize the critical dimensions of features formed using this pattern oflines 164 andspaces 162, the pitch may be at or near the limits of the photolithographic technique used to pattern thephotodefinable layer 160. For example, for photolithography utilizing 248 nm light, the pitch of thelines 164 can be about 1000 Å (100 nm). Thus, the pitch may be at the minimum pitch of the photolithographic technique and the spacer formed in the pattern as discussed below may advantageously have a pitch below the minimum pitch of the photolithographic technique. - As shown in
FIG. 9 , thespaces 162 may be widened by etching the photoresist material of thelines 164, to form modifiedspaces 162 a and lines 164 a. The photoresist lines 164 are etched using an isotropic etch to “shrink” those features. Suitable etches include etches using an oxygen-containing plasma, e.g., a SO2/O2/N2/Ar plasma, a Cl2/O2/He plasma or an HBr/O2/N2 plasma. The extent of the etch is selected so that the widths of thelines 164 a are substantially equal to the desired spacing between the later-formed spacers (172 inFIG. 11 ), as will be appreciated from the discussion below. For example, the width of thelines 164 may be reduced to 800-1200 Å (80-120 nm) or even further reduced to about 400-700 Å (40-70 nm). Advantageously, the width-reducing etch allows thelines 164 a to be narrower than would otherwise be possible using the photolithographic technique used to pattern the selectivelydefinable layer 160. In addition, the etch may smooth the edges by removing material of the resistlines 164 a, thus improving the line edge roughness uniformity of those lines. While the critical dimensions of thelines 164 a may be etched below the resolution limits of the photolithographic technique, it will be appreciated that this etch does not alter the pitch of thespaces 162 a and lines 164 a, since the distance between identical relative points in these features remains the same. - Next, as shown in
FIG. 10 , alayer 170 of spacer material is preferably blanket deposited conformally over exposed surfaces, including thehard mask layer 130 and the top and sidewalls of the patterned, modifieddefinable layer 160 a. The spacer material may be any material that can act as a mask for transferring a pattern to the underlyinghard mask layer 130. The spacer material is selected for deposition with good step coverage, at a temperature compatible with the modifieddefinable layer 160 a, and suitability for etching relative to the modifieddefinable layer 160 a and the underlyinghard mask layer 130. Materials for thelayer 170 may include silicon, silicon oxides and silicon nitrides. In the illustrated embodiment, the spacer material is a silicon oxide deposited at a relatively low temperature, such as 75° C., which provides particular advantages in combination with other selected materials of the masking stack. - Methods for depositing the material of the
spacer layer 170 may include chemical vapor deposition, e.g., using O3 and TEOS to form silicon oxide, and atomic layer deposition, e.g., using a silicon precursor with an oxygen or nitrogen precursor to form silicon oxides and nitrides, respectively. The thickness of thespacer layer 170 is preferentially determined based upon the desired width of the spacers 172 (FIG. 11 ). For example, in this embodiment, thelayer 170 is deposited to a thickness of about 200-800 Å (20-80 nm). In other embodiments, thelayer 170 may be deposited to a thickness ranging between 400-600 Å (40-60 nm). In still other embodiments, the layer may range between about 100-300 Å (10-30 nm) or to a greater or lesser extent than illustrated. Thespacer layer 170 formed over thefirst pattern 106 offeatures 105 in theperiphery 104 of thedevice 100 may see uneven steps ranging about 250 Å (25 nm) in size, which will be stripped away when forming thespacers 172 as shown inFIG. 11 without substantial alteration of thefeatures 105 as formed. - Turning now to
FIG. 11 , thespacers 172 are now formed in thesecond pattern 108 by exposing the silicon oxide material of thespacer layer 170 to an anisotropic etch to remove spacer material fromhorizontal surfaces 180 of the partially formeddevice 100 while stopping on the surface of the firsthard mask layer 140 and the secondhard mask layer 130. Such an etch, also known as “spacer etch,” may be performed using a fluorocarbon plasma containing, for example and without limitation, CF4/CHF3, C4F8/CH2F2 or CHF3/Ar plasma. The material of the modifieddefinable layer 160 a may be selectively retained betweenadjacent spacers 172 while further processing to remove portions of the spacer material is performed in accordance with embodiments of the invention as described below. Beneficially, retaining the material used to form thelines 164 a of the modifieddefinable layer 160 a betweenadjacent spacers 172 enhances the quality of a portion of thespacers 172 by not subjecting the material to extra processing or cleaning steps that may undesirably erode or otherwise damage or displace the spacers prior to their ultimate pattern transfer to theunderlying substrate 110. - Optionally, in other embodiments of the invention as shown in
FIG. 12 , the modifieddefinable layer 160 a may be removed to leave thespacers 172 in freestanding alignment. In such an instance, the modifieddefinable layer 160 a may be selectively removed using an organic strip process as described above. Optional etch chemistries may include an oxygen-containing plasma etch, such as etching using an O2 plasma strip. - Thus, pitch reduction or multiplication for
spacers 172 has been accomplished. In the illustrated embodiment, the pitch of thespacers 172 is roughly half that of thephotoresist lines 164 and spaces 162 (FIG. 8 ) originally formed by photolithography. Where thephotoresist lines 164 had a pitch of about 2000 Å (200 nm),spacers 172 having a pitch of about 1000 Å (100 nm) or less may be formed. It will be appreciated that, because thespacers 172 are formed on opposing sidewalls of each of the features orlines 164 a, thespacers 172 generally follow the outline of the pattern of features orlines 164 a in the modifiedphotodefinable layer 160 a and, so, form a closed loop around the ends of thelines 164 a. Thespacers 172 form relatively smaller features of thesecond pattern 108 that may be transferred to theunderlying substrate 110 together with the relativelylarger features 105 forming thefirst pattern 106. Advantageously, thefirst pattern 106 and thesecond pattern 108 may now be subjected to so-called “loop chop” process to eliminate undesirable closed loops or other portions of pattern material before transferring the mask to thesubstrate 110. - Optionally, a second pattern of spacers may be formed after the first pattern of features is formed by utilizing other methods of pitch multiplication. Other methods of pitch multiplication may require layering different or select layers of material above the substrate in addition to the layers mentioned herein. For example, a method of forming a pattern of spacers by pitch multiplication is described in paragraphs [0056]-[0092] and FIGS. 2A-10 of U.S. Pub. No. 2006/0046422 to Tran et al., dated Mar. 2, 2006, the entire disclosure of which is incorporated by reference herein.
- In methods according to embodiments of the invention, spacer material in the form of loops of spacer material connecting
adjacent spacers 172 is etched to remove the loops and isolate thespacers 172. This etch may be used to form two separate lines ofspacers 172 initially connected at their adjacent ends by a loop of spacer material extending around the end of aline 164 a corresponding to two separate conductive paths to be formed in thesubstrate 110. It will be appreciated that more than two lines may be formed, if desired, by etching thespacers 172 at more than two locations. Other suitable method for cutting off the ends of the loops is disclosed in U.S. Pub. No. 2006/0046422 to Tran et al., dated Mar. 2, 2006, the entire disclosure of which is incorporated by reference herein. - To form the separate lines, a protective mask is formed over parts of the lines to be retained and the exposed, unprotected part of the loop of spacer material connecting the spacer lines are then etched. The protective mask is then removed to leave a plurality of physically separated and electrically isolated lines comprised of
spacers 172. - With reference to
FIG. 13 , a protective material forming aprotective layer 181 is selectively deposited around and over thespacers 172 and the parts of thelayers pattern 108, and, in this embodiment, is selectively deposited around and over thefeatures 105 forming thepattern 106. The material of theprotective layer 181 may be a photodefinable material such as photoresist as described above and is sufficiently thick to protect the underlying mask during the etch. Optionally, an anti-reflective coating (“ARC”) (not shown) may be provided under theprotective layer 181, e.g., above thepatterns FIG. 14 , aprotective mask 182 is subsequently patterned in theprotective layer 181, e.g., by photolithography, to protect desired portions of theunderlying patterns pattern 106 forming thefeatures 105 may be entirely, partially or not covered depending upon the relative resistance to etching during the etch. To separate thespacers 172 of each loop into two separate lines, portions of the loops are exposed for etching in at least two separate locations. To simplify processing, the exposed portions of the loops are generally the ends of the loops formed by thespacers 172, as illustrated. - In other embodiments, it will be appreciated that the
protective layer 181 may be formed of any material that may be selectively removed, e.g., relative to thespacers 172, thelayers protective mask 182 may be formed in another material, e.g., photoresist, overlying theprotective layer 181. - Advantageously, where the ends of the
spacers 172 extend in a straight line, the length and simple geometry of the straight lines may minimize the precision required for forming theprotective mask 182; that is, the protective mask need only be formed so that it leaves the ends of thespacers 172 exposed. Thus, by centering the mask a selected distance from the ends of thespacers 172, a misaligned mask may cause slightly more or less of thespacers 172 to be exposed, but may still accomplish the objective of leaving the ends adequately exposed. While the margin of error for aligning theprotective mask 182 is larger than if theprotective mask 182 were required to form a geometrically complex shape, it is recognized that other shapes may be formed in theprotective mask 182 different from the rectangular shape of theprotective mask 182 as illustrated. See, for example, U.S. Pub. No. 2006/0046422 to Tran et al., the disclosure of which is incorporated herein in its entirety by reference. - With reference to
FIG. 15A , the exposed portions of thespacers 172 are etched away leaving the exposed portions of thephotoresist lines 164 a and thefeatures 105 ofpattern 106. Where thespacers 172 are foamed from silicon oxide or nitride, suitable etch chemistries may include a fluorocarbon etch or in the case ofspacers 172 formed of an oxide, such as silicon oxide, the exposed loops of thespacers 172 may be isotropically etched using a wet chemistry, for example, a buffered oxide etch. One suitable etchant for a silicon dioxide spacer material is an HF/H2O wet etch at a 500:1 dilution ratio. After being etched, thespacers 172 no longer form a loop with a neighboringspacer 172 as illustrated. Thespacers 172 as etched thus forms a modifiedpattern 109 offeatures 105 andspacers 172 with the material of theprotective mask 182 removed.FIG. 15B shows a side view of the resulting structure, taken along the vertical plane as indicated inFIG. 15A with the material of thelines 164 a removed. - Optionally, where the
protective mask 182 is sufficiently thick and thelines 164 a were not previously removed, the exposed portions of thephotoresist lines 164 a may be descummed or etched away in order to facilitate etching the exposed portions of thespacers 172. For example, an O2/N2 reactive ion etch, an O2 etch, or a CF4 and/or CHF3 plasma etch may be employed. Also, the exposed surface of the partially fabricateddevice 100, i.e., the portion not protected by theprotective mask 182, may be cleaned prior to the etching the exposed portions of thespacers 172. - With reference to
FIGS. 15A and 15B , the materials of theprotective mask 182 and of thelines 164 a are selectively removed. Where the material is photoresist or optional ARC, etch chemistries include anisotropic etches, such as with an SO2-containing plasma. In other embodiments, the mask of the partially formeddevice 100 may be subjected to an ashing process to remove the material oflayers pattern 109 is compatible with the ashing process. It will be appreciated that thespacers 172 and thefeatures 105 are not attacked during this removal act and that the primaryhard mask layer 120 is protected by the secondhard mask layer 130. Advantageously, by selectively removing the material of thelines 164 a together with the material of theprotective mask 182, the inner portions of thespacers 172 are subjected to less processing than would be if the material of thelines 164 a was removed prior to the “loop chop” process, beneficially enhancing resolution and reducing variations and defects when thepattern 109 is transferred to theunderlying substrate 110. - According to embodiments of the invention, the modified
pattern 109 comprising thespacers 172 and thefeatures 105 of thepatterns substrate 110. - With reference to
FIG. 16 , the secondhard mask layer 130 and primaryhard mask layer 120 are etched to transfer the modifiedpattern 109 down to themask layer 120, to form a pattern of components of mixed feature size in themask layer 120. - Optionally, before transferring the modified pattern into the
layers pattern 109 is cleaned. As noted above, the carbon material forming thelayers hard mask layer 130, causing a modifiedpattern 109 having undesirably non-uniform feature sizes. Thus, the modifiedpattern 109 is cleaned by stripping off an organic material. The cleaning may be accomplished using, e.g., an isotropic etch with O2 plasma and may be done simultaneously while stripping of theprotective mask 182. For example, O2 wet clean with an H2O, H2O2, NH4OH or so-called “SCI” solution. - Turning to
FIG. 16 , the modifiedpattern 109 is transferred to themask layer 120. The transfer is accomplished by anisotropically etching the secondhard mask layer 130 and theprimary mask layer 120, using an SO2-containing plasma. Other suitable etch chemistries include a Cl2/O2, HBr/O2/N2 or SiCl4/O2N2/HBr or SiCl4/O2-containing plasma. As noted above, the SO2-containing plasma is particularly suitable as it has been found to have excellent selectivity for the amorphous carbon of themask layer 120 and the DARC of thehard mask layer 130 relative to the material of thespacers 172 and thefeatures 105. Thus, a thick enough mask may be formed in theprimary mask layer 120 to later effectively transfer the mask pattern to thesubstrate 110, particularly through multiple materials of the substrate using selective etch chemistries and without wearing away themask layer 120 before the pattern transfer is complete. - After the modified
pattern 109 is transferred to themask layer 120, thepattern 109 is transferred to thesubstrate 110 using the patternedmask layer 120 as a mask. Given the disparate materials used for themask layer 120 and the substrate 110 (e.g., amorphous carbon and silicon or silicon compounds, respectively), the pattern transfer can be readily accomplished using conventional etch chemistries appropriate for etching the material or materials of thesubstrate 110 to form the final structures therein. The process used to transfer the modifiedpattern 109 from themask layer 120 and into thesubstrate 110 may include any suitable process known to a person of ordinary skill in the art. - The
spacers 172 and thefeatures 105 of the modifiedpattern 109 may be employed to respectively form interconnect lines such as word lines and associated integrated device features, such as landing pads as transferred into the substrate. Methods for forming interconnects and landing pads are disclosed in U.S. Pub. No. 2006/0046422 to Tran et al., dated Mar. 2, 2006, the entire disclosure of which was previously incorporated herein by reference. Other methods for forming interconnects and landing pad are disclosed in U.S. Pat. No. 7,115,525 to Abatchev et al., dated Oct. 3, 2006, and U.S. Pub. No. 2006/0211260 to Tran et al., dated Sep. 21, 2006, the entire disclosures of which are incorporated herein by reference. - It will also be appreciated that the pitch of the
pattern 108 may be more than doubled as is shown in the drawing figures herein, particularly before the modifiedpattern 109 is transferred to the substrate. For example, thepattern 108 may be further pitch multiplied by forming spacers around thespacers 172, then removing thespacers 172, then forming spacers around the spacers that were formerly around thespacers 172, and so on. For example, a method for further pitch multiplication is discussed in U.S. Pat. No. 5,328,810 to Lowrey et al., the entire disclosure of which is incorporated herein by reference. In addition, while embodiments of the invention may advantageously be applied to form a modifiedpattern 109 having both pitch multiplied and conventionally photolithographically defined features, thepatterns - In addition, the embodiments of the invention may be employed multiple times throughout an integrated device fabrication process to form pitch multiplied features and conventional features in a plurality of layers or vertical levels, which may be vertically contiguous or non-contiguous and vertically separated. In such cases, each of the individual levels to be patterned would constitute a
substrate 110 and the various layers 120-181 may be formed over the individual level to be patterned. It will also be appreciated that the particular composition and height of the various layers 120-181 discussed above may be varied depending upon a particular application. In one regard, thelayer 120 may be sufficiently thin in order to provide structural stability to the mask, to protect the substrate material throughout fabrication, and to allow the mask to be transferred into thesubstrate 110 without complete removal of the material oflayer 120 before the final etch is finished. For example, the thickness of thelayer 120 may be varied depending upon the identity of thesubstrate 110, e.g., the chemical composition of the substrate, whether the substrate comprises single or multiple layers of material, the depth of features to be formed, for example, and the available etch chemistries, without limitation. In some cases, one or more layers of layers 120-181 may be omitted or more layers may be added. For example, thelayer 120 may be omitted in cases where thehard mask layer 130 is sufficiently durable to adequately transfer a modifiedpattern 109 to thesubstrate 110. - Also, while “processing” through the various mask layers involves etching an underlying layer, processing through the mask layers may involve subjecting layers underlying the mask layers to any semiconductor fabrication process. For example, processing may involve ion implantation, diffusion doping, depositing, or wet etching, without limitation, through the mask layers and onto underlying layers. In addition, the mask layers may be used as a stop or barrier for chemical mechanical polishing (CMP) or CMP may be performed on any of the layers to allow for both planarization and etching of the underlying layers, as disclosed in U.S. Provisional Patent Application No. 60/666,031, filed Mar. 28, 2005, the entire disclosure of which is incorporated by reference herein.
- It will be appreciated that the “substrate” to which patterns are transferred may include a layer of a single material, a plurality of layers of different materials, a layer or layers having regions of different materials or structures in them, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate may comprise doped polysilicon, an electrical device active area, a silicide, or a metal layer, such as a tungsten, aluminum or copper layer, or combinations thereof. In some embodiments, the mask features discussed herein may directly correspond to the desired placement of conductive features, such as interconnects, in the substrate. In other embodiments, the substrate may be an insulator and the location of mask features may correspond to the desired location of insulators, such as in damascene metallization. Examples of structures formed in the substrate include gate stacks and shallow trench isolation structures.
- Further, in any of the acts described herein above, transferring a pattern from an overlying level to an underlying level involves forming features or spacers in the underlying level that generally correspond to features or spacers in the overlying level. For example, the path of lines in the underlying level will generally follow the path of lines in the overlying level and the location of other features in the underlying level will correspond to the location of similar features or spacers in the overlying level. The precise shapes and sizes of features and spacers may vary from the overlying level to the underlying level, however. For example, depending upon etch chemistries and conditions, the sizes of and relative spacing between the features and spacers forming the transferred patterns may be enlarged or diminished relative to the pattern on the overlying level, while still resembling the same initial “pattern,” as are seen from the example of shrinking the lines in the embodiments described above. Thus, even with some changes in the dimensions of features or spacers, the transferred pattern, or patterns, is still considered to be the same pattern, or patterns, as the initial pattern. In contrast, forming spacers around mask features, e.g., the lines, may change the pattern.
- Embodiments of the invention provide reverse pitch reduction flow enabling improved pattern transfer and the formation of differently sized features in conjunction with the use of pitch multiplication.
- In methods according to embodiments of the invention, a sequence of layers of materials is formed that allow formation of a mask for processing a substrate to fabricate, for example, a memory chip or other integrated circuit device incorporating at least two regions on the active surface thereof having structural elements of substantially differing feature size. Thereafter, a first pattern of features is formed where conventional photolithography may be used to form the first pattern defining features in the mask, the features being generally formed in one region of the device, e.g., the peripheral region of the memory chip. Subsequently, a second pattern of spacers is formed using pitch multiplication. The second pattern of spacers form an element array in another region of the device, e.g., the memory array of the memory chip, advantageously eliminating acts conventionally required to form the spacers when subsequent features of various sizes are required to be formed therewith. The quality of the pattern of spacers may be improved and enhanced for subsequent transfer to the underlying substrate while potentially eliminating additional layering, cleaning, and etching acts otherwise conventionally required in order to form a device having respective features of diverse dimensions in the region of the memory array and in the peripheral region. The second pattern may completely or partially overlap the first pattern, or, in some embodiments, may be completely formed in different regions of the device, e.g., the periphery of the memory chip. The first pattern and the second pattern may be selectively covered by a protective mask and subjected to a so-called “loop chop” process to eliminate undesirable closed loops in order to obtain a modified pattern for transfer to the substrate. Optionally, a “loop chop” may be omitted during fabrication for a particular polarity of a level, thus saving an additional masking step.
- Embodiments of the invention facilitate combining the patterns forming the differently sized spacers and features and successfully transferring the spacer and feature sizes and configurations to the underlying substrate while subjecting the spacers, with their size below the minimum pitch of the photolithographic technique used for patterning them, to fewer process acts which might compromise the quality of the transfer.
- In further embodiments of the invention, the pattern of pitch-multiplied resolution spacers may be configured as an array.
- While particular embodiments of the invention have been shown and described, numerous variations and other embodiments will occur to those of ordinary skill in the art. Accordingly, the invention is only limited in terms of the scope of the appended claims.
Claims (20)
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US10714350B2 (en) | 2016-11-01 | 2020-07-14 | ASM IP Holdings, B.V. | Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
KR102546317B1 (en) | 2016-11-15 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Gas supply unit and substrate processing apparatus including the same |
KR20180068582A (en) | 2016-12-14 | 2018-06-22 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11581186B2 (en) | 2016-12-15 | 2023-02-14 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus |
US11447861B2 (en) | 2016-12-15 | 2022-09-20 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus and a method of forming a patterned structure |
KR20180070971A (en) | 2016-12-19 | 2018-06-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US10269558B2 (en) | 2016-12-22 | 2019-04-23 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US10867788B2 (en) | 2016-12-28 | 2020-12-15 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US11390950B2 (en) | 2017-01-10 | 2022-07-19 | Asm Ip Holding B.V. | Reactor system and method to reduce residue buildup during a film deposition process |
US10468261B2 (en) | 2017-02-15 | 2019-11-05 | Asm Ip Holding B.V. | Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures |
US10529563B2 (en) | 2017-03-29 | 2020-01-07 | Asm Ip Holdings B.V. | Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures |
KR102457289B1 (en) | 2017-04-25 | 2022-10-21 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing a thin film and manufacturing a semiconductor device |
US10770286B2 (en) | 2017-05-08 | 2020-09-08 | Asm Ip Holdings B.V. | Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures |
US10892156B2 (en) | 2017-05-08 | 2021-01-12 | Asm Ip Holding B.V. | Methods for forming a silicon nitride film on a substrate and related semiconductor device structures |
US10886123B2 (en) | 2017-06-02 | 2021-01-05 | Asm Ip Holding B.V. | Methods for forming low temperature semiconductor layers and related semiconductor device structures |
US11306395B2 (en) | 2017-06-28 | 2022-04-19 | Asm Ip Holding B.V. | Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus |
US10685834B2 (en) | 2017-07-05 | 2020-06-16 | Asm Ip Holdings B.V. | Methods for forming a silicon germanium tin layer and related semiconductor device structures |
KR20190009245A (en) | 2017-07-18 | 2019-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods for forming a semiconductor device structure and related semiconductor device structures |
US11018002B2 (en) | 2017-07-19 | 2021-05-25 | Asm Ip Holding B.V. | Method for selectively depositing a Group IV semiconductor and related semiconductor device structures |
US10541333B2 (en) | 2017-07-19 | 2020-01-21 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US11374112B2 (en) | 2017-07-19 | 2022-06-28 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US10590535B2 (en) | 2017-07-26 | 2020-03-17 | Asm Ip Holdings B.V. | Chemical treatment, deposition and/or infiltration apparatus and method for using the same |
US10770336B2 (en) | 2017-08-08 | 2020-09-08 | Asm Ip Holding B.V. | Substrate lift mechanism and reactor including same |
US10692741B2 (en) | 2017-08-08 | 2020-06-23 | Asm Ip Holdings B.V. | Radiation shield |
US11769682B2 (en) | 2017-08-09 | 2023-09-26 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US11139191B2 (en) | 2017-08-09 | 2021-10-05 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US11830730B2 (en) | 2017-08-29 | 2023-11-28 | Asm Ip Holding B.V. | Layer forming method and apparatus |
KR102491945B1 (en) | 2017-08-30 | 2023-01-26 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11056344B2 (en) | 2017-08-30 | 2021-07-06 | Asm Ip Holding B.V. | Layer forming method |
US11295980B2 (en) | 2017-08-30 | 2022-04-05 | Asm Ip Holding B.V. | Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures |
KR102630301B1 (en) | 2017-09-21 | 2024-01-29 | 에이에스엠 아이피 홀딩 비.브이. | Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same |
US10844484B2 (en) | 2017-09-22 | 2020-11-24 | Asm Ip Holding B.V. | Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US10658205B2 (en) | 2017-09-28 | 2020-05-19 | Asm Ip Holdings B.V. | Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber |
US10403504B2 (en) | 2017-10-05 | 2019-09-03 | Asm Ip Holding B.V. | Method for selectively depositing a metallic film on a substrate |
US10319588B2 (en) | 2017-10-10 | 2019-06-11 | Asm Ip Holding B.V. | Method for depositing a metal chalcogenide on a substrate by cyclical deposition |
US10923344B2 (en) | 2017-10-30 | 2021-02-16 | Asm Ip Holding B.V. | Methods for forming a semiconductor structure and related semiconductor structures |
US10910262B2 (en) | 2017-11-16 | 2021-02-02 | Asm Ip Holding B.V. | Method of selectively depositing a capping layer structure on a semiconductor device structure |
US11022879B2 (en) | 2017-11-24 | 2021-06-01 | Asm Ip Holding B.V. | Method of forming an enhanced unexposed photoresist layer |
TWI791689B (en) | 2017-11-27 | 2023-02-11 | 荷蘭商Asm智慧財產控股私人有限公司 | Apparatus including a clean mini environment |
JP7214724B2 (en) | 2017-11-27 | 2023-01-30 | エーエスエム アイピー ホールディング ビー.ブイ. | Storage device for storing wafer cassettes used in batch furnaces |
US10304680B1 (en) * | 2017-12-22 | 2019-05-28 | Macronix International Co., Ltd. | Fabricating semiconductor devices having patterns with different feature sizes |
US10872771B2 (en) | 2018-01-16 | 2020-12-22 | Asm Ip Holding B. V. | Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures |
TW202325889A (en) | 2018-01-19 | 2023-07-01 | 荷蘭商Asm 智慧財產控股公司 | Deposition method |
CN111630203A (en) | 2018-01-19 | 2020-09-04 | Asm Ip私人控股有限公司 | Method for depositing gap filling layer by plasma auxiliary deposition |
US11018047B2 (en) | 2018-01-25 | 2021-05-25 | Asm Ip Holding B.V. | Hybrid lift pin |
USD880437S1 (en) | 2018-02-01 | 2020-04-07 | Asm Ip Holding B.V. | Gas supply plate for semiconductor manufacturing apparatus |
US11081345B2 (en) | 2018-02-06 | 2021-08-03 | Asm Ip Holding B.V. | Method of post-deposition treatment for silicon oxide film |
US10896820B2 (en) | 2018-02-14 | 2021-01-19 | Asm Ip Holding B.V. | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
JP7124098B2 (en) | 2018-02-14 | 2022-08-23 | エーエスエム・アイピー・ホールディング・ベー・フェー | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
US10731249B2 (en) | 2018-02-15 | 2020-08-04 | Asm Ip Holding B.V. | Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus |
KR102636427B1 (en) | 2018-02-20 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method and apparatus |
US10975470B2 (en) | 2018-02-23 | 2021-04-13 | Asm Ip Holding B.V. | Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment |
US11473195B2 (en) | 2018-03-01 | 2022-10-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus and a method for processing a substrate |
US11629406B2 (en) | 2018-03-09 | 2023-04-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate |
US11114283B2 (en) | 2018-03-16 | 2021-09-07 | Asm Ip Holding B.V. | Reactor, system including the reactor, and methods of manufacturing and using same |
KR102646467B1 (en) | 2018-03-27 | 2024-03-11 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electrode on a substrate and a semiconductor device structure including an electrode |
US11230766B2 (en) | 2018-03-29 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
US11088002B2 (en) | 2018-03-29 | 2021-08-10 | Asm Ip Holding B.V. | Substrate rack and a substrate processing system and method |
KR102501472B1 (en) | 2018-03-30 | 2023-02-20 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method |
KR20190128558A (en) | 2018-05-08 | 2019-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures |
TW202349473A (en) | 2018-05-11 | 2023-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Methods for forming a doped metal carbide film on a substrate and related semiconductor device structures |
KR102596988B1 (en) | 2018-05-28 | 2023-10-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate and a device manufactured by the same |
US11718913B2 (en) | 2018-06-04 | 2023-08-08 | Asm Ip Holding B.V. | Gas distribution system and reactor system including same |
US11270899B2 (en) | 2018-06-04 | 2022-03-08 | Asm Ip Holding B.V. | Wafer handling chamber with moisture reduction |
US11286562B2 (en) | 2018-06-08 | 2022-03-29 | Asm Ip Holding B.V. | Gas-phase chemical reactor and method of using same |
KR102568797B1 (en) | 2018-06-21 | 2023-08-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing system |
US10797133B2 (en) | 2018-06-21 | 2020-10-06 | Asm Ip Holding B.V. | Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures |
WO2020003000A1 (en) | 2018-06-27 | 2020-01-02 | Asm Ip Holding B.V. | Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material |
CN112292478A (en) | 2018-06-27 | 2021-01-29 | Asm Ip私人控股有限公司 | Cyclic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials |
KR20200002519A (en) | 2018-06-29 | 2020-01-08 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing a thin film and manufacturing a semiconductor device |
US10612136B2 (en) | 2018-06-29 | 2020-04-07 | ASM IP Holding, B.V. | Temperature-controlled flange and reactor system including same |
US10388513B1 (en) | 2018-07-03 | 2019-08-20 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10755922B2 (en) | 2018-07-03 | 2020-08-25 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10767789B2 (en) | 2018-07-16 | 2020-09-08 | Asm Ip Holding B.V. | Diaphragm valves, valve components, and methods for forming valve components |
US11053591B2 (en) | 2018-08-06 | 2021-07-06 | Asm Ip Holding B.V. | Multi-port gas injection system and reactor system including same |
US10883175B2 (en) | 2018-08-09 | 2021-01-05 | Asm Ip Holding B.V. | Vertical furnace for processing substrates and a liner for use therein |
US10829852B2 (en) | 2018-08-16 | 2020-11-10 | Asm Ip Holding B.V. | Gas distribution device for a wafer processing apparatus |
US11430674B2 (en) | 2018-08-22 | 2022-08-30 | Asm Ip Holding B.V. | Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
CN110875313A (en) * | 2018-08-30 | 2020-03-10 | 长鑫存储技术有限公司 | Active area array and forming method thereof, semiconductor device and forming method thereof |
KR20200030162A (en) | 2018-09-11 | 2020-03-20 | 에이에스엠 아이피 홀딩 비.브이. | Method for deposition of a thin film |
US11024523B2 (en) | 2018-09-11 | 2021-06-01 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
US11049751B2 (en) | 2018-09-14 | 2021-06-29 | Asm Ip Holding B.V. | Cassette supply system to store and handle cassettes and processing apparatus equipped therewith |
CN110970344A (en) | 2018-10-01 | 2020-04-07 | Asm Ip控股有限公司 | Substrate holding apparatus, system including the same, and method of using the same |
US11232963B2 (en) | 2018-10-03 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR102592699B1 (en) | 2018-10-08 | 2023-10-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same |
US10957549B2 (en) * | 2018-10-08 | 2021-03-23 | Micron Technology, Inc. | Methods of forming semiconductor devices using mask materials, and related semiconductor devices and systems |
US10847365B2 (en) | 2018-10-11 | 2020-11-24 | Asm Ip Holding B.V. | Method of forming conformal silicon carbide film by cyclic CVD |
US10811256B2 (en) | 2018-10-16 | 2020-10-20 | Asm Ip Holding B.V. | Method for etching a carbon-containing feature |
KR102546322B1 (en) | 2018-10-19 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
KR102605121B1 (en) | 2018-10-19 | 2023-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
USD948463S1 (en) | 2018-10-24 | 2022-04-12 | Asm Ip Holding B.V. | Susceptor for semiconductor substrate supporting apparatus |
US11087997B2 (en) | 2018-10-31 | 2021-08-10 | Asm Ip Holding B.V. | Substrate processing apparatus for processing substrates |
KR20200051105A (en) | 2018-11-02 | 2020-05-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and substrate processing apparatus including the same |
US11572620B2 (en) | 2018-11-06 | 2023-02-07 | Asm Ip Holding B.V. | Methods for selectively depositing an amorphous silicon film on a substrate |
US11031242B2 (en) | 2018-11-07 | 2021-06-08 | Asm Ip Holding B.V. | Methods for depositing a boron doped silicon germanium film |
US10818758B2 (en) | 2018-11-16 | 2020-10-27 | Asm Ip Holding B.V. | Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures |
US10847366B2 (en) | 2018-11-16 | 2020-11-24 | Asm Ip Holding B.V. | Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process |
US11217444B2 (en) | 2018-11-30 | 2022-01-04 | Asm Ip Holding B.V. | Method for forming an ultraviolet radiation responsive metal oxide-containing film |
KR102636428B1 (en) | 2018-12-04 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | A method for cleaning a substrate processing apparatus |
US11158513B2 (en) | 2018-12-13 | 2021-10-26 | Asm Ip Holding B.V. | Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures |
JP2020096183A (en) | 2018-12-14 | 2020-06-18 | エーエスエム・アイピー・ホールディング・ベー・フェー | Method of forming device structure using selective deposition of gallium nitride, and system for the same |
TWI819180B (en) | 2019-01-17 | 2023-10-21 | 荷蘭商Asm 智慧財產控股公司 | Methods of forming a transition metal containing film on a substrate by a cyclical deposition process |
KR20200091543A (en) | 2019-01-22 | 2020-07-31 | 에이에스엠 아이피 홀딩 비.브이. | Semiconductor processing device |
CN111524788B (en) | 2019-02-01 | 2023-11-24 | Asm Ip私人控股有限公司 | Method for topologically selective film formation of silicon oxide |
KR20200102357A (en) | 2019-02-20 | 2020-08-31 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus and methods for plug fill deposition in 3-d nand applications |
TW202104632A (en) | 2019-02-20 | 2021-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Cyclical deposition method and apparatus for filling a recess formed within a substrate surface |
TW202044325A (en) | 2019-02-20 | 2020-12-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of filling a recess formed within a surface of a substrate, semiconductor structure formed according to the method, and semiconductor processing apparatus |
KR102626263B1 (en) | 2019-02-20 | 2024-01-16 | 에이에스엠 아이피 홀딩 비.브이. | Cyclical deposition method including treatment step and apparatus for same |
TW202100794A (en) | 2019-02-22 | 2021-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing apparatus and method for processing substrate |
US11742198B2 (en) | 2019-03-08 | 2023-08-29 | Asm Ip Holding B.V. | Structure including SiOCN layer and method of forming same |
KR20200108243A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Structure Including SiOC Layer and Method of Forming Same |
KR20200108242A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer |
KR20200116033A (en) | 2019-03-28 | 2020-10-08 | 에이에스엠 아이피 홀딩 비.브이. | Door opener and substrate processing apparatus provided therewith |
KR20200116855A (en) | 2019-04-01 | 2020-10-13 | 에이에스엠 아이피 홀딩 비.브이. | Method of manufacturing semiconductor device |
KR20200123380A (en) | 2019-04-19 | 2020-10-29 | 에이에스엠 아이피 홀딩 비.브이. | Layer forming method and apparatus |
KR20200125453A (en) | 2019-04-24 | 2020-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Gas-phase reactor system and method of using same |
KR20200130121A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Chemical source vessel with dip tube |
KR20200130118A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Method for Reforming Amorphous Carbon Polymer Film |
KR20200130652A (en) | 2019-05-10 | 2020-11-19 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing material onto a surface and structure formed according to the method |
JP2020188255A (en) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | Wafer boat handling device, vertical batch furnace, and method |
USD947913S1 (en) | 2019-05-17 | 2022-04-05 | Asm Ip Holding B.V. | Susceptor shaft |
USD975665S1 (en) | 2019-05-17 | 2023-01-17 | Asm Ip Holding B.V. | Susceptor shaft |
USD935572S1 (en) | 2019-05-24 | 2021-11-09 | Asm Ip Holding B.V. | Gas channel plate |
USD922229S1 (en) | 2019-06-05 | 2021-06-15 | Asm Ip Holding B.V. | Device for controlling a temperature of a gas supply unit |
KR20200141003A (en) | 2019-06-06 | 2020-12-17 | 에이에스엠 아이피 홀딩 비.브이. | Gas-phase reactor system including a gas detector |
KR20200143254A (en) | 2019-06-11 | 2020-12-23 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method |
USD944946S1 (en) | 2019-06-14 | 2022-03-01 | Asm Ip Holding B.V. | Shower plate |
USD931978S1 (en) | 2019-06-27 | 2021-09-28 | Asm Ip Holding B.V. | Showerhead vacuum transport |
KR20210005515A (en) | 2019-07-03 | 2021-01-14 | 에이에스엠 아이피 홀딩 비.브이. | Temperature control assembly for substrate processing apparatus and method of using same |
JP2021015791A (en) | 2019-07-09 | 2021-02-12 | エーエスエム アイピー ホールディング ビー.ブイ. | Plasma device and substrate processing method using coaxial waveguide |
CN112216646A (en) | 2019-07-10 | 2021-01-12 | Asm Ip私人控股有限公司 | Substrate supporting assembly and substrate processing device comprising same |
KR20210010307A (en) | 2019-07-16 | 2021-01-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210010816A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Radical assist ignition plasma system and method |
KR20210010820A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods of forming silicon germanium structures |
US11643724B2 (en) | 2019-07-18 | 2023-05-09 | Asm Ip Holding B.V. | Method of forming structures using a neutral beam |
CN112242296A (en) | 2019-07-19 | 2021-01-19 | Asm Ip私人控股有限公司 | Method of forming topologically controlled amorphous carbon polymer films |
TW202113936A (en) | 2019-07-29 | 2021-04-01 | 荷蘭商Asm Ip私人控股有限公司 | Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation |
CN112309899A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112309900A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
US11587814B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587815B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11227782B2 (en) | 2019-07-31 | 2022-01-18 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
CN112323048B (en) | 2019-08-05 | 2024-02-09 | Asm Ip私人控股有限公司 | Liquid level sensor for chemical source container |
USD965524S1 (en) | 2019-08-19 | 2022-10-04 | Asm Ip Holding B.V. | Susceptor support |
USD965044S1 (en) | 2019-08-19 | 2022-09-27 | Asm Ip Holding B.V. | Susceptor shaft |
JP2021031769A (en) | 2019-08-21 | 2021-03-01 | エーエスエム アイピー ホールディング ビー.ブイ. | Production apparatus of mixed gas of film deposition raw material and film deposition apparatus |
USD949319S1 (en) | 2019-08-22 | 2022-04-19 | Asm Ip Holding B.V. | Exhaust duct |
USD930782S1 (en) | 2019-08-22 | 2021-09-14 | Asm Ip Holding B.V. | Gas distributor |
USD940837S1 (en) | 2019-08-22 | 2022-01-11 | Asm Ip Holding B.V. | Electrode |
USD979506S1 (en) | 2019-08-22 | 2023-02-28 | Asm Ip Holding B.V. | Insulator |
KR20210024423A (en) | 2019-08-22 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for forming a structure with a hole |
KR20210024420A (en) | 2019-08-23 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane |
US11286558B2 (en) | 2019-08-23 | 2022-03-29 | Asm Ip Holding B.V. | Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film |
KR20210029090A (en) | 2019-09-04 | 2021-03-15 | 에이에스엠 아이피 홀딩 비.브이. | Methods for selective deposition using a sacrificial capping layer |
KR20210029663A (en) | 2019-09-05 | 2021-03-16 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11562901B2 (en) | 2019-09-25 | 2023-01-24 | Asm Ip Holding B.V. | Substrate processing method |
CN112593212B (en) | 2019-10-02 | 2023-12-22 | Asm Ip私人控股有限公司 | Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process |
TW202129060A (en) | 2019-10-08 | 2021-08-01 | 荷蘭商Asm Ip控股公司 | Substrate processing device, and substrate processing method |
KR20210043460A (en) | 2019-10-10 | 2021-04-21 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming a photoresist underlayer and structure including same |
KR20210045930A (en) | 2019-10-16 | 2021-04-27 | 에이에스엠 아이피 홀딩 비.브이. | Method of Topology-Selective Film Formation of Silicon Oxide |
US11637014B2 (en) | 2019-10-17 | 2023-04-25 | Asm Ip Holding B.V. | Methods for selective deposition of doped semiconductor material |
KR20210047808A (en) | 2019-10-21 | 2021-04-30 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus and methods for selectively etching films |
US11646205B2 (en) | 2019-10-29 | 2023-05-09 | Asm Ip Holding B.V. | Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same |
KR20210054983A (en) | 2019-11-05 | 2021-05-14 | 에이에스엠 아이피 홀딩 비.브이. | Structures with doped semiconductor layers and methods and systems for forming same |
US11501968B2 (en) | 2019-11-15 | 2022-11-15 | Asm Ip Holding B.V. | Method for providing a semiconductor device with silicon filled gaps |
KR20210062561A (en) | 2019-11-20 | 2021-05-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure |
US11450529B2 (en) | 2019-11-26 | 2022-09-20 | Asm Ip Holding B.V. | Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface |
CN112951697A (en) | 2019-11-26 | 2021-06-11 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112885693A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112885692A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
JP2021090042A (en) | 2019-12-02 | 2021-06-10 | エーエスエム アイピー ホールディング ビー.ブイ. | Substrate processing apparatus and substrate processing method |
KR20210070898A (en) | 2019-12-04 | 2021-06-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11885013B2 (en) | 2019-12-17 | 2024-01-30 | Asm Ip Holding B.V. | Method of forming vanadium nitride layer and structure including the vanadium nitride layer |
KR20210080214A (en) | 2019-12-19 | 2021-06-30 | 에이에스엠 아이피 홀딩 비.브이. | Methods for filling a gap feature on a substrate and related semiconductor structures |
KR20210095050A (en) | 2020-01-20 | 2021-07-30 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming thin film and method of modifying surface of thin film |
TW202130846A (en) | 2020-02-03 | 2021-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming structures including a vanadium or indium layer |
TW202146882A (en) | 2020-02-04 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of verifying an article, apparatus for verifying an article, and system for verifying a reaction chamber |
US11776846B2 (en) | 2020-02-07 | 2023-10-03 | Asm Ip Holding B.V. | Methods for depositing gap filling fluids and related systems and devices |
TW202146715A (en) | 2020-02-17 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for growing phosphorous-doped silicon layer and system of the same |
KR20210116240A (en) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate handling device with adjustable joints |
KR20210116249A (en) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | lockout tagout assembly and system and method of using same |
KR20210117157A (en) | 2020-03-12 | 2021-09-28 | 에이에스엠 아이피 홀딩 비.브이. | Method for Fabricating Layer Structure Having Target Topological Profile |
KR20210124042A (en) | 2020-04-02 | 2021-10-14 | 에이에스엠 아이피 홀딩 비.브이. | Thin film forming method |
TW202146689A (en) | 2020-04-03 | 2021-12-16 | 荷蘭商Asm Ip控股公司 | Method for forming barrier layer and method for manufacturing semiconductor device |
TW202145344A (en) | 2020-04-08 | 2021-12-01 | 荷蘭商Asm Ip私人控股有限公司 | Apparatus and methods for selectively etching silcon oxide films |
US11821078B2 (en) | 2020-04-15 | 2023-11-21 | Asm Ip Holding B.V. | Method for forming precoat film and method for forming silicon-containing film |
KR20210132600A (en) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element |
KR20210132605A (en) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Vertical batch furnace assembly comprising a cooling gas supply |
CN113555279A (en) | 2020-04-24 | 2021-10-26 | Asm Ip私人控股有限公司 | Method of forming vanadium nitride-containing layers and structures including the same |
KR20210134226A (en) | 2020-04-29 | 2021-11-09 | 에이에스엠 아이피 홀딩 비.브이. | Solid source precursor vessel |
KR20210134869A (en) | 2020-05-01 | 2021-11-11 | 에이에스엠 아이피 홀딩 비.브이. | Fast FOUP swapping with a FOUP handler |
KR20210141379A (en) | 2020-05-13 | 2021-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Laser alignment fixture for a reactor system |
KR20210143653A (en) | 2020-05-19 | 2021-11-29 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210145078A (en) | 2020-05-21 | 2021-12-01 | 에이에스엠 아이피 홀딩 비.브이. | Structures including multiple carbon layers and methods of forming and using same |
TW202201602A (en) | 2020-05-29 | 2022-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing device |
US11335569B2 (en) * | 2020-06-17 | 2022-05-17 | Winbond Electronics Corp. | Conductive wire structure and manufacturing method thereof |
TW202218133A (en) | 2020-06-24 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming a layer provided with silicon |
TW202217953A (en) | 2020-06-30 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing method |
KR20220010438A (en) | 2020-07-17 | 2022-01-25 | 에이에스엠 아이피 홀딩 비.브이. | Structures and methods for use in photolithography |
TW202204662A (en) | 2020-07-20 | 2022-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Method and system for depositing molybdenum layers |
US11501804B2 (en) | 2020-08-13 | 2022-11-15 | Micron Technology, Inc. | Microelectronic devices including semiconductive pillar structures, and related electronic systems |
US11812603B2 (en) | 2020-08-13 | 2023-11-07 | Micron Technology, Inc. | Microelectronic devices including semiconductive pillar structures, and related electronic systems |
TW202212623A (en) | 2020-08-26 | 2022-04-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming metal silicon oxide layer and metal silicon oxynitride layer, semiconductor structure, and system |
USD990534S1 (en) | 2020-09-11 | 2023-06-27 | Asm Ip Holding B.V. | Weighted lift pin |
USD1012873S1 (en) | 2020-09-24 | 2024-01-30 | Asm Ip Holding B.V. | Electrode for semiconductor processing apparatus |
TW202229613A (en) | 2020-10-14 | 2022-08-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing material on stepped structure |
TW202217037A (en) | 2020-10-22 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing vanadium metal, structure, device and a deposition assembly |
TW202223136A (en) | 2020-10-28 | 2022-06-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming layer on substrate, and semiconductor processing system |
CN114446869A (en) * | 2020-11-06 | 2022-05-06 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
KR20220076343A (en) | 2020-11-30 | 2022-06-08 | 에이에스엠 아이피 홀딩 비.브이. | an injector configured for arrangement within a reaction chamber of a substrate processing apparatus |
US11946137B2 (en) | 2020-12-16 | 2024-04-02 | Asm Ip Holding B.V. | Runout and wobble measurement fixtures |
TW202231903A (en) | 2020-12-22 | 2022-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate |
US11411006B1 (en) * | 2021-04-16 | 2022-08-09 | Nanya Technology Corporation | Manufacturing method of memory structure |
USD1023959S1 (en) | 2021-05-11 | 2024-04-23 | Asm Ip Holding B.V. | Electrode for substrate processing apparatus |
USD981973S1 (en) | 2021-05-11 | 2023-03-28 | Asm Ip Holding B.V. | Reactor wall for substrate processing apparatus |
USD980813S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas flow control plate for substrate processing apparatus |
USD980814S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas distributor for substrate processing apparatus |
USD990441S1 (en) | 2021-09-07 | 2023-06-27 | Asm Ip Holding B.V. | Gas flow control plate |
Citations (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5047117A (en) * | 1990-09-26 | 1991-09-10 | Micron Technology, Inc. | Method of forming a narrow self-aligned, annular opening in a masking layer |
US5254218A (en) * | 1992-04-22 | 1993-10-19 | Micron Technology, Inc. | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer |
US5411909A (en) * | 1993-02-22 | 1995-05-02 | Micron Technology, Inc. | Method of forming a planar thin film transistor |
US5488011A (en) * | 1994-11-08 | 1996-01-30 | Micron Technology, Inc. | Method of forming contact areas between vertical conductors |
US5573837A (en) * | 1992-04-22 | 1996-11-12 | Micron Technology, Inc. | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer |
US5686357A (en) * | 1995-07-10 | 1997-11-11 | Micron Technology, Inc. | Method for forming a contact during the formation of a semiconductor device |
US5770479A (en) * | 1996-01-11 | 1998-06-23 | Micron Technology, Inc. | Bonding support for leads-over-chip process |
US5835225A (en) * | 1994-11-30 | 1998-11-10 | Micron Technology, Inc. | Surface properties detection by reflectance metrology |
US5851916A (en) * | 1995-11-03 | 1998-12-22 | Micron Technology, Inc. | Formation of a self-aligned integrated circuit structures using planarization to form a top surface |
US5866453A (en) * | 1995-09-14 | 1999-02-02 | Micron Technology, Inc. | Etch process for aligning a capacitor structure and an adjacent contact corridor |
US5869843A (en) * | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US5897372A (en) * | 1995-11-01 | 1999-04-27 | Micron Technology, Inc. | Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer |
US5980349A (en) * | 1997-05-14 | 1999-11-09 | Micron Technology, Inc. | Anodically-bonded elements for flat panel displays |
US6121665A (en) * | 1998-02-27 | 2000-09-19 | Micron Technology, Inc. | Methods of forming field effect transistors and field effect transistor circuitry |
US6124164A (en) * | 1998-09-17 | 2000-09-26 | Micron Technology, Inc. | Method of making integrated capacitor incorporating high K dielectric |
US20010036745A1 (en) * | 1999-09-02 | 2001-11-01 | Micron Technology, Inc. | Method of forming a mask |
US6326652B1 (en) * | 1999-06-18 | 2001-12-04 | Micron Technology, Inc., | CMOS imager with a self-aligned buried contact |
US6328620B1 (en) * | 1998-12-04 | 2001-12-11 | Micron Technology, Inc. | Apparatus and method for forming cold-cathode field emission displays |
US6348411B1 (en) * | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method of making a contact structure |
US6387600B1 (en) * | 1999-08-25 | 2002-05-14 | Micron Technology, Inc. | Protective layer during lithography and etch |
US6420250B1 (en) * | 2000-03-03 | 2002-07-16 | Micron Technology, Inc. | Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates |
US6465865B1 (en) * | 1996-01-05 | 2002-10-15 | Micron Technology, Inc. | Isolated structure and method of fabricating such a structure on a substrate |
US6492212B1 (en) * | 2001-10-05 | 2002-12-10 | International Business Machines Corporation | Variable threshold voltage double gated transistors and method of fabrication |
US6515350B1 (en) * | 2000-02-22 | 2003-02-04 | Micron Technology, Inc. | Protective conformal silicon nitride films and spacers |
US6554671B1 (en) * | 1997-05-14 | 2003-04-29 | Micron Technology, Inc. | Method of anodically bonding elements for flat panel displays |
US6624024B1 (en) * | 2002-08-29 | 2003-09-23 | Micron Technology, Inc. | Method and apparatus for a flash memory device comprising a source local interconnect |
US6656371B2 (en) * | 2001-09-27 | 2003-12-02 | Micron Technology, Inc. | Methods of forming magnetoresisitive devices |
US6823693B1 (en) * | 1998-03-06 | 2004-11-30 | Micron Technology, Inc. | Anodic bonding |
US20050029619A1 (en) * | 2003-08-05 | 2005-02-10 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US20060046422A1 (en) * | 2004-08-31 | 2006-03-02 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US20060046200A1 (en) * | 2004-09-01 | 2006-03-02 | Abatchev Mirzafer K | Mask material conversion |
US7071067B1 (en) * | 1997-06-09 | 2006-07-04 | Micron Technology, Inc. | Fabrication of integrated devices using nitrogen implantation |
US7074717B2 (en) * | 2003-03-04 | 2006-07-11 | Micron Technology, Inc. | Damascene processes for forming conductive structures |
US7202171B2 (en) * | 2001-01-03 | 2007-04-10 | Micron Technology, Inc. | Method for forming a contact opening in a semiconductor device |
US20070224823A1 (en) * | 2006-03-23 | 2007-09-27 | Sandhu Gurtej S | Topography directed patterning |
US20080001187A1 (en) * | 2006-06-29 | 2008-01-03 | Roger Allen Booth | Bulk FinFET Device |
US20080008969A1 (en) * | 2006-07-10 | 2008-01-10 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
US20080057692A1 (en) * | 2006-08-30 | 2008-03-06 | Wells David H | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US7341906B2 (en) * | 2005-05-19 | 2008-03-11 | Micron Technology, Inc. | Method of manufacturing sidewall spacers on a memory device, and device comprising same |
US20080122125A1 (en) * | 2006-11-29 | 2008-05-29 | Micron Technology, Inc. | Methods to reduce the critical dimension of semiconductor devices and partially fabricated semiconductor devices having reduced critical dimensions |
US20080220600A1 (en) * | 2007-03-05 | 2008-09-11 | Micron Technology, Inc. | Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask |
US7435536B2 (en) * | 2004-09-02 | 2008-10-14 | Micron Technology, Inc. | Method to align mask patterns |
US20080299774A1 (en) * | 2007-06-04 | 2008-12-04 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US20090035584A1 (en) * | 2007-07-30 | 2009-02-05 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction and associated structures |
US20090258492A1 (en) * | 2005-06-02 | 2009-10-15 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US20100003797A1 (en) * | 2008-07-03 | 2010-01-07 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage |
US7648919B2 (en) * | 2005-03-28 | 2010-01-19 | Tran Luan C | Integrated circuit fabrication |
US20100092891A1 (en) * | 2005-03-15 | 2010-04-15 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7709390B2 (en) * | 2007-05-31 | 2010-05-04 | Micron Technology, Inc. | Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features |
US20100112489A1 (en) * | 2006-09-14 | 2010-05-06 | Micron Technology, Inc. | Efficient pitch multiplication process |
US7759197B2 (en) * | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US20100203727A1 (en) * | 2004-09-02 | 2010-08-12 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7776744B2 (en) * | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7790531B2 (en) * | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US7808053B2 (en) * | 2006-12-29 | 2010-10-05 | Intel Corporation | Method, apparatus, and system for flash memory |
US7829262B2 (en) * | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7884022B2 (en) * | 2005-03-15 | 2011-02-08 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
US7902074B2 (en) * | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US7993957B2 (en) * | 2002-02-20 | 2011-08-09 | Micron Technology, Inc. | Phase change memory cell and manufacturing method thereof using minitrenches |
US8039399B2 (en) * | 2008-10-09 | 2011-10-18 | Micron Technology, Inc. | Methods of forming patterns utilizing lithography and spacers |
US8334211B2 (en) * | 2006-04-25 | 2012-12-18 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US8389383B1 (en) * | 2011-04-05 | 2013-03-05 | Micron Technology, Inc. | Patterned semiconductor bases, and patterning methods |
US8563229B2 (en) * | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US20130323929A1 (en) * | 2008-03-21 | 2013-12-05 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US20140091434A1 (en) * | 2012-09-28 | 2014-04-03 | Micron Technology, Inc. | Patterned Bases, and Patterning Methods |
US20160225634A1 (en) * | 2015-02-04 | 2016-08-04 | International Business Machines Corporation | Method for quadruple frequency finfets with single-fin removal |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4091406A (en) * | 1976-11-01 | 1978-05-23 | Rca Corporation | Combination glass/low temperature deposited Siw Nx Hy O.sub.z |
US5328810A (en) * | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
US5618383A (en) * | 1994-03-30 | 1997-04-08 | Texas Instruments Incorporated | Narrow lateral dimensioned microelectronic structures and method of forming the same |
US6297129B2 (en) * | 1997-04-22 | 2001-10-02 | Micron Technology, Inc. | Methods of forming integrated circuitry, and methods of forming dynamic random access memory circuitry |
US6025221A (en) * | 1997-08-22 | 2000-02-15 | Micron Technology, Inc. | Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks |
US6573030B1 (en) * | 2000-02-17 | 2003-06-03 | Applied Materials, Inc. | Method for depositing an amorphous carbon layer |
US6688584B2 (en) * | 2001-05-16 | 2004-02-10 | Micron Technology, Inc. | Compound structure for reduced contact resistance |
US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
US6955961B1 (en) * | 2004-05-27 | 2005-10-18 | Macronix International Co., Ltd. | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution |
US7473644B2 (en) * | 2004-07-01 | 2009-01-06 | Micron Technology, Inc. | Method for forming controlled geometry hardmasks including subresolution elements |
US7271106B2 (en) * | 2004-08-31 | 2007-09-18 | Micron Technology, Inc. | Critical dimension control for integrated circuits |
US7442976B2 (en) * | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
KR100640640B1 (en) * | 2005-04-19 | 2006-10-31 | 삼성전자주식회사 | Method of forming fine pattern of semiconductor device using fine pitch hardmask |
US7429536B2 (en) * | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7396781B2 (en) * | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US7572572B2 (en) * | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7687342B2 (en) * | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7393789B2 (en) * | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7375038B2 (en) * | 2005-09-28 | 2008-05-20 | Applied Materials, Inc. | Method for plasma etching a chromium layer through a carbon hard mask suitable for photomask fabrication |
US8003310B2 (en) * | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US7429533B2 (en) * | 2006-05-10 | 2008-09-30 | Lam Research Corporation | Pitch reduction |
US7795149B2 (en) * | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US8367303B2 (en) * | 2006-07-14 | 2013-02-05 | Micron Technology, Inc. | Semiconductor device fabrication and dry develop process suitable for critical dimension tunability and profile control |
US8129289B2 (en) * | 2006-10-05 | 2012-03-06 | Micron Technology, Inc. | Method to deposit conformal low temperature SiO2 |
US7842616B2 (en) * | 2007-01-22 | 2010-11-30 | Advanced Technology Development Facility, Inc. | Methods for fabricating semiconductor structures |
KR100822592B1 (en) * | 2007-03-23 | 2008-04-16 | 주식회사 하이닉스반도체 | Method of forming a micro pattern in a semiconductor device |
US7759242B2 (en) * | 2007-08-22 | 2010-07-20 | Qimonda Ag | Method of fabricating an integrated circuit |
-
2007
- 2007-07-30 US US11/830,449 patent/US8980756B2/en active Active
-
2008
- 2008-07-18 WO PCT/US2008/070407 patent/WO2009017982A2/en active Application Filing
- 2008-07-30 TW TW097128887A patent/TWI391988B/en active
-
2015
- 2015-03-02 US US14/635,023 patent/US20150170905A1/en not_active Abandoned
-
2019
- 2019-01-16 US US16/249,369 patent/US10522348B2/en active Active
- 2019-11-22 US US16/692,440 patent/US11348788B2/en active Active
-
2022
- 2022-05-05 US US17/662,160 patent/US20220262626A1/en active Pending
Patent Citations (172)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5047117A (en) * | 1990-09-26 | 1991-09-10 | Micron Technology, Inc. | Method of forming a narrow self-aligned, annular opening in a masking layer |
US5254218A (en) * | 1992-04-22 | 1993-10-19 | Micron Technology, Inc. | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer |
US5573837A (en) * | 1992-04-22 | 1996-11-12 | Micron Technology, Inc. | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer |
US5411909A (en) * | 1993-02-22 | 1995-05-02 | Micron Technology, Inc. | Method of forming a planar thin film transistor |
US5691547A (en) * | 1993-02-22 | 1997-11-25 | Micron Technology, Inc. | Planar thin film transistor structures |
US5844254A (en) * | 1993-02-22 | 1998-12-01 | Micron Technology, Inc. | Planar thin film transistor structures |
US6049093A (en) * | 1993-02-22 | 2000-04-11 | Micron Technology, Inc. | Planar thin film transistor formation |
US5488011A (en) * | 1994-11-08 | 1996-01-30 | Micron Technology, Inc. | Method of forming contact areas between vertical conductors |
US5835225A (en) * | 1994-11-30 | 1998-11-10 | Micron Technology, Inc. | Surface properties detection by reflectance metrology |
US5869843A (en) * | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US6077729A (en) * | 1995-06-07 | 2000-06-20 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cellis thereof |
US5686357A (en) * | 1995-07-10 | 1997-11-11 | Micron Technology, Inc. | Method for forming a contact during the formation of a semiconductor device |
US5866453A (en) * | 1995-09-14 | 1999-02-02 | Micron Technology, Inc. | Etch process for aligning a capacitor structure and an adjacent contact corridor |
US6274423B1 (en) * | 1995-09-14 | 2001-08-14 | Micron Technology, Inc. | Etch process for aligning a capacitor structure and an adjacent contact corridor |
US5897372A (en) * | 1995-11-01 | 1999-04-27 | Micron Technology, Inc. | Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer |
US6117767A (en) * | 1995-11-01 | 2000-09-12 | Micron Technology, Inc. | Method of forming an integrated circuit structure |
US5851916A (en) * | 1995-11-03 | 1998-12-22 | Micron Technology, Inc. | Formation of a self-aligned integrated circuit structures using planarization to form a top surface |
US6100180A (en) * | 1995-11-03 | 2000-08-08 | Micron Technology Inc | Formation of a self-aligned integrated circuit structure using planarization to form a top surface |
US6420259B1 (en) * | 1995-11-03 | 2002-07-16 | Micron Technology, Inc. | Formation of a self-aligned structure |
US6465865B1 (en) * | 1996-01-05 | 2002-10-15 | Micron Technology, Inc. | Isolated structure and method of fabricating such a structure on a substrate |
US5770479A (en) * | 1996-01-11 | 1998-06-23 | Micron Technology, Inc. | Bonding support for leads-over-chip process |
US6294824B1 (en) * | 1996-01-11 | 2001-09-25 | Micron Technology, Inc. | Bonding support for leads-over-chip process |
US6422906B1 (en) * | 1997-05-14 | 2002-07-23 | Micron Technology, Inc. | Anodically-bonded elements for flat panel displays |
US6545406B2 (en) * | 1997-05-14 | 2003-04-08 | Micron Technology, Inc. | Anodically-bonded elements for flat panel displays |
US6734619B2 (en) * | 1997-05-14 | 2004-05-11 | Micron Technology, Inc. | Anodically bonded elements for flat-panel displays |
US6554671B1 (en) * | 1997-05-14 | 2003-04-29 | Micron Technology, Inc. | Method of anodically bonding elements for flat panel displays |
US5980349A (en) * | 1997-05-14 | 1999-11-09 | Micron Technology, Inc. | Anodically-bonded elements for flat panel displays |
US6981904B2 (en) * | 1997-05-14 | 2006-01-03 | Micron Technology, Inc. | Anodically-bonded elements for flat panel displays |
US6329750B1 (en) * | 1997-05-14 | 2001-12-11 | Micron Technology, Inc. | Anodically-bonded elements for flat panel displays |
US6716080B2 (en) * | 1997-05-14 | 2004-04-06 | Micron Technology, Inc. | Anodically bonded elements for flat-panel displays |
US7071067B1 (en) * | 1997-06-09 | 2006-07-04 | Micron Technology, Inc. | Fabrication of integrated devices using nitrogen implantation |
US6746907B2 (en) * | 1998-02-27 | 2004-06-08 | Micron Technology, Inc. | Methods of forming field effect transistors and field effect transistor circuitry |
US6271067B1 (en) * | 1998-02-27 | 2001-08-07 | Micron Technology, Inc. | Methods of forming field effect transistors and field effect transistor circuitry |
US6958519B2 (en) * | 1998-02-27 | 2005-10-25 | Micron Technology, Inc. | Methods of forming field effect transistors and field effect transistor circuitry |
US6307238B1 (en) * | 1998-02-27 | 2001-10-23 | Micron Technology, Inc. | Methods of forming field effect transistors and field effect transistor circuitry |
US6121665A (en) * | 1998-02-27 | 2000-09-19 | Micron Technology, Inc. | Methods of forming field effect transistors and field effect transistor circuitry |
US6734502B2 (en) * | 1998-02-27 | 2004-05-11 | Micron Technology, Inc. | Field effect transistor circuitry |
US6823693B1 (en) * | 1998-03-06 | 2004-11-30 | Micron Technology, Inc. | Anodic bonding |
US6740916B1 (en) * | 1998-09-03 | 2004-05-25 | Micron Technology, Inc. | Contact structure for integrated circuit devices |
US7968403B2 (en) * | 1998-09-03 | 2011-06-28 | Micron Technology, Inc. | Method of fabricating a sleeve insulator for a contact structure |
US6348411B1 (en) * | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method of making a contact structure |
US7115506B2 (en) * | 1998-09-03 | 2006-10-03 | Micron Technology, Inc. | Method of making a contact structure |
US6124164A (en) * | 1998-09-17 | 2000-09-26 | Micron Technology, Inc. | Method of making integrated capacitor incorporating high K dielectric |
US6351005B1 (en) * | 1998-09-17 | 2002-02-26 | Micron Technology, Inc. | Integrated capacitor incorporating high K dielectric |
US6328620B1 (en) * | 1998-12-04 | 2001-12-11 | Micron Technology, Inc. | Apparatus and method for forming cold-cathode field emission displays |
US6717351B2 (en) * | 1998-12-04 | 2004-04-06 | Micron Technology, Inc. | Apparatus and method for forming cold-cathode field emission displays |
US6767811B2 (en) * | 1999-06-18 | 2004-07-27 | Micron Technology, Inc. | CMOS imager with a self-aligned buried contact |
US6326652B1 (en) * | 1999-06-18 | 2001-12-04 | Micron Technology, Inc., | CMOS imager with a self-aligned buried contact |
US6495434B1 (en) * | 1999-06-18 | 2002-12-17 | Micron Technology, Inc. | CMOS imager with a self-aligned buried contact |
US6844580B2 (en) * | 1999-06-18 | 2005-01-18 | Micron Technology, Inc. | CMOS imager with a self-aligned buried contact |
US7037771B2 (en) * | 1999-06-18 | 2006-05-02 | Micron Technology Inc. | CMOS imager with a self-aligned buried contact |
US6387600B1 (en) * | 1999-08-25 | 2002-05-14 | Micron Technology, Inc. | Protective layer during lithography and etch |
US6475921B2 (en) * | 1999-09-02 | 2002-11-05 | Micron Technology, Inc. | Mask for producing rectangular openings in a substrate |
US6624085B2 (en) * | 1999-09-02 | 2003-09-23 | Micron Technology, Inc. | Semiconductor structure, capacitor, mask and methods of manufacture thereof |
US20010036745A1 (en) * | 1999-09-02 | 2001-11-01 | Micron Technology, Inc. | Method of forming a mask |
US20010036743A1 (en) * | 1999-09-02 | 2001-11-01 | Micron Technology, Inc. | Mask for producing rectangular openings in a substrate |
US6410453B1 (en) * | 1999-09-02 | 2002-06-25 | Micron Technology, Inc. | Method of processing a substrate |
US6455439B2 (en) * | 1999-09-02 | 2002-09-24 | Micron Technology, Inc. | Method of forming a mask |
US6515350B1 (en) * | 2000-02-22 | 2003-02-04 | Micron Technology, Inc. | Protective conformal silicon nitride films and spacers |
US6806175B2 (en) * | 2000-02-22 | 2004-10-19 | Micron Technology, Inc. | Method for forming protective films and spacers |
US6770927B2 (en) * | 2000-03-03 | 2004-08-03 | Micron Technology, Inc. | Structures comprising transistor gates |
US6501114B2 (en) * | 2000-03-03 | 2002-12-31 | Micron Technology, Inc. | Structures comprising transistor gates |
US6420250B1 (en) * | 2000-03-03 | 2002-07-16 | Micron Technology, Inc. | Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates |
US7202171B2 (en) * | 2001-01-03 | 2007-04-10 | Micron Technology, Inc. | Method for forming a contact opening in a semiconductor device |
US6656371B2 (en) * | 2001-09-27 | 2003-12-02 | Micron Technology, Inc. | Methods of forming magnetoresisitive devices |
US20030067017A1 (en) * | 2001-10-05 | 2003-04-10 | Meikei Ieong | Variable threshold voltage double gated transistors and method of fabrication |
US6492212B1 (en) * | 2001-10-05 | 2002-12-10 | International Business Machines Corporation | Variable threshold voltage double gated transistors and method of fabrication |
US7993957B2 (en) * | 2002-02-20 | 2011-08-09 | Micron Technology, Inc. | Phase change memory cell and manufacturing method thereof using minitrenches |
US6624024B1 (en) * | 2002-08-29 | 2003-09-23 | Micron Technology, Inc. | Method and apparatus for a flash memory device comprising a source local interconnect |
US8053899B2 (en) * | 2003-03-04 | 2011-11-08 | Micron Technology, Inc. | Semiconductor devices including damascene trenches with conductive structures |
US7074717B2 (en) * | 2003-03-04 | 2006-07-11 | Micron Technology, Inc. | Damascene processes for forming conductive structures |
US20060267152A1 (en) * | 2003-08-05 | 2006-11-30 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US7153753B2 (en) * | 2003-08-05 | 2006-12-26 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US20050029619A1 (en) * | 2003-08-05 | 2005-02-10 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US7262428B2 (en) * | 2003-08-05 | 2007-08-28 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US20050087842A1 (en) * | 2003-08-05 | 2005-04-28 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US7368790B2 (en) * | 2003-08-05 | 2008-05-06 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US20120044735A1 (en) * | 2004-08-31 | 2012-02-23 | Round Rock Research, Llc. | Structures with increased photo-alignment margins |
US8030222B2 (en) * | 2004-08-31 | 2011-10-04 | Round Rock Research, Llc | Structures with increased photo-alignment margins |
US20060046422A1 (en) * | 2004-08-31 | 2006-03-02 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US20060046200A1 (en) * | 2004-09-01 | 2006-03-02 | Abatchev Mirzafer K | Mask material conversion |
US20130105976A1 (en) * | 2004-09-02 | 2013-05-02 | Micron Technology, Inc. | Method to align mask patterns |
US20100203727A1 (en) * | 2004-09-02 | 2010-08-12 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7435536B2 (en) * | 2004-09-02 | 2008-10-14 | Micron Technology, Inc. | Method to align mask patterns |
US20100092890A1 (en) * | 2004-09-02 | 2010-04-15 | Micron Technology, Inc. | Method to align mask patterns |
US8216949B2 (en) * | 2004-09-02 | 2012-07-10 | Round Rock Research, Llc | Method for integrated circuit fabrication using pitch multiplication |
US8674512B2 (en) * | 2004-09-02 | 2014-03-18 | Micron Technology, Inc. | Method to align mask patterns |
US8338085B2 (en) * | 2004-09-02 | 2012-12-25 | Micron Technology, Inc. | Method to align mask patterns |
US8119535B2 (en) * | 2005-03-15 | 2012-02-21 | Round Rock Research, Llc | Pitch reduced patterns relative to photolithography features |
US8048812B2 (en) * | 2005-03-15 | 2011-11-01 | Round Rock Research, Llc | Pitch reduced patterns relative to photolithography features |
US8207576B2 (en) * | 2005-03-15 | 2012-06-26 | Round Rock Research, Llc | Pitch reduced patterns relative to photolithography features |
US20100092891A1 (en) * | 2005-03-15 | 2010-04-15 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US20120256309A1 (en) * | 2005-03-15 | 2012-10-11 | Luan Tran | Integrated Circuit Having Pitch Reduced Patterns Relative To Photolithography Features |
US7884022B2 (en) * | 2005-03-15 | 2011-02-08 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
US8598632B2 (en) * | 2005-03-15 | 2013-12-03 | Round Rock Research Llc | Integrated circuit having pitch reduced patterns relative to photoithography features |
US20100210111A1 (en) * | 2005-03-15 | 2010-08-19 | Round Rock Research, Llc | Pitch reduced patterns relative to photolithography features |
US9412594B2 (en) * | 2005-03-28 | 2016-08-09 | Micron Technology, Inc. | Integrated circuit fabrication |
US7776683B2 (en) * | 2005-03-28 | 2010-08-17 | Micron Technology, Inc. | Integrated circuit fabrication |
US7648919B2 (en) * | 2005-03-28 | 2010-01-19 | Tran Luan C | Integrated circuit fabrication |
US8158476B2 (en) * | 2005-03-28 | 2012-04-17 | Micron Technology, Inc. | Integrated circuit fabrication |
US9147608B2 (en) * | 2005-03-28 | 2015-09-29 | Micron Technology, Inc. | Integrated circuit fabrication |
US8507341B2 (en) * | 2005-03-28 | 2013-08-13 | Micron Technology, Inc. | Integrated circuit fabrication |
US8859362B2 (en) * | 2005-03-28 | 2014-10-14 | Micron Technology, Inc. | Integrated circuit fabrication |
US7341906B2 (en) * | 2005-05-19 | 2008-03-11 | Micron Technology, Inc. | Method of manufacturing sidewall spacers on a memory device, and device comprising same |
US8865598B2 (en) * | 2005-06-02 | 2014-10-21 | Micron Technology, Inc. | Method for positioning spacers in pitch multiplication |
US8173550B2 (en) * | 2005-06-02 | 2012-05-08 | Micron Technology, Inc. | Method for positioning spacers for pitch multiplication |
US9117766B2 (en) * | 2005-06-02 | 2015-08-25 | Micron Technology, Inc. | Method for positioning spacers in pitch multiplication |
US20110269252A1 (en) * | 2005-06-02 | 2011-11-03 | Micron Technology, Inc. | Method for positioning spacers for pitch multiplication |
US8003542B2 (en) * | 2005-06-02 | 2011-08-23 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US8598041B2 (en) * | 2005-06-02 | 2013-12-03 | Micron Technology, Inc. | Method for positioning spacers in pitch multiplication |
US20120202350A1 (en) * | 2005-06-02 | 2012-08-09 | Micron Technology, Inc. | Method for positioning spacers in pitch multiplication |
US20090258492A1 (en) * | 2005-06-02 | 2009-10-15 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US20140087563A1 (en) * | 2005-06-02 | 2014-03-27 | Micron Technology, Inc. | Method for positioning spacers in pitch multiplication |
US20150024602A1 (en) * | 2005-06-02 | 2015-01-22 | Micron Technology, Inc | Method for positioning spacers in pitch multiplication |
US8609324B2 (en) * | 2005-08-31 | 2013-12-17 | Micron Technology, Inc. | Method of forming pitch multiplied contacts |
US8426118B2 (en) * | 2005-08-31 | 2013-04-23 | Micron Technology, Inc. | Method of forming pitch multiplied contacts |
US7829262B2 (en) * | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US8043915B2 (en) * | 2005-09-01 | 2011-10-25 | Micron Technology, Inc. | Pitch multiplied mask patterns for isolated features |
US9099314B2 (en) * | 2005-09-01 | 2015-08-04 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US20120061807A1 (en) * | 2005-09-01 | 2012-03-15 | Micron Technology, Inc. | Pitch multiplied mask patterns for isolated features |
US8431971B2 (en) * | 2005-09-01 | 2013-04-30 | Micron Technology, Inc. | Pitch multiplied mask patterns for isolated features |
US20100243161A1 (en) * | 2005-09-01 | 2010-09-30 | Micron Technology, Inc. | Pitch multiplied mask patterns for isolated features |
US7759197B2 (en) * | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7776744B2 (en) * | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US20070224823A1 (en) * | 2006-03-23 | 2007-09-27 | Sandhu Gurtej S | Topography directed patterning |
US20130105937A1 (en) * | 2006-04-07 | 2013-05-02 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US9184159B2 (en) * | 2006-04-07 | 2015-11-10 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US7902074B2 (en) * | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US8334211B2 (en) * | 2006-04-25 | 2012-12-18 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US9553082B2 (en) * | 2006-04-25 | 2017-01-24 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US8889020B2 (en) * | 2006-04-25 | 2014-11-18 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US20080001187A1 (en) * | 2006-06-29 | 2008-01-03 | Roger Allen Booth | Bulk FinFET Device |
US7517764B2 (en) * | 2006-06-29 | 2009-04-14 | International Business Machines Corporation | Bulk FinFET device |
US20080008969A1 (en) * | 2006-07-10 | 2008-01-10 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
US20140038416A1 (en) * | 2006-08-30 | 2014-02-06 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate ic structures |
US9478497B2 (en) * | 2006-08-30 | 2016-10-25 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US20080057692A1 (en) * | 2006-08-30 | 2008-03-06 | Wells David H | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US20150054168A1 (en) * | 2006-08-30 | 2015-02-26 | Micron Technology, Inc. | Single Spacer Process for Multiplying Pitch by a Factor Greater Than Two and Related Intermediate IC Structures |
US8883644B2 (en) * | 2006-08-30 | 2014-11-11 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US20100029081A1 (en) * | 2006-08-30 | 2010-02-04 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate ic structures |
US8557704B2 (en) * | 2006-08-30 | 2013-10-15 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US20130256827A1 (en) * | 2006-09-14 | 2013-10-03 | Micron Technology, Inc. | Efficient pitch multiplication process |
US8450829B2 (en) * | 2006-09-14 | 2013-05-28 | Micron Technology, Inc. | Efficient pitch multiplication process |
US8012674B2 (en) * | 2006-09-14 | 2011-09-06 | Micron Technology, Inc. | Efficient pitch multiplication process |
US20100112489A1 (en) * | 2006-09-14 | 2010-05-06 | Micron Technology, Inc. | Efficient pitch multiplication process |
US9035416B2 (en) * | 2006-09-14 | 2015-05-19 | Micron Technology, Inc. | Efficient pitch multiplication process |
US20110291224A1 (en) * | 2006-09-14 | 2011-12-01 | Micron Technology, Inc. | Efficient pitch multiplication process |
US20080122125A1 (en) * | 2006-11-29 | 2008-05-29 | Micron Technology, Inc. | Methods to reduce the critical dimension of semiconductor devices and partially fabricated semiconductor devices having reduced critical dimensions |
US7808053B2 (en) * | 2006-12-29 | 2010-10-05 | Intel Corporation | Method, apparatus, and system for flash memory |
US20080220600A1 (en) * | 2007-03-05 | 2008-09-11 | Micron Technology, Inc. | Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask |
US7709390B2 (en) * | 2007-05-31 | 2010-05-04 | Micron Technology, Inc. | Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features |
US20080299774A1 (en) * | 2007-06-04 | 2008-12-04 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US20090035584A1 (en) * | 2007-07-30 | 2009-02-05 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction and associated structures |
US8980756B2 (en) * | 2007-07-30 | 2015-03-17 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction |
US8563229B2 (en) * | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US9412591B2 (en) * | 2007-07-31 | 2016-08-09 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US8390034B2 (en) * | 2007-12-18 | 2013-03-05 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US8932960B2 (en) * | 2007-12-18 | 2015-01-13 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US7790531B2 (en) * | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US20130323929A1 (en) * | 2008-03-21 | 2013-12-05 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US9048194B2 (en) * | 2008-03-21 | 2015-06-02 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US20100003797A1 (en) * | 2008-07-03 | 2010-01-07 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage |
US8928111B2 (en) * | 2008-07-03 | 2015-01-06 | Micron Technology, Inc. | Transistor with high breakdown voltage having separated drain extensions |
US8076208B2 (en) * | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
US20120074500A1 (en) * | 2008-07-03 | 2012-03-29 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage |
US8039399B2 (en) * | 2008-10-09 | 2011-10-18 | Micron Technology, Inc. | Methods of forming patterns utilizing lithography and spacers |
US20130161799A1 (en) * | 2011-04-05 | 2013-06-27 | Micron Technology, Inc. | Patterned Semiconductor Bases, and Patterning Methods |
US8593001B2 (en) * | 2011-04-05 | 2013-11-26 | Micron Technology, Inc. | Patterned semiconductor bases |
US8389383B1 (en) * | 2011-04-05 | 2013-03-05 | Micron Technology, Inc. | Patterned semiconductor bases, and patterning methods |
US8921034B2 (en) * | 2012-09-28 | 2014-12-30 | Micron Technology, Inc. | Patterned bases, and patterning methods |
US20140091434A1 (en) * | 2012-09-28 | 2014-04-03 | Micron Technology, Inc. | Patterned Bases, and Patterning Methods |
US20160225634A1 (en) * | 2015-02-04 | 2016-08-04 | International Business Machines Corporation | Method for quadruple frequency finfets with single-fin removal |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10522348B2 (en) | 2007-07-30 | 2019-12-31 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction |
US11348788B2 (en) | 2007-07-30 | 2022-05-31 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction |
US20160035571A1 (en) * | 2013-12-04 | 2016-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography Using High Selectivity Spacers for Pitch Reduction |
US9773676B2 (en) * | 2013-12-04 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography using high selectivity spacers for pitch reduction |
US20180012761A1 (en) * | 2013-12-04 | 2018-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography Using High Selectivity Spacers for Pitch Reduction |
US10014175B2 (en) * | 2013-12-04 | 2018-07-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography using high selectivity spacers for pitch reduction |
US10007182B2 (en) | 2016-01-11 | 2018-06-26 | Samsung Electronics Co., Ltd. | Photoresist composition and method of manufacturing semiconductor device using the same |
US9882028B2 (en) * | 2016-06-29 | 2018-01-30 | International Business Machines Corporation | Pitch split patterning for semiconductor devices |
CN109326521A (en) * | 2017-07-31 | 2019-02-12 | 台湾积体电路制造股份有限公司 | Multiple patterning method |
US10763118B2 (en) | 2018-07-11 | 2020-09-01 | International Business Machines Corporation | Cyclic selective deposition for tight pitch patterning |
US10818505B2 (en) | 2018-08-15 | 2020-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned double patterning process and semiconductor structure formed using thereof |
US11676822B2 (en) | 2018-08-15 | 2023-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned double patterning process and semiconductor structure formed using thereof |
Also Published As
Publication number | Publication date |
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WO2009017982A3 (en) | 2009-04-02 |
US20090035584A1 (en) | 2009-02-05 |
US10522348B2 (en) | 2019-12-31 |
US20190148135A1 (en) | 2019-05-16 |
TW200913015A (en) | 2009-03-16 |
WO2009017982A2 (en) | 2009-02-05 |
US20200090929A1 (en) | 2020-03-19 |
US11348788B2 (en) | 2022-05-31 |
US20220262626A1 (en) | 2022-08-18 |
TWI391988B (en) | 2013-04-01 |
US8980756B2 (en) | 2015-03-17 |
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