US20150155263A1 - Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding - Google Patents
Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding Download PDFInfo
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- US20150155263A1 US20150155263A1 US14/096,325 US201314096325A US2015155263A1 US 20150155263 A1 US20150155263 A1 US 20150155263A1 US 201314096325 A US201314096325 A US 201314096325A US 2015155263 A1 US2015155263 A1 US 2015155263A1
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Definitions
- Assemblies of vertically stacked semiconductor chips having direct vertical electrical interconnections using through silicon vias (TSV) offer improvements in integration density and speed of information access.
- TSV through silicon vias
- Wafer-to-wafer bonding techniques can be used to join wafers together in vertically stacked wafer assemblies, which can then be diced into individual stacked semiconductor chip assemblies containing stacks of two or more semiconductor chips each. Each individual stacked semiconductor chip assembly may have through silicon vias extending in a vertical direction of the assembly for electrically connecting the chips therein.
- Wafer-to-wafer bonding techniques include metal-to-metal bonding in which flat metal elements, typically a plurality of discrete metal pads, at a surface of one wafer are joined with corresponding flat metal elements at a surface of a second wafer.
- Hybrid bonding in which metal elements of respective wafers bond together as well as oxide elements of the respective wafers, leave large portions of the respective wafers unbonded, which include among others, kerf regions disposed between adjacent undiced semiconductor chips of a wafer.
- the unbonded areas can provide a potential source of cracking or chipping defects when dicing a stacked wafer assembly into a plurality of individual stacked semiconductor chip assemblies, especially in the case of wafer multi-stacking.
- a method of forming a stacked assembly of semiconductor chips includes metallurgically joining kerf metal elements exposed in a kerf region of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing semiconductor chips of the first wafer with corresponding semiconductor chips of the second wafer which they face.
- the assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including a semiconductor chip of the first wafer and a semiconductor chip of the second wafer affixed therewith.
- a wafer subassembly for use in forming a plurality of individual assemblies of stacked semiconductor chips.
- the wafer subassembly may include a semiconductor wafer and a plurality of kerf metal elements disposed in kerf regions at the surface of the wafer, the kerf regions disposed in dicing lanes between adjacent undiced semiconductor chips of the wafer, the kerf metal elements being configured for direct metal to metal bonding with corresponding kerf metal elements of a second wafer subassembly to form a stacked wafer assembly.
- FIG. 5 is a plan view illustrating a structure of a wafer in accordance with a variation of the embodiment shown in FIG. 3 .
- FIG. 7 is a detailed partial plan view further illustrating a portion of the wafer shown in FIG. 5 in accordance with one variation thereof.
- FIG. 10 is a detailed partial plan view further illustrating a portion of the wafer shown in FIG. 9 .
- first and second wafers can be assembled with one another by metallurgically joining metal elements in the kerf and in the chips.
- the elements in the chip serve as primarily electrical connections, while the elements in the kerf serve primarily as mechanical support and additional crack-stop and delamination protection structures.
- the kerf elements are disposed in dicing lanes of each wafer with corresponding kerf metal elements of the other wafer and affixing undiced semiconductor chips of the first semiconductor wafer with corresponding undiced semiconductor chips of the second wafer. Then the assembled wafers are cut along the dicing lanes into a plurality of assemblies of stacked semiconductor chips. Cutting the assembled wafers with a saw along the dicing lanes typically removes the kerf metal elements such that they are absent from the individual assemblies of stacked semiconductor chips. However, some of these additional kerf structures may also remain on the chip.
- the method can be used in conjunction with assembly techniques in which chip metal elements disposed in undiced semiconductor chips regions of a first wafer are joined with corresponding chip metal elements of a second wafer which they face.
- the method can be used in conjunction with assembly techniques in which oxide elements in undiced semiconductor chips regions of a first wafer face and are joined with corresponding oxide elements of a second wafer.
- the wafers may be thinned prior to joining. For example, with the wafers shown in FIG. 1 , the thickness of the first wafer 100 in a direction orthogonal to its surface 101 can be less than 100 microns between opposite surfaces of the first wafer.
- the corresponding thickness of the second wafer can be less than 100 microns. Referring to FIG.
- First and second wafers 100 , 200 each having metal elements at corresponding surfaces thereof, are shown in a state prior to the metal elements of the first wafer being metallurgically joined with corresponding metal elements of the second wafer.
- First wafer 100 includes undiced semiconductor chips 110 and 112 which are integral portions of a semiconductor wafer, as well as kerf region 120 being another integral portion of the first semiconductor wafer disposed between the undiced semiconductor chips 110 , 120 .
- boundaries 111 , 113 may be somewhat fluid as the width of the kerf region, and hence the exact location of the boundaries can depend upon the width of the cut produced by a saw used to sever the semiconductor chips from one another.
- a bulk semiconductor layer of the first wafer 100 can extend continuously within each of the regions occupied by the undiced first and second semiconductor chips and the kerf region 120 .
- the second wafer 200 has a similar structure of undiced semiconductor chips 210 and 212 which are integral portions of a semiconductor wafer, as well as kerf region 220 being another integral portion of the first semiconductor wafer disposed between the undiced semiconductor chips 210 , 220 .
- Metal crack stop barriers 130 , 230 of each chip are further shown in FIG. 1 , these being within the areas of the undiced semiconductor chips 110 , 112 of the second wafer adjacent to the boundaries 111 , 113 thereof.
- the chips in FIGS. 1 and 2 are shown as aligned and/or bonded in a slightly misaligned state. The slight misalignment that results is not intentional, but rather a tolerable result of processing in accordance with the embodiments of the invention.
- the first wafer 100 further includes a plurality of kerf metal elements 122 in the kerf region 120 at a surface 101 of the first wafer which face corresponding kerf metal elements 222 in the kerf region 220 at a surface 201 of the second wafer.
- a plurality of chip metal elements 132 at surfaces of the undiced semiconductor chips 110 , 112 of the first wafer can be facing corresponding chip metal elements 232 at surfaces of the undiced semiconductor chips 210 , 212 of the second wafer.
- the kerf metal elements and the chip metal elements are metal pads which may be formed of copper and may project above a surface of a dielectric layer, e.g., an oxide layer, at the surface of the wafer.
- the resulting stacked wafer assemblies are cut along the dicing lanes represented by kerf regions 120 , 120 ′ to form a plurality of individual stacked semiconductor chip assemblies.
- the cutting process e.g., sawing process, can result in the removal the kerf metal elements 122 such that the kerf metal elements may be absent from the stacked semiconductor chip assemblies.
- the joined kerf metal elements can provide additional support to the chips of each wafer when dicing the stacked wafer assembly into the individual stacked assemblies of chips and also serve as additional crack-stops and delamination protection. This support can be especially advantageous when, as is common, the wafers have been thinned prior to being joined such that each wafer has a thickness 100 microns or less between its opposite major surfaces.
- FIG. 5 illustrates a variation of the embodiment shown in FIG. 3 , in which the kerf metal elements 522 are provided in the respective kerf regions 120 as a plurality of discrete metal elements which are disposed adjacent to each of the undiced semiconductor chips 100 of each wafer.
- FIG. 6 depicts a particular example in which the length and width dimensions of each kerf metal element 622 in the horizontal and vertical layout directions of the wafer are about the same.
- FIG. 7 depicts another example in which the length dimension of each kerf metal element 722 is much greater than the width dimension of each kerf metal element.
- FIG. 8 depicts yet another example in which the width dimension of each kerf metal element 822 can be greater than the width dimension of each kerf metal element.
- FIGS. 9 and 10 illustrate another variation in which the kerf metal elements include individual rectangular frame elements 922 .
- each individual rectangular frame element 922 surrounds an individual undiced semiconductor chip 100 of one of the wafers.
- the kerf metal elements of each wafer can also include discrete metal elements 924 provided as individually separated pads in the kerf region between the rectangular frame elements 922 .
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Abstract
Description
- The present invention relates to a method for performing direct wafer-to-wafer bonding, including wafer multi-stacking, through metal features such as metal pads, lines, or patterns, on surfaces of the wafer to one another, prior to severing the joined wafers into individual units each containing a chip of a wafer and a chip of another wafer bonded to the wafer.
- Assemblies of vertically stacked semiconductor chips having direct vertical electrical interconnections using through silicon vias (TSV) offer improvements in integration density and speed of information access.
- Wafer-to-wafer bonding techniques can be used to join wafers together in vertically stacked wafer assemblies, which can then be diced into individual stacked semiconductor chip assemblies containing stacks of two or more semiconductor chips each. Each individual stacked semiconductor chip assembly may have through silicon vias extending in a vertical direction of the assembly for electrically connecting the chips therein. Wafer-to-wafer bonding techniques include metal-to-metal bonding in which flat metal elements, typically a plurality of discrete metal pads, at a surface of one wafer are joined with corresponding flat metal elements at a surface of a second wafer.
- Metal-to-metal bonding techniques are subject to variations in bond strength between wafers due to misalignment between the metal elements of one wafer relative to the metal elements of another wafer to which they are to be bonded. Such misalignment can result in metal to oxide contact in a non-controlled fashion, or metal elements of one wafer not bonding with those of the other wafer.
- Hybrid bonding, in which metal elements of respective wafers bond together as well as oxide elements of the respective wafers, leave large portions of the respective wafers unbonded, which include among others, kerf regions disposed between adjacent undiced semiconductor chips of a wafer. The unbonded areas can provide a potential source of cracking or chipping defects when dicing a stacked wafer assembly into a plurality of individual stacked semiconductor chip assemblies, especially in the case of wafer multi-stacking.
- Despite these existing ways of joining wafers to one another, further improvements can be made.
- According to an aspect of the invention, a method of forming a stacked assembly of semiconductor chips includes metallurgically joining kerf metal elements exposed in a kerf region of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing semiconductor chips of the first wafer with corresponding semiconductor chips of the second wafer which they face. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including a semiconductor chip of the first wafer and a semiconductor chip of the second wafer affixed therewith. The simultaneous joining of such kerf metal elements, and optionally crackstop elements, which can be done simultaneously or at a different time than the joining of electrical connection elements for inter-chip connections between respective chips of the assembly, provides mechanical support to the assembly during the subsequent cutting into individual stacked chip assemblies.
- In accordance with another aspect of the invention, a wafer subassembly is provided for use in forming a plurality of individual assemblies of stacked semiconductor chips. The wafer subassembly may include a semiconductor wafer and a plurality of kerf metal elements disposed in kerf regions at the surface of the wafer, the kerf regions disposed in dicing lanes between adjacent undiced semiconductor chips of the wafer, the kerf metal elements being configured for direct metal to metal bonding with corresponding kerf metal elements of a second wafer subassembly to form a stacked wafer assembly.
-
FIG. 1 is a sectional view illustrating first and second wafer assemblies each having metal elements at corresponding surfaces thereof. -
FIG. 2 is a sectional view illustrating a joined stacked wafer assembly formed by joining the first and second wafer assemblies shown inFIG. 1 . -
FIG. 3 is a plan view illustrating a wafer corresponding to the stacked wafer assembly shown inFIG. 2 . -
FIG. 4 is a detailed partial plan view further illustrating a portion of the wafer shown inFIG. 3 . -
FIG. 5 is a plan view illustrating a structure of a wafer in accordance with a variation of the embodiment shown inFIG. 3 . -
FIG. 6 is a detailed partial plan view further illustrating a portion of the wafer shown inFIG. 5 in accordance with one variation thereof. -
FIG. 7 is a detailed partial plan view further illustrating a portion of the wafer shown inFIG. 5 in accordance with one variation thereof. -
FIG. 8 is a detailed partial plan view further illustrating a portion of the wafer shown inFIG. 5 in accordance with one variation thereof. -
FIG. 9 is a plan view illustrating a structure of a wafer in accordance with a variation of the embodiment shown inFIG. 3 . -
FIG. 10 is a detailed partial plan view further illustrating a portion of the wafer shown inFIG. 9 . - As will be described further below, first and second wafers can be assembled with one another by metallurgically joining metal elements in the kerf and in the chips. The elements in the chip serve as primarily electrical connections, while the elements in the kerf serve primarily as mechanical support and additional crack-stop and delamination protection structures. The kerf elements are disposed in dicing lanes of each wafer with corresponding kerf metal elements of the other wafer and affixing undiced semiconductor chips of the first semiconductor wafer with corresponding undiced semiconductor chips of the second wafer. Then the assembled wafers are cut along the dicing lanes into a plurality of assemblies of stacked semiconductor chips. Cutting the assembled wafers with a saw along the dicing lanes typically removes the kerf metal elements such that they are absent from the individual assemblies of stacked semiconductor chips. However, some of these additional kerf structures may also remain on the chip.
- The method can be used in conjunction with assembly techniques in which chip metal elements disposed in undiced semiconductor chips regions of a first wafer are joined with corresponding chip metal elements of a second wafer which they face. In another example, the method can be used in conjunction with assembly techniques in which oxide elements in undiced semiconductor chips regions of a first wafer face and are joined with corresponding oxide elements of a second wafer. The wafers may be thinned prior to joining. For example, with the wafers shown in
FIG. 1 , the thickness of thefirst wafer 100 in a direction orthogonal to itssurface 101 can be less than 100 microns between opposite surfaces of the first wafer. The corresponding thickness of the second wafer can be less than 100 microns. Referring toFIG. 1 , first andsecond wafers First wafer 100 includesundiced semiconductor chips kerf region 120 being another integral portion of the first semiconductor wafer disposed between theundiced semiconductor chips undiced semiconductor chips adjacent kerf region 120 of the first wafer, are shown at 111 and 113, respectively. Theseboundaries wafer 100 shown inFIG. 1 , a bulk semiconductor layer of thefirst wafer 100 can extend continuously within each of the regions occupied by the undiced first and second semiconductor chips and thekerf region 120. Thesecond wafer 200 has a similar structure ofundiced semiconductor chips kerf region 220 being another integral portion of the first semiconductor wafer disposed between theundiced semiconductor chips crack stop barriers FIG. 1 , these being within the areas of theundiced semiconductor chips boundaries FIGS. 1 and 2 are shown as aligned and/or bonded in a slightly misaligned state. The slight misalignment that results is not intentional, but rather a tolerable result of processing in accordance with the embodiments of the invention. - The
first wafer 100 further includes a plurality ofkerf metal elements 122 in thekerf region 120 at asurface 101 of the first wafer which face correspondingkerf metal elements 222 in thekerf region 220 at asurface 201 of the second wafer. In addition, a plurality ofchip metal elements 132 at surfaces of theundiced semiconductor chips chip metal elements 232 at surfaces of theundiced semiconductor chips -
FIG. 2 illustrates a further stage of processing in which thekerf metal elements - Undiced semiconductor chips of the
first wafer 100 are also affixed with corresponding undiced semiconductor chips of thesecond wafer 200. In one example, correspondingchip metal elements -
FIG. 3 further illustrates the corresponding wafer assembly in whichkerf regions 120 which extend in a horizontal layout direction of thewafer 100 are seen therein being generally coextensive with horizontal dicing lanes, andkerf regions 120′ which extend in a vertical layout direction of thewafer 100 and are generally coextensive with vertical dicing lanes. Kerf metal elements inFIG. 3 extend full widths of chords which traverse the generally circular area of thewafer 100. Further detail of the structure shown inFIG. 3 can be seen in the detailed partial plan view provided inFIG. 4 . - Referring to
FIG. 3 , in one example, the kerf metal elements of each wafer may include at least one continuouskerf metal element 322 which has a first portion extending in a first direction of a length of afirst dicing lane 120′ parallel to an edge of a firstundiced semiconductor chip 312 and parallel to an edge of a secondundiced semiconductor chip 312′, and a second portion extending in the first direction, the second portion crossing asecond dicing lane 120 that extends in a second direction between the firstundiced semiconductor chip 312 and the secondundiced semiconductor chip 322. - After joining the kerf metal elements and affixing the undiced semiconductor chips of the respective wafers with one another, the resulting stacked wafer assemblies are cut along the dicing lanes represented by
kerf regions kerf metal elements 122 such that the kerf metal elements may be absent from the stacked semiconductor chip assemblies. - The joined kerf metal elements can provide additional support to the chips of each wafer when dicing the stacked wafer assembly into the individual stacked assemblies of chips and also serve as additional crack-stops and delamination protection. This support can be especially advantageous when, as is common, the wafers have been thinned prior to being joined such that each wafer has a
thickness 100 microns or less between its opposite major surfaces.FIG. 5 illustrates a variation of the embodiment shown inFIG. 3 , in which thekerf metal elements 522 are provided in therespective kerf regions 120 as a plurality of discrete metal elements which are disposed adjacent to each of theundiced semiconductor chips 100 of each wafer.FIGS. 6 , 7, and 8 provide a more detailed view of the kerf metal elements ofFIG. 5 for the portion ofFIG. 5 in the dashed outline therein.FIG. 6 depicts a particular example in which the length and width dimensions of eachkerf metal element 622 in the horizontal and vertical layout directions of the wafer are about the same.FIG. 7 depicts another example in which the length dimension of eachkerf metal element 722 is much greater than the width dimension of each kerf metal element.FIG. 8 depicts yet another example in which the width dimension of eachkerf metal element 822 can be greater than the width dimension of each kerf metal element. -
FIGS. 9 and 10 illustrate another variation in which the kerf metal elements include individualrectangular frame elements 922. In this case, each individualrectangular frame element 922 surrounds an individualundiced semiconductor chip 100 of one of the wafers. In addition to the rectangular frame elements, the kerf metal elements of each wafer can also includediscrete metal elements 924 provided as individually separated pads in the kerf region between therectangular frame elements 922. - While the invention has been described in accordance with certain preferred embodiments thereof, those skilled in the art will understand the many modifications and enhancements which can be made thereto without departing from the true scope and spirit of the invention, which is limited only by the claims appended below.
Claims (20)
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US14/096,325 US9059333B1 (en) | 2013-12-04 | 2013-12-04 | Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding |
US14/716,959 US20150255417A1 (en) | 2013-12-04 | 2015-05-20 | Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding |
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