US20150147862A1 - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
- Publication number
- US20150147862A1 US20150147862A1 US14/612,397 US201514612397A US2015147862A1 US 20150147862 A1 US20150147862 A1 US 20150147862A1 US 201514612397 A US201514612397 A US 201514612397A US 2015147862 A1 US2015147862 A1 US 2015147862A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor device
- transistor
- forming
- involved
- accordance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 460
- 238000000034 method Methods 0.000 title claims description 298
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 239000000758 substrate Substances 0.000 claims abstract description 109
- 238000002955 isolation Methods 0.000 claims description 72
- 238000000059 patterning Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 69
- 229910052814 silicon oxide Inorganic materials 0.000 description 69
- 229910052581 Si3N4 Inorganic materials 0.000 description 47
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 47
- 239000010410 layer Substances 0.000 description 32
- 238000005530 etching Methods 0.000 description 30
- 239000012535 impurity Substances 0.000 description 29
- 238000009792 diffusion process Methods 0.000 description 20
- 230000015654 memory Effects 0.000 description 20
- 229910003481 amorphous carbon Inorganic materials 0.000 description 19
- 239000003990 capacitor Substances 0.000 description 18
- 150000002500 ions Chemical class 0.000 description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 14
- 238000001039 wet etching Methods 0.000 description 14
- 238000001312 dry etching Methods 0.000 description 13
- 230000002093 peripheral effect Effects 0.000 description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 9
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 3
- -1 ammonium fluorosilicate Chemical compound 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
Definitions
- the present invention relates to a semiconductor device, a method of forming a semiconductor device, and a data processing system.
- DRAMs dynamic random access memories
- the recess (trench) FET has a structure in which a trench (also called a groove) is formed in a semiconductor substrate to obtain a channel having a three-dimensional structure.
- Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2005-064500, JP-A-2007-027753, and JP-A-2007-305827 disclose that the fin FET has a structure in which a fin is formed between trenches to obtain a channel having a three-dimensional structure.
- the trench FET is formed by forming a trench in a semiconductor substrate and forming a gate electrode within the trench while a gate insulating film is interposed between the gate electrode and the semiconductor substrate.
- a channel of the trench FET has a three-dimensional structure.
- the fin FET is formed by forming a gate electrode over a gate insulting film so as to cross over a fin protruding from a bottom surface of the trenches formed in the semiconductor substrate. Consequently, the channel has a three-dimensional structure. In any case, it is possible to suppress the short channel effects because the gate length can be lengthened with respect to the channel width.
- the buried gate transistor has a structure in which a gate electrode is buried in the semiconductor substrate.
- the gate electrode of the buried gate transistor does not protrude from the surface of the substrate because the gate electrode (word line) is buried in the semiconductor substrate.
- word line the gate electrode
- bit lines are located over the semiconductor substrate. This will increase flexibility of layouts of capacitors, contact plugs, and the like, which are included in the memory cell and formed over the semiconductor substrate. This will reduce the difficulty of processing the capacitors, the contact plugs, and the like.
- a semiconductor device may include, but is not limited to, a semiconductor substrate including a fin.
- the fin includes first and second fin portions.
- the first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate.
- the second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate.
- the fin has a channel region.
- a semiconductor device may include, but is not limited to, the following elements.
- a semiconductor substrate includes an active region.
- the active region has a fin.
- the fin includes first, second, and third fin portions.
- the first fin portion extends substantially in a first horizontal direction to a surface of the semiconductor substrate.
- the second and third fin portions extend substantially in a vertical direction to the surface of the semiconductor substrate.
- An isolation region defines the active region.
- a word line extends over the isolation region and the active region.
- the word line extends across the fin.
- the word line extends substantially in a second horizontal direction perpendicular to the first horizontal direction.
- the word line has first and second portions.
- the first portion is interposed between the second and third fin portions.
- the second portion is over the isolation region.
- the first portion is smaller in width than the second portion.
- a semiconductor device may include, but is not limited to, the following elements.
- a semiconductor substrate has a fin having a channel region in the vicinity of a surface of the fin.
- the fin includes an end portion.
- the end portion has first and second channel portions of the channel region.
- the first and second channel portions are opposed to each other.
- the first and second channel portions extend substantially vertical to a surface of the semiconductor substrate.
- a diffusion region has a bottom. The bottom is in contact with the end portion and with the first and second channel portions.
- FIG. 1 is a fragmentary plan view illustrating a semiconductor device in accordance with one embodiment of the present invention
- FIG. 2 is a fragmentary enlarged perspective view illustrating part of the semiconductor device shown in FIG. 1 in accordance with one embodiment of the present invention
- FIG. 3 is a fragmentary cross sectional elevation view illustrating a channel structure of the semiconductor device shown in FIG. 1 in accordance with one embodiment of the present invention
- FIG. 4 is a fragmentary cross sectional elevation view illustrating the channel structure of the semiconductor device shown in FIG. 1 in accordance with one embodiment of the present invention
- FIG. 5 is a fragmentary cross sectional elevation view illustrating a channel structure of a semiconductor device in accordance with the related art
- FIG. 6 is a figure showing relationships between a height of a fin portion and a driving current (I on ) in accordance with the semiconductor device of the present invention and the related art;
- FIG. 7 is a figure showing relationships between a height of a fin portion and a threshold voltage (V t ) in accordance with semiconductor device of the present invention and the related art;
- FIG. 8 is a figure showing relationships between a height of a fin portion and a subthreshold swing (SS) in accordance with semiconductor device of the present invention and the related art;
- FIG. 9A is a fragmentary plan view illustrating a transistor in a step involved in the method of forming the semiconductor device shown in FIG. 1 in accordance with one embodiment of the present invention.
- FIG. 9B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 9C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 9D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 9E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 9F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 10A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 10B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 10A , illustrating the transistor in a step, subsequent to the step of FIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 10C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 10A , illustrating the transistor in a step, subsequent to the step of FIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 10D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 10A , illustrating the transistor in a step, subsequent to the step of FIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 10E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 10A , illustrating the transistor in a step, subsequent to the step of FIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 10F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 10A , illustrating the transistor in a step, subsequent to the step of FIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 11A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 11B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 11A , illustrating the transistor in a step, subsequent to the step of FIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 11C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 11A , illustrating the transistor in a step, subsequent to the step of FIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 11D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 11A , illustrating the transistor in a step, subsequent to the step of FIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 11E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 11A , illustrating the transistor in a step, subsequent to the step of FIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 11F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 11A , illustrating the transistor in a step, subsequent to the step of FIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 12A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 12B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 12A , illustrating the transistor in a step, subsequent to the step of FIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 12C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 12A , illustrating the transistor in a step, subsequent to the step of FIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 12D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 12A , illustrating the transistor in a step, subsequent to the step of FIGS. 11A through 11 F, involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 12E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 12A , illustrating the transistor in a step, subsequent to the step of FIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 12F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 12A , illustrating the transistor in a step, subsequent to the step of FIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 13A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 13B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 13A , illustrating the transistor in a step, subsequent to the step of FIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 13C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 13A , illustrating the transistor in a step, subsequent to the step of FIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 13D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 13A , illustrating the transistor in a step, subsequent to the step of FIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 13E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 13A , illustrating the transistor in a step, subsequent to the step of FIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 13F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 13A , illustrating the transistor in a step, subsequent to the step of FIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 14A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 14B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 14A , illustrating the transistor in a step, subsequent to the step of FIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 14C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 14A , illustrating the transistor in a step, subsequent to the step of FIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 14D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 14A , illustrating the transistor in a step, subsequent to the step of FIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 14E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 14A , illustrating the transistor in a step, subsequent to the step of FIGS. 13A through 13 F, involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 14F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 14A , illustrating the transistor in a step, subsequent to the step of FIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 15A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 15B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 15A , illustrating the transistor in a step, subsequent to the step of FIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 15C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 15A , illustrating the transistor in a step, subsequent to the step of FIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 15D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 15A , illustrating the transistor in a step, subsequent to the step of FIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 15E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 15A , illustrating the transistor in a step, subsequent to the step of FIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 15F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 15A , illustrating the transistor in a step, subsequent to the step of FIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 16A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 16B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 16A , illustrating the transistor in a step, subsequent to the step of FIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 16C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 16A , illustrating the transistor in a step, subsequent to the step of FIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 16D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 16A , illustrating the transistor in a step, subsequent to the step of FIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 16E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 16A , illustrating the transistor in a step, subsequent to the step of FIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 16F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 16A , illustrating the transistor in a step, subsequent to the step of FIGS. 15A through 15 F, involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 17A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 17B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 17A , illustrating the transistor in a step, subsequent to the step of FIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 17C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 17A , illustrating the transistor in a step, subsequent to the step of FIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 17D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 17A , illustrating the transistor in a step, subsequent to the step of FIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 17E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 17A , illustrating the transistor in a step, subsequent to the step of FIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 17F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 17A , illustrating the transistor in a step, subsequent to the step of FIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 18A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 18B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 18A , illustrating the transistor in a step, subsequent to the step of FIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 18C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 18A , illustrating the transistor in a step, subsequent to the step of FIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 18D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 18A , illustrating the transistor in a step, subsequent to the step of FIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 18E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 18A , illustrating the transistor in a step, subsequent to the step of FIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 18F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 18A , illustrating the transistor in a step, subsequent to the step of FIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 19A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 19B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 19A , illustrating the transistor in a step, subsequent to the step of FIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 19C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 19A , illustrating the transistor in a step, subsequent to the step of FIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 19D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 19A , illustrating the transistor in a step, subsequent to the step of FIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 19E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 19A , illustrating the transistor in a step, subsequent to the step of FIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 19F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 19A , illustrating the transistor in a step, subsequent to the step of FIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 20A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 20B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 20A , illustrating the transistor in a step, subsequent to the step of FIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 20C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 20A , illustrating the transistor in a step, subsequent to the step of FIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 20D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 20A , illustrating the transistor in a step, subsequent to the step of FIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 20E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 20A , illustrating the transistor in a step, subsequent to the step of FIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 20F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 20A , illustrating the transistor in a step, subsequent to the step of FIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 21A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 21B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 21A , illustrating the transistor in a step, subsequent to the step of FIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 21C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 21A , illustrating the transistor in a step, subsequent to the step of FIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 21D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 21A , illustrating the transistor in a step, subsequent to the step of FIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 21E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 21A , illustrating the transistor in a step, subsequent to the step of FIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 21F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 21A , illustrating the transistor in a step, subsequent to the step of FIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 22A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 22B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 22A , illustrating the transistor in a step, subsequent to the step of FIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 22C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 22A , illustrating the transistor in a step, subsequent to the step of FIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 22D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 22A , illustrating the transistor in a step, subsequent to the step of FIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 22E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 22A , illustrating the transistor in a step, subsequent to the step of FIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 22F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 22A , illustrating the transistor in a step, subsequent to the step of FIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 23A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 23B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 23A , illustrating the transistor in a step, subsequent to the step of FIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 23C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 23A , illustrating the transistor in a step, subsequent to the step of FIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 23D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 23A , illustrating the transistor in a step, subsequent to the step of FIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 23E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 23A , illustrating the transistor in a step, subsequent to the step of FIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 23F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 23A , illustrating the transistor in a step, subsequent to the step of FIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 24A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 24B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 24A , illustrating the transistor in a step, subsequent to the step of FIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 24C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 24A , illustrating the transistor in a step, subsequent to the step of FIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 24D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 24A , illustrating the transistor in a step, subsequent to the step of FIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 24E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 24A , illustrating the transistor in a step, subsequent to the step of FIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 24F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 24A , illustrating the transistor in a step, subsequent to the step of FIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 25A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 25B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 25A , illustrating the transistor in a step, subsequent to the step of FIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 25C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 25A , illustrating the transistor in a step, subsequent to the step of FIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 25D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 25A , illustrating the transistor in a step, subsequent to the step of FIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 25E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 25A , illustrating the transistor in a step, subsequent to the step of FIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 25F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 25A , illustrating the transistor in a step, subsequent to the step of FIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 26A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 26B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 26A , illustrating the transistor in a step, subsequent to the step of FIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 26C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 26A , illustrating the transistor in a step, subsequent to the step of FIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 26D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 26A , illustrating the transistor in a step, subsequent to the step of FIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 26E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 26A , illustrating the transistor in a step, subsequent to the step of FIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 26F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 26A , illustrating the transistor in a step, subsequent to the step of FIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 27A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 27B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 27A , illustrating the transistor in a step, subsequent to the step of FIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 27C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 27A , illustrating the transistor in a step, subsequent to the step of FIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 27D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 27A , illustrating the transistor in a step, subsequent to the step of FIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 27E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 27A , illustrating the transistor in a step, subsequent to the step of FIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 27F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line of FIG. 27A , illustrating the transistor in a step, subsequent to the step of FIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 28A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 27A through 27F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 28B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 28A , illustrating the transistor in a step, subsequent to the step of FIGS. 27A through 27F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 28C is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 28A , illustrating the transistor in a step, subsequent to the step of FIGS. 27A through 27F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 29A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 28A through 28F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention
- FIG. 29B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 29A , illustrating the transistor in a step, subsequent to the step of FIGS. 28A through 28F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 29C is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 29A , illustrating the transistor in a step, subsequent to the step of FIGS. 28A through 28 F, involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 30A is a fragmentary cross sectional elevation view, taken along an X1-X1′ line, illustrating the transistor and a cylindrical capacitor in a step, subsequent to the step of FIGS. 29A through 29F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 30B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line, illustrating the transistor and a crown capacitor in a step, subsequent to the step of FIGS. 27A through 27F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention;
- FIG. 31 is a fragmentary plan view illustrating a semiconductor device in accordance with another embodiment of the present invention.
- FIG. 32 is a fragmentary perspective view illustrating a part of the semiconductor device in accordance with another embodiment of the present invention.
- FIG. 33 is a fragmentary cross sectional elevation view illustrating a channel structure of the semiconductor device shown in FIG. 31 in accordance with another embodiment of the present invention.
- FIG. 34A is a fragmentary plan view illustrating a transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention.
- FIG. 34B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 34A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 34C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 34A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 34D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 34A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 34E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 34A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 35A is a fragmentary plan view illustrating the transistor in a step, subsequent to the step of FIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 35B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 35A , illustrating the transistor in a step, subsequent to the step of FIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 35C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 35A , illustrating the transistor in a step, subsequent to the step of FIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 35D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 35A , illustrating the transistor in a step, subsequent to the step of FIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 35E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 35A , illustrating the transistor in a step, subsequent to the step of FIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 36A is a fragmentary plan view illustrating the transistor in a step, subsequent to the step of FIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 36B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 36A , illustrating the transistor in a step, subsequent to the step of FIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 36C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 36A , illustrating the transistor in a step, subsequent to the step of FIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 36D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 36A , illustrating the transistor in a step, subsequent to the step of FIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 36E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 36A , illustrating the transistor in a step, subsequent to the step of FIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 37A is a fragmentary plan view illustrating the transistor in a step, subsequent to the step of FIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 37B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 37A , illustrating the transistor in a step, subsequent to the step of FIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 37C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 37A , illustrating the transistor in a step, subsequent to the step of FIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 37D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 37A , illustrating the transistor in a step, subsequent to the step of FIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 37E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 37A , illustrating the transistor in a step, subsequent to the step of FIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 38A is a fragmentary plan view illustrating the transistor in a step, subsequent to the step of FIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 38B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 38A , illustrating the transistor in a step, subsequent to the step of FIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 38C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 38A , illustrating the transistor in a step, subsequent to the step of FIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 38D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 38A , illustrating the transistor in a step, subsequent to the step of FIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 38E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 38A , illustrating the transistor in a step, subsequent to the step of FIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 39A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 38A through 38F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 39B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 39A , illustrating the transistor in a step, subsequent to the step of FIGS. 38A through 38F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 39C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 39A , illustrating the transistor in a step, subsequent to the step of FIGS. 38A through 38F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 39D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 39A , illustrating the transistor in a step, subsequent to the step of FIGS. 38A through 38 F, involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 39E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 39A , illustrating the transistor in a step, subsequent to the step of FIGS. 38A through 38F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 40A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 40B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 40A , illustrating the transistor in a step, subsequent to the step of FIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 40C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 40A , illustrating the transistor in a step, subsequent to the step of FIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 40D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 40A , illustrating the transistor in a step, subsequent to the step of FIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 40E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 40A , illustrating the transistor in a step, subsequent to the step of FIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 41A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 41B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 41A , illustrating the transistor in a step, subsequent to the step of FIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 41C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 41A , illustrating the transistor in a step, subsequent to the step of FIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 41D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 41A , illustrating the transistor in a step, subsequent to the step of FIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 41E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 41A , illustrating the transistor in a step, subsequent to the step of FIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 42A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 42B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 42A , illustrating the transistor in a step, subsequent to the step of FIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 42C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 42A , illustrating the transistor in a step, subsequent to the step of FIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 42D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 42A , illustrating the transistor in a step, subsequent to the step of FIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 42E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 42A , illustrating the transistor in a step, subsequent to the step of FIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 43A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 43B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 43A , illustrating the transistor in a step, subsequent to the step of FIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 43C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 43A , illustrating the transistor in a step, subsequent to the step of FIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 43D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 43A , illustrating the transistor in a step, subsequent to the step of FIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 43E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 43A , illustrating the transistor in a step, subsequent to the step of FIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 44A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 44B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 44A , illustrating the transistor in a step, subsequent to the step of FIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention;
- FIG. 44C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 44A , illustrating the transistor in a step, subsequent to the step of FIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 44D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 44A , illustrating the transistor in a step, subsequent to the step of FIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 44E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 44A , illustrating the transistor in a step, subsequent to the step of FIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention
- FIG. 45 is a fragmentary plan view illustrating a semiconductor device in accordance with still another embodiment of the present invention.
- FIG. 46 is a fragmentary perspective view illustrating a part of the semiconductor device shown in FIG. 45 in accordance with still another embodiment of the present invention.
- FIG. 47 is a fragmentary cross sectional elevation view illustrating a channel structure of the semiconductor device shown in FIG. 45 in accordance with still another embodiment of the present invention.
- FIG. 48A is a fragmentary plan view illustrating a transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention.
- FIG. 48B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 48A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 48C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 48A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 48D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 48A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 48E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 48A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 49A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 49B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 49A , illustrating the transistor in a step, subsequent to the step of FIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 49C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 49A , illustrating the transistor in a step, subsequent to the step of FIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 49D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 49A , illustrating the transistor in a step, subsequent to the step of FIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 49E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 49A , illustrating the transistor in a step, subsequent to the step of FIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 50A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 50B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 50A , illustrating the transistor in a step, subsequent to the step of FIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 50C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 50A , illustrating the transistor in a step, subsequent to the step of FIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 50D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 50A , illustrating the transistor in a step, subsequent to the step of FIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 50E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 50A , illustrating the transistor in a step, subsequent to the step of FIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 51A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step of FIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 51B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line of FIG. 51A , illustrating the transistor in a step, subsequent to the step of FIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 51C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line of FIG. 51A , illustrating the transistor in a step, subsequent to the step of FIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 51D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line of FIG. 51A , illustrating the transistor in a step, subsequent to the step of FIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention;
- FIG. 51E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line of FIG. 51A , illustrating the transistor in a step, subsequent to the step of FIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention
- FIG. 52 is a brief configuration diagram illustrating a data processing system including the semiconductor device in accordance with the embodiments of the present invention.
- FIG. 53 is a fragmentary enlarged perspective view illustrating a part of a semiconductor device in accordance with the related art.
- a transistor as shown in FIG. 53 has the channel of the three-dimensional structure described above.
- the transistor is formed as follows.
- An isolation region 101 and an active region 102 are formed in a surface portion of a semiconductor substrate 100 .
- Trench portions 103 and 104 for a buried gate electrode are formed in the isolation region 101 and the active region 102 , respectively.
- a fin portion 107 is a protrusion which is a part of the active region 102 between the trench portions 103 .
- a saddle fin gate electrode 106 is formed by burying a conductive material in the trench portions 103 and 104 while a gate insulating film 105 is interposed between the saddle fin gate electrode 106 and the semiconductor substrate. That is, the saddle fin gate electrode 106 crosses over the fin portion 107 .
- An upper surface 107 a of the fin portion 107 is located to be higher than a bottom surface of the trench portion 103 and to be lower than an upper surface of the active region 102 (an upper surface of the semiconductor substrate 100 ). This is because the trench portion 104 in the active region 102 is shallower than the trench portion 103 formed in the isolation region 102 .
- a source region 108 a and a drain region 108 b are formed, by implanting ions, in two active regions 102 between which the gate electrode 106 is interposed.
- widths of the trench portions 103 and 104 for the buried gate electrode become narrow due to the reduction in dimensions of the memory cell described above.
- widths of channel regions formed in the upper surface 107 a and a side surface 107 b of the fin portion 107 also become narrow in correspondence with the widths of the buried gate trench portions 103 and 104 . Therefore, in some cases, it is difficult to sufficiently secure an ON current due to a short channel effect.
- a semiconductor device may include, but is not limited to, a semiconductor substrate including a fin.
- the fin includes first and second fin portions.
- the first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate.
- the second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate.
- the fin has a channel region.
- the fin further may further include, but is not limited to, a third fin portion extending substantially in the vertical direction.
- the semiconductor device may further include, but is not limited to, source and drain regions having bottoms which contact tops of the second and third fin portions, respectively.
- the semiconductor device may further include, but is not limited to, a first side wall insulating film on a first side surface of the source and a second side wall insulating film on a second side surface of the drain.
- the second side surface faces toward the first side surface.
- the semiconductor device may include, but is not limited to, the following elements.
- the second fin portion has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces.
- the third fin portion has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the forth and fifth side surfaces.
- the third and sixth side surfaces face toward each other.
- the semiconductor device may further include, but is not limited to, a gate insulating film and a gate electrode.
- the gate insulating film covers the first through sixth side surfaces.
- the gate electrode contacts the gate insulating film.
- the gate electrode faces toward the first through sixth side surfaces.
- the gate insulating film is interposed between the gate electrode and the first through sixth side surfaces.
- the semiconductor device may further include, but is not limited to, an isolation region adjacent to the fin.
- the semiconductor device may include, but is not limited to, a top surface of the gate electrode being lower in level than a top surface of the isolation region.
- the semiconductor device may include, but is not limited to, the isolation region having a trench beside the fin.
- a distance between the third and sixth surfaces is smaller than a width of the trench, the width being defined in a direction from the third surface to the sixth surface.
- a semiconductor device may include, but is not limited to, the following elements.
- a semiconductor substrate includes an active region.
- the active region has a fin.
- the fin includes first, second, and third fin portions.
- the first fin portion extends substantially in a first horizontal direction to a surface of the semiconductor substrate.
- the second and third fin portions extend substantially in a vertical direction to the surface of the semiconductor substrate.
- An isolation region defines the active region.
- a word line extends over the isolation region and the active region.
- the word line extends across the fin.
- the word line extends substantially in a second horizontal direction perpendicular to the first horizontal direction.
- the word line has first and second portions.
- the first portion is interposed between the second and third fin portions.
- the second portion is over the isolation region.
- the first portion is smaller in width than the second portion.
- the semiconductor device may further include, but is not limited to, source and drain regions in the active region and a channel region in the active region.
- the channel region is located below the source and drain regions.
- the channel region is formed in the vicinity of a surface region of the fin.
- the semiconductor device may further include, but is not limited to, a first side wall insulating film on a first side surface of the source and a second side wall insulating film on a second side surface of the drain.
- the second side surface faces toward the first side surface.
- the semiconductor device may include, but is not limited to, the following elements.
- the second fin portion has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces.
- the third fin portion has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the forth and fifth side surfaces.
- the third and sixth side surfaces face toward each other.
- the semiconductor device may further include, but is not limited to, a gate insulating film covering the first through sixth side surfaces.
- the first portion contacts the gate insulating film.
- the first portion faces toward the first through sixth side surfaces.
- the gate insulating film is interposed between the first portion and the first through sixth side surfaces.
- the semiconductor device may include, but is not limited to, a top surface of the word line is lower in level than a top surface of the isolation region.
- a semiconductor device may include, but is not limited to, the following elements.
- a semiconductor substrate has a fin having a channel region in the vicinity of a surface of the fin.
- the fin includes an end portion.
- the end portion has first and second channel portions of the channel region.
- the first and second channel portions are opposed to each other.
- the first and second channel portions extend substantially vertical to a surface of the semiconductor substrate.
- a diffusion region has a bottom. The bottom is in contact with the end portion and with the first and second channel portions.
- the semiconductor device may include, but is not limited to, the end portion having a third channel portion of the channel region.
- the third channel portion is adjacent to the first and second channel portions.
- the third channel portion extends substantially vertical to the surface of the semiconductor substrate. The bottom is in contact with the third channel portion.
- the semiconductor device may further include, but is not limited to, a gate insulating film covering the channel region and a gate electrode contacting the gate insulating film.
- the gate electrode faces toward the first through third channel portions.
- the gate insulating film is interposed between the gate electrode and the first through third channel portions.
- the semiconductor device may include, but is not limited to, a top surface of the gate electrode is lower in level than a top surface of the isolation region.
- the semiconductor device may further include, but is not limited to, a first side wall insulating film on a side surface of the diffusion region.
- a method for forming a semiconductor device may include, but is not limited to, the following processes.
- An isolation region is formed in a semiconductor substrate.
- the isolation region defines an active region.
- the active region and the isolation region are selectively etched to form first and second trench portions, respectively.
- the first and second trench portions are adjacent to each other.
- Side surfaces and a bottom surface of the second trench portion are etched to form a fin in the active region.
- the method may further include, but is not limited to, forming a mask over the active region and the isolation region before selectively etching the active region and the isolation region.
- etching the side surfaces and the bottom surface of the second trench portion may include, but is not limited to, etching the side surfaces and the bottom surface of the second trench portion while the mask remains.
- etching the side surfaces and the bottom surface of the second trench portion may include, but is not limited to, wet etching the side surfaces and the bottom surface of the second trench portion.
- etching the side surfaces and the bottom surface of the second trench portion may include, but is not limited to, etching the bottom surface of the second trench portion by an anisotropic etching process and etching the side surfaces and the bottom surface of the second trench portion by an isotropic etching process.
- the method may further include, but is not limited to, forming a conductive film filling the first and second trench portion.
- FIG. 1 is a plan view of the semiconductor device 1 .
- FIG. 2 is a fragmentary enlarged perspective view illustrating part of the semiconductor device 1 .
- the semiconductor device 1 functions as a DRAM. As shown in FIGS. 1 and 2 , the semiconductor device 1 includes a cell array region SA and a peripheral circuit region CA in a semiconductor substrate 2 .
- the peripheral circuit region CA is located in the vicinity of the cell array region SA.
- a plurality of memory cells are arranged in a matrix in the cell array region SA.
- a circuit for controlling operations of each memory cell is disposed in the peripheral circuit area CA.
- Each of the memory cells arranged in the cell array region SA includes a selection transistor and a capacitor electrically connected to any one of a source and a drain of the selection transistor.
- a plurality of isolation regions 5 and a plurality of active regions 6 are alternately arranged in stripes.
- the plurality of active regions 6 are insulated and isolated by the isolation regions 5 .
- the plurality of isolation regions 5 are formed as follows.
- a plurality of isolation trench portions 3 extending in a first direction are formed in the semiconductor substrate 2 .
- the plurality of isolation regions 5 called shallow trench isolation (STI) are formed by burying isolation insulating films 4 (a silicon oxide film 26 and a silicon nitride film 31 ) in the plurality of isolation trench portions 3 .
- a plurality of word lines 7 extend in a second direction crossing the isolation regions 5 and the active regions 6 .
- the plurality of word lines 7 are arranged in stripes.
- the word line 7 includes a gate electrode 8 of the selection transistor.
- the gate electrode 8 is a buried gate electrode.
- the gate electrode 8 is formed as follows. Conductive materials are buried in first and second trench portions 9 and 10 which are buried gate trench portions formed in the isolation region 5 and the active region 6 , respectively while a gate insulating film 11 is interposed between the gate electrode 8 and the semiconductor substrate 2 .
- the first trench portion 9 is formed in the active region 6 in the cell array region SA.
- the second trench portion 10 is formed in the isolation region 5 .
- the second trench portion 10 is greater in depth than the first trench portion 9 .
- the bottom portion of the second trench portion 10 is greater in width in the first direction than the first trench portion 9 .
- the active region 6 includes a fin.
- the fin includes first and second fin portions 12 a and 12 b .
- the first fin portion 12 a protrudes substantially in the vertical direction to the surface of the semiconductor substrate 2 .
- the first fin portion 12 a extends substantially in a horizontal direction to the surface of the semiconductor substrate.
- the first fin portion 12 a is positioned between the second trench portions 10 .
- the second fin portions 12 b protrude substantially in the horizontal direction.
- the second fin portions 12 b extend substantially in the vertical direction.
- the second fin portions 12 b are connected continuously to the first fin portion 12 a .
- the second fin portions 12 b extends continuously from the opposite sides of the first fin portion 12 a .
- Each of the second fin portions 12 b is positioned between the second trench portions 10 .
- the presence of the first fin portion 12 a causes that the second trench portion 10 is greater in depth than the first trench portion 9 .
- the presence of the second fin portions 12 b causes that the bottom portion of the second trench portion 10 is greater in width in the first direction than the first trench portion 9 .
- a third fin (channel) portion 12 c is present.
- the semiconductor device 1 may include, but is not limited to, an isolation insulating film 4 which includes the silicon oxide film 26 and the silicon nitride film 31 .
- the silicon oxide film 26 and the silicon nitride film 31 are sequentially buried in the isolation trench portion 3 .
- the second trench portion 10 includes an upper trench portion 10 a and a lower trench portion 10 b .
- the upper trench portion 10 a is formed in the silicon nitride film 31 so as to have the same width W1 as the first trench portion 9 .
- the lower trench portion 10 b is formed in the silicon oxide film 26 located below the upper trench portion 10 a so as to have a greater width W2 than the width W1 of the upper trench portion 10 a .
- the second trench portion 10 has a cross-sectional shape that is line-symmetric with respect to a line extending in the second direction perpendicular to the first direction and extending through a center of the first trench portion 9 .
- the “width” is defined in the first direction.
- a dimension in a depth direction of the upper trench portion 10 a is the same as thicknesses of a drain region 13 a and a source region 13 b .
- the upper trench portion 10 a is formed in the vicinity of a surface of the active region 6 , that is, the surface portion of the semiconductor substrate 2 .
- the first fin portion 12 a forms a first channel region FCU having the width W1 in the first direction.
- a surface portion of the first fin portion 12 a forms the first channel region FCU.
- the pair of second fin portions 12 b forms second channel regions FCS extending substantially in the vertical direction to the surface of the semiconductor substrate 2 from both ends of the first fin portion 12 a .
- surface portions of the pair of second fin portions 12 b form the second channel regions FCS.
- Each of the second fin portions 12 b has first and second channel portions of the second channel region FCS.
- the fin has the opposite end portions which may, in some cases, be the second fin portions 12 b .
- the first and second channel portions are opposed to each other.
- the first and second channel portions extend substantially in the direction vertical to the surface of the semiconductor substrate.
- the semiconductor device 1 may include, but is not limited to, the gate insulating film 11 covering the surfaces of the first and second fin portions 12 a and 12 b .
- a part of the word line 7 functions as the gate electrode 8 .
- the gate electrode 8 is buried in the buried gate trench portions 9 and 10 so as to cross over the first and second fin portions 12 a and 12 b while the gate insulating film 11 is interposed between the gate electrode 8 and the semiconductor substrate 2 . Therefore, the semiconductor device 1 has a saddle fin channel structure.
- the drain region 13 a and the source region 13 b are respectively provided by implanting ions.
- the drain region 13 a and the source region 13 b function as a source and a drain of the selection transistor, respectively.
- the drain region 13 a and the source region 13 b have bottoms which are connected to the tops of the second fin portions 12 b , which are located under the drain region 13 a and the source region 13 b , respectively.
- the semiconductor device 1 may include, but is not limited to, the gate electrode 8 , the drain region 13 a and the source region 13 b (the impurity diffusion layers), the pair of second fin portions 12 b (the second channel regions FCS), the first fin portion 12 a (the first channel region FCU), and the gate insulating film 11 .
- the gate electrode 8 is located below the surface of the semiconductor substrate 2 .
- the gate electrode 8 is buried in the first and second trench portions 9 and 10 extending in the second direction.
- the gate electrode 8 is interposed between the drain region 13 a and the source region 13 b .
- the drain region 13 a and the source region 13 b respectively have upper surfaces in positions that are higher in level than the upper surface of the gate electrode 8 .
- the pair of second fin portions 12 b (the second channel regions FCS) is continuously connected to the respective bottom surfaces of the drain region 13 a and the source region 13 b .
- the pair of second fin portions 12 b (the second channel regions FCS) extends substantially in the depth direction that is vertical to the surface of the semiconductor substrate 2 from the respective bottom surfaces of the drain region 13 a and the source region 13 b .
- One of the pair of second fin portions 12 b has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces.
- the other of the pair of second fin portions 12 b has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the fourth and fifth side surfaces.
- the third and sixth side surfaces face toward each other.
- the distance between the third and sixth surfaces is smaller than the width of the lower trench portion 10 b .
- the first fin portion 12 a is connected to lower portions of the pair of second fin portions 12 b .
- the first fin portion 12 a extends in the first direction between the pair of second fin portions 12 b .
- the gate insulating film 11 covers the surfaces of the first and second fin portions 12 a and 12 b .
- the gate insulating film 11 covers the first through sixth side surfaces.
- the gate electrode 8 contacts the gate insulating film 11 .
- the gate electrode 8 faces toward the first through sixth side surfaces while the gate insulating film 11 being interposed between the gate electrode and the first through sixth side surfaces.
- the semiconductor device 1 has a buried gate transistor.
- electric charges released from the source region 13 b propagate through one second fin portion 12 b , the first fin portion 12 a , and the other second fin portion 12 b and then enter into the drain region 13 a.
- the pair of second fin portions 12 b (the second channel regions FCS) are provided to extend substantially in the direction vertical to the surface of the semiconductor substrate 2 from both ends of the first fin portion 12 a (the first channel region FCU). Therefore, the pair of second fin portions 12 b (the second channel regions FCS) will ensure the extended length of the channel region in the first direction, as compared to the related art.
- the channel region may include the second channel regions FCS extending in the direction vertical to the surface of the semiconductor substrate 2 , that is, in the direction vertical to the bottom surfaces of the drain region 13 a and the source region 13 b .
- the second channel regions FCS extending in the vertical direction will contribute to suppress the short channel effects of the switching transistor of the semiconductor device 1 , which secures a sufficient ON current I on .
- FIG. 1 schematically shows that some isolation regions 5 and some active regions 6 are arranged and formed in the cell array region SA.
- the dummy word line is a buried wiring for isolation (a dummy gate).
- a predetermined potential is applied to the dummy word line, so that adjacent transistors on the same active region are isolated.
- the parasitic transistor is in an OFF state and isolated by applying the predetermined potential to the dummy word line.
- the dummy word wiring is formed as follows. The trench portions having the same configuration as the word lines 7 are simultaneously formed. A conductive material is buried in the trench portions.
- a method of forming the semiconductor device 1 will be described with reference to FIGS. 9A to 29C .
- FIGS. 9A , 10 A, 11 A, 12 A, 13 A, 14 A, 15 A, 16 A, 17 A, 18 A, 19 A, 20 A, 21 A, 22 A, 23 A, 24 A, 25 A, 26 A, 27 A, 28 A, and 29 A are fragmentary plan views illustrating a transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention.
- FIGS. 9B , 10 B, 11 B, 12 B, 13 B, 14 B, 15 B, 16 B, 17 B, 18 B, 19 B, 20 B, 21 B, 22 B, 23 B, 24 B, 25 B, 26 B, 27 B, 28 B, and 29 B are fragmentary cross-sectional elevation views taken along an X1-X1′ line.
- FIGS. 9C , 10 C, 11 C, 12 C, 13 C, 14 C, 15 C, 16 C, 17 C, 18 C, 19 C, 20 C, 21 C, 22 C, 23 C, 24 C, 25 C, 26 C, and 27 C are cross-sectional elevation views taken along an X2-X2′ line.
- FIGS. 9D , 10 D, 11 D, 12 D, 13 D, 14 D, 15 D, 16 D, 17 D, 18 D, 19 D, 20 D, 21 D, 22 D, 23 D, 24 D, 25 D, 26 D, and 27 D are cross-sectional elevation views taken along a Y1-Y1′ line.
- FIGS. 9D , 10 D, 11 D, 12 D, 13 D, 14 D, 15 D, 16 D, 17 D, 18 D, 19 D, 20 D, 21 D, 22 D, 23 D, 24 D, 25 D, 26 D, and 27 D are cross-sectional elevation views taken along a Y1-Y1′ line.
- FIGS. 9E , 10 E, 11 E, 12 E, 13 E, 14 E, 15 E, 16 E, 17 E, 18 E, 19 E, 20 E, 21 E, 22 E, 23 E, 24 E, 25 E, 26 E, 27 E, 28 C, and 29 C are cross-sectional elevation views taken along a Y2-Y2′ line.
- FIGS. 9F , 10 F, 11 F, 12 F, 13 F, 14 F, 15 F, 16 F, 17 F, 18 F, 19 F, 20 F, 21 F, 22 F, 23 F, 24 F, 25 F, 26 F, and 27 F are cross-sectional elevation views taken along a Y3-Y3′ line.
- the Y1-Y1′ line and the Y2-Y2′ line indicate cross-sectional portions in a region inside the cell array region SA.
- the Y3-Y3′ line indicates a cross-sectional portion in a boundary region crossing over a cell array region SA and a peripheral circuit region CA.
- the isolation regions 5 and the active regions 6 as described above are arranged and formed in plural. However, a state in which some isolation regions 5 and some active regions 6 arranged and formed in the cell array region SA are enlarged is schematically shown for convenience in FIGS.
- a semiconductor substrate 2 is prepared before processing.
- the semiconductor substrate 2 may be, but is not limited to, a single crystal substrate containing a predetermined concentration of impurities, for example, a silicon single crystal substrate containing impurities.
- a mask layer 24 is formed in which a silicon nitride film 21 , an amorphous carbon film 22 , and an antireflective (BARC) film 23 are sequentially stacked.
- a photoresist (PR) is applied on the mask layer 24 .
- the PR is patterned using lithography technique, thereby forming a resist pattern 25 having a shape corresponding to the active region.
- An opening portion 25 a in a position corresponding to an isolation region 5 and an opening portion 25 b in the peripheral circuit region CA are formed using the resist pattern 25 .
- the mask layer 24 is patterned by an anisotropic dry etching process using the resist pattern 25 .
- the resist pattern 25 on the mask layer 24 is removed with the progression of etching.
- the shape of the resist pattern 25 is reflected to the mask layer 24 .
- the mask layer 24 can be patterned to the shape corresponding to the resist pattern 25 .
- the mask layer 24 is also removed while the pattern of the mask layer 24 corresponding to the shape of the resist pattern 25 is maintained with the progression of etching.
- the antireflective (BARC) film 23 is completely removed.
- the mask layer 24 including the amorphous carbon film 22 and the silicon nitride film 21 remains to have an opening portion 24 a in a position corresponding to the isolation region 5 and an opening portion 24 b in the peripheral circuit region CA remains.
- the semiconductor substrate 2 is patterned by an anisotropic dry etching process using the patterned mask layer 24 .
- the shape of the mask layer 24 depends on the surface of the semiconductor substrate 2 .
- a plurality of isolation trench portions 3 extending in the first direction are arranged and formed in stripes.
- a trench portion 3 A with a greater width than the isolation trench portion 3 is formed in the peripheral circuit region CA.
- the amorphous carbon film 22 included in the mask layer 24 is removed by an etching process.
- a silicon oxide film 26 is formed with a thickness sufficient to be buried in the isolation trench portion 3 and the trench portion 3 A by a high-density plasma-chemical vapor deposition (HDP-CVD) method over the entire surface of the semiconductor substrate 2 .
- a surface on which the silicon oxide film 26 is formed is polished by chemical mechanical polishing (CMP) and planarized until the surface of the silicon nitride film 21 serving as a stopper is shown.
- the silicon oxide film 26 is selectively removed by a wet etching process using hydrofluoric acid (HF). Thereby, the silicon oxide film 26 is adjusted to be the same in height as the surface of the semiconductor substrate 2 .
- the silicon nitride film 21 is removed by a wet etching process using hot phosphoric acid (H 3 PO 4 ).
- H 3 PO 4 hot phosphoric acid
- the isolation region 5 and the active region 6 are formed to be alternately adjacent while extending in the first direction. As described above, the isolation region 5 is formed by burying the silicon oxide film 26 in the isolation trench portion 3 as the isolation insulating film 4 .
- the active region 6 is isolated by the isolation region 5 .
- a silicon oxide film 27 is formed by oxidizing the surface of the semiconductor substrate 2 (the active region 6 ) positioned between the silicon oxide films 26 by thermal oxidation (in situ steam generation (ISSG)).
- a non-doped silicon film 28 is formed over the entire surface of the semiconductor substrate 2 .
- Low-concentration N-type impurities phosphorus or the like
- the impurity diffusion layer 29 functions as a drain region 13 a or a source region 13 b of the semiconductor device 1 .
- a photo resist is applied on the semiconductor substrate 2 .
- a resist pattern (not shown) is formed to cover the peripheral circuit region CA while patterning the photo resist by a lithography technique. As shown in FIGS. 14A to 14F , the non-doped silicon film 28 remains on the peripheral circuit region CA, and the non-doped silicon film 28 within the cell array region SA is removed by a dry etching process using the resist pattern.
- a part of the silicon oxide film 26 and the silicon oxide film 27 are selectively removed by an anisotropic selective etching process. Thereby, a trench portion 30 is formed between the impurity diffusion layers 29 in the isolation region 5 .
- a bottom surface of the trench portion 30 is leveled to a top surface of a gate electrode 8 to be formed in a subsequent process which will be described later. That is, an upper surface of the silicon oxide film 26 which forms a bottom surface of the trench portion 30 is the same in level as the upper surface of the gate electrode 8 formed in the subsequent process. Also, the upper surface of the silicon oxide film 26 is the same in level as a bottom surface of the impurity diffusion layer 29 .
- a protective oxide film (not shown) is formed and a silicon nitride film 31 covering the surface of the semiconductor substrate 2 is buried in the trench portion 30 .
- an amorphous carbon film 32 is formed on the silicon nitride film 31 .
- a photo resist is applied on the amorphous carbon film 32 .
- the photo resist is patterned by a lithography technique. Thereby, there is formed a resist pattern (not shown) having opening portions which are located at positions where the buried gate trench portions 9 and 10 will be formed.
- the amorphous carbon film 32 is patterned by a dry etching process using the resist pattern.
- the resist pattern on the amorphous carbon film 32 is removed with the progression of etching.
- the shape of the resist pattern depends on the amorphous carbon film 32 .
- opening portions 32 a are formed in a position where the buried gate trench portions 9 and 10 will be formed.
- parts shown through the opening portion 32 a are removed by an anisotropic etching process using the patterned amorphous carbon film 32 as a mask.
- the amorphous carbon film 32 over the silicon nitride film 31 is also simultaneously removed.
- the silicon nitride film 31 , the silicon oxide film 26 , the impurity diffusion layer 29 , and the surface portion of the semiconductor substrate 2 shown through the opening portion 32 a are etched at the constant speed.
- the first trench portion 9 is formed in at least the surface portion of the semiconductor substrate 2 (the active region 6 ).
- An upper trench portion 10 a serving as a part of the second trench portion 10 is formed in the silicon nitride film 31 (the isolation region 5 ).
- the silicon oxide film 26 forming a bottom surface of the upper trench portion 10 a shown in FIG. 18C is selectively removed by a wet etching process using a solution containing HF as shown in FIGS. 19A to 19F . It is possible to etch the silicon oxide film 26 to the silicon nitride film 31 at a high selectivity using the HF-containing solution. Therefore, the silicon oxide film 26 under the silicon nitride film 31 is selectively removed without removing the silicon nitride film 31 . Because the wet etching process is an isotropic etching process, the silicon oxide film 26 forming the bottom surface of the upper trench portion 10 a is etched in a depth direction and a width direction. Therefore, under the upper trench portion 10 a , a lower trench portion 10 b is formed to be 2 ⁇ W wider than the upper trench portion 10 a.
- the wet etching process by the HF-containing solution is used for forming the lower trench portion 10 b in this embodiment, but the present embodiment is not limited thereto.
- a chemical dry etching method using anhydrous hydrogen fluoride gas and ammonia gas may be used.
- the semiconductor substrate 2 is set in an etching device.
- the semiconductor substrate 2 is kept in the etching device under the condition at 20 mTorr and at 37° C. for 1 minute while a constant amount of anhydrous hydrogen fluoride gas and ammonia gas are supplied to the etching device. Thereby, ammonium fluorosilicate is formed on the surface of the silicon oxide film 26 .
- the ammonium fluorosilicate is sublimed and removed if the temperature is raised to 180° C.
- an etching amount of the silicon oxide film 26 is 5 nm in thickness direction, and the etching amount can be controlled by setting a condition of the chemical dry etching method.
- the silicon oxide film 26 is etched since the chemical dry etching method is an isotropic etching process. Other structure members than the silicon oxide film 26 are not affected by the chemical dry etching method.
- the lower trench portion 10 b can be formed with higher precision than in the above-described wet etching method.
- the second trench portions 10 are formed in the isolation regions 5 of both sides between which the active region 6 is interposed.
- the first fin portion 12 a which is a first part of the active region 6 protruding by ⁇ D in the substantially vertical direction to the surface of the substrate.
- the pair of second fin portions 12 b is formed to be continuously connected to the first fin portion 12 a .
- the pair of second fin portions 12 b extends substantially in the horizontal direction to the surface of the substrate.
- the second fin portions 12 b are second parts of the active region 6 which are shown by ⁇ W from the silicon oxide film 26 .
- the surfaces of the first and second fin portions 12 a and 12 b are oxidized by thermal oxidation (ISSG: In Situ Steam Generation), so that the gate insulating film 11 made of a silicon oxide film is formed.
- a conductive film 33 is formed to cover the surface of the semiconductor substrate 2 and to be buried in the buried gate trench portions 9 and 10 .
- the surface of the conductive film 33 is polished by CMP for planarization until the surface of the silicon nitride film 31 serving as a stopper is shown.
- An etch-back process is performed until the surface of the conductive film 33 is the same in level as the surface of the silicon oxide film 26 as shown in FIG. 21C .
- the gate electrode 8 is formed.
- the gate electrode 8 serves as the word line 7 in the memory cell region SA.
- a silicon oxide film 34 serving as a cap insulating film of the gate electrode 8 is formed by an HDP-CVD method over the entire surface of the semiconductor substrate 2 .
- the surface of the silicon oxide film 34 is polished by CMP for planarization until the surface of the silicon nitride film 31 is shown.
- the silicon nitride film 31 formed in the peripheral circuit region CA serves as the stopper.
- the silicon oxide film 34 is selectively removed by a wet etching process using HF (etch-back process) until a surface of the silicon oxide film 34 is the same in level as the surface of the silicon nitride film 31 formed in the cell array region SA.
- a selection transistor included in a memory cell is formed as the semiconductor device 1 shown in FIGS. 1 and 2 described above in the cell array region SA.
- the pair of second fin portions 12 b (the second channel regions FCS) are formed to extend in the direction vertical to the surface of the semiconductor substrate 2 from both ends of the first fin portion 12 a (the first channel region FCU) as shown in FIG. 3 described above.
- the pair of second fin portions 12 b (the second channel regions FCS) will ensure the extended length of the channel region in the first direction.
- a bit line electrically connected to any one of a source and a drain of the selection transistor, a capacitor electrically connected to the other, and a wiring layer thereon are sequentially formed, so that a DRAM in which a plurality of memory cells are arranged within the cell array region SA can be formed.
- a resist pattern 35 having an opening portion 35 a is formed over the semiconductor substrate 2 .
- the opening portion 35 a is located in a position corresponding to a bit contact hole 36 which will be formed.
- the bit contact hole 36 is a trench for forming the bit line.
- the silicon nitride film 31 shown through the opening portion 35 a is removed by an anisotropic etching process using the resist pattern 35 as a mask.
- the anisotropic etching process is performed until the impurity diffusion layer 29 formed in the cell array region SA and the non-doped silicon film 28 formed in the peripheral circuit region CA are shown.
- the bit contact hole 36 is formed to extend in the direction (the second direction) parallel to the gate electrode 8 .
- a stack of an impurity-containing polysilicon film 37 a and a tungsten silicide film 37 b is formed.
- the stack of an impurity-containing polysilicon film 37 a and a tungsten silicide film 37 b will be processed into the bit line 37 in later steps.
- the impurity-containing polysilicon film 37 a covers the semiconductor substrate 2 .
- the impurity-containing polysilicon film 37 a is buried in the bit contact hole 36 .
- the impurity-containing polysilicon film 37 a may be formed to contain an impurity in the film formation step by a CVD method. In other cases, after the non-doped silicon film is formed, the impurity may be implanted by ion implantation.
- a resist pattern (not shown) is formed to cover a position where the bit line 37 is formed on the stack of an impurity-containing polysilicon film 37 a and a tungsten silicide film 37 b .
- the stack of an impurity-containing polysilicon film 37 a and a tungsten silicide film 37 b is patterned by a dry etching process.
- the bit line 37 is formed to extend in the direction (the second direction) parallel to the gate electrode 8 .
- the bit line 37 may be formed by the following method. After the tungsten silicide film 37 b is formed, a cover silicon nitride film is formed.
- the cover silicon nitride film is patterned to have a predetermined pattern. Further, the underlying tungsten silicide film 37 b and the impurity-containing polysilicon film 37 a are etched using the cover silicon nitride film as a mask.
- a space between the bit lines 37 is filled by applying spin-on dielectrics (SOD) over the semiconductor substrate 2 .
- SOD spin-on dielectrics
- the SOD is modified to solid state by an annealing process, thereby forming an SOD film (an insulating film) 38 .
- a resist pattern (not shown) is formed on the SOD film 38 .
- the resist pattern has an opening portion in a position where a capacitor contact plug will be formed.
- a contact hole 39 is formed by patterning the SOD film 38 by a dry etching process using the resist pattern as a mask.
- a capacitor contact plug 40 is formed by burying a conductive material in the contact hole 39 .
- An insulating film 41 is formed on the SOD film 38 .
- the insulating film 41 has an opening portion in a position overlapping the capacitor contact plug 40 .
- a capacitor contact pad 42 electrically connected to the capacitor contact plug 40 is formed to be buried in the opening portion.
- a capacitor 46 including a lower electrode 43 , a capacitor insulating film 44 , and an upper electrode 45 is formed to overlap the capacitor contact pad 42 .
- the capacitor 46 is not particularly limited. In some cases, there may be provided a cylindrical capacitor structure using only an outer wall of the lower electrode 43 as the electrode shown in FIG. 30A . In other cases, there may be provided a crown capacitor structure using an inner wall and an outer wall of the lower electrode 43 as the electrode shown in FIG. 30B .
- An interlayer insulating film 47 is formed on the capacitor 46 .
- a wiring layer 48 is formed on the interlayer insulating film 47 . Thereby, there is formed a DRAM including the plurality of memory cells arranged within the cell array region SA.
- a semiconductor device 50 as shown in FIGS. 31 and 32 will be described as the second embodiment.
- FIG. 31 is a fragmentary plan view illustrating the semiconductor device 50 .
- FIG. 32 is a fragmentary perspective view in which main parts of the semiconductor device 50 are enlarged.
- the same parts as those of the semiconductor device 1 in the first embodiment are denoted by the same reference numerals in the drawings and their descriptions are omitted.
- the semiconductor device 50 has the following configuration as shown in FIGS. 31 and 32 .
- the isolation insulating film 4 As the isolation insulating film 4 , the silicon oxide film 26 is buried in the isolation trench portion 3 .
- the second trench portion 10 having the upper trench portion 10 a and the lower trench portion 10 b is formed in the silicon oxide film 26 .
- a side wall film 51 (a silicon nitride film) extending in the second direction is formed to cover both side surfaces of the first trench portion 9 and the upper trench portion 10 a described above.
- the silicon nitride film 31 is provided to cover the top of the silicon oxide film 26 .
- the silicon nitride film, which is not on the silicon oxide film 26 is provided as the side wall film 51 to cover both side surfaces of the first trench portion 9 and the upper trench portion 10 a described above.
- the rest of the configuration of the semiconductor device 50 is substantially the same as that of the semiconductor device 1 .
- the first and second fin portions 12 a and 12 b are provided so that a channel region is longer in the first direction than that in the related art.
- the second trench portion 10 includes the upper trench portion 10 a and the lower trench portion 10 b formed in the silicon oxide film 26 .
- the upper trench portion 10 a has the same width W1 as the first trench portion 9 .
- the lower trench portion 10 b is formed under the upper trench portion 10 a .
- the lower trench portion 10 b has a greater width W2 than the upper trench portion 10 a .
- the second trench portion 10 has a cross-sectional shape that is line-symmetric with respect to a line extending in the second direction perpendicular to the first direction and extending through a center of the first trench portion 9 .
- ⁇ D depth of the first trench portion 9
- the first fin portion 12 a in the first trench portion 9 protrudes in the substantially vertical direction to the surface of the substrate by the ⁇ D.
- the first fin portion 12 a provides the first channel region FCU having the width W1 in the first direction.
- the pair of second fin portions 12 b forms second channel regions FCS extending in a direction vertical to the surface of the semiconductor substrate 2 from both ends of the first fin portion 12 a .
- the width in the first direction of the second channel regions FCS (here, the direction perpendicular to the surface of the semiconductor substrate 2 ) is ⁇ D.
- the semiconductor device 50 may include, but is not limited to, the gate insulating film 11 and the gate electrode 8 .
- the gate insulating film 11 covers the surfaces of the first and second fin portions 12 a and 12 b .
- a part of the gate electrode 8 is buried in the buried gate trench portions 9 and 10 so as to extend across the first and second fin portions 12 a and 12 b while the gate insulating film 11 is interposed between the gate electrode 8 and the first fin portion 12 a and between the gate electrode 8 and the second fin portion 12 b . Therefore, the semiconductor device 50 has the saddle fin channel structure.
- the drain region 13 a and the source region 13 b are provided in parts of the active regions 6 between which the gate electrode 8 is interposed.
- the drain region 13 a and the source region 13 b function as the source and the drain of the selection transistor, respectively.
- the drain region 13 a and the source region 13 b are formed by implanting ions.
- the drain region 13 a and the source region 13 b are connected to the tops of the second fin portions 12 b located thereunder.
- the semiconductor device 50 may include, but is not limited to, the gate electrode 8 , the drain region 13 a , the source region 13 b , the first fin portion 12 a (the first channel region FCU), the pair of second fin portions 12 b (the second channel regions FCS), and the gate insulating film 11 .
- the gate electrode 8 is located below the surface of the semiconductor substrate 2 .
- the gate electrode 8 is buried in the first and second trench portions 9 and 10 extending in the second direction.
- the gate electrode 8 is interposed between the drain region 13 a and the source region 13 b .
- the drain region 13 a and the source region 13 b respectively have upper surfaces in positions that are higher than the upper surface of the gate electrode 8 .
- the pair of second fin portions 12 b is continuously connected to the respective bottom surfaces of the drain region 13 a and the source region 13 b .
- the pair of second fin portions 12 b extends substantially in the depth direction (the horizontal direction to the surface of the semiconductor substrate 2 ) from the respective bottom surfaces of the drain region 13 a and the source region 13 b .
- One of the pair of second fin portions 12 b has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces.
- the other of the pair of second fin portions 12 b has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the forth and fifth side surfaces.
- the third and sixth side surfaces face toward each other. A distance between the third and sixth surfaces is smaller than a width of the lower trench portion 10 b .
- the first fin portion 12 a is connected to lower portions of the pair of second fin portions 12 b .
- the first fin portion 12 a extends in the first direction between the pair of second fin portions 12 b .
- the gate insulating film 11 covers the surfaces of the first and second fin portions 12 a and 12 b .
- the gate insulating film 11 covers the first through sixth side surfaces.
- the gate electrode 8 contacts the gate insulating film 11 .
- the gate electrode 8 faces toward the first through sixth side surfaces while the gate insulating film 11 being interposed between the gate electrode and the first through sixth side surfaces. Therefore, the semiconductor device 50 has a buried gate transistor.
- electric charges released from the source region 13 b propagate through one second fin portion 12 b , the first fin portion 12 a , and the other second fin portion 12 b and then enter into the drain region 13 a.
- the pair of second fin portions 12 b (the second channel regions FCS) are provided to extend substantially in the direction vertical to the surface of the semiconductor substrate 2 from both ends of the first fin portion 12 a (the first channel region FCU).
- the pair of second fin portions 12 b (the second channel regions FCS) will ensure the extended length of the channel region in the first direction as compared to the related art.
- the channel region can extend in the direction vertical to the surface of the semiconductor substrate 2 , that is, in the direction vertical to the bottom surfaces of the drain region 13 a and the source region 13 b . Consequently, a sufficient ON current I on can be secured by suppressing short channel effect.
- the silicon oxide film 26 is buried in the isolation trench portion 3 as the isolation insulating film 4 .
- the upper trench portion 10 a and the lower trench portion 10 b included in the second trench portion 10 are formed in the silicon oxide film 26 .
- the side wall film 51 extending in the second direction is formed to cover both side surfaces of the first trench portion 9 and the upper trench portion 10 a described above.
- the side wall film 51 is made of a silicon nitride film to be described later, it is possible to further suppress a junction leak of the drain region 13 a and the source region 13 b (the impurity diffusion layers) from being increased compared to the semiconductor device 1 .
- the side wall films 51 (the silicon nitride film) with small thickness are located on side surfaces of the trench portions 9 and 10 a.
- a method of forming the semiconductor device 50 will be described with reference to FIGS. 34A to 38E .
- FIGS. 34A , 35 A, 36 A, 37 A, and 38 A are fragmentary plan views illustrating a transistor in a step involved in the method of forming the semiconductor device 50 .
- FIGS. 34B , 35 B, 36 B, 37 B, and 38 B are fragmentary cross-sectional elevation views taken along an X1-X1′ line illustrating the transistor in a step involved in the method of forming the semiconductor device 50 .
- FIGS. 34C , 35 C, 36 C, 37 C, and 38 C are fragmentary cross-sectional elevation views taken along an X2-X2′ line illustrating the transistor in a step involved in the method of forming the semiconductor device 50 .
- FIGS. 34A , 35 A, 36 A, 37 A, and 38 A are fragmentary plan views illustrating a transistor in a step involved in the method of forming the semiconductor device 50 .
- FIGS. 34B , 35 B, 36 B, 37 B, and 38 B are fragmentary cross-sectional elevation views taken along an X1-
- FIGS. 34D , 35 D, 36 D, 37 D, and 38 D are fragmentary cross-sectional elevation views taken along an Y1-Y1′ line illustrating the transistor in a step involved in the method of forming the semiconductor device 50 .
- FIGS. 34E , 35 E, 36 E, 37 E, and 38 E are fragmentary cross-sectional elevation views taken along an Y2-Y2′ line illustrating the transistor in a step involved in the method of forming the semiconductor device 50 .
- the line Y1-Y1′ and the line Y2-Y2′ indicate cross-sectional portions in a region inside the cell array region SA.
- FIGS. 34A , 35 A, 36 A, 37 A, and 38 A a plurality of isolation regions 5 and a plurality of active regions 6 are arranged.
- a state in which some isolation regions 5 and some active regions 6 arranged in the cell array region SA are enlarged is schematically shown for convenience in FIGS. 34A , 35 A, 36 A, 37 A, and 38 A.
- the semiconductor device 50 is formed by the processes of forming the semiconductor device 1 shown in FIGS. 9A to 14F , their descriptions are omitted.
- a silicon nitride film 52 and an amorphous carbon film 53 are sequentially stacked over the semiconductor substrate 2 as shown in FIGS. 34A to 34E .
- a photo resist is applied on the amorphous carbon film 53 .
- the photo resist is patterned by a lithography technique. Thereby, a resist pattern (not shown) having an opening portion is formed in a position where the buried gate trench portions 9 and 10 will be formed.
- the amorphous carbon film 53 and the silicon nitride film 52 are patterned by a dry etching process using the resist pattern as a mask. At this time, the resist pattern on the amorphous carbon film 53 is removed with the progression of etching.
- the shape of the resist pattern is reflected to the amorphous carbon film 53 and the silicon nitride film 52 .
- opening portions 53 a and 52 a are formed in a position where the buried gate trench portion 9 will be formed.
- parts shown through the opening portions 53 a and 52 a are removed by an anisotropic etching process using the patterned amorphous carbon film 53 and the patterned silicon nitride film 52 as a mask.
- the amorphous carbon film 53 is also simultaneously removed.
- the silicon oxide film 26 , the impurity diffusion layer 29 , and the surface portion of the semiconductor substrate 2 shown through the opening portion 52 a are etched at the constant speed.
- the first trench portion 9 is formed in at least the surface portion of the semiconductor substrate 2 (the active region 6 ).
- the upper trench portion 10 a serving as a part of the second trench portion 10 is formed in the silicon oxide film 26 .
- a pair of side wall films 51 are formed to cover both side surfaces of the first trench portion 9 and the upper trench portion 10 a .
- a silicon nitride film is formed to cover the surface of the semiconductor substrate 2 .
- the silicon nitride film is formed with such a thickness that it is not completely buried inside the trench portions 9 and 10 a .
- the silicon nitride film is etched back by an anisotropic dry etching process.
- the silicon nitride film remains only on side surfaces of the trench portions 9 and 10 a .
- the side wall films 51 can be formed to cover both side surfaces of the first trench portion 9 and the upper trench portion 10 a.
- the semiconductor substrate 2 (silicon) shown through the first trench portion 9 and the silicon oxide film 26 shown through the upper trench portion 10 a are removed at the constant speed by an etching process. Thereby, a trench portion is formed under the side wall films 51 which are formed on the side surfaces of the trench portions 9 and 10 a.
- the silicon oxide film 26 shown through the upper trench portion 10 a is selectively removed by a wet etching process using a solution containing HF. It is possible to etch the silicon oxide film 26 at a high selectivity to the silicon nitride film (the side wall film 51 ) by using the HF-containing solution. Therefore, the silicon oxide film 26 which is not covered by the silicon nitride film (the side wall film 51 ) is selectively removed without removing the silicon nitride film (the side wall film 51 ).
- the wet etching process is an isotropic etching process.
- the silicon oxide film 26 shown through the upper trench portion 10 a is etched in a depth direction and a width direction. Under the upper trench portion 10 a , the lower trench portion 10 b is formed to be 2 ⁇ W wider than the upper trench portion 10 a as shown in FIG. 38C .
- the wet etching process using the HF-containing solution is used as a method of forming the lower trench portion 10 b in this embodiment, but the present invention is not limited thereto.
- a chemical dry etching method using anhydrous hydrogen fluoride gas and ammonia gas may be used as disclosed in the above-described first embodiment.
- the second trench portions 10 are formed in the isolation regions 5 of both sides between which the active region 6 is interposed.
- a first fin portion 12 a which is a first part of the active region 6 protruding by ⁇ D from the bottom surface of the second trench portion 10 .
- a pair of second fin portions 12 b is formed to be continuous to the first fin portion 12 a .
- the pair of second fin portions 12 b extends in the substantially vertical direction to the surface of the semiconductor substrate 2 .
- the second fin portions 12 b is second parts of the active region 6 which are shown by ⁇ W from the silicon oxide film 26 .
- the surfaces of the first and second fin portions 12 a and 12 b are oxidized by thermal oxidation (ISSG: In Situ Steam Generation), so that the gate insulating film 11 made of a silicon oxide film is formed.
- the conductive film 33 is formed to cover the surface of the semiconductor substrate 2 and to be buried in the buried gate trench portions 9 and 10 .
- the surface of the conductive film 33 is polished by CMP for planarization until the surface of the silicon nitride film 52 serving as a stopper is shown.
- An etch-back process is performed until the surface of the conductive film 33 is substantially the same in level as a bottom of the impurity diffusion layer 29 .
- the gate electrode 8 is formed.
- the gate electrode 8 serves as the word line 7 in the memory cell region SA.
- a silicon oxide film 34 a serving as a cap insulating film of the gate electrode 8 is formed by an HDP-CVD method over the entire surface of the semiconductor substrate 2 .
- the surface of the silicon oxide film 34 is polished by CMP for planarization until the surface of the silicon nitride film 31 is shown.
- the silicon oxide film 34 a is selectively removed by a wet etching process using HF (an etch-back process) until a surface of the silicon oxide film 34 a is the same in level as the surface of the semiconductor substrate 2 . Thereafter, parts of the silicon nitride film 52 and the side wall film 51 described above is removed by a wet etching process using hot phosphoric acid (H 3 PO 4 ).
- a silicon oxide film 34 b is formed by an HDP-CVD method over the entire surface of the semiconductor substrate 2 .
- bit contact hole 36 There is formed a resist pattern (not shown) having an opening portion which is formed in a position where the bit contact hole 36 will be formed. Using the resist pattern as a mask, the silicon oxide film 34 b shown through the opening portion is removed by an anisotropic etching process. The bit contact hole 36 is formed to extend in the direction (second direction) parallel to the gate electrode 8 .
- Processes after the process shown in FIGS. 44A to 44E are basically identical to the processes for forming the semiconductor device 1 shown in FIGS. 26A to 30B , and thus their descriptions are omitted. Through the above processes, the semiconductor device 50 shown in FIGS. 31 and 32 described above can be manufactured.
- FIGS. 45 and 46 Another semiconductor device 70 as shown in FIGS. 45 and 46 will be described as the third embodiment.
- FIG. 45 is a fragmentary plan view illustrating the semiconductor device 70 .
- FIG. 46 is a fragmentary perspective view in which main parts of the semiconductor device 70 are enlarged.
- the same parts as those of the semiconductor device 1 are denoted by the same reference numerals in the drawings and their descriptions are omitted.
- the semiconductor device 70 has the following configuration as shown in FIGS. 45 and 46 .
- the isolation insulating film 4 As the isolation insulating film 4 , the silicon oxide film 26 is buried in the isolation trench portion 3 .
- the upper trench portion 10 a and the lower trench portion 10 b included in the second trench portion 10 are formed. Except that the side wall film 51 (the silicon nitride film) shown in the second embodiment is not provided, the rest of the configuration is substantially the same as that of the semiconductor device 50 .
- the first and second fin portions 12 a and 12 b are provided so that a channel region is longer in the first direction than that in the related art.
- the second trench portion 10 includes the upper trench portion 10 a and the lower trench portion 10 b formed in the silicon oxide film 26 .
- the upper trench portion 10 a has the same width W1 as the first trench portion 9 .
- the lower trench portion 10 b is located under the upper trench portion 10 a .
- the lower trench portion 10 b has a greater width W2 than the upper trench portion 10 a .
- the second trench portion 10 has a cross-sectional shape that is line-symmetric with respect to a line extending in the second direction perpendicular to the first direction and extending through a center of the first trench portion 9 .
- the first fin portion 12 a provides the first channel region FCU having the width W1 in the first direction.
- a surface portion of the first fin portion 12 a forms the first channel region FCU.
- the pair of second fin portions 12 b forms the second channel regions FCS extending in the direction vertical to the surface of the semiconductor substrate 2 from both ends of the first fin portion 12 a .
- surface portions of the pair of second fin portions 12 b form the second channel region FCS.
- Each of the second fin portions 12 b includes an end portion having first and second channel portions of the second channel region FCS.
- the first and second channel portions are opposed to each other.
- the first and second channel portions extend substantially vertical to a surface of the semiconductor substrate.
- the semiconductor device 70 may include, but is not limited to, the gate insulating film 11 and the gate electrode 8 .
- the gate insulating film 11 covers the surfaces of the first and second fin portions 12 a and 12 b .
- a part of the word line 7 functions as the gate electrode 8 .
- the gate electrode 8 is buried in the buried gate trench portions 9 and 10 so as to cross over the first and second fin portions 12 a and 12 b while the gate insulating film 11 is interposed between the gate electrode 8 and the first fin portion 12 a and between the gate electrode 8 and the second fin portion 12 b .
- the semiconductor device 70 has the saddle fin channel structure.
- the drain region 13 a and the source region 13 b (the impurity diffusion layers) are provided.
- the drain region 13 a and the source region 13 b function as the source and the drain of the selection transistor, respectively.
- the drain region 13 a and the source region 13 b are formed by implanting ions.
- the drain region 13 a and the source region 13 b have bottoms which are connected to the tops of the second fin portions 12 b located under the drain region 13 a and the source region 13 b , respectively.
- the semiconductor device 70 may include, but is not limited to, the gate electrode 8 , the drain region 13 a and the source region 13 b (the impurity diffusion layers), the first fin portion 12 a (the first channel region FCU), the pair of second fin portions 12 b (the second channel regions FCS), and the gate insulating film 11 .
- the gate electrode 8 is located below the surface of the semiconductor substrate 2 .
- the gate electrode 8 is buried in the first and second trench portions 9 and 10 extending in the second direction.
- the drain region 13 a and the source region 13 b are located on both sides between which the gate electrode 8 is interposed.
- the drain region 13 a and the source region 13 b respectively have upper surfaces in positions that are higher than the upper surface of the gate electrode 8 .
- the pair of second fin portions 12 b is connected to the respective bottom surfaces of the drain region 13 a and the source region 13 b .
- the pair of second fin portions 12 b extends substantially in the depth direction (the horizontal direction to the surface of the semiconductor substrate 2 ) from the respective bottom surfaces of the drain region 13 a and the source region 13 b .
- One of the pair of second fin portions 12 b has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces.
- the other of the pair of second fin portions 12 b has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the forth and fifth side surfaces.
- the third and sixth side surfaces face toward each other. The distance between the third and sixth surfaces is smaller than the width of the lower trench portion 10 b .
- the first fin portion 12 a is connected to lower portions of the pair of second fin portions 12 b .
- the first fin portion 12 a extends in the first direction between the pair of second fin portions 12 b .
- the gate insulating film 11 covers the surfaces of the first and second fin portions 12 a and 12 b .
- the gate insulating film 11 covers the first through sixth side surfaces.
- the gate electrode 8 contacts the gate insulating film 11 .
- the gate electrode 8 faces toward the first through sixth side surfaces while the gate insulating film 11 being interposed between the gate electrode 8 and the first through sixth side surfaces. Therefore, the semiconductor device 70 has the buried gate transistor.
- an electric charge released from the source region 13 b enters the drain region 13 a by sequentially passing through one second fin portion 12 b , the first fin portion 12 a , and the other second fin portion 12 b.
- the pair of second fin portions 12 b (the second channel regions FCS) are provided to extend in the direction vertical to the surface of the semiconductor substrate 2 from both ends of the first fin portion 12 a (the first channel region FCU) in the first direction.
- the pair of second fin portions 12 b (the second channel regions FCS) will ensure the extended length of the channel region in the first direction as compared to the related art.
- the channel region can extend in the direction vertical to the surface of the semiconductor substrate 2 , that is, in the direction vertical to the bottom surfaces of the drain region 13 a and the source region 13 b . Consequently, a sufficient ON current can be secured by suppressing a short channel effect.
- the silicon oxide film 26 is buried in the isolation trench portion 3 as the isolation insulating film 4 .
- the upper trench portion 10 a and the lower trench portion 10 b included in the first trench portion 10 are formed in the silicon oxide film 26 .
- the side wall film 51 is removed.
- junction leakage can be further suppressed because there is no silicon nitride film in the vicinity of the drain region 13 a and the source region 13 b (the impurity diffusion layers) in the semiconductor device 70 .
- a method of forming the semiconductor device 70 will be described with reference to FIGS. 48A to 51E .
- FIGS. 48A , 49 A, 50 A, and 51 A are fragmentary plan views illustrating a transistor in a step involved in the method of forming the semiconductor device 70 .
- FIGS. 48B , 49 B, 50 B, and 51 B are fragmentary cross-sectional elevation views taken along an X1-X1′ line illustrating the transistor in a step involved in the method of forming the semiconductor device 70 .
- FIGS. 48C , 49 C, 50 C, and 51 C are fragmentary cross-sectional elevation views taken along an X2-X2′ line illustrating the transistor in a step involved in the method of forming the semiconductor device 70 .
- FIGS. 48A , 49 A, 50 A, and 51 A are fragmentary plan views illustrating a transistor in a step involved in the method of forming the semiconductor device 70 .
- FIGS. 48B , 49 B, 50 B, and 51 B are fragmentary cross-sectional elevation views taken along an X1-X1′ line illustrating the transistor in a step involved in the
- FIGS. 48D , 49 D, 50 D, and 51 D are fragmentary cross-sectional elevation views taken along an Y1-Y1′ line illustrating the transistor in a step involved in the method of forming the semiconductor device 70 .
- FIGS. 48E , 49 E, 50 E, and 51 E are fragmentary cross-sectional elevation views taken along an Y2-Y2′ line illustrating the transistor in a step involved in the method of forming the semiconductor device 70 .
- the line Y1-Y1′ and the line Y2-Y2′ indicate cross-sectional portions in a region inside the cell array region SA.
- FIGS. 48A , 49 A, 50 A, and 51 A a plurality of isolation regions 5 and a plurality of active regions 6 are arranged.
- a state in which some isolation regions 5 and some active regions 6 arranged and formed in the cell array region SA are enlarged is schematically shown for convenience in FIGS. 48A , 49 A, 50 A, and 51 A.
- the semiconductor device 70 is formed by the processes of forming the semiconductor device 1 shown in FIGS. 9A to 14F . Thereafter, the semiconductor device 70 is formed by the processes of forming the semiconductor device 50 shown in FIGS. 34A to 38E . Therefore, their descriptions are omitted.
- the side wall film 51 and the silicon nitride film 52 are removed by a wet etching process using a hot phosphoric acid (H 3 PO 4 ) after the process shown in FIGS. 38A to 38E .
- H 3 PO 4 hot phosphoric acid
- the surfaces of the first and second fin portions 12 a and 12 b are oxidized by thermal oxidation (ISSG: In Situ Steam Generation), so that the gate insulating film 11 made of a silicon oxide film is formed.
- the conductive film 33 is formed to cover the surface of the semiconductor substrate 2 and to be buried in the buried gate trench portions 9 and 10 .
- the surface of the conductive film 33 is polished by CMP for planarization until the surface of the silicon oxide film 27 serving as a stopper is shown. An etch-back process is performed until the surface of the conductive film 33 is substantially the same in level as the bottom of the diffusion layer 29 . Thereby, the gate electrode 8 is formed. The top surface of the gate electrode 8 is lower in level than the top surface of the isolation region 5 .
- the gate electrode 8 serves as the word line 7 in the memory cell region SA.
- the silicon oxide film 34 a is formed by an HDP-CVD method over the entire surface of the semiconductor substrate 2 .
- the silicon oxide film 34 a has a sufficient thickness to be buried in the trench portions 9 and 10 .
- the surface of the conductive film 34 a is polished by CMP for planarization until the surface of the silicon oxide film 27 serving as a stopper is shown.
- the silicon oxide film 34 a serves as a cap insulating film of the gate electrode 8 .
- the silicon oxide film 34 b is formed by an HDP-CVD method over the entire surface of the semiconductor substrate 2 .
- a resist pattern (not shown) having an opening portion which is formed in a position where the bit contact hole 36 will be formed.
- the silicon oxide film 34 b shown through the opening portion is removed by an anisotropic etching process.
- the bit contact hole 36 is formed to extend in the direction (second direction) parallel to the gate electrode 8 .
- Processes after the process shown in FIGS. 51A to 51E are basically identical to the processes for forming the semiconductor device 1 shown in FIGS. 26A to 30B , and thus their descriptions are omitted. Through the above processes, the semiconductor device 70 shown in FIGS. 45 and 46 described above can be manufactured.
- the data processing system 400 is an example of a system including the semiconductor device 1 , 50 , or 70 .
- the data processing system 400 may include, but is not limited to, a computer system.
- the data processing system 400 may include, but is not limited to, a data processor 420 and a DRAM 460 according to the first through third embodiments.
- the data processor 420 may include, but is not limited to, a microprocessor (MPU), a digital signal processor (DSP), or the like.
- the data processor 420 is connected to the DRAM 460 via a system bus 410 . However, it may be connected by a local bus without involving the system bus 410 .
- One system bus 410 is shown in FIG. 52 , but serial and parallel connections may be made via a connector or the like, if necessary.
- a storage device 430 , an I/O device 440 , and a ROM 450 of the data processing system 400 are connected to the system bus 410 , if necessary, but are not essential constituent elements.
- the I/O device 440 may be only any one of an input device or an output device.
- the number of each element in the data processing system 400 is not particularly limited, and may be at least one or more.
- the comparison evaluation test was performed by comparing the characteristics of driving currents I on , threshold voltages V t , and subthreshold swings (SS) between the semiconductor device of the present invention shown in FIG. 4 and the semiconductor device of the related art shown in FIG. 5 . Evaluation results of the driving currents I on , the threshold voltages V t , and the subthreshold swings (SS) are respectively shown in FIGS. 6 to 8 .
- a current pass (CP) of an arrow shown in FIGS. 4 and 5 indicates a current path serving as a channel.
- the semiconductor device of the present invention shown in FIG. 4 has the same saddle fin channel structure as the semiconductor device 1 shown in FIG. 3 .
- the pair of second fin portions 12 b (the second channel regions FCS) are provided to extend in the direction vertical to the surface of the semiconductor substrate 2 from both ends of the first fin portion 12 a (the first channel region FCU).
- the source region 13 a and the drain region 13 b are provided on the pair of second fin portions 12 b .
- the gate electrode 8 is buried in the buried gate trench portions 9 and 10 .
- the semiconductor device of the related art shown in FIG. 5 is the same as the semiconductor device 1 shown in FIG. 3 , except that it has the saddle fin channel structure having only the first fin portion 12 a (the first channel region FCU).
- the results of the driving currents I on , the threshold voltages V t , and the subthreshold swings (SS) were evaluated when a protrusion amount ⁇ D of the first fin portion 12 a was 0, 10, and 20 nm.
- the results of the driving currents I on , the threshold voltages V t , and the subthreshold swings (SS) were evaluated in the same manner as the semiconductor device of the present invention.
- a protrusion amount ⁇ W of the second fin portion 12 b in the semiconductor device of the present invention was designated as 10 nm and all of a physical size, an applied voltage, and the like had the same conditions.
- the semiconductor device of the present invention (solid line) is greater in I on value than the semiconductor device of the related art (broken line) by about 3 ⁇ A.
- the driving current of the transistor needs to have stable characteristics for a stable operation of the semiconductor device even when the transistor is miniaturized. It is preferable that the driving current of the transistor have a large value. Therefore, it can be seen that the semiconductor device of the present invention is superior to the semiconductor device of the related art.
- the semiconductor device of the present invention (solid line) is less in V t value than the semiconductor device of the related art (broken line) as a whole.
- the semiconductor device of the present invention is less in V t value than the semiconductor device of the related art by about 0.07V.
- the threshold voltage of the transistor be a low voltage to satisfy the requirement of low power consumption of the semiconductor device. Therefore, it can be seen that the semiconductor device of the present invention is superior to the semiconductor device of the related art.
- the semiconductor device of the present invention (solid line) is less in subthreshold swings (SS) than the semiconductor device of the related art (broken line) as a whole.
- the semiconductor device of the present invention is less in subthreshold swings (SS) than the semiconductor device of the related art (broken line) by about 6 mV/decade.
- the subthreshold swing of the transistor is an ON/OFF characteristic index. From a point of view of a high-speed operation of the semiconductor device, it is preferable that the subthreshold swing be a small value. Therefore, it can be seen that the semiconductor device of the present invention is superior to the semiconductor device of the related art.
- the semiconductor device of the present invention has results indicating superiority to the semiconductor device of the related art in the respective characteristics of the threshold voltage V t , the driving current I on , and the subthreshold swing (SS).
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate. The fin has a channel region.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device, a method of forming a semiconductor device, and a data processing system.
- Priority is claimed on Japanese Patent Application No. 2010-115538, May 19, 2010, the content of which is incorporated herein by reference.
- 2. Description of the Related Art
- Recently, dimensions of transistors have become smaller due to miniaturization of semiconductor elements. The dimensional reductions of the transistors will cause remarkable short channel effects of the transistors. As the dimensions of memory cells in dynamic random access memories (DRAMs) and the like are reduced, the channel lengths of transistors are also reduced, which may cause degradation of the performance of transistors. The deterioration in retention of memory cells or writing characteristics has been problematic.
- In view of the above, recess (trench) field effect transistors (FETs), fin FETs, and the like have been developed. The recess (trench) FET has a structure in which a trench (also called a groove) is formed in a semiconductor substrate to obtain a channel having a three-dimensional structure. Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2005-064500, JP-A-2007-027753, and JP-A-2007-305827 disclose that the fin FET has a structure in which a fin is formed between trenches to obtain a channel having a three-dimensional structure.
- The trench FET is formed by forming a trench in a semiconductor substrate and forming a gate electrode within the trench while a gate insulating film is interposed between the gate electrode and the semiconductor substrate. A channel of the trench FET has a three-dimensional structure. The fin FET is formed by forming a gate electrode over a gate insulting film so as to cross over a fin protruding from a bottom surface of the trenches formed in the semiconductor substrate. Consequently, the channel has a three-dimensional structure. In any case, it is possible to suppress the short channel effects because the gate length can be lengthened with respect to the channel width.
- A study has been carried out to adopt buried gate transistors for selecting transistors included in memory cells in the DRAMs due to reduction in size of the memory cell. The buried gate transistor has a structure in which a gate electrode is buried in the semiconductor substrate.
- The gate electrode of the buried gate transistor does not protrude from the surface of the substrate because the gate electrode (word line) is buried in the semiconductor substrate. Among wirings connected to memory cells, only bit lines are located over the semiconductor substrate. This will increase flexibility of layouts of capacitors, contact plugs, and the like, which are included in the memory cell and formed over the semiconductor substrate. This will reduce the difficulty of processing the capacitors, the contact plugs, and the like.
- In one embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate. The fin has a channel region.
- In another embodiment, a semiconductor device may include, but is not limited to, the following elements. A semiconductor substrate includes an active region. The active region has a fin. The fin includes first, second, and third fin portions. The first fin portion extends substantially in a first horizontal direction to a surface of the semiconductor substrate. The second and third fin portions extend substantially in a vertical direction to the surface of the semiconductor substrate. An isolation region defines the active region. A word line extends over the isolation region and the active region. The word line extends across the fin. The word line extends substantially in a second horizontal direction perpendicular to the first horizontal direction. The word line has first and second portions. The first portion is interposed between the second and third fin portions. The second portion is over the isolation region. The first portion is smaller in width than the second portion.
- In still another embodiment, a semiconductor device may include, but is not limited to, the following elements. A semiconductor substrate has a fin having a channel region in the vicinity of a surface of the fin. The fin includes an end portion. The end portion has first and second channel portions of the channel region. The first and second channel portions are opposed to each other. The first and second channel portions extend substantially vertical to a surface of the semiconductor substrate. A diffusion region has a bottom. The bottom is in contact with the end portion and with the first and second channel portions.
- The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a fragmentary plan view illustrating a semiconductor device in accordance with one embodiment of the present invention; -
FIG. 2 is a fragmentary enlarged perspective view illustrating part of the semiconductor device shown inFIG. 1 in accordance with one embodiment of the present invention; -
FIG. 3 is a fragmentary cross sectional elevation view illustrating a channel structure of the semiconductor device shown inFIG. 1 in accordance with one embodiment of the present invention; -
FIG. 4 is a fragmentary cross sectional elevation view illustrating the channel structure of the semiconductor device shown inFIG. 1 in accordance with one embodiment of the present invention; -
FIG. 5 is a fragmentary cross sectional elevation view illustrating a channel structure of a semiconductor device in accordance with the related art; -
FIG. 6 is a figure showing relationships between a height of a fin portion and a driving current (Ion) in accordance with the semiconductor device of the present invention and the related art; -
FIG. 7 is a figure showing relationships between a height of a fin portion and a threshold voltage (Vt) in accordance with semiconductor device of the present invention and the related art; -
FIG. 8 is a figure showing relationships between a height of a fin portion and a subthreshold swing (SS) in accordance with semiconductor device of the present invention and the related art; -
FIG. 9A is a fragmentary plan view illustrating a transistor in a step involved in the method of forming the semiconductor device shown inFIG. 1 in accordance with one embodiment of the present invention; -
FIG. 9B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 9C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 9D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 9E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 9F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 9A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 10A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 10B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 10A , illustrating the transistor in a step, subsequent to the step ofFIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 10C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 10A , illustrating the transistor in a step, subsequent to the step ofFIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 10D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 10A , illustrating the transistor in a step, subsequent to the step ofFIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 10E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 10A , illustrating the transistor in a step, subsequent to the step ofFIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 10F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 10A , illustrating the transistor in a step, subsequent to the step ofFIGS. 9A through 9F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 11A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 11B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 11A , illustrating the transistor in a step, subsequent to the step ofFIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 11C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 11A , illustrating the transistor in a step, subsequent to the step ofFIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 11D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 11A , illustrating the transistor in a step, subsequent to the step ofFIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 11E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 11A , illustrating the transistor in a step, subsequent to the step ofFIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 11F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 11A , illustrating the transistor in a step, subsequent to the step ofFIGS. 10A through 10F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 12A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 12B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 12A , illustrating the transistor in a step, subsequent to the step ofFIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 12C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 12A , illustrating the transistor in a step, subsequent to the step ofFIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 12D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 12A , illustrating the transistor in a step, subsequent to the step ofFIGS. 11A through 11F, involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 12E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 12A , illustrating the transistor in a step, subsequent to the step ofFIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 12F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 12A , illustrating the transistor in a step, subsequent to the step ofFIGS. 11A through 11F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 13A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 13B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 13A , illustrating the transistor in a step, subsequent to the step ofFIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 13C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 13A , illustrating the transistor in a step, subsequent to the step ofFIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 13D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 13A , illustrating the transistor in a step, subsequent to the step ofFIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 13E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 13A , illustrating the transistor in a step, subsequent to the step ofFIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 13F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 13A , illustrating the transistor in a step, subsequent to the step ofFIGS. 12A through 12F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 14A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 14B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 14A , illustrating the transistor in a step, subsequent to the step ofFIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 14C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 14A , illustrating the transistor in a step, subsequent to the step ofFIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 14D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 14A , illustrating the transistor in a step, subsequent to the step ofFIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 14E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 14A , illustrating the transistor in a step, subsequent to the step ofFIGS. 13A through 13F, involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 14F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 14A , illustrating the transistor in a step, subsequent to the step ofFIGS. 13A through 13F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 15A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 15B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 15A , illustrating the transistor in a step, subsequent to the step ofFIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 15C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 15A , illustrating the transistor in a step, subsequent to the step ofFIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 15D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 15A , illustrating the transistor in a step, subsequent to the step ofFIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 15E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 15A , illustrating the transistor in a step, subsequent to the step ofFIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 15F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 15A , illustrating the transistor in a step, subsequent to the step ofFIGS. 14A through 14F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 16A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 16B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 16A , illustrating the transistor in a step, subsequent to the step ofFIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 16C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 16A , illustrating the transistor in a step, subsequent to the step ofFIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 16D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 16A , illustrating the transistor in a step, subsequent to the step ofFIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 16E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 16A , illustrating the transistor in a step, subsequent to the step ofFIGS. 15A through 15F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 16F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 16A , illustrating the transistor in a step, subsequent to the step ofFIGS. 15A through 15F, involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 17A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 17B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 17A , illustrating the transistor in a step, subsequent to the step ofFIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 17C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 17A , illustrating the transistor in a step, subsequent to the step ofFIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 17D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 17A , illustrating the transistor in a step, subsequent to the step ofFIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 17E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 17A , illustrating the transistor in a step, subsequent to the step ofFIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 17F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 17A , illustrating the transistor in a step, subsequent to the step ofFIGS. 16A through 16F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 18A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 18B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 18A , illustrating the transistor in a step, subsequent to the step ofFIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 18C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 18A , illustrating the transistor in a step, subsequent to the step ofFIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 18D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 18A , illustrating the transistor in a step, subsequent to the step ofFIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 18E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 18A , illustrating the transistor in a step, subsequent to the step ofFIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 18F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 18A , illustrating the transistor in a step, subsequent to the step ofFIGS. 17A through 17F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 19A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 19B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 19A , illustrating the transistor in a step, subsequent to the step ofFIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 19C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 19A , illustrating the transistor in a step, subsequent to the step ofFIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 19D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 19A , illustrating the transistor in a step, subsequent to the step ofFIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 19E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 19A , illustrating the transistor in a step, subsequent to the step ofFIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 19F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 19A , illustrating the transistor in a step, subsequent to the step ofFIGS. 18A through 18F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 20A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 20B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 20A , illustrating the transistor in a step, subsequent to the step ofFIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 20C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 20A , illustrating the transistor in a step, subsequent to the step ofFIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 20D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 20A , illustrating the transistor in a step, subsequent to the step ofFIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 20E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 20A , illustrating the transistor in a step, subsequent to the step ofFIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 20F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 20A , illustrating the transistor in a step, subsequent to the step ofFIGS. 19A through 19F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 21A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 21B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 21A , illustrating the transistor in a step, subsequent to the step ofFIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 21C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 21A , illustrating the transistor in a step, subsequent to the step ofFIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 21D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 21A , illustrating the transistor in a step, subsequent to the step ofFIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 21E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 21A , illustrating the transistor in a step, subsequent to the step ofFIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 21F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 21A , illustrating the transistor in a step, subsequent to the step ofFIGS. 20A through 20F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 22A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 22B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 22A , illustrating the transistor in a step, subsequent to the step ofFIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 22C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 22A , illustrating the transistor in a step, subsequent to the step ofFIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 22D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 22A , illustrating the transistor in a step, subsequent to the step ofFIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 22E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 22A , illustrating the transistor in a step, subsequent to the step ofFIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 22F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 22A , illustrating the transistor in a step, subsequent to the step ofFIGS. 21A through 21F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 23A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 23B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 23A , illustrating the transistor in a step, subsequent to the step ofFIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 23C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 23A , illustrating the transistor in a step, subsequent to the step ofFIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 23D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 23A , illustrating the transistor in a step, subsequent to the step ofFIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 23E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 23A , illustrating the transistor in a step, subsequent to the step ofFIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 23F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 23A , illustrating the transistor in a step, subsequent to the step ofFIGS. 22A through 22F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 24A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 24B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 24A , illustrating the transistor in a step, subsequent to the step ofFIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 24C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 24A , illustrating the transistor in a step, subsequent to the step ofFIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 24D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 24A , illustrating the transistor in a step, subsequent to the step ofFIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 24E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 24A , illustrating the transistor in a step, subsequent to the step ofFIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 24F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 24A , illustrating the transistor in a step, subsequent to the step ofFIGS. 23A through 23F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 25A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 25B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 25A , illustrating the transistor in a step, subsequent to the step ofFIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 25C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 25A , illustrating the transistor in a step, subsequent to the step ofFIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 25D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 25A , illustrating the transistor in a step, subsequent to the step ofFIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 25E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 25A , illustrating the transistor in a step, subsequent to the step ofFIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 25F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 25A , illustrating the transistor in a step, subsequent to the step ofFIGS. 24A through 24F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 26A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 26B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 26A , illustrating the transistor in a step, subsequent to the step ofFIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 26C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 26A , illustrating the transistor in a step, subsequent to the step ofFIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 26D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 26A , illustrating the transistor in a step, subsequent to the step ofFIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 26E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 26A , illustrating the transistor in a step, subsequent to the step ofFIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 26F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 26A , illustrating the transistor in a step, subsequent to the step ofFIGS. 25A through 25F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 27A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 27B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 27A , illustrating the transistor in a step, subsequent to the step ofFIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 27C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 27A , illustrating the transistor in a step, subsequent to the step ofFIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 27D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 27A , illustrating the transistor in a step, subsequent to the step ofFIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 27E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 27A , illustrating the transistor in a step, subsequent to the step ofFIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 27F is a fragmentary cross sectional elevation view, taken along a Y3-Y3′ line ofFIG. 27A , illustrating the transistor in a step, subsequent to the step ofFIGS. 26A through 26F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 28A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 27A through 27F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 28B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 28A , illustrating the transistor in a step, subsequent to the step ofFIGS. 27A through 27F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 28C is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 28A , illustrating the transistor in a step, subsequent to the step ofFIGS. 27A through 27F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 29A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 28A through 28F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 29B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 29A , illustrating the transistor in a step, subsequent to the step ofFIGS. 28A through 28F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 29C is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 29A , illustrating the transistor in a step, subsequent to the step ofFIGS. 28A through 28F, involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 30A is a fragmentary cross sectional elevation view, taken along an X1-X1′ line, illustrating the transistor and a cylindrical capacitor in a step, subsequent to the step ofFIGS. 29A through 29F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 30B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line, illustrating the transistor and a crown capacitor in a step, subsequent to the step ofFIGS. 27A through 27F , involved in the method of forming the semiconductor device in accordance with one embodiment of the present invention; -
FIG. 31 is a fragmentary plan view illustrating a semiconductor device in accordance with another embodiment of the present invention; -
FIG. 32 is a fragmentary perspective view illustrating a part of the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 33 is a fragmentary cross sectional elevation view illustrating a channel structure of the semiconductor device shown inFIG. 31 in accordance with another embodiment of the present invention; -
FIG. 34A is a fragmentary plan view illustrating a transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 34B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 34A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 34C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 34A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 34D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 34A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 34E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 34A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 35A is a fragmentary plan view illustrating the transistor in a step, subsequent to the step ofFIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 35B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 35A , illustrating the transistor in a step, subsequent to the step ofFIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 35C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 35A , illustrating the transistor in a step, subsequent to the step ofFIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 35D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 35A , illustrating the transistor in a step, subsequent to the step ofFIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 35E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 35A , illustrating the transistor in a step, subsequent to the step ofFIGS. 34A through 34F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 36A is a fragmentary plan view illustrating the transistor in a step, subsequent to the step ofFIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 36B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 36A , illustrating the transistor in a step, subsequent to the step ofFIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 36C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 36A , illustrating the transistor in a step, subsequent to the step ofFIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 36D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 36A , illustrating the transistor in a step, subsequent to the step ofFIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 36E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 36A , illustrating the transistor in a step, subsequent to the step ofFIGS. 35A through 35F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 37A is a fragmentary plan view illustrating the transistor in a step, subsequent to the step ofFIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 37B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 37A , illustrating the transistor in a step, subsequent to the step ofFIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 37C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 37A , illustrating the transistor in a step, subsequent to the step ofFIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 37D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 37A , illustrating the transistor in a step, subsequent to the step ofFIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 37E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 37A , illustrating the transistor in a step, subsequent to the step ofFIGS. 36A through 36F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 38A is a fragmentary plan view illustrating the transistor in a step, subsequent to the step ofFIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 38B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 38A , illustrating the transistor in a step, subsequent to the step ofFIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 38C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 38A , illustrating the transistor in a step, subsequent to the step ofFIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 38D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 38A , illustrating the transistor in a step, subsequent to the step ofFIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 38E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 38A , illustrating the transistor in a step, subsequent to the step ofFIGS. 37A through 37F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 39A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 38A through 38F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 39B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 39A , illustrating the transistor in a step, subsequent to the step ofFIGS. 38A through 38F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 39C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 39A , illustrating the transistor in a step, subsequent to the step ofFIGS. 38A through 38F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 39D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 39A , illustrating the transistor in a step, subsequent to the step ofFIGS. 38A through 38F, involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 39E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 39A , illustrating the transistor in a step, subsequent to the step ofFIGS. 38A through 38F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 40A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 40B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 40A , illustrating the transistor in a step, subsequent to the step ofFIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 40C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 40A , illustrating the transistor in a step, subsequent to the step ofFIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 40D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 40A , illustrating the transistor in a step, subsequent to the step ofFIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 40E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 40A , illustrating the transistor in a step, subsequent to the step ofFIGS. 39A through 39F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 41A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 41B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 41A , illustrating the transistor in a step, subsequent to the step ofFIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 41C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 41A , illustrating the transistor in a step, subsequent to the step ofFIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 41D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 41A , illustrating the transistor in a step, subsequent to the step ofFIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 41E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 41A , illustrating the transistor in a step, subsequent to the step ofFIGS. 40A through 40F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 42A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 42B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 42A , illustrating the transistor in a step, subsequent to the step ofFIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 42C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 42A , illustrating the transistor in a step, subsequent to the step ofFIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 42D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 42A , illustrating the transistor in a step, subsequent to the step ofFIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 42E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 42A , illustrating the transistor in a step, subsequent to the step ofFIGS. 41A through 41F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 43A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 43B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 43A , illustrating the transistor in a step, subsequent to the step ofFIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 43C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 43A , illustrating the transistor in a step, subsequent to the step ofFIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 43D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 43A , illustrating the transistor in a step, subsequent to the step ofFIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 43E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 43A , illustrating the transistor in a step, subsequent to the step ofFIGS. 42A through 42F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 44A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 44B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 44A , illustrating the transistor in a step, subsequent to the step ofFIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 44C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 44A , illustrating the transistor in a step, subsequent to the step ofFIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 44D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 44A , illustrating the transistor in a step, subsequent to the step ofFIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 44E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 44A , illustrating the transistor in a step, subsequent to the step ofFIGS. 43A through 43F , involved in the method of forming the semiconductor device in accordance with another embodiment of the present invention; -
FIG. 45 is a fragmentary plan view illustrating a semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 46 is a fragmentary perspective view illustrating a part of the semiconductor device shown inFIG. 45 in accordance with still another embodiment of the present invention; -
FIG. 47 is a fragmentary cross sectional elevation view illustrating a channel structure of the semiconductor device shown inFIG. 45 in accordance with still another embodiment of the present invention; -
FIG. 48A is a fragmentary plan view illustrating a transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 48B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 48A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 48C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 48A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 48D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 48A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 48E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 48A , illustrating the transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 49A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 49B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 49A , illustrating the transistor in a step, subsequent to the step ofFIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 49C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 49A , illustrating the transistor in a step, subsequent to the step ofFIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 49D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 49A , illustrating the transistor in a step, subsequent to the step ofFIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 49E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 49A , illustrating the transistor in a step, subsequent to the step ofFIGS. 48A through 48F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 50A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 50B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 50A , illustrating the transistor in a step, subsequent to the step ofFIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 50C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 50A , illustrating the transistor in a step, subsequent to the step ofFIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 50D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 50A , illustrating the transistor in a step, subsequent to the step ofFIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 50E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 50A , illustrating the transistor in a step, subsequent to the step ofFIGS. 49A through 49F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 51A is a fragmentary plan view illustrating a transistor in a step, subsequent to the step ofFIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 51B is a fragmentary cross sectional elevation view, taken along an X1-X1′ line ofFIG. 51A , illustrating the transistor in a step, subsequent to the step ofFIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 51C is a fragmentary cross sectional elevation view, taken along an X2-X2′ line ofFIG. 51A , illustrating the transistor in a step, subsequent to the step ofFIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 51D is a fragmentary cross sectional elevation view, taken along a Y1-Y1′ line ofFIG. 51A , illustrating the transistor in a step, subsequent to the step ofFIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 51E is a fragmentary cross sectional elevation view, taken along a Y2-Y2′ line ofFIG. 51A , illustrating the transistor in a step, subsequent to the step ofFIGS. 50A through 50F , involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention; -
FIG. 52 is a brief configuration diagram illustrating a data processing system including the semiconductor device in accordance with the embodiments of the present invention; and -
FIG. 53 is a fragmentary enlarged perspective view illustrating a part of a semiconductor device in accordance with the related art. - Before describing the present invention, the related art will be explained in detail, in order to facilitate the understanding of the present invention.
- A transistor as shown in
FIG. 53 has the channel of the three-dimensional structure described above. The transistor is formed as follows. Anisolation region 101 and anactive region 102 are formed in a surface portion of asemiconductor substrate 100. Trenchportions isolation region 101 and theactive region 102, respectively. Afin portion 107 is a protrusion which is a part of theactive region 102 between thetrench portions 103. A saddlefin gate electrode 106 is formed by burying a conductive material in thetrench portions gate insulating film 105 is interposed between the saddlefin gate electrode 106 and the semiconductor substrate. That is, the saddlefin gate electrode 106 crosses over thefin portion 107. Anupper surface 107 a of thefin portion 107 is located to be higher than a bottom surface of thetrench portion 103 and to be lower than an upper surface of the active region 102 (an upper surface of the semiconductor substrate 100). This is because thetrench portion 104 in theactive region 102 is shallower than thetrench portion 103 formed in theisolation region 102. Asource region 108 a and adrain region 108 b (impurity diffusion layers) are formed, by implanting ions, in twoactive regions 102 between which thegate electrode 106 is interposed. - However, widths of the
trench portions upper surface 107 a and aside surface 107 b of thefin portion 107 also become narrow in correspondence with the widths of the buriedgate trench portions - Embodiments of the invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teaching of the embodiments of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purpose.
- In one embodiment, a semiconductor device may include, but is not limited to, a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate. The fin has a channel region.
- In some cases, the fin further may further include, but is not limited to, a third fin portion extending substantially in the vertical direction.
- In some cases, the semiconductor device may further include, but is not limited to, source and drain regions having bottoms which contact tops of the second and third fin portions, respectively.
- In some cases, the semiconductor device may further include, but is not limited to, a first side wall insulating film on a first side surface of the source and a second side wall insulating film on a second side surface of the drain. The second side surface faces toward the first side surface.
- In some cases, the semiconductor device may include, but is not limited to, the following elements. The second fin portion has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces. The third fin portion has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the forth and fifth side surfaces. The third and sixth side surfaces face toward each other.
- In some cases, the semiconductor device may further include, but is not limited to, a gate insulating film and a gate electrode. The gate insulating film covers the first through sixth side surfaces. The gate electrode contacts the gate insulating film. The gate electrode faces toward the first through sixth side surfaces. The gate insulating film is interposed between the gate electrode and the first through sixth side surfaces.
- In some cases, the semiconductor device may further include, but is not limited to, an isolation region adjacent to the fin.
- In some cases, the semiconductor device may include, but is not limited to, a top surface of the gate electrode being lower in level than a top surface of the isolation region.
- In some cases, the semiconductor device may include, but is not limited to, the isolation region having a trench beside the fin. A distance between the third and sixth surfaces is smaller than a width of the trench, the width being defined in a direction from the third surface to the sixth surface.
- In another embodiment, a semiconductor device may include, but is not limited to, the following elements. A semiconductor substrate includes an active region. The active region has a fin. The fin includes first, second, and third fin portions. The first fin portion extends substantially in a first horizontal direction to a surface of the semiconductor substrate. The second and third fin portions extend substantially in a vertical direction to the surface of the semiconductor substrate. An isolation region defines the active region. A word line extends over the isolation region and the active region. The word line extends across the fin. The word line extends substantially in a second horizontal direction perpendicular to the first horizontal direction. The word line has first and second portions. The first portion is interposed between the second and third fin portions. The second portion is over the isolation region. The first portion is smaller in width than the second portion.
- In some cases, the semiconductor device may further include, but is not limited to, source and drain regions in the active region and a channel region in the active region. The channel region is located below the source and drain regions. The channel region is formed in the vicinity of a surface region of the fin.
- In some cases, the semiconductor device may further include, but is not limited to, a first side wall insulating film on a first side surface of the source and a second side wall insulating film on a second side surface of the drain. The second side surface faces toward the first side surface.
- In some cases, the semiconductor device may include, but is not limited to, the following elements. The second fin portion has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces. The third fin portion has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the forth and fifth side surfaces. The third and sixth side surfaces face toward each other.
- In some cases, the semiconductor device may further include, but is not limited to, a gate insulating film covering the first through sixth side surfaces. The first portion contacts the gate insulating film. The first portion faces toward the first through sixth side surfaces. The gate insulating film is interposed between the first portion and the first through sixth side surfaces.
- In some cases, the semiconductor device may include, but is not limited to, a top surface of the word line is lower in level than a top surface of the isolation region.
- In still another embodiment, a semiconductor device may include, but is not limited to, the following elements. A semiconductor substrate has a fin having a channel region in the vicinity of a surface of the fin. The fin includes an end portion. The end portion has first and second channel portions of the channel region. The first and second channel portions are opposed to each other. The first and second channel portions extend substantially vertical to a surface of the semiconductor substrate. A diffusion region has a bottom. The bottom is in contact with the end portion and with the first and second channel portions.
- In some cases, the semiconductor device may include, but is not limited to, the end portion having a third channel portion of the channel region. The third channel portion is adjacent to the first and second channel portions. The third channel portion extends substantially vertical to the surface of the semiconductor substrate. The bottom is in contact with the third channel portion.
- In some cases, the semiconductor device may further include, but is not limited to, a gate insulating film covering the channel region and a gate electrode contacting the gate insulating film. The gate electrode faces toward the first through third channel portions. The gate insulating film is interposed between the gate electrode and the first through third channel portions.
- In some cases, the semiconductor device may include, but is not limited to, a top surface of the gate electrode is lower in level than a top surface of the isolation region.
- In some cases, the semiconductor device may further include, but is not limited to, a first side wall insulating film on a side surface of the diffusion region.
- In still another embodiment, a method for forming a semiconductor device may include, but is not limited to, the following processes. An isolation region is formed in a semiconductor substrate. The isolation region defines an active region. The active region and the isolation region are selectively etched to form first and second trench portions, respectively. The first and second trench portions are adjacent to each other. Side surfaces and a bottom surface of the second trench portion are etched to form a fin in the active region.
- In some cases, the method may further include, but is not limited to, forming a mask over the active region and the isolation region before selectively etching the active region and the isolation region.
- In some cases, etching the side surfaces and the bottom surface of the second trench portion may include, but is not limited to, etching the side surfaces and the bottom surface of the second trench portion while the mask remains.
- In some cases, etching the side surfaces and the bottom surface of the second trench portion may include, but is not limited to, wet etching the side surfaces and the bottom surface of the second trench portion.
- In some cases, etching the side surfaces and the bottom surface of the second trench portion may include, but is not limited to, etching the bottom surface of the second trench portion by an anisotropic etching process and etching the side surfaces and the bottom surface of the second trench portion by an isotropic etching process.
- In some cases, the method may further include, but is not limited to, forming a conductive film filling the first and second trench portion.
- Hereinafter, a semiconductor device according to an embodiment of the invention will be described in detail with reference to the drawings. In the embodiment, an example of applying the invention to a DRAM (Dynamic Random Access Memory) as the semiconductor device will be described. In the drawings used for the following description, to easily understand characteristics, there is a case where characteristic parts are enlarged and shown for convenience′ sake, and ratios of constituent elements may not be the same as in reality. Materials, sizes, and the like exemplified in the following description are just examples. The invention is not limited thereto and may be appropriately modified within a scope which does not deviate from the concept of the invention.
- The structure of a
semiconductor device 1 will be described as the first embodiment with reference toFIGS. 1 and 2 .FIG. 1 is a plan view of thesemiconductor device 1.FIG. 2 is a fragmentary enlarged perspective view illustrating part of thesemiconductor device 1. - The
semiconductor device 1 functions as a DRAM. As shown inFIGS. 1 and 2 , thesemiconductor device 1 includes a cell array region SA and a peripheral circuit region CA in asemiconductor substrate 2. The peripheral circuit region CA is located in the vicinity of the cell array region SA. A plurality of memory cells are arranged in a matrix in the cell array region SA. A circuit for controlling operations of each memory cell is disposed in the peripheral circuit area CA. Each of the memory cells arranged in the cell array region SA includes a selection transistor and a capacitor electrically connected to any one of a source and a drain of the selection transistor. - In the cell array region SA, a plurality of
isolation regions 5 and a plurality ofactive regions 6 are alternately arranged in stripes. The plurality ofactive regions 6 are insulated and isolated by theisolation regions 5. The plurality ofisolation regions 5 are formed as follows. A plurality ofisolation trench portions 3 extending in a first direction are formed in thesemiconductor substrate 2. The plurality ofisolation regions 5 called shallow trench isolation (STI) are formed by burying isolation insulating films 4 (asilicon oxide film 26 and a silicon nitride film 31) in the plurality ofisolation trench portions 3. - In the cell array region SA, a plurality of
word lines 7 extend in a second direction crossing theisolation regions 5 and theactive regions 6. The plurality ofword lines 7 are arranged in stripes. Theword line 7 includes agate electrode 8 of the selection transistor. Thegate electrode 8 is a buried gate electrode. Thegate electrode 8 is formed as follows. Conductive materials are buried in first andsecond trench portions isolation region 5 and theactive region 6, respectively while agate insulating film 11 is interposed between thegate electrode 8 and thesemiconductor substrate 2. - In some cases, the
first trench portion 9 is formed in theactive region 6 in the cell array region SA. Thesecond trench portion 10 is formed in theisolation region 5. Thesecond trench portion 10 is greater in depth than thefirst trench portion 9. The bottom portion of thesecond trench portion 10 is greater in width in the first direction than thefirst trench portion 9. Theactive region 6 includes a fin. The fin includes first andsecond fin portions first fin portion 12 a protrudes substantially in the vertical direction to the surface of thesemiconductor substrate 2. Thefirst fin portion 12 a extends substantially in a horizontal direction to the surface of the semiconductor substrate. Thefirst fin portion 12 a is positioned between thesecond trench portions 10. Thesecond fin portions 12 b protrude substantially in the horizontal direction. Thesecond fin portions 12 b extend substantially in the vertical direction. Thesecond fin portions 12 b are connected continuously to thefirst fin portion 12 a. Thesecond fin portions 12 b extends continuously from the opposite sides of thefirst fin portion 12 a. Each of thesecond fin portions 12 b is positioned between thesecond trench portions 10. The presence of thefirst fin portion 12 a causes that thesecond trench portion 10 is greater in depth than thefirst trench portion 9. The presence of thesecond fin portions 12 b causes that the bottom portion of thesecond trench portion 10 is greater in width in the first direction than thefirst trench portion 9. Optionally, a third fin (channel) portion 12 c is present. - As shown in
FIG. 3 , thesemiconductor device 1 may include, but is not limited to, anisolation insulating film 4 which includes thesilicon oxide film 26 and thesilicon nitride film 31. Thesilicon oxide film 26 and thesilicon nitride film 31 are sequentially buried in theisolation trench portion 3. Thesecond trench portion 10 includes anupper trench portion 10 a and alower trench portion 10 b. Theupper trench portion 10 a is formed in thesilicon nitride film 31 so as to have the same width W1 as thefirst trench portion 9. Thelower trench portion 10 b is formed in thesilicon oxide film 26 located below theupper trench portion 10 a so as to have a greater width W2 than the width W1 of theupper trench portion 10 a. Thesecond trench portion 10 has a cross-sectional shape that is line-symmetric with respect to a line extending in the second direction perpendicular to the first direction and extending through a center of thefirst trench portion 9. Here, the “width” is defined in the first direction. - A dimension in a depth direction of the
upper trench portion 10 a is the same as thicknesses of adrain region 13 a and asource region 13 b. Theupper trench portion 10 a is formed in the vicinity of a surface of theactive region 6, that is, the surface portion of thesemiconductor substrate 2. - In this case, the
first fin portion 12 a in thefirst trench portion 9 protrudes substantially in the vertical direction to the surface of the substrate by a difference ΔD (=D2−D1) between a depth D1 of thefirst trench portion 9 and a depth D2 of thesecond trench portion 10. Thefirst fin portion 12 a forms a first channel region FCU having the width W1 in the first direction. In some cases, a surface portion of thefirst fin portion 12 a forms the first channel region FCU. - A pair of the
second fin portions 12 b in thefirst trench portion 9 respectively protrude substantially in the horizontal direction to the surface of the substrate by half (ΔW) a difference 2ΔW (=W2−W1) between the width W1 of thefirst trench portion 9 and the width W2 of the second trench portion 10 (thelower trench portion 10 b). The pair ofsecond fin portions 12 b forms second channel regions FCS extending substantially in the vertical direction to the surface of thesemiconductor substrate 2 from both ends of thefirst fin portion 12 a. In some cases, surface portions of the pair ofsecond fin portions 12 b form the second channel regions FCS. Each of thesecond fin portions 12 b has first and second channel portions of the second channel region FCS. The fin has the opposite end portions which may, in some cases, be thesecond fin portions 12 b. The first and second channel portions are opposed to each other. The first and second channel portions extend substantially in the direction vertical to the surface of the semiconductor substrate. - The
semiconductor device 1 may include, but is not limited to, thegate insulating film 11 covering the surfaces of the first andsecond fin portions word line 7 functions as thegate electrode 8. Thegate electrode 8 is buried in the buriedgate trench portions second fin portions gate insulating film 11 is interposed between thegate electrode 8 and thesemiconductor substrate 2. Therefore, thesemiconductor device 1 has a saddle fin channel structure. - In parts of the
active regions 6 between which thegate electrode 8 is interposed, thedrain region 13 a and thesource region 13 b (impurity diffusion layers) are respectively provided by implanting ions. Thedrain region 13 a and thesource region 13 b function as a source and a drain of the selection transistor, respectively. Thedrain region 13 a and thesource region 13 b have bottoms which are connected to the tops of thesecond fin portions 12 b, which are located under thedrain region 13 a and thesource region 13 b, respectively. - As described above, the
semiconductor device 1 may include, but is not limited to, thegate electrode 8, thedrain region 13 a and thesource region 13 b (the impurity diffusion layers), the pair ofsecond fin portions 12 b (the second channel regions FCS), thefirst fin portion 12 a (the first channel region FCU), and thegate insulating film 11. Thegate electrode 8 is located below the surface of thesemiconductor substrate 2. Thegate electrode 8 is buried in the first andsecond trench portions gate electrode 8 is interposed between thedrain region 13 a and thesource region 13 b. Thedrain region 13 a and thesource region 13 b respectively have upper surfaces in positions that are higher in level than the upper surface of thegate electrode 8. The pair ofsecond fin portions 12 b (the second channel regions FCS) is continuously connected to the respective bottom surfaces of thedrain region 13 a and thesource region 13 b. The pair ofsecond fin portions 12 b (the second channel regions FCS) extends substantially in the depth direction that is vertical to the surface of thesemiconductor substrate 2 from the respective bottom surfaces of thedrain region 13 a and thesource region 13 b. One of the pair ofsecond fin portions 12 b has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces. The other of the pair ofsecond fin portions 12 b has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the fourth and fifth side surfaces. The third and sixth side surfaces face toward each other. The distance between the third and sixth surfaces is smaller than the width of thelower trench portion 10 b. Thefirst fin portion 12 a is connected to lower portions of the pair ofsecond fin portions 12 b. Thefirst fin portion 12 a extends in the first direction between the pair ofsecond fin portions 12 b. Thegate insulating film 11 covers the surfaces of the first andsecond fin portions gate insulating film 11 covers the first through sixth side surfaces. Thegate electrode 8 contacts thegate insulating film 11. Thegate electrode 8 faces toward the first through sixth side surfaces while thegate insulating film 11 being interposed between the gate electrode and the first through sixth side surfaces. Thesemiconductor device 1 has a buried gate transistor. - In the
semiconductor device 1 having the above-described structure, electric charges released from thesource region 13 b propagate through onesecond fin portion 12 b, thefirst fin portion 12 a, and the othersecond fin portion 12 b and then enter into thedrain region 13 a. - In the
semiconductor device 1 according to the present embodiment is applied as described above, the pair ofsecond fin portions 12 b (the second channel regions FCS) are provided to extend substantially in the direction vertical to the surface of thesemiconductor substrate 2 from both ends of thefirst fin portion 12 a (the first channel region FCU). Therefore, the pair ofsecond fin portions 12 b (the second channel regions FCS) will ensure the extended length of the channel region in the first direction, as compared to the related art. - Thus, it is possible to increase the ON current Ion by reducing the resistance of the entire channel compared to the related art in which only the bottom portion has the saddle fin channel structure. Therefore, even when the widths of the buried
gate trench portions semiconductor device 1, the channel region may include the second channel regions FCS extending in the direction vertical to the surface of thesemiconductor substrate 2, that is, in the direction vertical to the bottom surfaces of thedrain region 13 a and thesource region 13 b. The second channel regions FCS extending in the vertical direction will contribute to suppress the short channel effects of the switching transistor of thesemiconductor device 1, which secures a sufficient ON current Ion. - In the cell array region SA shown in
FIG. 1 described above, a number of theisolation regions 5 and theactive regions 6 as described above may be arranged and formed.FIG. 1 schematically shows that someisolation regions 5 and someactive regions 6 are arranged and formed in the cell array region SA. In thesemiconductor device 1, although not shown, twoword lines 7 operating for a normal transistor and a dummy word line are disposed next to the word lines 7. The dummy word line is a buried wiring for isolation (a dummy gate). A predetermined potential is applied to the dummy word line, so that adjacent transistors on the same active region are isolated. Alternatively, the parasitic transistor is in an OFF state and isolated by applying the predetermined potential to the dummy word line. The dummy word wiring is formed as follows. The trench portions having the same configuration as theword lines 7 are simultaneously formed. A conductive material is buried in the trench portions. - A method of forming the
semiconductor device 1 will be described with reference toFIGS. 9A to 29C . -
FIGS. 9A , 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, and 29A are fragmentary plan views illustrating a transistor in a step involved in the method of forming the semiconductor device in accordance with still another embodiment of the present invention.FIGS. 9B , 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, 28B, and 29B are fragmentary cross-sectional elevation views taken along an X1-X1′ line.FIGS. 9C , 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C, 22C, 23C, 24C, 25C, 26C, and 27C are cross-sectional elevation views taken along an X2-X2′ line.FIGS. 9D , 10D, 11D, 12D, 13D, 14D, 15D, 16D, 17D, 18D, 19D, 20D, 21D, 22D, 23D, 24D, 25D, 26D, and 27D are cross-sectional elevation views taken along a Y1-Y1′ line.FIGS. 9E , 10E, 11E, 12E, 13E, 14E, 15E, 16E, 17E, 18E, 19E, 20E, 21E, 22E, 23E, 24E, 25E, 26E, 27E, 28C, and 29C are cross-sectional elevation views taken along a Y2-Y2′ line.FIGS. 9F , 10F, 11F, 12F, 13F, 14F, 15F, 16F, 17F, 18F, 19F, 20F, 21F, 22F, 23F, 24F, 25F, 26F, and 27F are cross-sectional elevation views taken along a Y3-Y3′ line. The Y1-Y1′ line and the Y2-Y2′ line indicate cross-sectional portions in a region inside the cell array region SA. The Y3-Y3′ line indicates a cross-sectional portion in a boundary region crossing over a cell array region SA and a peripheral circuit region CA. - In the cell array region SA shown in
FIGS. 9A , 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, and 29A, theisolation regions 5 and theactive regions 6 as described above are arranged and formed in plural. However, a state in which someisolation regions 5 and someactive regions 6 arranged and formed in the cell array region SA are enlarged is schematically shown for convenience inFIGS. 9A , 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, and 29A. - As shown in
FIGS. 9A to 9F , asemiconductor substrate 2 is prepared before processing. Thesemiconductor substrate 2 may be, but is not limited to, a single crystal substrate containing a predetermined concentration of impurities, for example, a silicon single crystal substrate containing impurities. - On the
semiconductor substrate 2, amask layer 24 is formed in which asilicon nitride film 21, anamorphous carbon film 22, and an antireflective (BARC)film 23 are sequentially stacked. A photoresist (PR) is applied on themask layer 24. The PR is patterned using lithography technique, thereby forming a resistpattern 25 having a shape corresponding to the active region. An openingportion 25 a in a position corresponding to anisolation region 5 and anopening portion 25 b in the peripheral circuit region CA are formed using the resistpattern 25. - As shown in
FIGS. 10A to 10F , themask layer 24 is patterned by an anisotropic dry etching process using the resistpattern 25. The resistpattern 25 on themask layer 24 is removed with the progression of etching. The shape of the resistpattern 25 is reflected to themask layer 24. Thereby, themask layer 24 can be patterned to the shape corresponding to the resistpattern 25. Themask layer 24 is also removed while the pattern of themask layer 24 corresponding to the shape of the resistpattern 25 is maintained with the progression of etching. When the patterning of themask layer 24 has been completed, for example, the antireflective (BARC)film 23 is completely removed. Themask layer 24 including theamorphous carbon film 22 and thesilicon nitride film 21 remains to have anopening portion 24 a in a position corresponding to theisolation region 5 and anopening portion 24 b in the peripheral circuit region CA remains. - The
semiconductor substrate 2 is patterned by an anisotropic dry etching process using the patternedmask layer 24. The shape of themask layer 24 depends on the surface of thesemiconductor substrate 2. In the cell array region SA of thesemiconductor substrate 2, a plurality ofisolation trench portions 3 extending in the first direction are arranged and formed in stripes. Atrench portion 3A with a greater width than theisolation trench portion 3 is formed in the peripheral circuit region CA. In forming theisolation trench portion 3 and thetrench portion 3A, theamorphous carbon film 22 included in themask layer 24 is removed by an etching process. - As shown in
FIGS. 11A to 11F , asilicon oxide film 26 is formed with a thickness sufficient to be buried in theisolation trench portion 3 and thetrench portion 3A by a high-density plasma-chemical vapor deposition (HDP-CVD) method over the entire surface of thesemiconductor substrate 2. A surface on which thesilicon oxide film 26 is formed is polished by chemical mechanical polishing (CMP) and planarized until the surface of thesilicon nitride film 21 serving as a stopper is shown. - As shown in
FIGS. 12A to 12F , thesilicon oxide film 26 is selectively removed by a wet etching process using hydrofluoric acid (HF). Thereby, thesilicon oxide film 26 is adjusted to be the same in height as the surface of thesemiconductor substrate 2. Thesilicon nitride film 21 is removed by a wet etching process using hot phosphoric acid (H3PO4). Thereby, theisolation region 5 and theactive region 6 are formed to be alternately adjacent while extending in the first direction. As described above, theisolation region 5 is formed by burying thesilicon oxide film 26 in theisolation trench portion 3 as theisolation insulating film 4. Theactive region 6 is isolated by theisolation region 5. - As shown in
FIGS. 13A to 13F , asilicon oxide film 27 is formed by oxidizing the surface of the semiconductor substrate 2 (the active region 6) positioned between thesilicon oxide films 26 by thermal oxidation (in situ steam generation (ISSG)). Anon-doped silicon film 28 is formed over the entire surface of thesemiconductor substrate 2. Low-concentration N-type impurities (phosphorus or the like) are ion-implanted into theactive region 6 disposed between thesilicon oxide films 26 through thenon-doped silicon film 28, so that animpurity diffusion layer 29 is formed in theactive region 6. Theimpurity diffusion layer 29 functions as adrain region 13 a or asource region 13 b of thesemiconductor device 1. - A photo resist is applied on the
semiconductor substrate 2. A resist pattern (not shown) is formed to cover the peripheral circuit region CA while patterning the photo resist by a lithography technique. As shown inFIGS. 14A to 14F , thenon-doped silicon film 28 remains on the peripheral circuit region CA, and thenon-doped silicon film 28 within the cell array region SA is removed by a dry etching process using the resist pattern. - As shown in
FIGS. 15A to 15F , a part of thesilicon oxide film 26 and thesilicon oxide film 27 are selectively removed by an anisotropic selective etching process. Thereby, atrench portion 30 is formed between the impurity diffusion layers 29 in theisolation region 5. A bottom surface of thetrench portion 30 is leveled to a top surface of agate electrode 8 to be formed in a subsequent process which will be described later. That is, an upper surface of thesilicon oxide film 26 which forms a bottom surface of thetrench portion 30 is the same in level as the upper surface of thegate electrode 8 formed in the subsequent process. Also, the upper surface of thesilicon oxide film 26 is the same in level as a bottom surface of theimpurity diffusion layer 29. - As shown in
FIGS. 16A to 16F , a protective oxide film (not shown) is formed and asilicon nitride film 31 covering the surface of thesemiconductor substrate 2 is buried in thetrench portion 30. - As shown in
FIGS. 17A to 17F , anamorphous carbon film 32 is formed on thesilicon nitride film 31. A photo resist is applied on theamorphous carbon film 32. The photo resist is patterned by a lithography technique. Thereby, there is formed a resist pattern (not shown) having opening portions which are located at positions where the buriedgate trench portions amorphous carbon film 32 is patterned by a dry etching process using the resist pattern. The resist pattern on theamorphous carbon film 32 is removed with the progression of etching. The shape of the resist pattern depends on theamorphous carbon film 32. In theamorphous carbon film 32, openingportions 32 a are formed in a position where the buriedgate trench portions - As shown in
FIGS. 18A to 18F , parts shown through the openingportion 32 a are removed by an anisotropic etching process using the patternedamorphous carbon film 32 as a mask. At this time, theamorphous carbon film 32 over thesilicon nitride film 31 is also simultaneously removed. Thereby, thesilicon nitride film 31, thesilicon oxide film 26, theimpurity diffusion layer 29, and the surface portion of thesemiconductor substrate 2 shown through the openingportion 32 a are etched at the constant speed. At this time, thefirst trench portion 9 is formed in at least the surface portion of the semiconductor substrate 2 (the active region 6). Anupper trench portion 10 a serving as a part of thesecond trench portion 10 is formed in the silicon nitride film 31 (the isolation region 5). - The
silicon oxide film 26 forming a bottom surface of theupper trench portion 10 a shown inFIG. 18C is selectively removed by a wet etching process using a solution containing HF as shown inFIGS. 19A to 19F . It is possible to etch thesilicon oxide film 26 to thesilicon nitride film 31 at a high selectivity using the HF-containing solution. Therefore, thesilicon oxide film 26 under thesilicon nitride film 31 is selectively removed without removing thesilicon nitride film 31. Because the wet etching process is an isotropic etching process, thesilicon oxide film 26 forming the bottom surface of theupper trench portion 10 a is etched in a depth direction and a width direction. Therefore, under theupper trench portion 10 a, alower trench portion 10 b is formed to be 2ΔW wider than theupper trench portion 10 a. - The wet etching process by the HF-containing solution is used for forming the
lower trench portion 10 b in this embodiment, but the present embodiment is not limited thereto. In some cases, a chemical dry etching method using anhydrous hydrogen fluoride gas and ammonia gas may be used. For example, after the processes shown inFIGS. 18A to 18F are completed, thesemiconductor substrate 2 is set in an etching device. Thesemiconductor substrate 2 is kept in the etching device under the condition at 20 mTorr and at 37° C. for 1 minute while a constant amount of anhydrous hydrogen fluoride gas and ammonia gas are supplied to the etching device. Thereby, ammonium fluorosilicate is formed on the surface of thesilicon oxide film 26. The ammonium fluorosilicate is sublimed and removed if the temperature is raised to 180° C. At this time, an etching amount of thesilicon oxide film 26 is 5 nm in thickness direction, and the etching amount can be controlled by setting a condition of the chemical dry etching method. Thesilicon oxide film 26 is etched since the chemical dry etching method is an isotropic etching process. Other structure members than thesilicon oxide film 26 are not affected by the chemical dry etching method. Thelower trench portion 10 b can be formed with higher precision than in the above-described wet etching method. - The
second trench portions 10 are formed in theisolation regions 5 of both sides between which theactive region 6 is interposed. There is formed thefirst fin portion 12 a which is a first part of theactive region 6 protruding by ΔD in the substantially vertical direction to the surface of the substrate. The pair ofsecond fin portions 12 b is formed to be continuously connected to thefirst fin portion 12 a. The pair ofsecond fin portions 12 b extends substantially in the horizontal direction to the surface of the substrate. Thesecond fin portions 12 b are second parts of theactive region 6 which are shown by ΔW from thesilicon oxide film 26. - As shown in
FIGS. 20A to 20F , the surfaces of the first andsecond fin portions gate insulating film 11 made of a silicon oxide film is formed. Aconductive film 33 is formed to cover the surface of thesemiconductor substrate 2 and to be buried in the buriedgate trench portions - As shown in
FIGS. 21A to 21F , the surface of theconductive film 33 is polished by CMP for planarization until the surface of thesilicon nitride film 31 serving as a stopper is shown. An etch-back process is performed until the surface of theconductive film 33 is the same in level as the surface of thesilicon oxide film 26 as shown inFIG. 21C . Thereby, thegate electrode 8 is formed. Thegate electrode 8 serves as theword line 7 in the memory cell region SA. - As shown in
FIGS. 22A to 22F , asilicon oxide film 34 serving as a cap insulating film of thegate electrode 8 is formed by an HDP-CVD method over the entire surface of thesemiconductor substrate 2. - As shown in
FIGS. 23A to 23F , the surface of thesilicon oxide film 34 is polished by CMP for planarization until the surface of thesilicon nitride film 31 is shown. Thesilicon nitride film 31 formed in the peripheral circuit region CA serves as the stopper. Thesilicon oxide film 34 is selectively removed by a wet etching process using HF (etch-back process) until a surface of thesilicon oxide film 34 is the same in level as the surface of thesilicon nitride film 31 formed in the cell array region SA. - Through the above-described processes, a selection transistor included in a memory cell is formed as the
semiconductor device 1 shown inFIGS. 1 and 2 described above in the cell array region SA. - In the
semiconductor device 1 formed by applying this embodiment, the pair ofsecond fin portions 12 b (the second channel regions FCS) are formed to extend in the direction vertical to the surface of thesemiconductor substrate 2 from both ends of thefirst fin portion 12 a (the first channel region FCU) as shown inFIG. 3 described above. The pair ofsecond fin portions 12 b (the second channel regions FCS) will ensure the extended length of the channel region in the first direction. - After the processes shown in
FIGS. 23A to 23F described above, a bit line electrically connected to any one of a source and a drain of the selection transistor, a capacitor electrically connected to the other, and a wiring layer thereon are sequentially formed, so that a DRAM in which a plurality of memory cells are arranged within the cell array region SA can be formed. - As shown in
FIGS. 24A to 24F , after the processes shown inFIGS. 23A to 23F described above, a resistpattern 35 having an openingportion 35 a is formed over thesemiconductor substrate 2. The openingportion 35 a is located in a position corresponding to abit contact hole 36 which will be formed. Thebit contact hole 36 is a trench for forming the bit line. - As shown in
FIGS. 25A to 25F , thesilicon nitride film 31 shown through the openingportion 35 a is removed by an anisotropic etching process using the resistpattern 35 as a mask. At this time, the anisotropic etching process is performed until theimpurity diffusion layer 29 formed in the cell array region SA and thenon-doped silicon film 28 formed in the peripheral circuit region CA are shown. Thereby, thebit contact hole 36 is formed to extend in the direction (the second direction) parallel to thegate electrode 8. - As shown in
FIGS. 26A to 26F , a stack of an impurity-containingpolysilicon film 37 a and atungsten silicide film 37 b is formed. The stack of an impurity-containingpolysilicon film 37 a and atungsten silicide film 37 b will be processed into thebit line 37 in later steps. The impurity-containingpolysilicon film 37 a covers thesemiconductor substrate 2. The impurity-containingpolysilicon film 37 a is buried in thebit contact hole 36. The impurity-containingpolysilicon film 37 a may be formed to contain an impurity in the film formation step by a CVD method. In other cases, after the non-doped silicon film is formed, the impurity may be implanted by ion implantation. - As shown in
FIGS. 27A to 27F , a resist pattern (not shown) is formed to cover a position where thebit line 37 is formed on the stack of an impurity-containingpolysilicon film 37 a and atungsten silicide film 37 b. Using the resist pattern, the stack of an impurity-containingpolysilicon film 37 a and atungsten silicide film 37 b is patterned by a dry etching process. Thereby, thebit line 37 is formed to extend in the direction (the second direction) parallel to thegate electrode 8. In some cases, thebit line 37 may be formed by the following method. After thetungsten silicide film 37 b is formed, a cover silicon nitride film is formed. Using the resist pattern, the cover silicon nitride film is patterned to have a predetermined pattern. Further, the underlyingtungsten silicide film 37 b and the impurity-containingpolysilicon film 37 a are etched using the cover silicon nitride film as a mask. - As shown in
FIGS. 28A to 28C , a space between the bit lines 37 is filled by applying spin-on dielectrics (SOD) over thesemiconductor substrate 2. Under a vapor (H2O) atmosphere, the SOD is modified to solid state by an annealing process, thereby forming an SOD film (an insulating film) 38. A resist pattern (not shown) is formed on theSOD film 38. The resist pattern has an opening portion in a position where a capacitor contact plug will be formed. Acontact hole 39 is formed by patterning theSOD film 38 by a dry etching process using the resist pattern as a mask. - As shown in
FIGS. 29A to 29C , acapacitor contact plug 40 is formed by burying a conductive material in thecontact hole 39. An insulatingfilm 41 is formed on theSOD film 38. The insulatingfilm 41 has an opening portion in a position overlapping thecapacitor contact plug 40. Acapacitor contact pad 42 electrically connected to thecapacitor contact plug 40 is formed to be buried in the opening portion. - As shown in
FIGS. 30A and 30B , acapacitor 46 including alower electrode 43, acapacitor insulating film 44, and anupper electrode 45 is formed to overlap thecapacitor contact pad 42. Thecapacitor 46 is not particularly limited. In some cases, there may be provided a cylindrical capacitor structure using only an outer wall of thelower electrode 43 as the electrode shown inFIG. 30A . In other cases, there may be provided a crown capacitor structure using an inner wall and an outer wall of thelower electrode 43 as the electrode shown inFIG. 30B . - An interlayer insulating
film 47 is formed on thecapacitor 46. Awiring layer 48 is formed on theinterlayer insulating film 47. Thereby, there is formed a DRAM including the plurality of memory cells arranged within the cell array region SA. - A
semiconductor device 50 as shown inFIGS. 31 and 32 will be described as the second embodiment. -
FIG. 31 is a fragmentary plan view illustrating thesemiconductor device 50.FIG. 32 is a fragmentary perspective view in which main parts of thesemiconductor device 50 are enlarged. In the following description, the same parts as those of thesemiconductor device 1 in the first embodiment are denoted by the same reference numerals in the drawings and their descriptions are omitted. - The
semiconductor device 50 has the following configuration as shown inFIGS. 31 and 32 . As theisolation insulating film 4, thesilicon oxide film 26 is buried in theisolation trench portion 3. Thesecond trench portion 10 having theupper trench portion 10 a and thelower trench portion 10 b is formed in thesilicon oxide film 26. A side wall film 51 (a silicon nitride film) extending in the second direction is formed to cover both side surfaces of thefirst trench portion 9 and theupper trench portion 10 a described above. - In the
semiconductor device 1 disclosed in the first embodiment, thesilicon nitride film 31 is provided to cover the top of thesilicon oxide film 26. In the present embodiment, the silicon nitride film, which is not on thesilicon oxide film 26, is provided as theside wall film 51 to cover both side surfaces of thefirst trench portion 9 and theupper trench portion 10 a described above. The rest of the configuration of thesemiconductor device 50 is substantially the same as that of thesemiconductor device 1. - In the
semiconductor device 50 like thesemiconductor device 1, the first andsecond fin portions - Specifically, in the
semiconductor device 50, thesilicon oxide film 26 is buried in theisolation trench portion 3 as theisolation insulating film 4 as shown inFIG. 33 . Thesecond trench portion 10 includes theupper trench portion 10 a and thelower trench portion 10 b formed in thesilicon oxide film 26. Theupper trench portion 10 a has the same width W1 as thefirst trench portion 9. Thelower trench portion 10 b is formed under theupper trench portion 10 a. Thelower trench portion 10 b has a greater width W2 than theupper trench portion 10 a. Thesecond trench portion 10 has a cross-sectional shape that is line-symmetric with respect to a line extending in the second direction perpendicular to the first direction and extending through a center of thefirst trench portion 9. - A difference between a depth D1 of the
first trench portion 9 and a depth D2 of thesecond trench portion 10 is denoted by ΔD (=D2−D1). In terms of thefirst fin portion 12 a, thefirst fin portion 12 a in thefirst trench portion 9 protrudes in the substantially vertical direction to the surface of the substrate by the ΔD. Thereby, thefirst fin portion 12 a provides the first channel region FCU having the width W1 in the first direction. - The difference between the width W1 of the
first trench portion 9 and the width W2 of thesecond trench portion 10 is denoted by 2ΔW (=W2−W1). In terms of the pair ofsecond fin portions 12 b, the pair of thesecond fin portions 12 b in thefirst trench portion 9 respectively protrude substantially in the horizontal direction to the surface of the substrate by half (ΔW) a difference 2ΔW (=W2−W1) between the width W1 of thefirst trench portion 9 and the width W2 of the second trench portion 10 (thelower trench portion 10 b). Thereby, the pair ofsecond fin portions 12 b forms second channel regions FCS extending in a direction vertical to the surface of thesemiconductor substrate 2 from both ends of thefirst fin portion 12 a. The width in the first direction of the second channel regions FCS (here, the direction perpendicular to the surface of the semiconductor substrate 2) is ΔD. - The
semiconductor device 50 may include, but is not limited to, thegate insulating film 11 and thegate electrode 8. Thegate insulating film 11 covers the surfaces of the first andsecond fin portions gate electrode 8 is buried in the buriedgate trench portions second fin portions gate insulating film 11 is interposed between thegate electrode 8 and thefirst fin portion 12 a and between thegate electrode 8 and thesecond fin portion 12 b. Therefore, thesemiconductor device 50 has the saddle fin channel structure. - In parts of the
active regions 6 between which thegate electrode 8 is interposed, thedrain region 13 a and thesource region 13 b (impurity diffusion layers) are provided. Thedrain region 13 a and thesource region 13 b function as the source and the drain of the selection transistor, respectively. Thedrain region 13 a and thesource region 13 b are formed by implanting ions. Thedrain region 13 a and thesource region 13 b are connected to the tops of thesecond fin portions 12 b located thereunder. - As described above, the
semiconductor device 50 may include, but is not limited to, thegate electrode 8, thedrain region 13 a, thesource region 13 b, thefirst fin portion 12 a (the first channel region FCU), the pair ofsecond fin portions 12 b (the second channel regions FCS), and thegate insulating film 11. Thegate electrode 8 is located below the surface of thesemiconductor substrate 2. Thegate electrode 8 is buried in the first andsecond trench portions gate electrode 8 is interposed between thedrain region 13 a and thesource region 13 b. Thedrain region 13 a and thesource region 13 b respectively have upper surfaces in positions that are higher than the upper surface of thegate electrode 8. The pair ofsecond fin portions 12 b is continuously connected to the respective bottom surfaces of thedrain region 13 a and thesource region 13 b. The pair ofsecond fin portions 12 b extends substantially in the depth direction (the horizontal direction to the surface of the semiconductor substrate 2) from the respective bottom surfaces of thedrain region 13 a and thesource region 13 b. One of the pair ofsecond fin portions 12 b has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces. The other of the pair ofsecond fin portions 12 b has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the forth and fifth side surfaces. The third and sixth side surfaces face toward each other. A distance between the third and sixth surfaces is smaller than a width of thelower trench portion 10 b. Thefirst fin portion 12 a is connected to lower portions of the pair ofsecond fin portions 12 b. Thefirst fin portion 12 a extends in the first direction between the pair ofsecond fin portions 12 b. Thegate insulating film 11 covers the surfaces of the first andsecond fin portions gate insulating film 11 covers the first through sixth side surfaces. Thegate electrode 8 contacts thegate insulating film 11. Thegate electrode 8 faces toward the first through sixth side surfaces while thegate insulating film 11 being interposed between the gate electrode and the first through sixth side surfaces. Therefore, thesemiconductor device 50 has a buried gate transistor. - In the
semiconductor device 50 having the above-described structure, electric charges released from thesource region 13 b propagate through onesecond fin portion 12 b, thefirst fin portion 12 a, and the othersecond fin portion 12 b and then enter into thedrain region 13 a. - In the
semiconductor device 50 according to the present embodiment is applied as described above, the pair ofsecond fin portions 12 b (the second channel regions FCS) are provided to extend substantially in the direction vertical to the surface of thesemiconductor substrate 2 from both ends of thefirst fin portion 12 a (the first channel region FCU). The pair ofsecond fin portions 12 b (the second channel regions FCS) will ensure the extended length of the channel region in the first direction as compared to the related art. - It is possible to increase the ON current Ion by reducing the resistance of the entire channel compared to the semiconductor device according to the related art, which has the saddle fin channel structure without
second fin portions 12 b. Therefore, even when the widths of the buriedgate trench portions semiconductor device 50, the channel region can extend in the direction vertical to the surface of thesemiconductor substrate 2, that is, in the direction vertical to the bottom surfaces of thedrain region 13 a and thesource region 13 b. Consequently, a sufficient ON current Ion can be secured by suppressing short channel effect. - In the
semiconductor device 50, thesilicon oxide film 26 is buried in theisolation trench portion 3 as theisolation insulating film 4. Theupper trench portion 10 a and thelower trench portion 10 b included in thesecond trench portion 10 are formed in thesilicon oxide film 26. Theside wall film 51 extending in the second direction is formed to cover both side surfaces of thefirst trench portion 9 and theupper trench portion 10 a described above. - When the
side wall film 51 is made of a silicon nitride film to be described later, it is possible to further suppress a junction leak of thedrain region 13 a and thesource region 13 b (the impurity diffusion layers) from being increased compared to thesemiconductor device 1. At this time, the side wall films 51 (the silicon nitride film) with small thickness are located on side surfaces of thetrench portions - A method of forming the
semiconductor device 50 will be described with reference toFIGS. 34A to 38E . -
FIGS. 34A , 35A, 36A, 37A, and 38A are fragmentary plan views illustrating a transistor in a step involved in the method of forming thesemiconductor device 50.FIGS. 34B , 35B, 36B, 37B, and 38B are fragmentary cross-sectional elevation views taken along an X1-X1′ line illustrating the transistor in a step involved in the method of forming thesemiconductor device 50.FIGS. 34C , 35C, 36C, 37C, and 38C are fragmentary cross-sectional elevation views taken along an X2-X2′ line illustrating the transistor in a step involved in the method of forming thesemiconductor device 50.FIGS. 34D , 35D, 36D, 37D, and 38D are fragmentary cross-sectional elevation views taken along an Y1-Y1′ line illustrating the transistor in a step involved in the method of forming thesemiconductor device 50.FIGS. 34E , 35E, 36E, 37E, and 38E are fragmentary cross-sectional elevation views taken along an Y2-Y2′ line illustrating the transistor in a step involved in the method of forming thesemiconductor device 50. The line Y1-Y1′ and the line Y2-Y2′ indicate cross-sectional portions in a region inside the cell array region SA. - In the cell array region SA shown in
FIGS. 34A , 35A, 36A, 37A, and 38A, a plurality ofisolation regions 5 and a plurality ofactive regions 6 are arranged. However, a state in which someisolation regions 5 and someactive regions 6 arranged in the cell array region SA are enlarged is schematically shown for convenience inFIGS. 34A , 35A, 36A, 37A, and 38A. - Because the
semiconductor device 50 is formed by the processes of forming thesemiconductor device 1 shown inFIGS. 9A to 14F , their descriptions are omitted. - After the above-described processes shown in
FIGS. 14A to 14F , asilicon nitride film 52 and anamorphous carbon film 53 are sequentially stacked over thesemiconductor substrate 2 as shown inFIGS. 34A to 34E . A photo resist is applied on theamorphous carbon film 53. The photo resist is patterned by a lithography technique. Thereby, a resist pattern (not shown) having an opening portion is formed in a position where the buriedgate trench portions amorphous carbon film 53 and thesilicon nitride film 52 are patterned by a dry etching process using the resist pattern as a mask. At this time, the resist pattern on theamorphous carbon film 53 is removed with the progression of etching. The shape of the resist pattern is reflected to theamorphous carbon film 53 and thesilicon nitride film 52. In theamorphous carbon film 53 and thesilicon nitride film 52, openingportions gate trench portion 9 will be formed. - As shown in
FIGS. 35A to 35E , parts shown through the openingportions amorphous carbon film 53 and the patternedsilicon nitride film 52 as a mask. At this time, theamorphous carbon film 53 is also simultaneously removed. Thereby, thesilicon oxide film 26, theimpurity diffusion layer 29, and the surface portion of thesemiconductor substrate 2 shown through the openingportion 52 a are etched at the constant speed. At this time, thefirst trench portion 9 is formed in at least the surface portion of the semiconductor substrate 2 (the active region 6). Theupper trench portion 10 a serving as a part of thesecond trench portion 10 is formed in thesilicon oxide film 26. - As shown in
FIGS. 36A to 36E , a pair ofside wall films 51 are formed to cover both side surfaces of thefirst trench portion 9 and theupper trench portion 10 a. In order to form theside wall films 51, a silicon nitride film is formed to cover the surface of thesemiconductor substrate 2. The silicon nitride film is formed with such a thickness that it is not completely buried inside thetrench portions trench portions side wall films 51 can be formed to cover both side surfaces of thefirst trench portion 9 and theupper trench portion 10 a. - As shown in
FIGS. 37A to 37E , the semiconductor substrate 2 (silicon) shown through thefirst trench portion 9 and thesilicon oxide film 26 shown through theupper trench portion 10 a are removed at the constant speed by an etching process. Thereby, a trench portion is formed under theside wall films 51 which are formed on the side surfaces of thetrench portions - As shown in
FIGS. 38A to 38E , thesilicon oxide film 26 shown through theupper trench portion 10 a is selectively removed by a wet etching process using a solution containing HF. It is possible to etch thesilicon oxide film 26 at a high selectivity to the silicon nitride film (the side wall film 51) by using the HF-containing solution. Therefore, thesilicon oxide film 26 which is not covered by the silicon nitride film (the side wall film 51) is selectively removed without removing the silicon nitride film (the side wall film 51). The wet etching process is an isotropic etching process. Thesilicon oxide film 26 shown through theupper trench portion 10 a is etched in a depth direction and a width direction. Under theupper trench portion 10 a, thelower trench portion 10 b is formed to be 2ΔW wider than theupper trench portion 10 a as shown inFIG. 38C . - The wet etching process using the HF-containing solution is used as a method of forming the
lower trench portion 10 b in this embodiment, but the present invention is not limited thereto. In some cases, a chemical dry etching method using anhydrous hydrogen fluoride gas and ammonia gas may be used as disclosed in the above-described first embodiment. - Thereby, the
second trench portions 10 are formed in theisolation regions 5 of both sides between which theactive region 6 is interposed. There is formed afirst fin portion 12 a which is a first part of theactive region 6 protruding by ΔD from the bottom surface of thesecond trench portion 10. A pair ofsecond fin portions 12 b is formed to be continuous to thefirst fin portion 12 a. The pair ofsecond fin portions 12 b extends in the substantially vertical direction to the surface of thesemiconductor substrate 2. Thesecond fin portions 12 b is second parts of theactive region 6 which are shown by ΔW from thesilicon oxide film 26. - As shown in
FIGS. 39A to 39E , the surfaces of the first andsecond fin portions gate insulating film 11 made of a silicon oxide film is formed. Theconductive film 33 is formed to cover the surface of thesemiconductor substrate 2 and to be buried in the buriedgate trench portions - As shown in
FIGS. 40A to 40E , the surface of theconductive film 33 is polished by CMP for planarization until the surface of thesilicon nitride film 52 serving as a stopper is shown. An etch-back process is performed until the surface of theconductive film 33 is substantially the same in level as a bottom of theimpurity diffusion layer 29. Thereby, thegate electrode 8 is formed. Thegate electrode 8 serves as theword line 7 in the memory cell region SA. - As shown in
FIGS. 41A to 41E , asilicon oxide film 34 a serving as a cap insulating film of thegate electrode 8 is formed by an HDP-CVD method over the entire surface of thesemiconductor substrate 2. - As shown in
FIGS. 42A to 42E , the surface of thesilicon oxide film 34 is polished by CMP for planarization until the surface of thesilicon nitride film 31 is shown. - As shown in
FIGS. 43A to 43E , thesilicon oxide film 34 a is selectively removed by a wet etching process using HF (an etch-back process) until a surface of thesilicon oxide film 34 a is the same in level as the surface of thesemiconductor substrate 2. Thereafter, parts of thesilicon nitride film 52 and theside wall film 51 described above is removed by a wet etching process using hot phosphoric acid (H3PO4). - As shown in
FIGS. 44A to 44E , asilicon oxide film 34 b is formed by an HDP-CVD method over the entire surface of thesemiconductor substrate 2. - There is formed a resist pattern (not shown) having an opening portion which is formed in a position where the
bit contact hole 36 will be formed. Using the resist pattern as a mask, thesilicon oxide film 34 b shown through the opening portion is removed by an anisotropic etching process. Thebit contact hole 36 is formed to extend in the direction (second direction) parallel to thegate electrode 8. - Processes after the process shown in
FIGS. 44A to 44E are basically identical to the processes for forming thesemiconductor device 1 shown inFIGS. 26A to 30B , and thus their descriptions are omitted. Through the above processes, thesemiconductor device 50 shown inFIGS. 31 and 32 described above can be manufactured. - Another
semiconductor device 70 as shown inFIGS. 45 and 46 will be described as the third embodiment. -
FIG. 45 is a fragmentary plan view illustrating thesemiconductor device 70.FIG. 46 is a fragmentary perspective view in which main parts of thesemiconductor device 70 are enlarged. In the following description, the same parts as those of thesemiconductor device 1 are denoted by the same reference numerals in the drawings and their descriptions are omitted. - The
semiconductor device 70 has the following configuration as shown inFIGS. 45 and 46 . As theisolation insulating film 4, thesilicon oxide film 26 is buried in theisolation trench portion 3. In thesilicon oxide film 26, theupper trench portion 10 a and thelower trench portion 10 b included in thesecond trench portion 10 are formed. Except that the side wall film 51 (the silicon nitride film) shown in the second embodiment is not provided, the rest of the configuration is substantially the same as that of thesemiconductor device 50. - In the
semiconductor device 70 like thesemiconductor devices second fin portions - In the
semiconductor device 70, thesilicon oxide film 26 is buried in theisolation trench portion 3 as theisolation insulating film 4 as shown inFIG. 47 . Thesecond trench portion 10 includes theupper trench portion 10 a and thelower trench portion 10 b formed in thesilicon oxide film 26. Theupper trench portion 10 a has the same width W1 as thefirst trench portion 9. Thelower trench portion 10 b is located under theupper trench portion 10 a. Thelower trench portion 10 b has a greater width W2 than theupper trench portion 10 a. Thesecond trench portion 10 has a cross-sectional shape that is line-symmetric with respect to a line extending in the second direction perpendicular to the first direction and extending through a center of thefirst trench portion 9. - A difference between a depth D1 of the
first trench portion 9 and a depth D2 of thesecond trench portion 10 is denoted by ΔD (=D2−D1). Thefirst fin portion 12 a in thefirst trench portion 9 protrudes in the substantially vertical direction to the surface of the substrate by a difference ΔD (=D2−D1) between a depth D1 of thefirst trench portion 9 and a depth D2 of thesecond trench portion 10. Thereby, thefirst fin portion 12 a provides the first channel region FCU having the width W1 in the first direction. In some cases, a surface portion of thefirst fin portion 12 a forms the first channel region FCU. - A difference between the width W1 of the
first trench portion 9 and the width W2 of thesecond trench portion 10 is denoted by 2ΔW (=W2−W1). The pair of thesecond fin portions 12 b in thefirst trench portion 9 respectively protrude in the substantially horizontal direction to the surface of the substrate by half (ΔW) a difference 2ΔW (=W2−W1) between the width W1 of thefirst trench portion 9 and the width W2 of the second trench portion 10 (thelower trench portion 10 b). Thereby, the pair ofsecond fin portions 12 b forms the second channel regions FCS extending in the direction vertical to the surface of thesemiconductor substrate 2 from both ends of thefirst fin portion 12 a. In some cases, surface portions of the pair ofsecond fin portions 12 b form the second channel region FCS. Each of thesecond fin portions 12 b includes an end portion having first and second channel portions of the second channel region FCS. The first and second channel portions are opposed to each other. The first and second channel portions extend substantially vertical to a surface of the semiconductor substrate. - The
semiconductor device 70 may include, but is not limited to, thegate insulating film 11 and thegate electrode 8. Thegate insulating film 11 covers the surfaces of the first andsecond fin portions word line 7 functions as thegate electrode 8. Thegate electrode 8 is buried in the buriedgate trench portions second fin portions gate insulating film 11 is interposed between thegate electrode 8 and thefirst fin portion 12 a and between thegate electrode 8 and thesecond fin portion 12 b. Thereby, thesemiconductor device 70 has the saddle fin channel structure. - In parts of the
active regions 6 between which thegate electrode 8 is interposed, thedrain region 13 a and thesource region 13 b (the impurity diffusion layers) are provided. Thedrain region 13 a and thesource region 13 b function as the source and the drain of the selection transistor, respectively. Thedrain region 13 a and thesource region 13 b are formed by implanting ions. Thedrain region 13 a and thesource region 13 b have bottoms which are connected to the tops of thesecond fin portions 12 b located under thedrain region 13 a and thesource region 13 b, respectively. - As described above, the
semiconductor device 70 may include, but is not limited to, thegate electrode 8, thedrain region 13 a and thesource region 13 b (the impurity diffusion layers), thefirst fin portion 12 a (the first channel region FCU), the pair ofsecond fin portions 12 b (the second channel regions FCS), and thegate insulating film 11. Thegate electrode 8 is located below the surface of thesemiconductor substrate 2. Thegate electrode 8 is buried in the first andsecond trench portions drain region 13 a and thesource region 13 b are located on both sides between which thegate electrode 8 is interposed. Thedrain region 13 a and thesource region 13 b respectively have upper surfaces in positions that are higher than the upper surface of thegate electrode 8. The pair ofsecond fin portions 12 b is connected to the respective bottom surfaces of thedrain region 13 a and thesource region 13 b. The pair ofsecond fin portions 12 b extends substantially in the depth direction (the horizontal direction to the surface of the semiconductor substrate 2) from the respective bottom surfaces of thedrain region 13 a and thesource region 13 b. One of the pair ofsecond fin portions 12 b has first and second side surfaces opposed to each other and a third side surface adjacent to the first and second side surfaces. The other of the pair ofsecond fin portions 12 b has fourth and fifth side surfaces opposed to each other and a sixth side surface adjacent to the forth and fifth side surfaces. The third and sixth side surfaces face toward each other. The distance between the third and sixth surfaces is smaller than the width of thelower trench portion 10 b. Thefirst fin portion 12 a is connected to lower portions of the pair ofsecond fin portions 12 b. Thefirst fin portion 12 a extends in the first direction between the pair ofsecond fin portions 12 b. Thegate insulating film 11 covers the surfaces of the first andsecond fin portions gate insulating film 11 covers the first through sixth side surfaces. Thegate electrode 8 contacts thegate insulating film 11. Thegate electrode 8 faces toward the first through sixth side surfaces while thegate insulating film 11 being interposed between thegate electrode 8 and the first through sixth side surfaces. Therefore, thesemiconductor device 70 has the buried gate transistor. - In the
semiconductor device 50 having the above-described structure, an electric charge released from thesource region 13 b enters thedrain region 13 a by sequentially passing through onesecond fin portion 12 b, thefirst fin portion 12 a, and the othersecond fin portion 12 b. - In the
semiconductor device 70 according to the present embodiment is applied as described above, the pair ofsecond fin portions 12 b (the second channel regions FCS) are provided to extend in the direction vertical to the surface of thesemiconductor substrate 2 from both ends of thefirst fin portion 12 a (the first channel region FCU) in the first direction. The pair ofsecond fin portions 12 b (the second channel regions FCS) will ensure the extended length of the channel region in the first direction as compared to the related art. - It is possible to increase the ON current Ion by reducing the resistance of the entire channel as compared with the semiconductor device according to the related art, which has the saddle fin channel structure without
second fin portions 12 b. Therefore, even when the widths of the buriedgate trench portions semiconductor device 70, the channel region can extend in the direction vertical to the surface of thesemiconductor substrate 2, that is, in the direction vertical to the bottom surfaces of thedrain region 13 a and thesource region 13 b. Consequently, a sufficient ON current can be secured by suppressing a short channel effect. - In the
semiconductor device 70, thesilicon oxide film 26 is buried in theisolation trench portion 3 as theisolation insulating film 4. Theupper trench portion 10 a and thelower trench portion 10 b included in thefirst trench portion 10 are formed in thesilicon oxide film 26. Theside wall film 51 is removed. - The above-described junction leakage can be further suppressed because there is no silicon nitride film in the vicinity of the
drain region 13 a and thesource region 13 b (the impurity diffusion layers) in thesemiconductor device 70. - A method of forming the
semiconductor device 70 will be described with reference toFIGS. 48A to 51E . -
FIGS. 48A , 49A, 50A, and 51A are fragmentary plan views illustrating a transistor in a step involved in the method of forming thesemiconductor device 70.FIGS. 48B , 49B, 50B, and 51B are fragmentary cross-sectional elevation views taken along an X1-X1′ line illustrating the transistor in a step involved in the method of forming thesemiconductor device 70.FIGS. 48C , 49C, 50C, and 51C are fragmentary cross-sectional elevation views taken along an X2-X2′ line illustrating the transistor in a step involved in the method of forming thesemiconductor device 70.FIGS. 48D , 49D, 50D, and 51D are fragmentary cross-sectional elevation views taken along an Y1-Y1′ line illustrating the transistor in a step involved in the method of forming thesemiconductor device 70.FIGS. 48E , 49E, 50E, and 51E are fragmentary cross-sectional elevation views taken along an Y2-Y2′ line illustrating the transistor in a step involved in the method of forming thesemiconductor device 70. The line Y1-Y1′ and the line Y2-Y2′ indicate cross-sectional portions in a region inside the cell array region SA. - In the cell array region SA shown in
FIGS. 48A , 49A, 50A, and 51A, a plurality ofisolation regions 5 and a plurality ofactive regions 6 are arranged. However, a state in which someisolation regions 5 and someactive regions 6 arranged and formed in the cell array region SA are enlarged is schematically shown for convenience inFIGS. 48A , 49A, 50A, and 51A. - The
semiconductor device 70 is formed by the processes of forming thesemiconductor device 1 shown inFIGS. 9A to 14F . Thereafter, thesemiconductor device 70 is formed by the processes of forming thesemiconductor device 50 shown inFIGS. 34A to 38E . Therefore, their descriptions are omitted. - As shown in
FIGS. 48A to 48E , theside wall film 51 and thesilicon nitride film 52 are removed by a wet etching process using a hot phosphoric acid (H3PO4) after the process shown inFIGS. 38A to 38E . As shown inFIGS. 49A to 49E , the surfaces of the first andsecond fin portions gate insulating film 11 made of a silicon oxide film is formed. Theconductive film 33 is formed to cover the surface of thesemiconductor substrate 2 and to be buried in the buriedgate trench portions conductive film 33 is polished by CMP for planarization until the surface of thesilicon oxide film 27 serving as a stopper is shown. An etch-back process is performed until the surface of theconductive film 33 is substantially the same in level as the bottom of thediffusion layer 29. Thereby, thegate electrode 8 is formed. The top surface of thegate electrode 8 is lower in level than the top surface of theisolation region 5. - The
gate electrode 8 serves as theword line 7 in the memory cell region SA. - As shown in
FIGS. 50A to 50E , thesilicon oxide film 34 a is formed by an HDP-CVD method over the entire surface of thesemiconductor substrate 2. Thesilicon oxide film 34 a has a sufficient thickness to be buried in thetrench portions conductive film 34 a is polished by CMP for planarization until the surface of thesilicon oxide film 27 serving as a stopper is shown. Thesilicon oxide film 34 a serves as a cap insulating film of thegate electrode 8. - As shown in
FIGS. 51A to 51E , thesilicon oxide film 34 b is formed by an HDP-CVD method over the entire surface of thesemiconductor substrate 2. - A resist pattern (not shown) having an opening portion which is formed in a position where the
bit contact hole 36 will be formed. Using the resist pattern as a mask, thesilicon oxide film 34 b shown through the opening portion is removed by an anisotropic etching process. Thebit contact hole 36 is formed to extend in the direction (second direction) parallel to thegate electrode 8. - Processes after the process shown in
FIGS. 51A to 51E are basically identical to the processes for forming thesemiconductor device 1 shown inFIGS. 26A to 30B , and thus their descriptions are omitted. Through the above processes, thesemiconductor device 70 shown inFIGS. 45 and 46 described above can be manufactured. - A
data processing system 400 as shown inFIG. 52 will be described. Thedata processing system 400 is an example of a system including thesemiconductor device data processing system 400 may include, but is not limited to, a computer system. - The
data processing system 400 may include, but is not limited to, adata processor 420 and aDRAM 460 according to the first through third embodiments. Thedata processor 420 may include, but is not limited to, a microprocessor (MPU), a digital signal processor (DSP), or the like. - The
data processor 420 is connected to theDRAM 460 via asystem bus 410. However, it may be connected by a local bus without involving thesystem bus 410. Onesystem bus 410 is shown inFIG. 52 , but serial and parallel connections may be made via a connector or the like, if necessary. - A
storage device 430, an I/O device 440, and aROM 450 of thedata processing system 400 are connected to thesystem bus 410, if necessary, but are not essential constituent elements. In some cases, the I/O device 440 may be only any one of an input device or an output device. The number of each element in thedata processing system 400 is not particularly limited, and may be at least one or more. - The comparison evaluation test was performed by comparing the characteristics of driving currents Ion, threshold voltages Vt, and subthreshold swings (SS) between the semiconductor device of the present invention shown in
FIG. 4 and the semiconductor device of the related art shown inFIG. 5 . Evaluation results of the driving currents Ion, the threshold voltages Vt, and the subthreshold swings (SS) are respectively shown inFIGS. 6 to 8 . - In the semiconductor devices shown in
FIGS. 4 and 5 , the same parts as those of the semiconductor device shown inFIG. 2 are denoted by the same reference numerals in the drawings. A current pass (CP) of an arrow shown inFIGS. 4 and 5 indicates a current path serving as a channel. - The semiconductor device of the present invention shown in
FIG. 4 has the same saddle fin channel structure as thesemiconductor device 1 shown inFIG. 3 . The pair ofsecond fin portions 12 b (the second channel regions FCS) are provided to extend in the direction vertical to the surface of thesemiconductor substrate 2 from both ends of thefirst fin portion 12 a (the first channel region FCU). Thesource region 13 a and thedrain region 13 b are provided on the pair ofsecond fin portions 12 b. Thegate electrode 8 is buried in the buriedgate trench portions - The semiconductor device of the related art shown in
FIG. 5 is the same as thesemiconductor device 1 shown inFIG. 3 , except that it has the saddle fin channel structure having only thefirst fin portion 12 a (the first channel region FCU). - For the semiconductor device of the present invention, the results of the driving currents Ion, the threshold voltages Vt, and the subthreshold swings (SS) were evaluated when a protrusion amount ΔD of the
first fin portion 12 a was 0, 10, and 20 nm. As a comparative example, for the semiconductor device of the related art, the results of the driving currents Ion, the threshold voltages Vt, and the subthreshold swings (SS) were evaluated in the same manner as the semiconductor device of the present invention. In this comparison evaluation test, a protrusion amount ΔW of thesecond fin portion 12 b in the semiconductor device of the present invention was designated as 10 nm and all of a physical size, an applied voltage, and the like had the same conditions. - As shown in
FIG. 6 , the semiconductor device of the present invention (solid line) is greater in Ion value than the semiconductor device of the related art (broken line) by about 3 μA. The driving current of the transistor needs to have stable characteristics for a stable operation of the semiconductor device even when the transistor is miniaturized. It is preferable that the driving current of the transistor have a large value. Therefore, it can be seen that the semiconductor device of the present invention is superior to the semiconductor device of the related art. - As shown in
FIG. 7 , the semiconductor device of the present invention (solid line) is less in Vt value than the semiconductor device of the related art (broken line) as a whole. In particular, when a height of thefin portion 12 a is 10 nm, the semiconductor device of the present invention is less in Vt value than the semiconductor device of the related art by about 0.07V. It is preferable that the threshold voltage of the transistor be a low voltage to satisfy the requirement of low power consumption of the semiconductor device. Therefore, it can be seen that the semiconductor device of the present invention is superior to the semiconductor device of the related art. - As shown in
FIG. 8 , the semiconductor device of the present invention (solid line) is less in subthreshold swings (SS) than the semiconductor device of the related art (broken line) as a whole. In particular, when the height of thefin portion 12 a is 10 nm, the semiconductor device of the present invention is less in subthreshold swings (SS) than the semiconductor device of the related art (broken line) by about 6 mV/decade. The subthreshold swing of the transistor is an ON/OFF characteristic index. From a point of view of a high-speed operation of the semiconductor device, it is preferable that the subthreshold swing be a small value. Therefore, it can be seen that the semiconductor device of the present invention is superior to the semiconductor device of the related art. - As described above, the semiconductor device of the present invention has results indicating superiority to the semiconductor device of the related art in the respective characteristics of the threshold voltage Vt, the driving current Ion, and the subthreshold swing (SS).
- As used herein, the following directional terms “forward, rearward, above, downward, vertical, horizontal, below, and transverse” as well as any other similar directional terms refer to those directions of an apparatus equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to an apparatus equipped with the present invention.
- Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
- The terms of degree such as “substantially,” “about,” and “approximately” as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. For example, these terms can be construed as including a deviation of at least ±5 percents of the modified term if this deviation would not negate the meaning of the word it modifies.
- It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
Claims (1)
1. A method for manufacturing a semiconductor device comprising:
patterning a semiconductor substrate;
forming an isolation region and an active region on the substrate, the isolation and active regions being alternately adjacent while extending in a first direction;
forming a first trench portion in at least a surface portion of the semiconductor substrate corresponding to the active region;
forming second trench portions on the isolation region, wherein the second trench portions comprise upper trench portions and lower trench portions, and wherein the lower trench portions are wider than the upper trench portions;
forming a first fin portion, which is a first part of the active region, and which protrudes in a vertical direction to the surface of the substrate; and
forming second fin portions which are continuously connected to the first fin portion and extend in a horizontal direction to the surface of the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/612,397 US20150147862A1 (en) | 2010-05-19 | 2015-02-03 | Method for manufacturing a semiconductor device |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010115538A JP5718585B2 (en) | 2010-05-19 | 2010-05-19 | Semiconductor device, manufacturing method thereof, and data processing system |
JP2010-115538 | 2010-05-19 | ||
US13/105,437 US8624333B2 (en) | 2010-05-19 | 2011-05-11 | Semiconductor device, method of forming semiconductor device, and data processing system |
US14/107,650 US20140103442A1 (en) | 2010-05-19 | 2013-12-16 | Semiconductor device, method of forming semiconductor device, and data processing system |
US14/612,397 US20150147862A1 (en) | 2010-05-19 | 2015-02-03 | Method for manufacturing a semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/107,650 Continuation US20140103442A1 (en) | 2010-05-19 | 2013-12-16 | Semiconductor device, method of forming semiconductor device, and data processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150147862A1 true US20150147862A1 (en) | 2015-05-28 |
Family
ID=44971812
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/105,437 Active 2031-10-18 US8624333B2 (en) | 2010-05-19 | 2011-05-11 | Semiconductor device, method of forming semiconductor device, and data processing system |
US14/107,650 Abandoned US20140103442A1 (en) | 2010-05-19 | 2013-12-16 | Semiconductor device, method of forming semiconductor device, and data processing system |
US14/612,397 Abandoned US20150147862A1 (en) | 2010-05-19 | 2015-02-03 | Method for manufacturing a semiconductor device |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/105,437 Active 2031-10-18 US8624333B2 (en) | 2010-05-19 | 2011-05-11 | Semiconductor device, method of forming semiconductor device, and data processing system |
US14/107,650 Abandoned US20140103442A1 (en) | 2010-05-19 | 2013-12-16 | Semiconductor device, method of forming semiconductor device, and data processing system |
Country Status (2)
Country | Link |
---|---|
US (3) | US8624333B2 (en) |
JP (1) | JP5718585B2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012253122A (en) * | 2011-06-01 | 2012-12-20 | Elpida Memory Inc | Semiconductor device manufacturing method and data processing system |
KR101797961B1 (en) * | 2011-06-09 | 2017-11-16 | 삼성전자주식회사 | Method for fabricating semiconductor device |
JP5856545B2 (en) | 2012-07-06 | 2016-02-09 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP2014022388A (en) * | 2012-07-12 | 2014-02-03 | Ps4 Luxco S A R L | Semiconductor device and method for manufacturing the same |
US8881209B2 (en) | 2012-10-26 | 2014-11-04 | Mobitv, Inc. | Feedback loop content recommendation |
US8735267B1 (en) | 2012-12-06 | 2014-05-27 | Nanya Technology Corporation | Buried word line structure and method of forming the same |
US10276436B2 (en) * | 2016-08-05 | 2019-04-30 | International Business Machines Corporation | Selective recessing to form a fully aligned via |
US10403714B2 (en) * | 2017-08-29 | 2019-09-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fill fins for semiconductor devices |
KR102420163B1 (en) | 2018-01-18 | 2022-07-12 | 삼성전자주식회사 | Integrated circuit device and method of manufacturing the same |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040262687A1 (en) * | 2003-06-27 | 2004-12-30 | In-Soo Jung | Fin field effect transistors and fabrication methods thereof |
US20110298050A1 (en) * | 2009-12-16 | 2011-12-08 | Institute of Microelectronics, Chinese Academy of Sciences | Fin transistor structure and method of fabricating the same |
US20110316080A1 (en) * | 2009-12-30 | 2011-12-29 | Institute of Microelectronics, Chinese Academy of Sciences | Fin transistor structure and method of fabricating the same |
US20120292715A1 (en) * | 2011-05-17 | 2012-11-22 | Hong Hyung-Seok | Semiconductor device and method of fabricating the same |
US20130082282A1 (en) * | 2011-09-30 | 2013-04-04 | Kabushiki Kaisha Toshiba | Silicon carbide semiconductor device |
US20130175624A1 (en) * | 2012-01-11 | 2013-07-11 | International Business Machines Corporation | Recessed source and drain regions for finfets |
US20130214357A1 (en) * | 2012-02-16 | 2013-08-22 | International Business Machines Corporation | Non-planar mosfet structures with asymmetric recessed source drains and methods for making the same |
US20140035066A1 (en) * | 2012-07-31 | 2014-02-06 | Shih-Hung Tsai | Non-Planar FET and Manufacturing Method Thereof |
US20140048870A1 (en) * | 2012-08-16 | 2014-02-20 | SK Hynix Inc. | Semiconductor device and method for forming the same |
Family Cites Families (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3378414B2 (en) * | 1994-09-14 | 2003-02-17 | 株式会社東芝 | Semiconductor device |
JPH09312331A (en) * | 1996-05-23 | 1997-12-02 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JP2001077189A (en) * | 1999-09-08 | 2001-03-23 | Sony Corp | Manufacture of semiconductor device |
KR100338783B1 (en) * | 2000-10-28 | 2002-06-01 | Samsung Electronics Co Ltd | Semiconductor device having expanded effective width of active region and fabricating method thereof |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
KR100481209B1 (en) * | 2002-10-01 | 2005-04-08 | 삼성전자주식회사 | MOS Transistor having multiple channels and method of manufacturing the same |
US6838322B2 (en) * | 2003-05-01 | 2005-01-04 | Freescale Semiconductor, Inc. | Method for forming a double-gated semiconductor device |
US7095065B2 (en) * | 2003-08-05 | 2006-08-22 | Advanced Micro Devices, Inc. | Varying carrier mobility in semiconductor devices to achieve overall design goals |
US7172943B2 (en) * | 2003-08-13 | 2007-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-gate transistors formed on bulk substrates |
JP2005064500A (en) | 2003-08-14 | 2005-03-10 | Samsung Electronics Co Ltd | Multi-structured silicon fin and manufacturing method for the same |
US7141851B2 (en) * | 2003-08-22 | 2006-11-28 | Samsung Electronics Co., Ltd. | Transistors having a recessed channel region |
JP4439358B2 (en) * | 2003-09-05 | 2010-03-24 | 株式会社東芝 | Field effect transistor and manufacturing method thereof |
US6963114B2 (en) * | 2003-12-29 | 2005-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | SOI MOSFET with multi-sided source/drain silicide |
KR100577562B1 (en) * | 2004-02-05 | 2006-05-08 | 삼성전자주식회사 | Method for fabricating fin field effect transistor and structure thereof |
KR100574971B1 (en) * | 2004-02-17 | 2006-05-02 | 삼성전자주식회사 | Semiconductor device having multi-gate structure and method of manufacturing the same |
KR100532204B1 (en) * | 2004-03-04 | 2005-11-29 | 삼성전자주식회사 | Transistor having the Fin structure and Method of manufacturing the same |
US7115947B2 (en) * | 2004-03-18 | 2006-10-03 | International Business Machines Corporation | Multiple dielectric finfet structure and method |
JP3964885B2 (en) * | 2004-05-19 | 2007-08-22 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP2006054431A (en) * | 2004-06-29 | 2006-02-23 | Infineon Technologies Ag | Transistor, memory cell array, and manufacturing method of the transistor |
US7098507B2 (en) * | 2004-06-30 | 2006-08-29 | Intel Corporation | Floating-body dynamic random access memory and method of fabrication in tri-gate technology |
KR100689211B1 (en) * | 2004-12-11 | 2007-03-08 | 경북대학교 산학협력단 | Saddle type MOS device |
KR100630725B1 (en) * | 2004-12-17 | 2006-10-02 | 삼성전자주식회사 | Semiconductor device having buried bit line and method of manufacturing the same |
KR100691006B1 (en) * | 2005-04-29 | 2007-03-09 | 주식회사 하이닉스반도체 | Cell transistor structure of memory device and method for fabricating the same |
KR100608377B1 (en) * | 2005-05-02 | 2006-08-08 | 주식회사 하이닉스반도체 | Method for fabricating cell transistor of memory device |
KR100630746B1 (en) * | 2005-05-06 | 2006-10-02 | 삼성전자주식회사 | Multi-bit and multi-level non-volatile memory device and methods of operating and fabricating the same |
KR100608380B1 (en) * | 2005-06-01 | 2006-08-08 | 주식회사 하이닉스반도체 | Transistor of memory device and method for fabricating the same |
KR100640653B1 (en) | 2005-07-15 | 2006-11-01 | 삼성전자주식회사 | Method of manufacturing semiconductor device having vertical channel and semiconductor device using the same |
KR100642384B1 (en) * | 2005-09-15 | 2006-11-03 | 주식회사 하이닉스반도체 | Transistor for semiconductor memory device and method of fabricating the same |
US7525160B2 (en) * | 2005-12-27 | 2009-04-28 | Intel Corporation | Multigate device with recessed strain regions |
KR100726150B1 (en) * | 2005-12-29 | 2007-06-13 | 주식회사 하이닉스반도체 | Method for manufacturing saddle type fin transistor |
KR100720238B1 (en) * | 2006-01-23 | 2007-05-23 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
JP2007305827A (en) | 2006-05-12 | 2007-11-22 | Elpida Memory Inc | Semiconductor device, and its manufacturing method |
KR100745885B1 (en) * | 2006-07-28 | 2007-08-02 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
KR100881818B1 (en) * | 2006-09-04 | 2009-02-03 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
US7399664B1 (en) * | 2007-02-28 | 2008-07-15 | International Business Machines Corporation | Formation of spacers for FinFETs (Field Effect Transistors) |
US7667271B2 (en) * | 2007-04-27 | 2010-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors |
KR20080099485A (en) * | 2007-05-09 | 2008-11-13 | 주식회사 하이닉스반도체 | Transistor in semiconductor device and method for manufacturing the same |
TW200847292A (en) * | 2007-05-29 | 2008-12-01 | Nanya Technology Corp | Method of manufacturing a self-aligned FinFET device |
JP2008300384A (en) * | 2007-05-29 | 2008-12-11 | Elpida Memory Inc | Semiconductor device and its manufacturing method |
JP5605975B2 (en) * | 2007-06-04 | 2014-10-15 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device, manufacturing method thereof, and data processing system |
US8866254B2 (en) * | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
US7915659B2 (en) * | 2008-03-06 | 2011-03-29 | Micron Technology, Inc. | Devices with cavity-defined gates and methods of making the same |
KR100990599B1 (en) * | 2008-05-30 | 2010-10-29 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor apparatus and semiconductor apparatus manufactured thereby |
KR101113794B1 (en) * | 2008-08-04 | 2012-02-27 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor integrated circuit device |
KR101087936B1 (en) * | 2009-11-30 | 2011-11-28 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming using the same |
JP2011159760A (en) * | 2010-01-29 | 2011-08-18 | Elpida Memory Inc | Method of manufacturing semiconductor device, and the semiconductor device |
US8310013B2 (en) * | 2010-02-11 | 2012-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a FinFET device |
US9202921B2 (en) * | 2010-03-30 | 2015-12-01 | Nanya Technology Corp. | Semiconductor device and method of making the same |
-
2010
- 2010-05-19 JP JP2010115538A patent/JP5718585B2/en not_active Expired - Fee Related
-
2011
- 2011-05-11 US US13/105,437 patent/US8624333B2/en active Active
-
2013
- 2013-12-16 US US14/107,650 patent/US20140103442A1/en not_active Abandoned
-
2015
- 2015-02-03 US US14/612,397 patent/US20150147862A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040262687A1 (en) * | 2003-06-27 | 2004-12-30 | In-Soo Jung | Fin field effect transistors and fabrication methods thereof |
US20110298050A1 (en) * | 2009-12-16 | 2011-12-08 | Institute of Microelectronics, Chinese Academy of Sciences | Fin transistor structure and method of fabricating the same |
US20110316080A1 (en) * | 2009-12-30 | 2011-12-29 | Institute of Microelectronics, Chinese Academy of Sciences | Fin transistor structure and method of fabricating the same |
US20120292715A1 (en) * | 2011-05-17 | 2012-11-22 | Hong Hyung-Seok | Semiconductor device and method of fabricating the same |
US20130082282A1 (en) * | 2011-09-30 | 2013-04-04 | Kabushiki Kaisha Toshiba | Silicon carbide semiconductor device |
US20130175624A1 (en) * | 2012-01-11 | 2013-07-11 | International Business Machines Corporation | Recessed source and drain regions for finfets |
US20130214357A1 (en) * | 2012-02-16 | 2013-08-22 | International Business Machines Corporation | Non-planar mosfet structures with asymmetric recessed source drains and methods for making the same |
US20140035066A1 (en) * | 2012-07-31 | 2014-02-06 | Shih-Hung Tsai | Non-Planar FET and Manufacturing Method Thereof |
US20140048870A1 (en) * | 2012-08-16 | 2014-02-20 | SK Hynix Inc. | Semiconductor device and method for forming the same |
Also Published As
Publication number | Publication date |
---|---|
JP2011243802A (en) | 2011-12-01 |
US20140103442A1 (en) | 2014-04-17 |
JP5718585B2 (en) | 2015-05-13 |
US20110284969A1 (en) | 2011-11-24 |
US8624333B2 (en) | 2014-01-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8624333B2 (en) | Semiconductor device, method of forming semiconductor device, and data processing system | |
KR102471722B1 (en) | Semiconductor memory device | |
US9472557B2 (en) | Memory transistors with buried gate electrodes | |
US9496383B2 (en) | Semiconductor device and method of forming the same | |
US7145220B2 (en) | Fin semiconductor device and method for fabricating the same | |
JP5731858B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
US8648415B2 (en) | Semiconductor device with impurity region with increased contact area | |
US7821060B2 (en) | Semiconductor device including trench gate transistor and method of forming the same | |
US8309425B2 (en) | Method of manufacturing semiconductor device | |
JP2006013529A (en) | Method for manufacturing semiconductor device | |
US20120211815A1 (en) | Semiconductor device and method of forming the same | |
JP2004172643A5 (en) | ||
US20140227855A1 (en) | Semiconductor device having gate trench and manufacturing method thereof | |
US20230197450A1 (en) | Methods of manufacturing semiconductor devices using enhanced patterning techniques | |
CN115411039A (en) | Semiconductor memory device with a plurality of memory cells | |
US6674111B2 (en) | Semiconductor device having a logic transistor therein | |
JP2009009988A (en) | Semiconductor device and its fabrication process | |
US20240032286A1 (en) | Integrated circuit devices | |
JP2012064632A (en) | Semiconductor device, and method of manufacturing the same | |
JP2015012120A (en) | Semiconductor device manufacturing method | |
JP4031777B2 (en) | Semiconductor device | |
KR20110079279A (en) | Semiconductor device and method for manufacturing the same | |
KR20110079281A (en) | Semiconductor device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |