US20150102406A1 - Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same - Google Patents

Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same Download PDF

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US20150102406A1
US20150102406A1 US14/052,075 US201314052075A US2015102406A1 US 20150102406 A1 US20150102406 A1 US 20150102406A1 US 201314052075 A US201314052075 A US 201314052075A US 2015102406 A1 US2015102406 A1 US 2015102406A1
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doped region
semiconductor substrate
conductivity type
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conductive layer
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Tsung-Hsiung LEE
Jui-Chun Chang
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Vanguard International Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like

Definitions

  • the present invention relates to integrated circuit (IC) devices, and in particular to a lateral double diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the same.
  • IC integrated circuit
  • LDMOS lateral double diffused metal-oxide-semiconductor
  • wireless communication products such as mobile phones and base stations have been developed greatly.
  • high-voltage elements of lateral double diffused metal-oxide-semiconductor (LDMOS) devices are often used as radio frequency (900 MHz-2.4 GHz) related elements therein.
  • LDMOS lateral double diffused metal-oxide-semiconductor
  • LDMOS devices not only have a higher operation frequency, but they are also capable of sustaining a higher breakdown voltage, thereby having a high output power so that they can be used as power amplifiers in wireless communication products.
  • LDMOS devices can be formed by conventional CMOS fabrications, LDMOS devices can be fabricated from a silicon substrate which is relatively cost-effective and employs mature fabrication techniques.
  • FIG. 1 a schematic cross section showing a conventional N-type lateral double diffused metal-oxide-semiconductor (LDMOS) device applicable in a radio frequency (RF) circuit element is illustrated.
  • the N-type LDMOS device mainly comprises a P+ type semiconductor substrate 100 , a P ⁇ type epitaxial semiconductor layer 102 formed over the P+ type semiconductor substrate 100 , and a gate structure G formed over a portion of the P ⁇ type epitaxial semiconductor layer 102 .
  • a P ⁇ type doped region 104 is disposed in the P ⁇ type epitaxial semiconductor layer 102 under the gate structure G and a portion of the P ⁇ type epitaxial semiconductor layer 102 under the left side of the gate structure G, and a N ⁇ type drift region 106 is disposed in a portion of the P ⁇ type epitaxial semiconductor layer 102 under the right side of the gate structure G.
  • a P+ type doped region 130 and a N+ type doped region 110 are disposed in a portion of the P type doped region 104 , and the P+ doped region 130 partially contacts a portion of the N+ type doped region 110 , thereby functioning as a contact region (e.g. P+ type doped region 130 ) and a source region (e.g.
  • N+ type doped region 110 of the N type LDMOS device, respectively, and another N+ type doped region 108 is disposed in a portion of the P ⁇ type epitaxial semiconductor layer 102 at the right side of the N ⁇ type drift region 106 to function as a drain region of the N type LDMOS device.
  • an insulating layer 112 is formed over the gate structure G, covering sidewalls and a top surface of the gate structure G and partially covering the N+ type doped regions 108 and 110 adjacent to the gate structure G.
  • the N type LDMOS further comprises a P+ type doped region substantially disposed in a portion of the P ⁇ type epitaxial semiconductor layer 102 under the N+ type doped region 110 and the P ⁇ type doped region 104 under the N+ type doped region 110 .
  • the P+ type doped region 120 physically connects the P ⁇ type doped region 104 with the P+ type semiconductor substrate 100 .
  • formation of the P+ type doped region 120 needs to perform ion implantations of high doping concentrations and high doping energies and thermal diffusion processes with a relatively high temperature above about 900° C., and a predetermined distance D1 is kept between the gate structure G and the N+ type doped region 110 at the left side of the gate structure G to ensure good performance of the N type LDMOS device. Therefore, formation of the P+ type doped region 120 and the predetermined distance D1 kept between the gate structure G and the N+ type doped region 110 increase the on-state resistance (Ron) of the N type LDMOS device and a dimension of the N type LDMOS device, which is unfavorable for further reduction of both the fabrication cost and the dimensions of the N type LDMOS device.
  • Ron on-state resistance
  • an improved lateral double diffused metal oxide semiconductor (LDMOS) device and method for fabricating the same are provided to reduce size and fabrication cost.
  • LDMOS lateral double diffused metal oxide semiconductor
  • An exemplary lateral double diffused metal oxide semiconductor (LDMOS) device comprises: a semiconductor substrate, having opposite first and second surfaces and a first conductivity type; a well region formed in a portion of the semiconductor substrate adjacent to the first surface thereof, having the first conductivity type; a gate structure disposed over a portion of the first surface of the semiconductor substrate; a first doped region disposed in a portion of the well region adjacent to a first side of the gate structure, having the first conductivity type; a second doped region disposed in a portion of the well region adjacent to a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type; a third doped region disposed in a portion of the first doped region, having the second conductivity type; a fourth doped region disposed in a portion of the second doped region, having the second conductivity type; a first trench formed in a portion of the third doped region, the first doped region, the well region, and the semiconductor substrate; a conductive contact formed
  • An exemplary method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device comprises: performing a semiconductor substrate, having opposite first and second surfaces and a first conductivity type; performing an ion implantation process, forming a well region in a portion of the semiconductor substrate adjacent to the first surface thereof, having the first conductivity type; forming a gate structure over a portion of the well region; forming a first doped region in a portion of the well region adjacent to a first side of the gate structure, having the first conductivity type; forming a second doped region in a portion of the well region at a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type; forming a third doped region in a portion of the first doped region, having the second conductivity type; forming a fourth doped region in a portion of the second doped region, having the second conductivity type; forming a trench in a portion of the third doping region, the first doped region, the well region
  • FIG. 1 is schematic cross section of a conventional lateral double diffused metal-oxide-semiconductor (LDMOS) device
  • FIGS. 2-6 are schematic cross sections showing a method for fabricating a lateral double diffused metal-oxide-semiconductor (LDMOS) device according to an embodiment of the invention.
  • LDMOS lateral double diffused metal-oxide-semiconductor
  • FIGS. 2-6 are schematic cross sections showing a method for fabricating a lateral double diffused metal-oxide-semiconductor (LDMOS) device applicable for a radio frequency (RF) circuit element according to an embodiment of the invention.
  • LDMOS lateral double diffused metal-oxide-semiconductor
  • a semiconductor substrate 200 such as a silicon substrate is first provided.
  • the semiconductor substrate 200 has a first conductivity type such as a P type conductivity, and a resistivity of about 5 ohms-cm ( ⁇ -cm)-15 ohms-cm ( ⁇ -cm).
  • the semiconductor substrate 200 has opposing surfaces A and B.
  • a sacrificial layer 202 is formed over the surface A of the semiconductor substrate 202 .
  • the sacrificial layer 202 may comprise materials such as silicon oxide and may be formed by a deposition process (not shown) such as thermal oxidation.
  • an ion implantation process 204 is performed to the semiconductor substrate 200 to implant dopants of the first conductivity type through the sacrificial layer 202 and into a portion of the semicondcutor substrate 200 , thereby forming a doped region 206 .
  • the dopants of the first conductive type implanted by the ion implantation process 204 can be, for example, dopants of P-type conductivity.
  • a thermal process (not shown) is performed to diffuse the dopants in the doped region 206 , thereby forming a well region 208 in the semiconductor substrate 200 .
  • the well region 208 comprises dopants of the first conductivity type, and has a resistivity of about 0.5 ohms-cm ( ⁇ -cm)-1 ohms-cm ( ⁇ -cm). In one embodiment, the resistivity of the well region 208 is lower than the resistivity of the semiconductor substrate 200 .
  • the sacrificial layer 202 over the surface A of the semiconductor substrate 200 is removed, and a patterned gate structure G is formed over a portion of the surface A of the semiconductor substrate 200 .
  • the gate structure G mainly comprises a gate dielectric layer 210 , a gate electrode 212 , and a hard mask layer 214 sequentially formed over a portion of the semiconductor substrate 200 .
  • the gate dielectric layer 210 , the gate electrode 212 , and the hard mask layer 214 of the gate structure G can be formed by conventional gate processes and related materials, and are not described here in detail for the purpose of simplicity.
  • a plurality of suitable masks (not shown) and a plurality of ion implant processes are then performed to form a doped region 216 in a portion of the semiconductor substrate 200 at the left side of the gate structure G, and a doped region 218 in a portion of the semiconductor substrate 200 at the right side of the gate structure G.
  • the doped region 216 has a first conductivity type such as P type
  • the doped region 218 has a second conductivity type such as N type opposite to the P type
  • the ion implant processes (not shown) for forming the doped regions 216 and 218 can be ion implant processes with tilted implantation angles.
  • another suitable implant mask (not shown) and an ion implantation process (not shown) are performed to form a doped region 220 and a doped region 222 in a portion of the doped regions 216 and 218 , respectively, on opposite sides of the gate structure G, and the configuration shown in FIG. 3 is formed after performing a thermal diffusion process (not shown).
  • the doped region 220 formed in a portion of the doped region 216 and the doped region 222 formed in a portion of the doped region 218 respectively has the second conductivity type, such as N type, and the ion implant process (not shown) for forming the doped regions 220 and 222 can be an ion implantation vertical to the surface A of the semiconductor substrate 200 .
  • the doped region 218 may function as a drift region, and the doped regions 220 and 222 may function as source and drain regions, respectively.
  • an insulating layer 224 is next formed over the semiconductor substrate 200 , and the insulating layer 224 conformably covers the surface A of the semiconductor substrate 200 and a plurality of sidewalls and a top surface of the gate structure G formed thereover.
  • a patterning process (not shown) is performed to form an opening 226 in a portion of the insulating layer 224 .
  • the opening 226 exposes a portion of the doped region 220 such that other portions of the the semiconductor substrate 200 and surfaces of the gate structure G are still covered by the insulating layer 224 .
  • the insulating layer 224 may comprise insulating materials such as silicon oxide and silicon nitride, and can be formed by a method such as chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • an etching process (not shown) is performed, using the insulating layer 224 as an etching mask, thereby forming a trench 228 in the semiconductor substrate 200 exposed by the opening 226 .
  • the trench 228 is formed with a depth H which mainly penetrates a portion of the doped region 220 , the doped region 216 , the well region 208 , and the semiconductor substrate 200 .
  • a conductive layer 230 and another conductive layer 232 are then sequentially deposited, wherein the conductive layer 230 conformably forms over surfaces of the insulating layer 224 and the bottom surface and the sidewalls of the semiconductor substrate 200 exposed by the trench 228 , and the conductive layer 232 is formed over the surfaces of the conductive layer 230 , thereby filling the trench 228 .
  • the conductive layers 230 and 232 are patterned by using a suitable patterning mask and a patterning process (both not shown). As shown in FIG.
  • the patterned conductive layers 230 and 232 are formed over the insulating layer 224 adjacent to the trench 228 , extending over the bottom surface and the sidewalls of the trench 228 , thereby covering surfaces of the well region 208 , and the doped regions 216 , 220 exposed by the trench 228 , and the conductive layers 230 and 232 also cover the gate structure G and a portion of the doped region 218 adjacent to the gate structure G. However, the conductive layers 230 and 232 do not cover the doped region 222 .
  • the portion of the conductive layers 230 and 232 formed in the trench 228 may function as a conductive contact.
  • the conductive layer 230 may comprise conductive materials such as Ti—TiN alloy
  • the conductive layer 232 may comprise conductive materials such as tungsten.
  • a dielectric material such as silicon oxide or spin-on-glass (SOG) is deposited over the conductive layers 230 and 232 , such that the dielectric material covers the conductive layer 232 , the insulating layer 224 , and the gate structure G, thereby forming an inter-layer dielectric (ILD) layer 234 with a substantially planar top surface.
  • a patterning process (not shown) comprising photolithography and etching steps is performed to form a trench 236 in a portion of the ILD layer 234 and the insulating layer 224 over a portion of the doped region 222 , and the trench 236 exposes a portion of the doped region 222 .
  • a conductive layer 238 and another conductive layer 240 are sequentially deposited, and the conductive layer 238 conformably forms over the surfaces of the ILD layer 234 and the sidewalls exposed by the trench 236 , and the conductive layer 240 is formed over the surface of the conductive layer 238 , thereby filling the trench 236 .
  • the portion of the conductive layers 238 and 240 formed in the trench 236 may function as a conductive contact.
  • the conductive layer 238 may comprise conductive materials such as Ti—TiN alloy, and the conductive layer 240 may comprise conductive materials such as tungsten.
  • a handling substrate (not shown) is used to bond with a surface of the conductive layer 240 and then the structure shown in FIG. 5 is reversed, and a thinning process (not shown) comprising steps such as etching, polishing or combinations thereof are then performed to reduce the thickness of the semiconductor substrate 200 from the surface B thereof.
  • the thinned semiconductor substrate 200 is assigned with a reference number 200 ′, and a thinned surface B′ of the thinned semiconductor substrate 200 ′ has a distance X to the bottom surface of the conductive layer 230 in the trench 228 .
  • the distance X is about 50-300 ⁇ m.
  • a patterning process (not shown) is performed by using a suitable patterned mask layer (not shown), thereby forming a trench 242 in the surface B′ of the thinned semiconductor substrate 200 ′, and the trench 242 exposes the bottom surface and portions of the sidewalls of the conductive layer 230 .
  • a deposition process (not shown) is performed to form a conductive layer 244 in the trench 242 .
  • the conductive layer 244 may comprise conductive materials such as Ti—TiN alloy, tungsten, AlCu alloy, AlSiCu alloy, and may be formed by a deposition process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • the formed conductive layer 244 may be processed by a planarization process (not shown), such that a surface of the conductive layer 244 is coplanar with the surface B′ of the thinned semiconductor substrate 200 .
  • a planarization process (not shown) is performed to form a blanket conductive layer 246 over the surface of the conductive layer 244 and the surface of the thinned semiconductor substrate 200 ′.
  • the conductive layer 246 may comprise conductive materials such as Ti—Ni—Ag alloy, and may be formed by a method such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Therefore, after removal of the handling substrate (not shown), an exemplar LDMOS device is substantially fabricated, as shown in FIG. 6 .
  • the gate structure G and the doped regions 220 and 222 of the LDMOS device shown in FIG. 6 may be properly electrically connected (e.g. through conductive layers 230 , 232 , 238 , and 240 ), and the regions with the first conductivity type can be P type regions, and the regions of the second conductivity type can be N type regions, such that the formed LDMOS device herein is an N type LDMOS device.
  • the doped region 220 may function as a source region and the doped region 222 may function as a drain region.
  • currents from the drain side e.g.
  • the doped region 222 may laterally flow toward the source side (e.g. doped region 220 ), and then arrive at the surface B′ of the thinned semiconductor substrate 200 ′ by the guidance of the doped region 216 , the conductive layers 230 and 232 , and the conductive layer 244 , and are then dissipated by the conductive layer 246 , such that undesired problems such as inductor coupling and cross-talk between adjacent circuit elements can be prevented.
  • the source side e.g. doped region 220
  • a predetermined distance D2 between the gate structure G and the doped region 234 at the right side of the trench 232 can be less than the predetermined distance D1 as shown in FIG. 1 . Therefore, when compared with the N type LDMOS device as shown in FIG. 1 , the N type LDMOS device shown in FIG. 6 may have the advantages of reduced size and fabrication cost, and formation of the conductive layers 244 and 246 also helps to reduce the on-state resistance (Ron) of the N type LDMOS device.
  • the regions with the first conductivity type of the LDMOS device shown in FIG. 6 can be N type regions, and the regions of the second conductivity type can be P type regions, such that the formed LDMOS device herein can be an P type LDMOS device.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to integrated circuit (IC) devices, and in particular to a lateral double diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the same.
  • 2. Description of the Related Art
  • Recently, due to the rapid development of communication devices such as mobile communication devices and personal communication devices, wireless communication products such as mobile phones and base stations have been developed greatly. In wireless communication products, high-voltage elements of lateral double diffused metal-oxide-semiconductor (LDMOS) devices are often used as radio frequency (900 MHz-2.4 GHz) related elements therein.
  • LDMOS devices not only have a higher operation frequency, but they are also capable of sustaining a higher breakdown voltage, thereby having a high output power so that they can be used as power amplifiers in wireless communication products. In addition, due to the fact that LDMOS devices can be formed by conventional CMOS fabrications, LDMOS devices can be fabricated from a silicon substrate which is relatively cost-effective and employs mature fabrication techniques.
  • In FIG. 1, a schematic cross section showing a conventional N-type lateral double diffused metal-oxide-semiconductor (LDMOS) device applicable in a radio frequency (RF) circuit element is illustrated. As shown in FIG. 1, the N-type LDMOS device mainly comprises a P+ type semiconductor substrate 100, a P− type epitaxial semiconductor layer 102 formed over the P+ type semiconductor substrate 100, and a gate structure G formed over a portion of the P− type epitaxial semiconductor layer 102. A P− type doped region 104 is disposed in the P− type epitaxial semiconductor layer 102 under the gate structure G and a portion of the P− type epitaxial semiconductor layer 102 under the left side of the gate structure G, and a N− type drift region 106 is disposed in a portion of the P− type epitaxial semiconductor layer 102 under the right side of the gate structure G. A P+ type doped region 130 and a N+ type doped region 110 are disposed in a portion of the P type doped region 104, and the P+ doped region 130 partially contacts a portion of the N+ type doped region 110, thereby functioning as a contact region (e.g. P+ type doped region 130) and a source region (e.g. N+ type doped region 110) of the N type LDMOS device, respectively, and another N+ type doped region 108 is disposed in a portion of the P− type epitaxial semiconductor layer 102 at the right side of the N− type drift region 106 to function as a drain region of the N type LDMOS device. In addition, an insulating layer 112 is formed over the gate structure G, covering sidewalls and a top surface of the gate structure G and partially covering the N+ type doped regions 108 and 110 adjacent to the gate structure G. Moreover, the N type LDMOS further comprises a P+ type doped region substantially disposed in a portion of the P− type epitaxial semiconductor layer 102 under the N+ type doped region 110 and the P− type doped region 104 under the N+ type doped region 110. The P+ type doped region 120 physically connects the P− type doped region 104 with the P+ type semiconductor substrate 100.
  • During operation of the N type LDMOS device shown in FIG. 1, due to the formation of the P+ type doped region 120, currents (not shown) from the drain side (e.g. N+ type doped region 108) laterally flow through a channel (not shown) underlying the gate structure G towards a source side (e.g. N+ type doped region 110), and are then guided by the P− type doped region 104 and the P+ type doped region 120, thereby arriving the P+ type semiconductor substrate 100, such that problems such as inductor coupling and cross-talk between adjacent circuit elements can be avoided. However, formation of the P+ type doped region 120 needs to perform ion implantations of high doping concentrations and high doping energies and thermal diffusion processes with a relatively high temperature above about 900° C., and a predetermined distance D1 is kept between the gate structure G and the N+ type doped region 110 at the left side of the gate structure G to ensure good performance of the N type LDMOS device. Therefore, formation of the P+ type doped region 120 and the predetermined distance D1 kept between the gate structure G and the N+ type doped region 110 increase the on-state resistance (Ron) of the N type LDMOS device and a dimension of the N type LDMOS device, which is unfavorable for further reduction of both the fabrication cost and the dimensions of the N type LDMOS device.
    • BRIEF SUMMARY OF THE INVENTION
  • Accordingly, an improved lateral double diffused metal oxide semiconductor (LDMOS) device and method for fabricating the same are provided to reduce size and fabrication cost.
  • An exemplary lateral double diffused metal oxide semiconductor (LDMOS) device comprises: a semiconductor substrate, having opposite first and second surfaces and a first conductivity type; a well region formed in a portion of the semiconductor substrate adjacent to the first surface thereof, having the first conductivity type; a gate structure disposed over a portion of the first surface of the semiconductor substrate; a first doped region disposed in a portion of the well region adjacent to a first side of the gate structure, having the first conductivity type; a second doped region disposed in a portion of the well region adjacent to a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type; a third doped region disposed in a portion of the first doped region, having the second conductivity type; a fourth doped region disposed in a portion of the second doped region, having the second conductivity type; a first trench formed in a portion of the third doped region, the first doped region, the well region, and the semiconductor substrate; a conductive contact formed in the first trench; a second trench formed in a portion of the semiconductor substrate adjacent to the second surface thereof, wherein the second trench exposes a portion of the conductive contact; a first conductive layer formed in second trench, contacting the conductive contact; and a second conductive layer formed over the second surface of the semiconductor substrate and the first conductive layer.
  • An exemplary method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device comprises: performing a semiconductor substrate, having opposite first and second surfaces and a first conductivity type; performing an ion implantation process, forming a well region in a portion of the semiconductor substrate adjacent to the first surface thereof, having the first conductivity type; forming a gate structure over a portion of the well region; forming a first doped region in a portion of the well region adjacent to a first side of the gate structure, having the first conductivity type; forming a second doped region in a portion of the well region at a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type; forming a third doped region in a portion of the first doped region, having the second conductivity type; forming a fourth doped region in a portion of the second doped region, having the second conductivity type; forming a trench in a portion of the third doping region, the first doped region, the well region, and the semiconductor substrate; forming a conductive contact in the first trench; thinning the semiconductor substrate from the second surface thereof; after thinning the semiconductor substrate, forming a second trench in a portion of the semiconductor substrate adjacent to the second surface thereof, exposing a portion of the conductive contact; forming a first conductive layer in the second trench; and forming a second conductive layer over the second surface of the semiconductor substrate and the first conductive layer.
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1 is schematic cross section of a conventional lateral double diffused metal-oxide-semiconductor (LDMOS) device; and
  • FIGS. 2-6 are schematic cross sections showing a method for fabricating a lateral double diffused metal-oxide-semiconductor (LDMOS) device according to an embodiment of the invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
  • FIGS. 2-6 are schematic cross sections showing a method for fabricating a lateral double diffused metal-oxide-semiconductor (LDMOS) device applicable for a radio frequency (RF) circuit element according to an embodiment of the invention.
  • Referring to FIG. 2, a semiconductor substrate 200 such as a silicon substrate is first provided. In one embodiment, the semiconductor substrate 200 has a first conductivity type such as a P type conductivity, and a resistivity of about 5 ohms-cm (Ω-cm)-15 ohms-cm (Ω-cm). The semiconductor substrate 200 has opposing surfaces A and B. Next, a sacrificial layer 202 is formed over the surface A of the semiconductor substrate 202. In one embodiment, the sacrificial layer 202 may comprise materials such as silicon oxide and may be formed by a deposition process (not shown) such as thermal oxidation. Next, an ion implantation process 204 is performed to the semiconductor substrate 200 to implant dopants of the first conductivity type through the sacrificial layer 202 and into a portion of the semicondcutor substrate 200, thereby forming a doped region 206. In one embodiment, the dopants of the first conductive type implanted by the ion implantation process 204 can be, for example, dopants of P-type conductivity.
  • In FIG. 3, a thermal process (not shown) is performed to diffuse the dopants in the doped region 206, thereby forming a well region 208 in the semiconductor substrate 200. Herein, the well region 208 comprises dopants of the first conductivity type, and has a resistivity of about 0.5 ohms-cm (Ω-cm)-1 ohms-cm (Ω-cm). In one embodiment, the resistivity of the well region 208 is lower than the resistivity of the semiconductor substrate 200. Next, the sacrificial layer 202 over the surface A of the semiconductor substrate 200 is removed, and a patterned gate structure G is formed over a portion of the surface A of the semiconductor substrate 200. The gate structure G mainly comprises a gate dielectric layer 210, a gate electrode 212, and a hard mask layer 214 sequentially formed over a portion of the semiconductor substrate 200. The gate dielectric layer 210, the gate electrode 212, and the hard mask layer 214 of the gate structure G can be formed by conventional gate processes and related materials, and are not described here in detail for the purpose of simplicity. Next, a plurality of suitable masks (not shown) and a plurality of ion implant processes (not shown) are then performed to form a doped region 216 in a portion of the semiconductor substrate 200 at the left side of the gate structure G, and a doped region 218 in a portion of the semiconductor substrate 200 at the right side of the gate structure G. In one embodiment, the doped region 216 has a first conductivity type such as P type, and the doped region 218 has a second conductivity type such as N type opposite to the P type, and the ion implant processes (not shown) for forming the doped regions 216 and 218 can be ion implant processes with tilted implantation angles. Next, another suitable implant mask (not shown) and an ion implantation process (not shown) are performed to form a doped region 220 and a doped region 222 in a portion of the doped regions 216 and 218, respectively, on opposite sides of the gate structure G, and the configuration shown in FIG. 3 is formed after performing a thermal diffusion process (not shown). In one embodiment, the doped region 220 formed in a portion of the doped region 216 and the doped region 222 formed in a portion of the doped region 218 respectively has the second conductivity type, such as N type, and the ion implant process (not shown) for forming the doped regions 220 and 222 can be an ion implantation vertical to the surface A of the semiconductor substrate 200. In one embodiment, the doped region 218 may function as a drift region, and the doped regions 220 and 222 may function as source and drain regions, respectively.
  • In FIG. 4, an insulating layer 224 is next formed over the semiconductor substrate 200, and the insulating layer 224 conformably covers the surface A of the semiconductor substrate 200 and a plurality of sidewalls and a top surface of the gate structure G formed thereover. Next, a patterning process (not shown) is performed to form an opening 226 in a portion of the insulating layer 224. As shown in FIG. 4, the opening 226 exposes a portion of the doped region 220 such that other portions of the the semiconductor substrate 200 and surfaces of the gate structure G are still covered by the insulating layer 224. In one embodiment, the insulating layer 224 may comprise insulating materials such as silicon oxide and silicon nitride, and can be formed by a method such as chemical vapor deposition (CVD). Next, an etching process (not shown) is performed, using the insulating layer 224 as an etching mask, thereby forming a trench 228 in the semiconductor substrate 200 exposed by the opening 226. The trench 228 is formed with a depth H which mainly penetrates a portion of the doped region 220, the doped region 216, the well region 208, and the semiconductor substrate 200. A conductive layer 230 and another conductive layer 232 are then sequentially deposited, wherein the conductive layer 230 conformably forms over surfaces of the insulating layer 224 and the bottom surface and the sidewalls of the semiconductor substrate 200 exposed by the trench 228, and the conductive layer 232 is formed over the surfaces of the conductive layer 230, thereby filling the trench 228. Next, the conductive layers 230 and 232 are patterned by using a suitable patterning mask and a patterning process (both not shown). As shown in FIG. 4, the patterned conductive layers 230 and 232 are formed over the insulating layer 224 adjacent to the trench 228, extending over the bottom surface and the sidewalls of the trench 228, thereby covering surfaces of the well region 208, and the doped regions 216, 220 exposed by the trench 228, and the conductive layers 230 and 232 also cover the gate structure G and a portion of the doped region 218 adjacent to the gate structure G. However, the conductive layers 230 and 232 do not cover the doped region 222. The portion of the conductive layers 230 and 232 formed in the trench 228 may function as a conductive contact. In one embodiment, the conductive layer 230 may comprise conductive materials such as Ti—TiN alloy, and the conductive layer 232 may comprise conductive materials such as tungsten.
  • In FIG. 5, a dielectric material such as silicon oxide or spin-on-glass (SOG) is deposited over the conductive layers 230 and 232, such that the dielectric material covers the conductive layer 232, the insulating layer 224, and the gate structure G, thereby forming an inter-layer dielectric (ILD) layer 234 with a substantially planar top surface. Next, a patterning process (not shown) comprising photolithography and etching steps is performed to form a trench 236 in a portion of the ILD layer 234 and the insulating layer 224 over a portion of the doped region 222, and the trench 236 exposes a portion of the doped region 222. Next, a conductive layer 238 and another conductive layer 240 are sequentially deposited, and the conductive layer 238 conformably forms over the surfaces of the ILD layer 234 and the sidewalls exposed by the trench 236, and the conductive layer 240 is formed over the surface of the conductive layer 238, thereby filling the trench 236. The portion of the conductive layers 238 and 240 formed in the trench 236 may function as a conductive contact. In one embodiment, the conductive layer 238 may comprise conductive materials such as Ti—TiN alloy, and the conductive layer 240 may comprise conductive materials such as tungsten.
  • In FIG. 6, a handling substrate (not shown) is used to bond with a surface of the conductive layer 240 and then the structure shown in FIG. 5 is reversed, and a thinning process (not shown) comprising steps such as etching, polishing or combinations thereof are then performed to reduce the thickness of the semiconductor substrate 200 from the surface B thereof. Herein, after the thinning process, the thinned semiconductor substrate 200 is assigned with a reference number 200′, and a thinned surface B′ of the thinned semiconductor substrate 200′ has a distance X to the bottom surface of the conductive layer 230 in the trench 228. In one embodiment, the distance X is about 50-300 μm.
  • Next, a patterning process (not shown) is performed by using a suitable patterned mask layer (not shown), thereby forming a trench 242 in the surface B′ of the thinned semiconductor substrate 200′, and the trench 242 exposes the bottom surface and portions of the sidewalls of the conductive layer 230. Next, a deposition process (not shown) is performed to form a conductive layer 244 in the trench 242. In one embodiment, the conductive layer 244 may comprise conductive materials such as Ti—TiN alloy, tungsten, AlCu alloy, AlSiCu alloy, and may be formed by a deposition process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The formed conductive layer 244 may be processed by a planarization process (not shown), such that a surface of the conductive layer 244 is coplanar with the surface B′ of the thinned semiconductor substrate 200. Next, another deposition process (not shown) is performed to form a blanket conductive layer 246 over the surface of the conductive layer 244 and the surface of the thinned semiconductor substrate 200′. In one embodiment, the conductive layer 246 may comprise conductive materials such as Ti—Ni—Ag alloy, and may be formed by a method such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Therefore, after removal of the handling substrate (not shown), an exemplar LDMOS device is substantially fabricated, as shown in FIG. 6.
  • In one embodiment, the gate structure G and the doped regions 220 and 222 of the LDMOS device shown in FIG. 6 may be properly electrically connected (e.g. through conductive layers 230, 232, 238, and 240), and the regions with the first conductivity type can be P type regions, and the regions of the second conductivity type can be N type regions, such that the formed LDMOS device herein is an N type LDMOS device. At this time, the doped region 220 may function as a source region and the doped region 222 may function as a drain region. In this embodiment, during operation of the LDMOS device shown in FIG. 6, currents from the drain side (e.g. the doped region 222) may laterally flow toward the source side (e.g. doped region 220), and then arrive at the surface B′ of the thinned semiconductor substrate 200′ by the guidance of the doped region 216, the conductive layers 230 and 232, and the conductive layer 244, and are then dissipated by the conductive layer 246, such that undesired problems such as inductor coupling and cross-talk between adjacent circuit elements can be prevented. In this embodiment, due to the formation of the conductive layers 230 and 232 formed in the trench 228 and the conductive layer 244 embedded in the thinned semiconductor layer 200′ contacting the conductive layer 246, such that ion implantation with high dosages and high energies for forming the P+ type doped region 120 as shown in FIG. 1 can be avoided, a predetermined distance D2 between the gate structure G and the doped region 234 at the right side of the trench 232 can be less than the predetermined distance D1 as shown in FIG. 1. Therefore, when compared with the N type LDMOS device as shown in FIG. 1, the N type LDMOS device shown in FIG. 6 may have the advantages of reduced size and fabrication cost, and formation of the conductive layers 244 and 246 also helps to reduce the on-state resistance (Ron) of the N type LDMOS device.
  • In addition, in another embodiment, the regions with the first conductivity type of the LDMOS device shown in FIG. 6 can be N type regions, and the regions of the second conductivity type can be P type regions, such that the formed LDMOS device herein can be an P type LDMOS device.
  • While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (10)

1. A lateral double diffused metal-oxide-semiconductor (LDMOS) device, comprising:
a semiconductor substrate, having opposing first and second surfaces and a first conductivity type;
a well region formed in a portion of the semiconductor substrate adjacent to the first surface thereof, having the first conductivity type;
a gate structure disposed over a portion of the first surface of the semiconductor substrate;
a first doped region disposed in a portion of the well region adjacent to a first side of the gate structure, having the first conductivity type;
a second doped region disposed in a portion of the well region adjacent to a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type;
a third doped region disposed in a portion of the first doped region, having the second conductivity type;
a fourth doped region disposed in a portion of the second doped region, having the second conductivity type;
a first trench formed in a portion of the third doped region, the first doped region, the well region, and the semiconductor substrate;
a conductive contact formed in the first trench;
a second trench formed in a portion of the semiconductor substrate adjacent to the second surface thereof, wherein the second trench does not penetrate the semiconductor substrate and exposes a portion of the conductive contact;
a first conductive layer formed in second trench, contacting the conductive contact; and
a second conductive layer formed over the second surface of the semiconductor substrate and the first conductive layer.
2. The LDMOS device as claimed in claim 1, wherein the first conductivity type is P type and the second conductivity type is N type, or the first conductivity type is N type and the second conductivity type is P type.
3. The LDMOS device as claimed in claim 1, wherein the third doped region is a source region and the fourth doped region is a drain region.
4. The LDMOS device as claimed in claim 1, wherein the well region has a resistivity lower than a resistivity of the semiconductor substrate.
5. The LDMOS device as claimed in claim 1, wherein the conductive contact comprises a third conductive layer, and a fourth conductive layer surrounded by the third conductive layer.
6. A method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device, comprising:
performing a semiconductor substrate, having opposite first and second surfaces and a first conductivity type;
performing an ion implantation process, forming a well region in a portion of the semiconductor substrate adjacent to the first surface thereof, having the first conductivity type;
forming a gate structure over a portion of the well region;
forming a first doped region in a portion of the well region adjacent to a first side of the gate structure, having the first conductivity type;
forming a second doped region in a portion of the well region at a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type;
forming a third doped region in a portion of the first doped region, having the second conductivity type;
forming a fourth doped region in a portion of the second doped region, having the second conductivity type;
forming a first trench in a portion of the third doping region, the first doped region, the well region, and the semiconductor substrate;
forming a conductive contact in the first trench;
thinning the semiconductor substrate from the second surface thereof;
after thinning the semiconductor substrate, forming a second trench in a portion of the semiconductor substrate adjacent to the second surface thereof, exposing a portion of the conductive contact, wherein the second trench does not penetrate the semiconductor substrate;
forming a first conductive layer in the second trench; and
forming a second conductive layer over the second surface of the semiconductor substrate and the first conductive layer.
7. The method as claimed in claim 6, wherein the first conductivity type is P type and the second conductivity type is N type, or the first conductivity type is N type and the second conductivity type is P type.
8. The method as claimed in claim 6, wherein the third doped region is a source region and the fourth doped region is a drain region.
9. The method as claimed in claim 6, wherein the well region has a resistivity lower than a resistivity of the semiconductor substrate.
10. The method as claimed in claim 6, wherein the conductive contact comprises a third conductive layer and a fourth conductive layer surrounded by the third conductive layer.
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