US20150060767A1 - Nanowires and nanowire fielde-effect transistors - Google Patents
Nanowires and nanowire fielde-effect transistors Download PDFInfo
- Publication number
- US20150060767A1 US20150060767A1 US14/536,953 US201414536953A US2015060767A1 US 20150060767 A1 US20150060767 A1 US 20150060767A1 US 201414536953 A US201414536953 A US 201414536953A US 2015060767 A1 US2015060767 A1 US 2015060767A1
- Authority
- US
- United States
- Prior art keywords
- nanowire
- crystal face
- section
- polygon
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000002070 nanowire Substances 0.000 title claims abstract description 247
- 239000004065 semiconductor Substances 0.000 claims abstract description 103
- 238000000137 annealing Methods 0.000 claims abstract description 17
- 239000013078 crystal Substances 0.000 claims description 100
- 230000005669 field effect Effects 0.000 claims description 46
- 239000000758 substrate Substances 0.000 claims description 46
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- -1 hafnium nitride Chemical class 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 2
- WOIHABYNKOEWFG-UHFFFAOYSA-N [Sr].[Ba] Chemical compound [Sr].[Ba] WOIHABYNKOEWFG-UHFFFAOYSA-N 0.000 claims description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 2
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 claims description 2
- SKKMWRVAJNPLFY-UHFFFAOYSA-N azanylidynevanadium Chemical compound [V]#N SKKMWRVAJNPLFY-UHFFFAOYSA-N 0.000 claims description 2
- 229910002113 barium titanate Inorganic materials 0.000 claims description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052746 lanthanum Inorganic materials 0.000 claims description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 claims description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052720 vanadium Inorganic materials 0.000 claims description 2
- 229910052727 yttrium Inorganic materials 0.000 claims description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- UZQSJWBBQOJUOT-UHFFFAOYSA-N alumane;lanthanum Chemical compound [AlH3].[La] UZQSJWBBQOJUOT-UHFFFAOYSA-N 0.000 claims 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 120
- 239000000463 material Substances 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 238000005530 etching Methods 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000007704 wet chemistry method Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052805 deuterium Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
- Y10S977/763—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less formed along or from crystallographic terraces or ridges
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/84—Manufacture, treatment, or detection of nanostructure
- Y10S977/89—Deposition of materials, e.g. coating, cvd, or ald
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region
Abstract
A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
Description
- This application claims the priority of Chinese patent application No. 201210513894.5, filed on Dec. 4, 2012, the entirety of which is incorporated herein by reference.
- The present invention generally relates to the field of semiconductor manufacturing technology and, more particularly, relates to techniques for fabricating nanowires and nanowire field-effect transistors.
- In order to follow the Moore's law, the feature sizes of semiconductor devices (for example, field-effect transistors) have been continuously shrinking. The switching characteristic of the transistors may become worse because of the short-channel effects and leakage current problem of a channel under the shrunk feature size. Therefore, improving the performance of the conventional field-effect transistors by shrinking their physical sizes has encountered some difficulties.
- Nanowire field-effect transistors (NWFETs) have been developed by existing technologies.
FIG. 1 illustrates an existing NWFET. The NWFET includes asilicon substrate 10, and an oxide buriedlayer 11 on thesilicon substrate 10. The NWFET also includes a plurality of convex structures on the oxide buriedlayer 11. Further, the NWFET includes afirst pad region 12 and asecond pad region 13 on the convex structures. Further, the NWFET also includes a plurality ofnanowires 14 suspending between thefirst pad region 12 and thesecond pad region 13. Thefirst pad region 12 and thesecond pad region 13 are used for subsequently forming a source region and a drain region. Thenanowires 14 are used as channel regions. A surrounding gate structure (not shown) may be formed to cover thenanowires 14. - The
nanowires 14 are used as channel regions in the NWFET, carriers in the nanowire channels may be away from surfaces of thenanowires 14 because of the quantum confinement effect, thus carrier transportations in the nanowire channels may be less affected by a surface scattering and a lateral electric field. Therefore, a relatively high carrier mobility may be obtained. Further, because the NWFET may have a relatively small channel, and a surrounding gate structure may be used as a gate structure, the modulating ability of the gate structure may be enhanced, and the threshold characteristics may be improved. Therefore, the short-channel effects may be effectively restrained, and the size of a field-effect transistor may be further shrunk. Further, because the surrounding gate structure of a NWFET may enhance the modulating ability of the gate structure of the NWFET, the requirement for thinning the gate dielectric layer may be alleviated. - However, how to optimize the performance of a NWFET is still one of urgent tasks for those skilled in the art. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
- One aspect of the present disclosure includes a method for fabricating a nanowire based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
- Another aspect of the present disclosure includes a nanowire field-effect transistor. The nanowire field-effect transistor includes a semiconductor substrate having a first substrate and a buried layer. The nanowire field-effect transistor also includes a nanowire having a circular cross-section. Further, the nanowire field-effect transistor includes a source region and a drain region. Further, the nanowire field-effect transistor also includes a surrounding gate structure having a gate dielectric layer and a metal gate layer.
- Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
-
FIG. 1 illustrates an existing nanowire field-effect transistor; -
FIG. 2 illustrates semiconductor structures corresponding to certain stages of an exemplary fabrication process for a nanowire consistent with certain disclosed embodiments; -
FIG. 3 illustrates semiconductor structures corresponding to certain stages of an exemplary fabrication process for a nanowire consistent with certain disclosed embodiments; -
FIG. 4 illustrates semiconductor structures corresponding to certain stages of an exemplary fabrication process for a nanowire consistent with certain disclosed embodiments; -
FIGS. 5-11 illustrate semiconductor structures corresponding to certain stages of an exemplary fabrication process for a nanowire field-effect transistor consistent with the disclosed embodiments. -
FIG. 12 illustrates a semiconductor structure corresponding a cross-section view of the semiconductor structure shown inFIG. 11 along the OO′ direction, -
FIG. 13 illustrates an exemplary fabrication process for a nanowire consistent with the disclosed embodiments; and -
FIG. 14 illustrates an exemplary fabrication process for a nanowire field-effect transistor consistent with the disclosed embodiment. - Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
- According to extensive investigations, a leakage current may be lowered in a nanowire field-effect transistor if a surface of the nanowire is smoothed. An anneal process may be used to smooth the surface of the nanowire, which may refer as a rounding process. Time of the annealing process may be reduced if the nanowire has a polygon cross-section. Therefore, the performance of the nanowire field-effect transistor may be enhanced, and the fabrication process may be simplified simultaneously if a nanowire with the polygon cross-section is formed before the annealing process.
-
FIG. 13 illustrates an exemplary fabrication process for a nanowire, andFIGS. 2-4 illustrate semiconductor structures corresponding certain stages of the exemplary fabrication process for a nanowire consistent with certain disclosed embodiments. - As shown in
FIG. 13 , at the beginning of the fabrication process, afirst nanowire 100 may be formed to provide a substrate for subsequently forming a semiconductor layer (S101). The left image inFIG. 2 illustrates a corresponding semiconductor structure. Thefirst nanowire 100 may have different cross-sections, such as a square cross-section, a rectangular cross-section, a triangle cross-section, or a hexagonal cross-section, etc. In one embodiment, thefirst nanowire 100 has a square cross-section. Thefirst nanowire 100 may have a (−100) crystal face AD, a (100) crystal face BC, a (0-10) crystal face AB, and a (010) face CD, which may provide surfaces for subsequently epitaxially growing a semiconductor layer, and prevent crystal defects being formed. - The
first nanowire 100 may be made of any appropriate semiconductor material, such as silicon, germanium, silicon germanium, carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, or any other III-V, II-VI compound semiconductors. Thefirst nanowire 100 may also be made of other appropriate material, such as piezoelectric material or metal material, etc. - Various processes may be used to form the
first nanowire 100, such as a microfabrication process, a nanofabrication process, a chemical vapor deposition process, or wet chemical process, etc. In one embodiment, thefirst nanowire 100 is formed by a microfabrication process. The microfabrication process for forming thefirst nanowire 100 may include sequentially: forming a first semiconductor layer, patterning the first semiconductor layer using a photo lithography process, and etching the first semiconductor layer to form thefirst nanowire 100 with a square cross-section. - Returning to
FIG. 13 , after forming thefirst nanowire 100, a semiconductor layer may be formed on the surfaces of the first nanowire 100 (S102). The middle image inFIG. 2 illustrates a corresponding semiconductor structure. - As shown in the middle image in
FIG. 2 , asemiconductor layer 101 is formed on the surfaces of thefirst nanowire 100. Thesemiconductor layer 101 may cover all the four surfaces of thefirst nanowire 100, which includes the (−100) crystal face AD, the (100) crystal face BC, the (0-10) crystal face AB, and the (010) crystal face CD. A contour of thesemiconductor layer 101 may be an octagon, thus a cross-section of a finally obtainedsecond nanowire 102 consisting of thefirst nanowire 100 and thesemiconductor layer 101 may be in an octagon shape too. - In one embodiment, the
semiconductor layer 102 may be made of a same material as thefirst nanowire 100, such as silicon, germanium, silicon germanium, carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, piezoelectric material, metal material or any other III-V, II-VI compound semiconductors, etc. If thesemiconductor layer 102 and thefirst nanowire 100 are made of a same material, crystal lattices may be well matched, thus crystal defects may be prevented. Further, types of materials may be reduced, the production cost may be lowered. In certain other embodiments, thesemiconductor layer 102 may also be made of a material different from thefirst nanowire 100. - The
semiconductor layer 102 may be formed by various processes, such as a chemical vapor deposition process, an atomic layer deposition process, a selective epitaxial growth process, or a wet chemical process, etc. In one embodiment, thesemiconductor layer 102 is formed by a selective epitaxial growth process. Specifically, a semiconductor material may be deposited on the (−100) crystal face AD, and a new (−100) crystal face ‘ah’ may be formed; the semiconductor material may be deposited on the (100) crystal face BC, and a new (100) crystal face de may be formed; the semiconductor material may be deposited on the (0-10) crystal face AB, and a new (0-10) crystal face ‘bc’ may be formed; and the semiconductor material may be deposited on the (010) crystal face CD, and a new (010) crystal face ‘gf’ may be formed. The semiconductor material may be deposited on the four crystal faces including AB, BC, CD, and AD simultaneously. - In addition, a (−1-10) crystal face ‘ab’ may be formed between the (−100) crystal face ah and the (0-10) crystal face ‘bc’; a (1-10) crystal face ‘cd’ may be formed between the (0-10) crystal face ‘bc’ and the (100) crystal face ‘de’; a (110) crystal face ‘ef’ may be formed between the (100) crystal face ‘de’ and the (010) crystal face ‘fg’; and a (−110) crystal face ‘gh’ may be formed between the (010) crystal face ‘fg’ and the (−100) crystal face ‘ah’. The crystal faces ‘ab’, ‘cd’, ‘gh’, and ‘ef’ may be formed simultaneously with depositing the semiconductor material.
- A growth rate of the semiconductor material at different crystal faces may be controlled to cause the growth rate at the (100) crystal face, the (−100) crystal face, the (010) crystal face and the (0-10) crystal face to be greater than the growth rate at the (110) crystal face, the (−110) crystal face, the (−1-10) crystal face and the (1-10) crystal face. Therefore, the
second nanowire 102 with the octagonal cross-section shown in the middle image inFIG. 2 may be formed. - Returning to
FIG. 13 , after forming thesecond nanowire 102, a thermal annealing process may be performed to form a third nanowire (S103). The right picture inFIG. 2 illustrates a corresponding semiconductor structure. - As shown in the right picture in
FIG. 2 , athird nanowire 103 is formed after a thermal annealing process. Thethird nanowire 103 may be formed by smoothing the surface of thesecond nanowire 102 using the thermal annealing process. The thermal annealing process for forming thethird nanowire 103 may refer to a rounding process. After the rounding process, thenanowire 103 may have a near circular surface. - The
second nanowire 102 having the octagonal section may be annealed in a helium, hydrogen, or deuterium environment at a temperature greater than approximately 900° C., i.e., the rounding process, the surface of thesecond nanowire 102 may be smoothed, and the cylindricalthird nanowire 103 with the circular cross-section may be formed. Other appropriate gas may also be used in the annealing process. If the cylindricalthird nanowire 103 is used as a channel of a transistor, a leakage current may be reduced, and a carrier mobility may be increased. - Compared to the
first nanowire 100 with the square cross-section, the octagonal cross-section of thesecond nanowire 102 may be more similar with a circular shape, thus the annealing may be relatively short. Therefore, a fabrication process for a nanowire may be simplified. - Optionally and additionally, at least one oxidization process and one etching process may be performed to cause the cross-section of the
third nanowire 103 more close to a theoretical circle, i.e., having an uniform radius. Referring to the middle picture inFIG. 2 , during the oxidization process a contact angle between oxygen and vertex angles of the octagon may be greater than a contact angle between oxygen and sides of the octagon, an area exposed in oxygen at the vertex angles may be relatively large, thus an oxidized thickness of the vertex angles may be relatively large too. During the etching process, the oxidized portion of thethird nanowire 103 may be removed. Therefore, the oxidized portion at the vertex angles may be removed more than the oxidized portion at the sides, the vertex angles of the octagon may be gradually rounded, and the cross-section of thethird nanowire 103 may be more close to a circle. - Various processes may be used to oxidize the
third nanowire 103, such as a thermal oxidation process, a chemical oxidation process, or a plasma oxidation process, etc. In one embodiment, thefirst nanowire 100 and thesemiconductor material 101 may be made of silicon, thus thesecond nanowire 102 and thethird nanowire 103 may be made of silicon. A thermal oxidation process may be used to oxidize a surface portion of thethird nanowire 103. - After oxidizing the
third nanowire 103, a diluted hydrogen fluoride solution may be used to removed silicon oxide layer on the surface of thethird nanowire 103, thus the cross-section of thethird nanowire 103 may be more close to a circle. Other appropriate process may also be used to remove the oxide layer, such as a plasma etching process, or other wet chemical etching process. -
FIG. 3 illustrates another process for forming a nanowire. The process for forming a nanowire shown inFIG. 3 is similar to the process shown inFIG. 2 . - Certain differences includes, referring to the left image in
FIG. 2 , afirst nanowire 120 with a rectangular cross-section, i.e., lengths of a side AB and a side CD may be greater than lengths of a side AD and a side BC. The side AB may correspond to a (−100) crystal face; the side CD may correspond to a (100) crystal face; the side AD may correspond to a (0-10) crystal face; and the side BC may correspond to a (010) crystal face. - After forming a
semiconductor material 121 covering thefirst nanowire 120, referring to the middle image inFIG. 3 , asecond nanowire 122 may be formed. A cross-section of thesecond nanowire 122 is a vertically extended octagon because the lengths of the side AB and the side CD may be greater than the lengths of the side AD and the side BC. A process for forming thesemiconductor material 121 may be similar to S102 shown inFIG. 13 described above. - Further, referring to the right image in
FIG. 3 , after forming thesecond nanowire 122 with the rectangular cross-section, athird nanowire 123 may be formed by an annealing process. A cross-section of thethird nanowire 123 may be elliptical because the cross section of thesecond nanowire 122 is rectangular. Thethird nanowire 123 having the elliptical cross-section may have a smooth surface. When thethird nanowire 123 is used as a channel of a transistor, a leakage current may be reduced, and a carrier mobility may be increased. A process for forming thethird nanowire 123 may be similar to S103 inFIG. 13 described above. -
FIG. 4 illustrates another process for forming a nanowire. The process for forming a nanowire shown inFIG. 4 is similar to the process shown inFIG. 2 . - Certain differences may include, after forming the
first nanowire 130, asemiconductor layer 131 may be only formed on the surface AB, the surface BC, and the surface CD of thefirst nanowire 130. The surface AD is not covered by thesemiconductor layer 131. A cross-section of thefirst nanowire 130 may be square or rectangular. A process for forming thesemiconductor material 131 may be similar to S102 shown inFIG. 13 described above. A semiconductor material may selectively grow on a portion of the surface of thefirst nanowire 130, i.e., the surface AB, the surface BC, and the surface CD. The surface AD may be covered by a substrate if thefirst nanowire 130 lays on the substrate. The surface may be also be covered by appropriate sacrificial material which may be removed after forming thesemiconductor layer 131. - Further, referring to the right image in
FIG. 4 , athird nanowire 133 may be formed by smoothing the surface of thesecond nanowire 132 having thefirst nanowire 130 and thesemiconductor layer 131 using a thermal annealing process. Thethird nanowire 133 may have a “Ω” shape cross-section. Thethird nanowire 133 having the a “Ω” shape cross-section may have a smooth surface. When thethird nanowire 133 is used as a channel of a transistor, a leakage current may be reduced, and a carrier mobility may be increased. A process for forming thethird nanowire 133 may be similar to S103 inFIG. 13 described above - In certain other embodiments, the
semiconductor layer 131 may cover only one or two of the faces of thefirst nanowire 130, thethird nanowire 133 with different cross-sections and a smooth surface may be formed after the thermal anneal process. When thethird nanowire 133 is used as a channel of a transistor, a leakage current may be reduced, and a carrier mobility may be increased. - In certain other embodiments, a cross-section of a second nanowire having a first nanowire and a semiconductor layer may be any type of polygonal, such as pentagonal, hexagonal, decagonal, or hex decagonal, etc. The second nanowire with a polygonal cross-section of may be formed by controlling the grate rate of the semiconductor layer at different crystal faces.
-
FIG. 14 illustrates an exemplary fabrication process for a nanowire field-effect transistor consistent with the disclosed embodiments,FIGS. 5-11 illustrate semiconductor structures corresponding to certain stages of an exemplary fabrication process for a nanowire field-effect transistor consistent with the disclosed embodiments, andFIG. 12 illustrates a semiconductor structure corresponding to a cross-section view of the semiconductor structure shown inFIG. 11 along the OO′ direction. - As shown in
FIG. 14 , at the beginning of the fabrication process, a semiconductor substrate with certain structures is provided (S201).FIG. 5 illustrates a corresponding semiconductor device. - As shown in
FIG. 5 , a semiconductor substrate is provided. The semiconductor substrate may have afirst substrate 200, a buriedlayer 201, and asecond substrate 202. Thefirst substrate 200, the buriedlayer 201 and thesecond substrate 202 may be made of a same material or different materials. Thefirst substrate 200, the buriedlayer 201 and thesecond substrate 202 may include any appropriate material, such as single crystal silicon, germanium, poly silicon, amorphous silicon, silicon germanium, carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, alloy semiconductor, or epitaxially grown materials. Thefirst substrate 200, the buriedlayer 201 and thesecond substrate 202 may also include any other appropriate material. - In one embodiment, the
first substrate 200 is silicon, the buriedlayer 201 is an oxide layer, and thesecond substrate 202 is silicon having a (100) crystal face. In another embodiment, thefirst substrate 200 is silicon, the buriedlayer 201 is silicon germanium, and thesecond substrate 202 is silicon with a (100) crystal face. The buriedlayer 201 made of silicon germanium and thesecond substrate 202 made of silicon may have different selective etching ratios, which may help to subsequently form a first nanowire. - Returning to
FIG. 14 , after providing the semiconductor substrate, the second substrate 202 (may refer to the second silicon substrate if thesecond substrate 202 is made of silicon) may be patterned to form a source region, a drain region, and a first nanowire (S202).FIG. 6 illustrates a corresponding semiconductor structure. - As shown in
FIG. 6 , an “H”shape structure 203 is formed by patterning thesecond substrate 202. Two parallel stripe regions of the “H”shape structure 203 may be asource region 2031 and adrain region 2032. A structure with a square cross-section between thesource region 2031 and thedrain region 2032 may be afirst nanowire 2033. Thefirst nanowire 2033 may have two surfaces (e.g., top and bottom surfaces) which may correspond to a (100) crystal face (top surface) and a (−100) crystal face (bottom surface), respectively. Thefirst nanowire 2033 may also have two side surfaces which may correspond to a (010) crystal face and a (0-10) crystal face, respectively. - Various processes may be used to form the
first nanowire 2033, such as a dry etching process including a plasma etching process and an ion be etching process, etc, or a wet etching process, etc. In one embodiment, thefirst nanowire 2033 is formed by patterning thesecond silicon substrate 202 using a dry etching process. - In certain other embodiments, the
first nanowire 2033 may be formed by an epitaxial growth process. Catalysts may be deposited on thesecond substrate 202, and afirst nanowire 2033 may be grown in a lateral direction on the surface of thesecond substrate 202. - In certain other embodiments, the “H”
shape structure 203 may also be a shape shown inFIG. 7 . As shown inFIG. 7 , there may be twoextended trapezoids 210 besides theparallel source region 2031 and drainregion 2032. The “H”shape structure 203 may also have other appropriate transfigurations. - Further, after forming the “H”
shape structure 203, a portion of the buriedlayer 201 underneath thefirst nanowire 2033 may be removed. The corresponding semiconductor structure is illustrated inFIG. 8 . - As shown in
FIG. 8 , a through-hole 205 may be formed after removing the portion of the buriedlayer 201 underneath thefirst nanowire 2033. Thefirst nanowire 2033 may be suspended after forming the through-hole 205, a semiconductor layer covering thefirst nanowire 2033 may be convenient to be formed subsequently. Further, a surrounding gate structure may also be convenient to be formed subsequently. That is, a space (may refer to the through hole 205) may be reserved for subsequently forming the semiconductor layer and the surrounding gate structure on the bottom of thefirst nanowire 2033. - In certain other embodiments, the portion of the
second substrate 201 underneath thefirst nanowire 2033 may be kept. Thus, a subsequently formed second nanowire may have a “Ω” shape cross section, and a subsequently formed surrounding gate structure may be unable to cover the bottom surface of thefirst nanowire 2033. - Returning to
FIG. 14 , after forming thefirst nanowire 2033, a semiconductor layer may be formed on thefirst nanowire 2033 to form a second nanowire (S203).FIG. 9 illustrates a corresponding semiconductor structure. - As shown in
FIG. 9 , asecond nanowire 2034 with an octagonal cross-section is formed. Thesecond nanowire 2034 may consist of thefirst nanowire 2033 and the semiconductor layer. - The semiconductor layer may be formed by any appropriate process, such as a chemical vapor deposition process, an atomic layer deposition process, a selective epitaxial growth process, or a wet chemical process, etc. In one embodiment, the semiconductor layer is formed by a selective epitaxial growth process.
- Specifically, the semiconductor material may be deposited on the surfaces of the (100) crystal face, the (−100) crystal face, the (010) crystal face, and the (0-10) crystal face. Therefore, a new (100) crystal face, a new (−100) crystal face, a new (010) crystal face, and a new (0-10) crystal face may be formed. A (110) crystal face, a (1-10) crystal face, a (−110) crystal face, and a (−1-10) crystal face may also be formed simultaneously. Therefore, the cross-section of the
second nanowire 2034 may be octagonal. A process for forming thesecond nanowire 2034 is similar to S102, the detailed descriptions are omitted herein. - Returning to
FIG. 14 , after forming thesecond nanowire 2034, a third nanowire with a smooth surface may be formed (S204).FIG. 10 illustrates a corresponding semiconductor structure. - As shown in
FIG. 10 a cylindricalthird nanowire 2035 is formed. Thethird nanowire 2035 may be formed by annealing thesecond nanowire 2034. A thermal annealing process may smooth the surface of thesecond nanowire 2034, and form a near circular surface, thus thethird nanowire 2035 with a circular cross-section may be formed. In certain other embodiment, the cross-section of thethird nanowire 2035 may be an elliptical shape or a “Ω” shape if thefirst nanowire 2033 has other appropriate type of cross-sections, as described previously. - Additionally and optionally, at least one thermal oxidation process and one etching process may be performed after the thermal annealling process. After the thermal oxidation process and the etching process, the
third nanowire 2035 may have a near theoretically circular cross-section. The thermal annealing process may use pure oxygen or diluted oxygen as a reaction gas, and heat the substrate with thethird nanowire 2035 at a certain temperature. The etching process may be a dry etching process including a plasma etching process or an ion beam etching process, or a wet etching process. In one embodiment, the etching process is a wet etching process. - Returning to
FIG. 14 , after forming thethird nanowire 2035, a gate structure may be formed on the third nanowire 2035 (S205).FIG. 11 illustrates a corresponding semiconductor structure. - As shown in
FIG. 11 , agate structure 204 is formed on thethird nanowire 2035. Thegate structure 204 may include any appropriate form. In one embodiment, thegate structure 204 may be a surrounding gate, i.e., thegate structure 204 may cover an entire surface of thethird nanowire 2035.FIG. 12 illustrates a cross-section view of the surroundinggate structure 204 along OO′ direction shown inFIG. 11 . - As shown in
FIG. 12 , the surroundinggate structure 204 may have agate dielectric layer 2041 covering the entire surface of thethird nanowire 2035 and agate layer 2042 covering an entire surface of thedielectric layer 2041. Thegate layer 2042 may also cover a portion of one surface of the buriedlayer 201. In certain other embodiments, if the portion of the buriedlayer 201 underneaththird nanowire 2035 is kept, e.g., the cross-section of thethird nanowire 2035 is a “Ω” shape, the surroundinggate structure 204 may be unable to cover a bottom surface of thethird nanowire 2035. - The
gate dielectric layer 2041 may be a high-K dielectric layer including one or more of hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, titanium oxide, strontium titanate, barium titanate, lanthanum aluminum oxide, yttrium oxide, hafnium oxynitride, zirconium oxynitride, lanthanum oxynitride, aluminum oxynitride, titanium oxynitride, barium strontium oxynitride, lanthanum aluminum oxy nitride and yttrium oxynitride. Various methods may be used to form thegate dielectric layer 2041, such as a chemical vapor deposition process, a physical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a metal organic deposition process, or a wet chemical process, etc. - The
gate layer 2042 may be made of one or more of aluminum, copper, gold, tungsten, tantalum, vanadium, titanium nitride, zirconium nitride, hafnium nitride, vanadium nitride, niobium nitride, tantalum nitride, tungsten nitride, aluminum titanium nitride, tantalum carbide, tantalum magnesium nitride, and tantalum carbo-nitride. Various processes may be used to form thegate layer 2042, such as a chemical vapor deposition process, a physical vapor deposition process, a flowable chemical vapor deposition process, an atomic layer deposition process, a metal organic deposition process, or an electroplating process, etc. - After forming the
gate structure 204, a planarization process may be performed on thegate structure 204 to remove an excess portion of gate structure materials. Top surfaces of thesource region 2031 and thedrain region 2032 may level with a top planarized surface of thegate structure 204 after the planarization process. The planarization process may include a mechanical polishing process, or a chemical mechanical polishing process. - Further, after forming the
gate structure 204, a source and a drain may be formed by doping thesource region 2031 and thedrain region 2032. Various processes may be used to dope thesource region 2031 and thedrain region 2032, such as an ion implantation process, or a thermal diffusion process. - When the cylindrical
third nanowire 2035 with the circular cross-section is used as a channel of a nanowire field-effect transistor, a leakage current may be reduced; and the carrier mobility may be improved. In certain other embodiment, when thethird nanowire 2035 with an elliptical cross section or a “Ω” shape cross-section is used as a channel of a nanowire field-effect transistor, a leakage current may also be reduced, and the carrier mobility may also be improved. Further, an anneal time for forming the nanowire field-effect transistor may be relatively short, thus a fabrication process may be simplified. - Thus, a nanowire field-effect transistor may be formed by the above disclosed processes and methods, and the corresponding nanowire field-effect transistor is illustrated in
FIG. 11 . The nanowire field-effect transistor includes a semiconductor substrate having afirst substrate 200 and a buriedlayer 201. The nanowire field-effect transistor also includes ananowire 2035 having a circular cross-section. Further, the nanowire field-effect transistor includes asource region 2031 and adrain region 2032. Further, the nanowire field-effect transistor also includes a surroundinggate structure 204 having agate dielectric layer 2041 and agate layer 2042. The detailed structures and intermediate structures are described above with respect to the fabrication methods. - The above detailed descriptions only illustrate certain exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention. Those skilled in the art can understand the specification as whole and technical features in the various embodiments can be combined into other embodiments understandable to those persons of ordinary skill in the art. Any equivalent or modification thereof, without departing from the spirit and principle of the present invention, falls within the true scope of the present invention. application:
Claims (22)
1-12. (canceled)
13. A nanowire field-effect transistor, comprising:
a first semiconductor substrate;
a buried layer on the first semiconductor substrate;
a nanowire suspended over the buried layer by a through-hole separating the nanowire from a top surface of the buried layer, wherein the nanowire comprises:
a first nanowire deposited on the buried layer, the first nanowire comprising a first polygon-shaped cross-section having a first number of sides, and
a semiconductor layer deposited on all exposed surface of the first nanowire, wherein the semiconductor layer has a second polygon-shaped cross-section containing the first polygon-shaped cross-section of the first nanowire, the second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number of sides,
wherein the nanowire is an annealed nanowire from annealing of the semiconductor layer and the first nanowire, to remove a substantial number of vertexes of the second polygon-shaped cross-section of the semiconductor layer, wherein the nanowire has a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section;
a gate structure covering the nanowire; and
a source and a drain connecting with the nanowire and both disposed on the buried layer.
14. The nanowire field-effect transistor according to claim 13 , wherein:
the nanowire has a circular cross-section, or an elliptical cross-section, or a “Ω” shape cross-section.
15. The nanowire field-effect transistor according to claim 13 , wherein:
the first semiconductor substrate is silicon,
the nanowire is silicon, and
the buried layer is silicon oxide.
16. (canceled)
17. The nanowire field-effect transistor according to claim 14 , wherein:
the gate structure comprises a surrounding gate structure surrounding the nanowire with a circular cross-section or an elliptical cross-section, and
the gate structure comprises a gate dielectric layer surrounding the nanowire, and a gate layer covering the gate dielectric layer.
18. The nanowire field effect transistor according to claim 14 , wherein:
a “Ω” shape gate structure surrounds the nanowire with a “Ω” shape cross-section.
19. The nanowire field-effect transistor according to claim 17 , wherein:
the gate layer is made of one or more of tungsten, aluminum, copper, gold, tantalum, vanadium, titanium nitride, zirconium nitride, hafnium nitride, vanadium nitride, niobium nitride, tantalum nitride, tungsten nitride, aluminum titanium nitride, tantalum carbide, tantalum magnesium nitride, and tantalum carbo-nitride.
20. The nanowire field-effect transistor according to claim 17 , wherein:
the gate dielectric layer is a high-K dielectric layer made of one or more of hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, titanium oxide, strontium titanate, barium titanate, lanthanum aluminum oxide, yttrium oxide, hafnium oxynitride, zirconium oxynitride, lanthanum oxynitride, aluminum oxynitride, titanium oxynitride, barium strontium oxynitride, lanthanum aluminum oxynitride and yttrium oxynitride.
21. The nanowire field-effect transistor according to claim 13 , wherein:
the first polygon of the first nanowire is a square or a rectangular; the first number is four; and the first nanowire has a (100) crystal face, a (−100) crystal face, a (010) crystal face, and a (0-10) crystal face.
22. The nanowire field-effect transistor according to claim 13 , wherein:
the second polygon of the semiconductor layer on the first nanowire has a side number greater than five, and the semiconductor layer at least has a (100) crystal face, a (−100) crystal face, a (010) crystal face, a (0-10) crystal face, a (1-10) crystal face, and a (110) crystal face.
23. The nanowire field-effect transistor according to claim 13 , wherein:
the second polygon is octagonal and the semiconductor layer on the first nanowire has a (100) crystal face, a (−100) crystal face, a (010) crystal face, a (0-10) crystal face, a (1-10) crystal face, a (110) crystal face, a (−110) crystal face, and a (−1-10) crystal face.
24. The nanowire field-effect transistor according to claim 13 , wherein:
the source and drain are disposed in parallel on the buried layer, and the first nanowire is connected to each of the source and drain by an extended trapezoid.
25. The nanowire field-effect transistor according to claim 13 , wherein:
the nanowire, the source, and the drain are formed from a second semiconductor substrate, and
each of the first semiconductor substrate, the nanowire, the source region, and the drain region comprises one or more of Si, SiGe, SiC, Ge, and III-V semiconductors.
26. A nanowire field-effect transistor, comprising:
a first semiconductor substrate;
a buried layer on the first semiconductor substrate;
a second semiconductor substrate on the buried layer, the second semiconductor substrate comprising a nanowire, a source, and a drain, the nanowire having one end connecting to the source and the other end connecting to the drain on the buried layer,
wherein the nanowire comprises:
a first nanowire deposited over the buried layer, the first nanowire comprising a first polygon-shaped cross-section having a first number of sides, and
a semiconductor layer deposited on all exposed surface of the first nanowire, wherein the semiconductor layer has a second polygon-shaped cross-section containing the first polygon-shaped cross-section of the first nanowire, the second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number of sides,
wherein the nanowire is an annealed nanowire from annealing of the semiconductor layer and the first nanowire, to remove a substantial number of vertexes of the second polygon-shaped cross-section of the semiconductor layer, wherein the nanowire has a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section; and
a gate structure covering the nanowire.
27. The nanowire field-effect transistor according to claim 26 , wherein:
the first nanowire is disposed on the buried layer and contacting the buried layer.
28. The nanowire field-effect transistor according to claim 26 , wherein:
the nanowire has a circular cross-section, or an elliptical cross-section, or a “Ω” shape cross-section.
29. The nanowire field effect transistor according to claim 26 , wherein:
the gate structure surrounds the nanowire and comprises a “Ω” shape gate structure surrounding on the nanowire with a “Ω” shape cross-section.
30. The nanowire field-effect transistor according to claim 26 , wherein:
the source and the drain are disposed in parallel on the buried layer, and the first nanowire is connected to each of the source and the drain by an extended trapezoid.
31. The nanowire field-effect transistor according to claim 26 , wherein:
each of the first semiconductor substrate and the second semiconductor substrate comprises one or more of Si, SiGe, SiC, Ge, and III-V semiconductors.
32. The nanowire field-effect transistor according to claim 26 , wherein:
the first polygon of the first nanowire is a square or a rectangular; the first number is four; and the first nanowire has a (100) crystal face, a (−100) crystal face, a (010) crystal face, and a (0-10) crystal face, and
the second polygon of the semiconductor layer on the first nanowire has a side number greater than five, and the semiconductor layer at least has a (100) crystal face, a (−100) crystal face, a (010) crystal face, a (0-10) crystal face, a (1-10) crystal face, and a (110) crystal face.
33. The nanowire field-effect transistor according to claim 26 , wherein:
the second polygon is octagonal and the semiconductor layer on the first nanowire has a (100) crystal face, a (−100) crystal face, a (010) crystal face, a (0-10) crystal face, a (1-10) crystal face, a (110) crystal face, a (−110) crystal face, and a (−1-10) crystal face.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/536,953 US20150060767A1 (en) | 2012-12-04 | 2014-11-10 | Nanowires and nanowire fielde-effect transistors |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210513894.5A CN103854971B (en) | 2012-12-04 | 2012-12-04 | The manufacture method of nano wire, the manufacture method of nano-wire field effect transistor |
CN2012-10513894.5 | 2012-12-04 | ||
US13/832,648 US8912545B2 (en) | 2012-12-04 | 2013-03-15 | Nanowires, nanowire fielde-effect transistors and fabrication method |
US14/536,953 US20150060767A1 (en) | 2012-12-04 | 2014-11-10 | Nanowires and nanowire fielde-effect transistors |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/832,648 Division US8912545B2 (en) | 2012-12-04 | 2013-03-15 | Nanowires, nanowire fielde-effect transistors and fabrication method |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150060767A1 true US20150060767A1 (en) | 2015-03-05 |
Family
ID=50824586
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/832,648 Active US8912545B2 (en) | 2012-12-04 | 2013-03-15 | Nanowires, nanowire fielde-effect transistors and fabrication method |
US14/536,953 Abandoned US20150060767A1 (en) | 2012-12-04 | 2014-11-10 | Nanowires and nanowire fielde-effect transistors |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/832,648 Active US8912545B2 (en) | 2012-12-04 | 2013-03-15 | Nanowires, nanowire fielde-effect transistors and fabrication method |
Country Status (2)
Country | Link |
---|---|
US (2) | US8912545B2 (en) |
CN (1) | CN103854971B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9496263B1 (en) | 2015-10-23 | 2016-11-15 | International Business Machines Corporation | Stacked strained and strain-relaxed hexagonal nanowires |
US10490477B2 (en) | 2015-07-16 | 2019-11-26 | Samsung Electronics Co., Ltd. | Semiconductor device |
US10804266B2 (en) | 2018-11-16 | 2020-10-13 | International Business Machines Corporation | Microelectronic device utilizing stacked vertical devices |
US10833089B2 (en) | 2018-11-16 | 2020-11-10 | International Business Machines Corporation | Buried conductive layer supplying digital circuits |
US11164879B2 (en) | 2018-11-16 | 2021-11-02 | International Business Machines Corporation | Microelectronic device with a memory element utilizing stacked vertical devices |
US11171142B2 (en) | 2018-11-16 | 2021-11-09 | International Business Machines Corporation | Integrated circuit with vertical structures on nodes of a grid |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9501738B1 (en) | 2012-08-16 | 2016-11-22 | Sandia Corporation | Cellular computational platform and neurally inspired elements thereof |
CN104143513B (en) * | 2013-05-09 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Nano vacuum field effect electron tube and forming method thereof |
US8901715B1 (en) * | 2013-07-05 | 2014-12-02 | Infineon Technologies Ag | Method for manufacturing a marked single-crystalline substrate and semiconductor device with marking |
US9627375B2 (en) * | 2014-02-07 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Indented gate end of non-planar transistor |
US10553718B2 (en) * | 2014-03-14 | 2020-02-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with core-shell structures |
US9543440B2 (en) * | 2014-06-20 | 2017-01-10 | International Business Machines Corporation | High density vertical nanowire stack for field effect transistor |
CN105374679B (en) * | 2014-08-26 | 2019-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
US9343529B2 (en) | 2014-09-05 | 2016-05-17 | International Business Machines Corporation | Method of formation of germanium nanowires on bulk substrates |
CN105513944B (en) * | 2014-09-26 | 2018-11-13 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and its manufacturing method |
CN107004703B (en) * | 2014-12-24 | 2021-09-07 | 英特尔公司 | Field effect transistor structure using germanium nanowires |
CN105810730B (en) * | 2014-12-29 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
US9496338B2 (en) * | 2015-03-17 | 2016-11-15 | International Business Machines Corporation | Wire-last gate-all-around nanowire FET |
CN106571367A (en) * | 2015-10-12 | 2017-04-19 | 上海新昇半导体科技有限公司 | Vacuum tube flash structure and manufacturing method thereof |
US9564317B1 (en) * | 2015-12-02 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a nanowire |
CN106856208B (en) * | 2015-12-08 | 2019-09-27 | 中芯国际集成电路制造(北京)有限公司 | Nanowire semiconductor device and forming method thereof |
CN107204311A (en) * | 2016-03-16 | 2017-09-26 | 上海新昇半导体科技有限公司 | Nanowire semiconductor device and its manufacture method |
CN107331611B (en) * | 2017-06-23 | 2021-06-04 | 江苏鲁汶仪器有限公司 | Method for three-dimensional self-limiting accurate manufacturing of silicon nanowire column |
CN109244072B (en) * | 2018-09-03 | 2021-05-18 | 芯恩(青岛)集成电路有限公司 | Semiconductor device structure and manufacturing method thereof |
CN109309096B (en) * | 2018-09-27 | 2020-11-13 | 上海华力微电子有限公司 | Flash memory structure and control method thereof |
CN111128748A (en) * | 2019-12-17 | 2020-05-08 | 西交利物浦大学 | Preparation method of dual-element high-dielectric-constant insulating layer based on self-combustion method |
CN113391384B (en) * | 2021-06-04 | 2022-05-17 | 武汉大学 | On-chip directional rectification super surface based on cascade nano microstructure and design method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110133169A1 (en) * | 2009-12-04 | 2011-06-09 | International Business Machines Corporation | Gate-All-Around Nanowire Tunnel Field Effect Transistors |
US20110310920A1 (en) * | 2008-06-30 | 2011-12-22 | Stc.Unm | Epitaxial growth of in-plane nanowires and nanowire devices |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62257761A (en) * | 1986-05-01 | 1987-11-10 | Oki Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit |
CA2532991A1 (en) * | 2003-08-04 | 2005-02-24 | Nanosys, Inc. | System and process for producing nanowire composites and electronic substrates therefrom |
KR100585157B1 (en) * | 2004-09-07 | 2006-05-30 | 삼성전자주식회사 | Metal-Oxide-Semiconductor transistor comprising multiple wire bridge channels and method of manufacturing the same |
TWI283066B (en) * | 2004-09-07 | 2007-06-21 | Samsung Electronics Co Ltd | Field effect transistor (FET) having wire channels and method of fabricating the same |
KR100594327B1 (en) * | 2005-03-24 | 2006-06-30 | 삼성전자주식회사 | Semiconductor device comprising nanowire having rounded section and method for manufacturing the same |
US7999251B2 (en) * | 2006-09-11 | 2011-08-16 | International Business Machines Corporation | Nanowire MOSFET with doped epitaxial contacts for source and drain |
WO2008057558A2 (en) * | 2006-11-07 | 2008-05-15 | Nanosys, Inc. | Systems and methods for nanowire growth |
US8368125B2 (en) * | 2009-07-20 | 2013-02-05 | International Business Machines Corporation | Multiple orientation nanowires with gate stack stressors |
US8384065B2 (en) * | 2009-12-04 | 2013-02-26 | International Business Machines Corporation | Gate-all-around nanowire field effect transistors |
-
2012
- 2012-12-04 CN CN201210513894.5A patent/CN103854971B/en active Active
-
2013
- 2013-03-15 US US13/832,648 patent/US8912545B2/en active Active
-
2014
- 2014-11-10 US US14/536,953 patent/US20150060767A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110310920A1 (en) * | 2008-06-30 | 2011-12-22 | Stc.Unm | Epitaxial growth of in-plane nanowires and nanowire devices |
US20110133169A1 (en) * | 2009-12-04 | 2011-06-09 | International Business Machines Corporation | Gate-All-Around Nanowire Tunnel Field Effect Transistors |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10490477B2 (en) | 2015-07-16 | 2019-11-26 | Samsung Electronics Co., Ltd. | Semiconductor device |
US9496263B1 (en) | 2015-10-23 | 2016-11-15 | International Business Machines Corporation | Stacked strained and strain-relaxed hexagonal nanowires |
US9761661B2 (en) | 2015-10-23 | 2017-09-12 | International Business Machines Corporation | Stacked strained and strain-relaxed hexagonal nanowires |
US9859367B2 (en) | 2015-10-23 | 2018-01-02 | International Business Machines Corporation | Stacked strained and strain-relaxed hexagonal nanowires |
US10804266B2 (en) | 2018-11-16 | 2020-10-13 | International Business Machines Corporation | Microelectronic device utilizing stacked vertical devices |
US10833089B2 (en) | 2018-11-16 | 2020-11-10 | International Business Machines Corporation | Buried conductive layer supplying digital circuits |
US11164879B2 (en) | 2018-11-16 | 2021-11-02 | International Business Machines Corporation | Microelectronic device with a memory element utilizing stacked vertical devices |
US11171142B2 (en) | 2018-11-16 | 2021-11-09 | International Business Machines Corporation | Integrated circuit with vertical structures on nodes of a grid |
Also Published As
Publication number | Publication date |
---|---|
CN103854971B (en) | 2016-10-05 |
US8912545B2 (en) | 2014-12-16 |
US20140151705A1 (en) | 2014-06-05 |
CN103854971A (en) | 2014-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8912545B2 (en) | Nanowires, nanowire fielde-effect transistors and fabrication method | |
US11456354B2 (en) | Bulk nanosheet with dielectric isolation | |
US11245033B2 (en) | Semiconductor devices with core-shell structures | |
TWI518909B (en) | Integrated circuit device and method for forming the same | |
TWI642181B (en) | Iii-v gate all around semiconductor device and method for manufaturing the same | |
US8575009B2 (en) | Two-step hydrogen annealing process for creating uniform non-planar semiconductor devices at aggressive pitch | |
KR101774824B1 (en) | Transistor having germanium channel on silicon nanowire and fabrication method thereof | |
US9514937B2 (en) | Tapered nanowire structure with reduced off current | |
US9837517B2 (en) | Method for making III-V nanowire quantum well transistor | |
US9768273B2 (en) | Method of forming a trench using epitaxial lateral overgrowth | |
US9985113B2 (en) | Fabrication process for mitigating external resistance of a multigate device | |
US9608115B2 (en) | FinFET having buffer layer between channel and substrate | |
US10553496B2 (en) | Complementary metal-oxide-semiconductor field-effect transistor and method thereof | |
TWI630719B (en) | Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor | |
US10032677B2 (en) | Method and structure to fabricate closely packed hybrid nanowires at scaled pitch | |
TWI525713B (en) | Non-planar transistor fin fabrication | |
CN102623382B (en) | Silicon on insulator (SOI)-based manufacturing method for three-dimensional array type silicon nano-wire metal oxide semiconductor field effect transistor | |
US20160005736A1 (en) | Ingaas finfet on patterned silicon substrate with inp as a buffer layer | |
EP3339245A1 (en) | Method for forming horizontal nanowires and devices manufactured thereof | |
CN102623338B (en) | Manufacturing method of longitudinal stacking grid-last type silicon-nanowire field effect transistor based on SOI (Silicon On Insulator) | |
TW201717323A (en) | Junctionless high voltage field effect device and the method for making the same | |
CN102683215B (en) | The preparation method of strained silicon nano wire NMOSFET | |
CN102646597B (en) | Method for preparing three-dimensional array type rear grid type SiNWFET (Si-Nanowire Metal-Oxide -Semiconductor Field Effect Transistor) based on bulk silicon |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |