CN109309096B - Flash memory structure and control method thereof - Google Patents
Flash memory structure and control method thereof Download PDFInfo
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- CN109309096B CN109309096B CN201811134024.0A CN201811134024A CN109309096B CN 109309096 B CN109309096 B CN 109309096B CN 201811134024 A CN201811134024 A CN 201811134024A CN 109309096 B CN109309096 B CN 109309096B
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Abstract
The invention relates to a flash memory structure, comprising: the nanowire is formed on a substrate, and a channel region, a source end and a drain end which are positioned on two sides of the channel region are arranged on the nanowire along the extension direction of the nanowire, and the source end and the drain end are respectively connected with a source electrode region and a drain electrode region in the substrate; and the first fence structure and the second fence structure are mutually isolated and arranged on two sides of the channel region in a surrounding manner along the extending direction vertical to the nanowire. The flash memory device with the flash memory structure can be improved in storage capacity compared with a flash memory device with a double-bit and unit storage mode. In the flash memory structure, a channel region is designed on a nanowire on a substrate, so that the first surrounding gate structure and/or the second surrounding gate structure have good electrostatic control capability on the channel region, and the problems of short channel effect and gate leakage encountered when the size of a device is reduced are favorably resisted.
Description
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a flash memory structure and a control method thereof.
Background
In the current semiconductor industry, integrated circuit products can be divided into three major categories: analog circuits, digital circuits, and digital/analog hybrid circuits. Among them, memory devices are an important type of digital circuits. Among the Memory devices, Flash memories (Flash memories) have been developed particularly rapidly in recent years. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up; and has the advantages of high integration level, high access speed, easy erasing and rewriting, and the like, thereby being widely applied to the fields of microcomputer, automatic control, and the like.
In the existing flash memory, a 1-Bit storage mode (Single-Bit) or a 2-Bit storage mode (2-Bit) structure is usually adopted for storage, but the storage capacity of two storage Bit designs is relatively small, and the requirement of the current market for a large-capacity memory cannot be met. And under the guidance of moore's law, the size of flash memory devices is getting smaller and smaller, but cannot be reduced infinitely, because when the size is reduced to a certain extent to reach the physical limit, serious short channel effect and gate leakage current will occur. Accordingly, the structure of the existing flash memory device still needs to be improved.
Disclosure of Invention
The invention provides a flash memory structure which can realize four-bit storage and carry out programming operation, erasing operation or reading operation on any one of four storage bits. And to combat the short channel effects and gate leakage problems encountered with shrinking flash memory structure dimensions.
The present invention provides a flash memory structure, comprising:
the nanowire is formed on a substrate, and a channel region, a source end and a drain end which are positioned on two sides of the channel region are arranged on the nanowire along the extension direction of the nanowire, and the source end and the drain end are respectively connected with a source electrode region and a drain electrode region in the substrate; and
the first fence structure and the second fence structure are mutually isolated and arranged on two sides of the channel region in a surrounding manner along the extending direction perpendicular to the nanowire.
Optionally, in the flash memory structure, the first wrap gate structure includes a first dielectric layer, a first charge storage layer, a second dielectric layer, and a first gate layer that are sequentially stacked along the surface of the nanowire, and the second wrap gate structure includes a third dielectric layer, a second charge storage layer, a fourth dielectric layer, and a second gate layer that are sequentially stacked along the surface of the nanowire, where the thickness of the second charge storage layer is greater than the thickness of the first charge storage layer, and the types of impurities doped in the first gate layer and the second gate layer are opposite.
Optionally, in the flash memory structure, the first gate layer includes P-type doped impurities, and the second gate layer includes N-type doped impurities.
Optionally, in the flash memory structure, a thickness of the first charge storage layer ranges from 3nm to 5nm, and a thickness of the second charge storage layer ranges from 48nm to 52 nm.
Optionally, in the flash memory structure, the thicknesses of the first dielectric layer and the third dielectric layer range from 2nm to 4nm, the thicknesses of the second dielectric layer and the fourth dielectric layer range from 5nm to 7nm, and the thicknesses of the first gate layer and the second gate layer range from 80nm to 100 nm.
Optionally, in the flash memory structure, the nanowire has a diameter range of 4nm to 6nm and a length range of 27nm to 33 nm.
Optionally, in the flash memory structure, the material of the nanowire includes silicon germanium.
Optionally, in the flash memory structure, the material of the source region and the drain region includes silicon germanium or silicon, and a molar percentage concentration of germanium in the nanowire is higher than that of germanium in the source region and the drain region.
Optionally, in the flash memory structure, the material of the charge storage layer includes silicon nitride, and the source region and the drain region include N-type doped impurities.
According to the control method of the flash memory structure, any one of four storage bits of the flash memory structure is controlled, wherein the first charge storage layer comprises two storage bits which are respectively located in a region of the first charge storage layer close to a source end and a region close to a drain end, and the second charge storage layer also comprises two storage bits which are respectively located in a region of the second charge storage layer close to the source end and the region of the drain end; the control method comprises the step of carrying out programming operation, erasing operation or reading operation on a designated storage bit, wherein the designated storage bit corresponds to a gate layer, and the gate layer is the gate layer which is close to the designated storage bit in the first gate layer and the second gate layer.
Optionally, in the control method, the programming operation includes:
and applying a voltage of 4.5-5.5V to the source terminal or the drain terminal close to the appointed storage bit, applying a voltage of 0V to the source terminal or the drain terminal far away from the appointed storage bit, and applying a voltage of 6.5-7.5V to the corresponding gate layer.
Optionally, in the control method, the erasing operation includes:
and applying a voltage of 4.5V-5.5V to the source terminal or the drain terminal close to the appointed storage bit, applying a voltage of 0V to the source terminal or the drain terminal far away from the appointed storage bit, and applying a voltage of-4.5V-5.5V to the corresponding gate layer.
Optionally, in the control method, the reading operation includes:
applying a voltage of 1V-1.5V to the source end or the drain end far away from the appointed storage bit, applying a voltage of 0V to the source end or the drain end close to the appointed storage bit, scanning the voltage of the corresponding grid layer to obtain a threshold voltage value, and judging the storage state of the appointed storage bit according to the threshold voltage value.
Optionally, in the control method, the current corresponding to the threshold voltage value is set to 1 × 10-6And A, performing voltage scanning on the corresponding gate layer by 0V-3V.
The flash memory structure provided by the invention comprises a nanowire formed on a substrate, and a first surrounding gate structure and a second surrounding gate structure, wherein a channel region, a source end and a drain end which are positioned at two sides of the channel region are arranged on the nanowire along the radial direction of the nanowire, the source end and the drain end are respectively connected with a source region and a drain region in the substrate, and the first surrounding gate structure and the second surrounding gate structure are mutually isolated and arranged at two sides of the channel region in a surrounding manner along the radial direction which is vertical to the nanowire. The first wrap gate structure and the second wrap gate structure are formed on the nanowire in a semi-surrounding mode (i.e., a surrounding mode in which a part of the wrap gate structure is surrounded and a part of the wrap gate structure is exposed), and are isolated from each other (i.e., electrically independent), so that when the flash memory structure is controlled, four storage bits can be formed in a region of the first charge storage layer and a region of the second charge storage layer, which are respectively close to the source terminal and the drain terminal, and four storage bits can be stored, so that four-bit storage can be realized. The four-bit memory design can greatly improve the storage capacity (for example, 16 state combinations from '0000' to '1111'), so that the flash memory device utilizing the flash memory structure of the invention can improve the storage capacity compared with the flash memory device of a double-bit and single-bit storage mode. Meanwhile, in the flash memory structure, the channel region is designed on the nanowire on the substrate, so that the first surrounding gate structure and/or the second surrounding gate structure have good electrostatic control capability on the channel region, and the problems of short channel effect and gate leakage encountered when the size of a device is reduced are favorably resisted.
The control method of the flash memory structure provided by the invention can perform programming operation, erasing operation or reading operation on any appointed storage bit in the flash memory structure, and is favorable for popularization and application of a flash memory device comprising the flash memory structure.
Drawings
Fig. 1 is a schematic diagram of a flash memory structure according to an embodiment of the present invention.
Fig. 2 is a schematic lateral cross-sectional view of a flash memory structure according to an embodiment of the invention.
Fig. 3 is a schematic longitudinal cross-sectional view of a flash memory structure according to an embodiment of the invention.
Wherein, 10-a first wrap gate structure; 11-a first dielectric layer; 12-a first charge storage layer; 13-a second dielectric layer; 14-a first gate layer; 15-an isolation layer; 20-a second wrap gate structure; 21-a third dielectric layer; 22-a second charge storage layer; 23-a fourth dielectric layer; 24-a second gate layer; 30-a channel region; 40-nanowires; 41-source end; 42-drain terminal; 51-a first storage bit; 52-a second memory bit; 53-a third storage bit; 54-fourth memory bit.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. Similarly, when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
The present invention provides a flash memory structure, as shown in fig. 1 to 3, fig. 1 is a schematic diagram of a flash memory structure according to an embodiment of the present invention; fig. 2 is a schematic lateral cross-sectional view of a flash memory structure according to an embodiment of the invention. Fig. 3 is a schematic longitudinal cross-sectional view of a flash memory structure according to an embodiment of the invention.
Specifically, referring to fig. 1 to 3, the flash memory structure includes: a nanowire 40 formed on a substrate, wherein the nanowire 40 is provided with a channel region 30, and a source terminal 41 and a drain terminal 42 located at two sides of the channel region 30 along an extending direction of the nanowire 40, and the source terminal 41 and the drain terminal 42 are respectively connected with a source region and a drain region (not shown) in the substrate; and a first wrap gate structure 10 and a second wrap gate structure 20, wherein the first wrap gate structure 10 and the second wrap gate structure 20 are isolated from each other and are arranged on two sides of the channel region 30 in a surrounding manner along a direction perpendicular to the extending direction of the nanowire 40.
Preferably, the diameter of the nanowire 40 ranges from 4nm to 6nm, and the length ranges from 27nm to 33 nm. The length range of the source end 41 and the drain end 42 is about 8-12 nm. The source terminal 41 and the drain terminal 42 may be doped N-type with a doping concentration of 10, for example17～1018/cm3The impurity to be doped includes arsenic or phosphorus. The transverse cross-section of the first boom structure 10 and the second boom structure 20 is not limited to a semi-circular arc shape as shown in the drawings, and in other embodiments, the transverse cross-section of the first boom structure 10 and the second boom structure 20 may also include a non-closed wavy line, a broken line, or the like.
Further, the first wrap gate structure 10 includes a first dielectric layer 11, a first charge storage layer 12, a second dielectric layer 13, and a first gate layer 14 that are sequentially stacked along the surface of the nanowire 40, and the second wrap gate structure 20 includes a third dielectric layer 21, a second charge storage layer 22, a fourth dielectric layer 23, and a second gate layer 24 that are sequentially stacked along the surface of the nanowire 40, where the first dielectric layer 11, the second dielectric layer 13, the third dielectric layer 21, and the fourth dielectric layer 23 may be made of an oxide, and specifically, the oxide may be silicon oxide or the like; the charge storage layer can adopt silicon nitride as a manufacturing material; the first gate layer 14 and the second gate layer 24 may be polysilicon layers. In this embodiment, the charge storage layer uses silicon nitride as a material for storing charges injected from the channel region 30. Therefore, in the present application, the first wrap gate structure 10 and the second wrap gate structure 20 disposed in the channel region 30 are electrically operated independently, and four-bit storage can be achieved. The design of four-Bit storage greatly improves the storage capacity of the flash memory, so that the flash memory structure of the embodiment has the storage capacity far larger than that of a double Bit (2-Bit) and a Single Bit (Single-Bit). Meanwhile, the strong electrostatic control capability of the first gate layer 14 and the second gate layer 24 on the channel region 30 in the flash memory structure is utilized to resist the short channel effect and the gate leakage problem encountered when the flash memory is scaled down.
Preferably, the thicknesses of the first wrap gate structure 10 and the second wrap gate structure 20 are different, specifically, the thickness of the stacked layer formed by the third dielectric layer 21, the second charge storage layer 22, and the fourth dielectric layer 23 may be greater than the thickness of the stacked layer formed by the first dielectric layer 11, the first charge storage layer 12, and the second dielectric layer 13, so that the threshold voltages of the flash memory devices corresponding to the first wrap gate structure 10 and the second wrap gate structure 20 are different, for example, the threshold voltage of the flash memory device corresponding to the second wrap gate structure 20 is higher than the threshold voltage of the flash memory device corresponding to the first wrap gate structure 10 by 3V to 4V, thereby preventing the storage bits corresponding to the first wrap gate structure 10 and the second wrap gate structure 20 in the flash memory structure from affecting each other.
In some embodiments, the thickness of the second charge storage layer 22 is much greater than the thickness of the first charge storage layer 12, for example, the first charge storage layer 12 has a thickness in the range of 3nm to 5nm and the second charge storage layer 22 has a thickness in the range of 48nm to 52 nm. In addition, the first gate layer 14 and the second gate layer 24 may be provided with different doping types, for example, the first gate layer 14 is doped with N-type doping impurities, the second gate layer 24 is doped with P-type doping impurities, or the first gate layer 14 is doped with P-type doping, and the second gate layer 24 is doped with N-type doping. In general, the work function difference between N-type doped polysilicon and P-type doped polysilicon to the silicon channel is different, so that the threshold voltages of the two gate-to-channel are different. Therefore, in this embodiment, whether the second charge storage layer 22 in the second wrap gate structure 20 stores electrons has no influence on the Id-Vg curve of the forward and reverse reading of the storage bit corresponding to the first wrap gate structure 10, and vice versa, that is, whether the first charge storage layer 12 stores electrons has no influence on the Id-Vg curve of the forward and reverse reading of the storage bit corresponding to the second wrap gate structure 20.
Further, the thickness of each deposition layer in the first wrap gate structure 10 and the second wrap gate structure 20 is exemplified as follows: in the first wrap gate structure 10: the thickness of the first dielectric layer 11 is 2-4 nm; the thickness of the first charge storage layer 12 is 3-5 nm; the thickness of the second dielectric layer 13 is 5-7 nm; the thickness of the first gate layer 14 is 80 to 100 nm. In the second wrap gate structure 20: the thickness of the third dielectric layer 21 is 2-4 nm; the thickness of the second charge storage layer 22 is 48-52 nm; the thickness of the fourth dielectric layer 23 is 5-7 nm; the thickness of the second gate layer 24 is 80-100 nm.
The invention designs a semi-enclosed first wrap gate structure 10 and a second wrap gate structure 20, and the isolation layer 15 is adopted for isolation, so that the electrical operation of the first wrap gate structure 10 and the second wrap gate structure 20 is independent. The isolation layer 15 is made of silicon oxide, silicon oxynitride, or other insulating materials.
In embodiments of the present invention, a material of a source region and a drain region in a substrate may be silicon germanium or silicon, a material of the nanowire 40 (including the channel region 30, the source terminal 41, and the drain terminal 42) may be silicon germanium, and in other embodiments, a material of the channel region 30, the source terminal 41, and the drain terminal 42 on the nanowire 40 may also be different materials, for example, the nanowire 40 of the channel region 30 is silicon germanium, and a material of the source terminal 41 and the drain terminal 42 respectively connected to the source region and the drain region in the substrate is silicon germanium or silicon germanium. Preferably, the molar percentage concentration of germanium in the nanowire 40 is higher than that in the source region and the drain region, so that the hole mobility of the channel region 30 can be improved, that is, the efficiency of hole injection in flash memory erase can be improved, and the erase speed can be improved.
The embodiment of the invention also provides a control method of the flash memory structure. The control method may control any one of the four storage bits of the flash memory structure. Wherein the first charge storage layer 12 includes two of the memory bits, respectively located in a region of the first charge storage layer 12 near the source terminal 41 (defined as a first memory bit 51) and near the drain terminal 42 (defined as a second memory bit 52), and the second charge storage layer 22 also includes two memory bits, respectively located in a region of the second charge storage layer 22 near the source terminal 41 (defined as a third memory bit 53) and near the drain terminal 42 (defined as a fourth memory bit 54); the control method includes performing a program operation, an erase operation, or a read operation on a designated one of the storage bits, the designated storage bit corresponding to one of the gate layers in the flash memory structure, the gate layer being one of the first gate layer 14 and the second gate layer 24 that is close to the designated storage bit.
Further, the control method comprises a programming operation, an erasing operation and a reading operation.
Wherein the programming operation comprises: applying a voltage of 4.5V to 5.5V to the source terminal 41 or the drain terminal 42 close to the designated bit, applying a voltage of 0V to the source terminal 41 or the drain terminal 42 far from the designated bit, and applying a voltage of 6.5V to 7.5V to the corresponding gate layer. Preferably, the physical mechanism of the program operation may be channel hot electron injection.
An example of the case where voltages are applied when programming the above four memory bits is as follows. When programming the first memory bit 51, Vg1 (i.e., the voltage applied to the first gate layer 14) is 7V, Vs (i.e., the voltage at the source terminal 41) is 5V, and Vd (i.e., the voltage at the drain terminal 42) is 0V. When programming the second memory bit 52, Vg1 (i.e., the voltage applied to the first gate layer 14) is 7V, Vd (i.e., the voltage at the drain terminal 42) is 5V, and Vs (i.e., the voltage at the source terminal 41) is 0V. When programming the third memory bit 53, Vg2 (i.e., the voltage applied to the second gate layer 24) is 7V, Vs (i.e., the voltage at the source terminal 41) is 5V, and Vd (i.e., the voltage at the drain terminal 42) is 0V. When programming the fourth memory bit 54, Vg2 (i.e., the voltage applied to the second gate layer 24) is 7V, Vd (i.e., the voltage at the drain terminal 42) is 5V, and Vs (i.e., the voltage at the source terminal 41) is 0V.
The erase operation includes: applying a voltage of 4.5V to 5.5V to the source terminal 41 or the drain terminal 42 close to the designated bit, applying a voltage of 0V to the source terminal 41 or the drain terminal 42 far from the designated bit, and applying a voltage of-4.5V to-5.5V to the corresponding gate layer. Preferably, the physical mechanism of the erase operation is band-to-band tunneling hot hole injection.
An example of the case where a voltage is applied when erasing the four memory bits is as follows. When erasing the first memory bit 51, Vg1 (i.e., the voltage applied to the first gate layer 14) is-5V, Vs (i.e., the voltage at the source terminal 41) is 5V, and Vd (i.e., the voltage at the drain terminal 42) is 0V. When erasing the second memory bit 52, Vg1 (i.e., the voltage applied to the first gate layer 14) is-5V, Vd (i.e., the voltage at the drain terminal 42) is 5V, and Vs (i.e., the voltage at the source terminal 41) is 0V. When erasing the third memory bit 53, Vg2 (i.e., the voltage applied to the second gate layer 24) is-5V, Vs (i.e., the voltage at the source terminal 41) is 5V, and Vd (i.e., the voltage at the drain terminal 42) is 0V. When erasing the fourth memory bit 54, Vg2 (i.e., the voltage applied to the second gate layer 24) is-5V, Vd (i.e., the voltage at the drain terminal 42) is 5V, and Vs (i.e., the voltage at the source terminal 41) is 0V.
The read operation includes: applying a voltage of 1V to 1.5V to the source terminal 41 or the drain terminal 42 far away from the designated storage bit, applying a voltage of 0V to the source terminal 41 or the drain terminal 42 close to the designated storage bit, scanning the voltage of the corresponding gate layer to obtain a threshold voltage value, and judging the storage state of the designated storage bit according to the threshold voltage value. The principle used here is that, for example, knowing that the first memory bit 51 has electrons or not, the addition of a positive Vd voltage to the drain terminal 42 (i.e., the terminal remote from the first memory bit 51) can cause it to mask the effect of the electrons in the second memory bit 52 on the threshold voltage value. Because the presence of electrons, if present in the second memory bit 52, raises the barrier of the channel region 30 near the drain 42, and the barrier of the channel region 30 near the drain 42 lowers after a positive voltage is applied to the drain 42, thereby removing the effect on the channel barrier of the presence of electrons in the second memory bit 52. Thus, the magnitude of the source-drain current and the threshold voltage obtained by the fixed current method are determined only by whether electrons are stored in the first memory bit 51, so that the information of the first memory bit 51 can be accurately read.
In the flash memory structure of this embodiment, it is preferable that the doping types of the first gate layer 14 and the second gate layer 24 are different, and the thicknesses of the first wrap gate structure 10 and the second wrap gate structure 20 are different, so that the threshold voltage value of the read operation of the memory bits located at the upper portion (i.e., the first memory bit 51 and the second memory bit 52) is different from the threshold voltage value of the read operation of the memory bits located at the lower portion (i.e., the third memory bit 53 and the fourth memory bit 54), so that the memory bits located at the first charge storage layer can be distinguished from the memory bits located at the second charge storage layer by the read operation. Specifically, since the first storage bit 51 and the second storage bit 52 belong to the first wrap gate structure 10 located at the upper part, the gate voltage is selectively applied to the first gate layer 14 during the read operation of the first storage bit 51 and the second storage bit 52; the third memory bit 53 and the fourth memory bit 54 belong to the lower second wrap gate structure 20, and the gate voltage is selectively applied to the second gate layer 24 for their read operation. Since the storage bits corresponding to the first and second wrap gate structures 10 and 20 have a difference in the read threshold voltage values, it is possible to easily distinguish between the upper and lower storage locations, that is, whether electrons are stored in the first storage bit 51 or the second storage bit 52 or in the third storage bit 53 or the fourth storage bit 54, depending on the threshold voltage value determined by the fixed current method at the time of the read operation.
In one embodiment, when a read operation is performed on any one of the four storage bits, a voltage scan may be performed on the gate layer of the wrap gate structure from 0V to 3V, and a current corresponding to a threshold voltage value to be read may be set to 1 × 10-6A, when the drain current of the flash memory device reaches 1 × 10-6At time a, a gate voltage value, i.e., a threshold voltage, can be obtained, which is a fixed current method. Then, comparing the threshold voltage value with a standard threshold voltage, and if the obtained threshold voltage value is smaller (smaller than the standard threshold voltage), judging that no electrons are stored in the corresponding storage bit; if the obtained threshold voltage value is larger (larger than the standard threshold voltage), it can be determined that electrons have been stored in the corresponding memory bit.
Further, the standard threshold voltage set by the storage bit of the first wrap gate structure 10 and the standard threshold voltage set by the storage bit of the second wrap gate structure 20 are different by 3V to 4V. The range of values for the standard threshold voltage may be set according to the performance of the flash memory structure. Specifically, the standard threshold voltage set for the memory bit of the first wrap gate structure 10 is an average of normal threshold voltage samples tested at least 50 times for the first memory bit 51 or the second memory bit 52. The standard threshold voltage set for the memory bit of the second wrap gate structure 20 is the average of normal samples of threshold voltage tested at least 50 times for the third memory bit 53 or the fourth memory bit 54.
An example of the case where a voltage is applied when reading the four memory bits is as follows. When reading the first memory bit 51, Vd (i.e., the voltage at the drain terminal 42) is set to 1.2V, Vs (i.e., the voltage at the source terminal 41) is set to 0, and Vg1 (i.e., the voltage applied to the first gate layer 14) is voltage swept from 0V to 3V at a specified current (e.g., 1 × 10)-6A) In the case of (3), if the obtained threshold voltage value is small, no electrons are stored, and if the obtained threshold voltage value is large, electrons are stored.
When reading the second memory bit 52, Vs (i.e., the voltage at the source terminal 41) is set to 1.2V, Vd (i.e., the voltage at the drain terminal 42) is set to 0, and Vg1 (i.e., the voltage applied to the first gate layer 14) is subjected to a voltage sweep of 0V to 3V, where, in the case of a given current, no electrons are stored if the obtained threshold voltage value is small, and electrons are stored if the obtained threshold voltage value is large.
When reading the third memory bit 53, Vd (i.e., the voltage at the drain terminal 42) is set to 1.2V, Vs (i.e., the voltage at the source terminal 41) is set to 0, and Vg2 (i.e., the voltage applied to the second gate layer 24) is subjected to a voltage sweep of 0V to 3V, where, in the case of a given current, no electrons are stored if the obtained threshold voltage value is small, and electrons are stored if the obtained threshold voltage value is large.
When reading the fourth memory bit 54, Vs (i.e., the voltage at the source terminal 41) is set to 1.2V, Vd (i.e., the voltage at the drain terminal 42) is set to 0, and Vg2 (i.e., the voltage applied to the second gate layer 24) is subjected to a voltage sweep of 0V to 3V, where, at a given current, no electrons are stored if the obtained threshold voltage value is small, and electrons are stored if the obtained threshold voltage value is large.
Further, since the types of the doped impurities in the first gate layer 14 and the second gate layer 24 are opposite, one is an N-type doped polysilicon gate, and the other is a P-type doped polysilicon gate. The work function difference of the two gate layers is different, and the thicknesses of the charge storage layers in the two surrounding gate structures are different, so that the threshold voltages of the two surrounding gate structures are different, and the threshold voltage of the second surrounding gate structure 20 is 3V to 4V higher than that of the first surrounding gate structure 10, so that the standard threshold voltage set by the storage bit of the first surrounding gate structure 10 and the standard threshold voltage set by the storage bit of the second surrounding gate structure 20 can be different by 3V to 4V, so as to distinguish the threshold voltage values read by the storage bit of the first surrounding gate structure 10 and the storage bit of the second surrounding gate structure 20.
Therefore, when the flash memory structure of the embodiment of the invention is controlled, four-bit storage can be realized by using the four storage bits. In this way, each storage bit can have two states, for example, "0" represents a state in which electrons are stored, and "1" represents a state in which electrons are not stored, so that 16 combined states can be obtained in total, namely, from "0000" to "1111", that is, 4-bit information can be stored.
In summary, in the flash memory structure provided by the present invention, the flash memory structure includes a nanowire formed on a substrate, and a first wrap gate structure and a second wrap gate structure, along a radial direction of the nanowire, the nanowire is provided with a channel region, and a source end and a drain end located at two sides of the channel region, the source end and the drain end are respectively connected to a source region and a drain region in the substrate, and along a radial direction perpendicular to the nanowire, the first wrap gate structure and the second wrap gate structure are isolated from each other and are disposed at two sides of the channel region in a wrapped manner. The first wrap gate structure and the second wrap gate structure are formed on the nanowire in a semi-surrounding mode (i.e., a surrounding mode in which a part of the wrap gate structure is surrounded and a part of the wrap gate structure is exposed), and are isolated from each other (i.e., electrically independent), so that when the flash memory structure is controlled, four storage bits can be formed in a region of the first charge storage layer and a region of the second charge storage layer, which are respectively close to the source terminal and the drain terminal, and four storage bits can be stored, so that four-bit storage can be realized. The four-bit memory design can greatly improve the storage capacity (for example, 16 state combinations from '0000' to '1111'), so that the flash memory device utilizing the flash memory structure of the invention can improve the storage capacity compared with the flash memory device of a double-bit and single-bit storage mode. Meanwhile, in the flash memory structure, the channel region is designed on the nanowire on the substrate, so that the first surrounding gate structure and/or the second surrounding gate structure have good electrostatic control capability on the channel region, and the problems of short channel effect and gate leakage encountered when the size of a device is reduced are favorably resisted.
The control method of the flash memory structure provided by the invention can perform programming operation, erasing operation or reading operation on any appointed storage bit in the flash memory structure, and is favorable for popularization and application of a flash memory device comprising the flash memory structure.
The foregoing embodiments are merely illustrative of the principles of the invention and its efficacy, and are not to be construed as limiting the invention. Those skilled in the art can make various changes, substitutions and alterations to the disclosed embodiments and technical contents without departing from the spirit and scope of the present invention.
Claims (14)
1. A flash memory structure, comprising:
the nanowire is formed on a substrate, and a channel region, a source end and a drain end which are positioned on two sides of the channel region are arranged on the nanowire along the extension direction of the nanowire, and the source end and the drain end are respectively connected with a source electrode region and a drain electrode region in the substrate; and
the first fence structure and the second fence structure are mutually isolated and arranged on two sides of the channel region in a surrounding manner along the extending direction perpendicular to the nanowire;
wherein the first wrap gate structure comprises a first charge storage layer formed on the surface of the nanowire, the first charge storage layer comprising two storage bits, and the second wrap gate structure comprises a second charge storage layer formed on the surface of the nanowire, the second charge storage layer comprising two storage bits.
2. The flash memory structure of claim 1, wherein the first wrap gate structure comprises a first dielectric layer, a first charge storage layer, a second dielectric layer and a first gate layer which are sequentially stacked along the surface of the nanowire, and the second wrap gate structure comprises a third dielectric layer, a second charge storage layer, a fourth dielectric layer and a second gate layer which are sequentially stacked along the surface of the nanowire, wherein the thickness of the second charge storage layer is greater than that of the first charge storage layer, and the types of impurities doped in the first gate layer and the second gate layer are opposite.
3. The flash memory structure of claim 2, wherein the first gate layer comprises P-type dopant impurities and the second gate layer comprises N-type dopant impurities.
4. The flash memory structure of claim 2, wherein the first charge storage layer has a thickness in a range of 3nm to 5nm, and the second charge storage layer has a thickness in a range of 48nm to 52 nm.
5. The flash memory structure of claim 2, wherein the first dielectric layer and the third dielectric layer have a thickness in a range of 2nm to 4nm, the second dielectric layer and the fourth dielectric layer have a thickness in a range of 5nm to 7nm, and the first gate layer and the second gate layer have a thickness in a range of 80nm to 100 nm.
6. The flash memory structure of claim 1, wherein the nanowires have a wire diameter ranging from 4nm to 6nm and a length ranging from 27nm to 33 nm.
7. The flash memory structure of claim 1, wherein the material of the nanowire comprises silicon germanium.
8. The flash memory structure of claim 7, wherein the source region and the drain region are comprised of silicon germanium or silicon, and wherein a molar percentage concentration of germanium in the nanowire is higher than a molar percentage concentration of germanium in the source region and the drain region.
9. The flash memory structure of claim 1, wherein a material of the first charge storage layer and the second charge storage layer comprises silicon nitride, and the source region and the drain region comprise N-type doping impurities.
10. A method of controlling a flash memory structure according to any one of claims 2 to 5, wherein any one of four memory bits of the flash memory structure is controlled, wherein the first charge storage layer comprises two of said memory bits located in a region of the first charge storage layer adjacent to the source terminal and a region adjacent to the drain terminal, respectively, and the second charge storage layer also comprises two memory bits located in a region of the second charge storage layer adjacent to the source terminal and a region adjacent to the drain terminal, respectively; the control method comprises the step of carrying out programming operation, erasing operation or reading operation on a designated storage bit, wherein the designated storage bit corresponds to a gate layer, and the gate layer is the gate layer which is close to the designated storage bit in the first gate layer and the second gate layer.
11. The control method of claim 10, wherein the programming operation comprises:
applying a voltage of 4.5-5.5V to the source terminal or the drain terminal close to the appointed storage bit, applying a voltage of 0V to the source terminal or the drain terminal far away from the appointed storage bit, and applying a voltage of 6.5-7.5V to the corresponding grid layer.
12. The control method of claim 10, wherein the erase operation comprises:
applying a voltage of 4.5-5.5V to the source terminal or the drain terminal close to the appointed storage bit, applying a voltage of 0V to the source terminal or the drain terminal far away from the appointed storage bit, and applying a voltage of-4.5-5.5V to the corresponding gate layer.
13. The control method of claim 10, wherein the read operation comprises:
applying a voltage of 1V-1.5V to the source end or the drain end far away from the appointed storage bit, applying a voltage of 0V to the source end or the drain end close to the appointed storage bit, scanning the voltage of the corresponding grid layer to obtain a threshold voltage value, and judging the storage state of the appointed storage bit according to the threshold voltage value.
14. The control method according to claim 13, wherein the threshold voltage value is set to a current of 1 x 10-6And A, performing 0V-3V voltage scanning on the corresponding grid layer.
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| CN103854971A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of nanowires and manufacturing method of nanowire field effect transistors |
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