CN109309096A - Flash memory structure and its control method - Google Patents
Flash memory structure and its control method Download PDFInfo
- Publication number
- CN109309096A CN109309096A CN201811134024.0A CN201811134024A CN109309096A CN 109309096 A CN109309096 A CN 109309096A CN 201811134024 A CN201811134024 A CN 201811134024A CN 109309096 A CN109309096 A CN 109309096A
- Authority
- CN
- China
- Prior art keywords
- layer
- flash memory
- voltage
- source
- storage position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
The present invention relates to a kind of flash memory structures, it include: nano wire formed on a substrate, along the extending direction of the nano wire, be provided with channel region and source and drain terminal positioned at the channel region two sides on the nano wire, the source and the drain terminal respectively in the substrate source area and drain region connect；And first enclosing structure and the second enclosing structure, along the extending direction perpendicular to the nano wire, first enclosing structure and second enclosing structure are mutually isolated and enclose the two sides for being set to the channel region.The application can be improved in terms of memory capacity using the flush memory device of flash memory structure compared with the flush memory device of dibit and unit storage mode.In flash memory structure, on the nano wire of channel region design on substrate, to which the first enclosing structure and/or the second enclosing structure have good static control ability to channel region, be conducive to the problem of resisting the short-channel effect and gate leakage that encounter in device dimensions shrink.
Description
Technical field
The present invention relates to semiconductor field, in particular to a kind of flash memory structure and its control method.
Background technique
In current semiconductor industry, IC products can be divided mainly into three categories type: analog circuit, digital circuit
With D/A hybrid circuit.Wherein, memory device is an important kind in digital circuit.And in memory device, in recent years
The development of flash memory (Flash Memory) is especially rapid.Being mainly characterized by keep for a long time in the case where not powered of flash memory is deposited
The information of storage；And have many advantages, such as that integrated level is high, access speed is fast, be easy to wipe and rewrite, thus in microcomputer, automation control
It is widely used etc. multinomial field.
In existing flash memory, 1 storage mode (Single-Bit) or dibit storage mode (2-Bit) are usually used
Structure stored, but two storage positions design memory capacity it is smaller, be not able to satisfy current market and large capacity deposited
The demand of reservoir.And under the guidance of Moore's Law, the size of flush memory device is smaller and smaller, but cannot infinitely reduce, because
For when diminution makes up to its physics limit to a certain extent, serious short-channel effect and gate leakage current will go out
It is existing.Therefore, the structure of existing flush memory device still needs to improve.
Summary of the invention
The present invention provides a kind of flash memory structures, and four storages may be implemented, carry out to any of four storage positions
Programming operation, erasing operation or read operation.And the short-channel effect and grid encountered when resisting flash memory structure size reduction is let out
The problem of leakage.
The present invention provides a kind of flash memory structures, comprising:
Nano wire formed on a substrate is provided with channel region on the nano wire along the extending direction of the nano wire
And source and drain terminal positioned at the channel region two sides, the source and the drain terminal respectively with the source area in the substrate
It is connected with drain region；And
First enclosing structure and the second enclosing structure, along the extending direction perpendicular to the nano wire, described first encloses grid
Structure and second enclosing structure are mutually isolated and enclose and be set to the two sides of the channel region.
Optionally, in the flash memory structure, first enclosing structure includes successively folding along the surface of the nano wire
First medium layer, the first charge storage layer, second dielectric layer and the first grid layer added, second enclosing structure includes edge
Third dielectric layer, the second charge storage layer, the 4th dielectric layer and the second grid layer that the surface of the nano wire is sequentially overlapped,
Wherein, the thickness of second charge storage layer is greater than the thickness of first charge storage layer, the first grid layer and institute
The type for stating impurity in second grid layer is opposite.
It optionally, include p-type impurity, the second grid in the first grid layer in the flash memory structure
It include n-type doping impurity in layer.
Optionally, in the flash memory structure, the thickness range of first charge storage layer is 3nm~5nm, described the
The thickness range of two charge storage layers is 48nm~52nm.
Optionally, in the flash memory structure, the thickness range of the first medium layer and the third dielectric layer is 2nm
The thickness range of~4nm, the second dielectric layer and the 4th dielectric layer is 5nm~7nm, the first grid layer and described
The thickness range of second grid layer is 80nm~100nm.
Optionally, in the flash memory structure, the wire range of the nano wire is 4nm~6nm, length range 27nm
~33nm.
Optionally, in the flash memory structure, the material of the nano wire includes germanium silicon.
Optionally, in the flash memory structure, the material of the source area and the drain region includes germanium silicon or silicon, and
And in the nano wire Mole percent specific concentration of germanium be higher than germanium in the source area and the drain region molar percentage it is dense
Degree.
Optionally, in the flash memory structure, the material of the charge storage layer includes silicon nitride, the source area and institute
Stating drain region includes n-type doping impurity.
A kind of control method of above-mentioned flash memory structure controls any of four storage positions of the flash memory structure
System, wherein first charge storage layer includes two storage positions, is located at first charge storage layer close to institute
The region of source and the region close to the drain terminal are stated, second charge storage layer also includes two storage positions, respectively position
In second charge storage layer close to the region of the source and the region of the drain terminal；The control method includes to finger
The storage position of fixed one is programmed operation, erasing operation or read operation, the specified storage position and a grid
Layer is corresponding, and the grid layer is in the first grid layer and the second grid layer close to the grid of the specified storage position
Layer.
Optionally, in the control method, the programming operation includes:
In the voltage of the source or drain terminal application 4.5V~5.5V close to the specified storage position, far from institute
The source or the drain terminal for stating specified storage position apply 0V voltage, and the corresponding grid layer apply 6.5V~
The voltage of 7.5V.
Optionally, in the control method, the erasing operation includes:
In the voltage of the source or drain terminal application 4.5V~5.5V close to the specified storage position, far from institute
The source or the drain terminal for stating specified storage position apply 0V voltage, and the corresponding grid layer application -4.5V~-
The voltage of 5.5V.
Optionally, in the control method, the read operation includes:
In the voltage of the source or drain terminal application 1V~1.5V far from the specified storage position, close to described
The source of specified storage position or the drain terminal apply 0V voltage, and scan the voltage of the corresponding grid layer to obtain
One threshold voltage numerical value judges the storage state of the specified storage position according to the threshold voltage numerical value.
Optionally, in the control method, the corresponding electric current of the threshold voltage numerical value is set as 1*10-6A, to described
Corresponding grid layer carries out 0V~3V voltage scanning.
Flash memory structure provided by the invention includes that nano wire formed on a substrate and the first enclosing structure and second enclose
Grid structure is provided with channel region and is located at the channel region two sides along the radial direction of the nano wire on the nano wire
Source and drain terminal, the source and the drain terminal respectively in the substrate source area and drain region connect, along perpendicular to
The radial direction of the nano wire, first enclosing structure and second enclosing structure it is mutually isolated and enclose be set to institute
State the two sides of channel region.(i.e. part surrounds simultaneously in a manner of semi-surrounding for above-mentioned first enclosing structure and second enclosing structure
And the encirclement mode for thering is part to expose) formed on nano wire, and mutually isolated (being independent in electrical property), to the sudden strain of a muscle
When depositing structure and being controlled, can the first charge storage layer and the second charge storage layer respectively close to the region of the source and
Four storage positions are formed close to the region of the drain terminal, so as to realize four storages.The design of four storages can be significantly
It improves memory capacity (such as sharing combinations of states in 16 from " 0000 " to " 1111 "), therefore utilizes flash memory structure of the invention
Flush memory device can be improved in terms of memory capacity compared with the flush memory device of dibit and unit storage mode.It is of the invention simultaneously
In flash memory structure, on the nano wire of channel region design on substrate, so that the first enclosing structure and/or the second enclosing structure are right
Channel region has good static control ability, is conducive to resist the short-channel effect encountered in device dimensions shrink and grid is let out
The problem of leakage.
The control method of above-mentioned flash memory structure provided by the invention, can be specified to any one in above-mentioned flash memory structure
Storage position be programmed operation, erasing operation or read operation, be conducive to include the flush memory device of above-mentioned flash memory structure popularization
Using.
Detailed description of the invention
Fig. 1 is the schematic diagram of flash memory structure provided in an embodiment of the present invention.
Fig. 2 is the horizontal section schematic diagram of flash memory structure provided in an embodiment of the present invention.
Fig. 3 is the longitudinal profile schematic diagram of flash memory structure provided in an embodiment of the present invention.
Wherein, the first enclosing structure of 10-；11- first medium layer；The first charge storage layer of 12-；13- second dielectric layer；
14- first grid layer；15- separation layer；The second enclosing structure of 20-；21- third dielectric layer；The second charge storage layer of 22-；23-
Four dielectric layers；24- second grid layer；30- channel region；40- nano wire；41- source；42- drain terminal；51- first stores position；52-
Second storage position；53- third stores position；54- the 4th stores position.
Specific embodiment
A specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following description,
Advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate
Ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
In the following description, it should be appreciated that when layer (or film), region, pattern or structure be referred to as substrate, layer (or
Film), region and/or when pattern "upper", it can be on another layer or substrate, and/or there may also be insert layers.
Similar, when layer is referred to as at another layer of "lower", it can be under another layer, and/or there may also be one
A or multiple insert layers.Furthermore it is possible to be carried out based on attached drawing about the reference in each layer "up" and "down".
It is flash memory structure provided in an embodiment of the present invention the present invention provides a kind of flash memory structure, such as Fig. 1 to Fig. 3, Fig. 1
Schematic diagram；Fig. 2 is the horizontal section schematic diagram of flash memory structure provided in an embodiment of the present invention.Fig. 3 provides for the embodiment of the present invention
Flash memory structure longitudinal profile schematic diagram.
Specifically, the flash memory structure includes: nano wire 40 formed on a substrate referring to figs. 1 to Fig. 3, received along described
The extending direction of rice noodles 40 is provided with channel region 30 and the source 41 positioned at 30 two sides of channel region on the nano wire 40
With drain terminal 42, the source 41 and the drain terminal 42 respectively in the substrate source area and drain region (not shown) connect；
And first enclosing structure 10 and the second enclosing structure 20, along the extending direction perpendicular to the nano wire 40, described first encloses
Grid structure 10 and second enclosing structure 20 are mutually isolated and enclose and be set to the two sides of the channel region 30.
Preferably, the wire range of the nano wire 40 is 4nm~6nm, and length range is 27nm~33nm.The source
41 and the length range of drain terminal 42 be about 8~12nm.The source 41 and drain terminal 42 for example can be n-type doping, doping concentration
It is 1017~1018/cm3, the impurity of doping includes arsenic or phosphorus.The horizontal section of first enclosing structure 10 and the second enclosing structure 20
It is not limited to half-circle-arc shape as shown in the drawings, in other embodiments, the first enclosing structure 10 and described second encloses grid knot
The horizontal section of structure 20 also may include the shapes such as non-closed wave, broken line.
Further, first enclosing structure 10 includes the first medium being sequentially overlapped along the surface of the nano wire 40
The 11, first charge storage layer 12 of layer, second dielectric layer 13 and first grid layer 14, second enclosing structure 20 include along institute
State third dielectric layer 21, the second charge storage layer 22, the 4th dielectric layer 23 and second that the surface of nano wire 40 is sequentially overlapped
Grid layer 24, wherein the first medium layer 11, second dielectric layer 13, third dielectric layer 21 and the 4th dielectric layer 23 can be adopted
Use oxide as its making material, specifically, the oxide can be silica etc.；The charge storage layer can use
Silicon nitride is as its making material；First grid layer 14 and second grid layer 24 can be polysilicon layer.It is described in the present embodiment
Charge storage layer uses silicon nitride as material, for storing the charge injected from channel region 30.Therefore, in the application, in ditch
The electrical operation of the first enclosing structure 10 and the second enclosing structure 20 that road area 30 is arranged is independent, it can be achieved that four storages.Four
The design of storage substantially increases the memory capacity of flash memory, and the flash memory structure of the present embodiment is allowed to have much larger than dibit (2-
) and the memory capacity of unit (Single-Bit) Bit.First grid layer 14 and second grid layer 24 in flash memory structure are utilized simultaneously
To the powerful static control ability of channel region 30, the short-channel effect and gate leakage encountered when flash memory size reduces can be resisted
The problem of.
Preferably, the first enclosing structure 10 is different with 20 thickness of the second enclosing structure, specifically, can make third dielectric layer
21, the second charge storage layer 22, superimposed layer composed by the 4th dielectric layer 23 thickness be greater than first medium layer 11, the first charge
The thickness of superimposed layer composed by accumulation layer 12, second dielectric layer 13, so that the first enclosing structure 10 and the second enclosing structure
The threshold voltage of 20 corresponding flush memory devices is different, for example, making the threshold value electricity of the corresponding flush memory device of the second enclosing structure 20
Corresponding high 3V to the 4V of flush memory device of the first enclosing structure of pressure ratio 10, thus avoid in flash memory structure with the first enclosing structure 10 and
The corresponding storage position of second enclosing structure 20 interacts.
In some embodiments, the thickness of the second charge storage layer 22 is much larger than the thickness of the first charge storage layer 12, for example,
The thickness range of first charge storage layer 12 is 3nm~5nm, and the thickness range of second charge storage layer 22 is 48nm
~52nm.Furthermore, it is possible to which first grid layer 14 and second grid layer 24, which is arranged, has different doping types, for example, making first
Doped N-type impurity in grid layer 14, doped p-type impurity or the first grid layer 14 in second grid layer 24
It is adulterated using p-type, the second grid layer 24 then uses n-type doping.Under normal conditions, n-type doping polysilicon and p-type doping are more
Crystal silicon is different to the work function difference of silicon channel, so that two grids are different to the threshold voltage of channel.Therefore in the present embodiment,
Whether the second charge storage layer 22 in two enclosing structures 20 stores electronics to the corresponding storage position of the first enclosing structure 10 just
It is not influenced to the Id-Vg curve of reverse read, vice versa, i.e., whether the first charge storage layer 12 stores electronics and enclose to second
The Id-Vg curve that the Direct/Reverse of the corresponding storage position of grid structure 20 is read does not influence.
Further, the thickness example of each sedimentary is such as in first enclosing structure 10 and second enclosing structure 20
Under: in first enclosing structure 10: the first medium layer 11 with a thickness of 2~4nm；First charge storage layer 12
With a thickness of 3~5nm；The second dielectric layer 13 with a thickness of 5~7nm；The first grid layer 14 with a thickness of 80~
100nm.In second enclosing structure 20: the third dielectric layer 21 with a thickness of 2~4nm；Second charge storage layer 22
With a thickness of 48~52nm；4th dielectric layer 23 with a thickness of 5~7nm；The second grid layer 24 with a thickness of 80~
100nm。
The present invention devises the first enclosing structure 10 and the second enclosing structure 20 of semi-surrounding, using the separation layer 15 into
Row isolation, so that the electrical operation of the first enclosing structure 10 and the second enclosing structure 20 is independent.The material of separation layer 15 is, for example,
Silica, silicon oxynitride or other insulating materials.
In the embodiment of the present invention, the material of source area and drain region in substrate can be germanium silicon or silicon, the nano wire
The material of 40 (including channel region 30, source 41 and drain terminals 42) can be germanium silicon, in further embodiments, on nano wire 40
Channel region 30, source 41 and drain terminal 42 also may include different materials, for example, make the 40 germanium silicon of nano wire of channel region 30,
And respectively in substrate source area and the material of source 41 and drain terminal 42 that connect of drain region be germanium silicon or silicon.Preferably, institute
The Mole percent specific concentration for stating germanium in nano wire 40 is higher than the Mole percent specific concentration of germanium in the source area and the drain region,
So as to so that the hole mobility of channel region 30 improves, it can the efficiency for improving hole injection in flash memory erasing is improved and wiped
The speed removed.
The embodiment of the invention also provides the control methods of above-mentioned flash memory structure.The control method can be to the sudden strain of a muscle
Any of the four storage positions for depositing structure are controlled.Wherein, first charge storage layer 12 includes depositing described in two
Storage space, be located at first charge storage layer 12 close to the region (being defined as the first storage position 51) of the source 41 and
Close to the region (being defined as the second storage position 52) of the drain terminal 42, second charge storage layer 22 also includes two storages
Position is located at second charge storage layer 22 close to the region (being defined as third storage position 53) of the source 41 and institute
State the region (being defined as the 4th storage position 54) of drain terminal 42；The control method includes carrying out to a specified storage position
Programming operation, erasing operation or read operation, the specified storage position is corresponding with a grid layer in flash memory structure, described
Grid layer is in the first grid layer 14 and the second grid layer 24 close to one of the specified storage position.
Further, the control method includes programming operation, erasing operation and read operation.
Wherein, the programming operation includes: in the source 41 or the drain terminal 42 close to the specified storage position
The voltage for applying 4.5V~5.5V, the source 41 or the drain terminal 42 far from the specified storage position apply 0V voltage,
And apply the voltage of 6.5V~7.5V in the corresponding grid layer.Preferably, the physical mechanism of this programming operation can be ditch
The injection of road thermoelectron.
The case where applying voltage when being programmed to aforementioned four storage position example is as follows.First storage position 51 is compiled
Cheng Shi, Vg1 (voltage applied on first grid layer 14)=7V, Vs (i.e. the voltage of source 41)=5V, Vd (i.e. drain terminal 42
Voltage)=0V.When being programmed to the second storage position 52, Vg1 (voltage applied on first grid layer 14)=7V, Vd
(i.e. the voltage of drain terminal 42)=5V, Vs (i.e. the voltage of source 41)=0V.When being programmed to third storage position 53, Vg2 (exists
The voltage applied on second grid layer 24)=7V, Vs (i.e. the voltage of source 41)=5V, Vd (i.e. the voltage of drain terminal 42)=0V.
When being programmed to the 4th storage position 54, Vg2 (voltage applied on second grid layer 24)=7V, Vd (i.e. drain terminal 42
Voltage)=5V, Vs (i.e. the voltage of source 41)=0V.
The erasing operation includes: in the source 41 or the application of the drain terminal 42 close to the specified storage position
The voltage of 4.5V~5.5V, the source 41 or the application 0V voltage of the drain terminal 42 far from the specified storage position, and
The voltage of the corresponding grid layer application -4.5V~-5.5V.Preferably, the physical mechanism of this erasing operation can be band band
Tunneling enhanced hot idle injection.
The case where applying voltage when wiping aforementioned four storage position example is as follows.It is carried out when to the first storage position 51
When erasing, Vg1 (voltage applied on first grid layer 14)=- 5V, Vs (i.e. the voltage of source 41)=5V, Vd (leak
The voltage at end 42)=0V.When wiping the second storage position 52, Vg1 (voltage applied on first grid layer 14)
=-5V, Vd (i.e. the voltage of drain terminal 42)=5V, Vs (i.e. the voltage of source 41)=0V.It is wiped when to third storage position 53
When, Vg2 (voltage applied on second grid layer 24)=- 5V, Vs (i.e. the voltage of source 41)=5V, Vd (i.e. drain terminal 42
Voltage)=0V.When wiping the 4th storage position 54, Vg2 (voltage applied on second grid layer 24)=-
5V, Vd (i.e. the voltage of drain terminal 42)=5V, Vs (i.e. the voltage of source 41)=0V.
The read operation includes: in the source 41 or the application of the drain terminal 42 1V far from the specified storage position
The voltage of~1.5V, the source 41 or the drain terminal 42 close to the specified storage position apply 0V voltage, and scanning pair
The voltage for the grid layer answered judges described specified deposit to obtain a threshold voltage numerical value, according to the threshold voltage numerical value
The storage state of storage space.Wherein used principle is exactly, such as it is to be understood that the first storage position 51 either with or without there being electronics, can be with
Cause in its second storage of shielding position 52 in drain terminal 42 (being exactly that one end far from the first storage position 51) plus Vd positive electricity pressure energy
Influence of the electronics to threshold voltage numerical value.Because if having electronics in the second storage position 52, the presence of electronics can make channel region
30 increase close to the potential barrier of drain terminal 42, and after drain terminal 42 plus a positive voltage, 30 potential barrier of channel region close to drain terminal 42 reduces,
Thus the influence to channel barrier for having electronics in the second storage position 52 is removed.Source-drain current size and by solid in this way
The threshold voltage that constant current method obtains only determines that thus we can be accurate by whether having electronics in the first storage position 51
Read the information of the first storage position 51.
In the flash memory structure of the present embodiment, preferably first grid layer 14 is different with the doping type of second grid layer 24, and
And first enclosing structure 10 and the second enclosing structure 20 thickness it is different, therefore (i.e. first stores position 51 for superposed storage position
With the second storage position 52) read operation threshold voltage numerical value and storage position (the i.e. third storage position 53 and that is located at lower part
Four storage positions 54) read operation threshold voltage numerical value it is different, therefore can be by read operation to positioned at the first charge storage layer
Storage position be located at the storage position of the second charge storage layer by layer distinguished.Specifically, due to the first storage position 51 and second
Storage position 52 belongs to superposed first enclosing structure 10, then to their read operation when selection to first grid layer 14 plus
Grid voltage；Third storage position 53 and the 4th storage position 54 belong to the second enclosing structure 20 positioned at lower part, then grasp to their reading
Selection is to second grid layer 24 plus grid voltage when making.Due to storage position corresponding with the first enclosing structure 10 and the second enclosing structure 20
Read threshold voltage numerical value has difference, therefore distinguishes the storage location of top and the bottom with can be convenient, that is to say, that electricity
Son is stored in the first storage position 51 or the second storage position 52, is also stored in third storage position 53 or the 4th storage position 54, can be according to
The threshold voltage numerical value determined when by read operation by fixed current method distinguishes.
In one embodiment, it when being read to any of aforementioned four storage position, can be enclosed to described
The grid layer of grid structure carries out 0V~3V voltage scanning, can set the corresponding electric current of threshold voltage numerical value to be read as 1*
10-6A, when flush memory device drain terminal electric current reaches 1*10-6When A, then it can get a grid voltage numerical value, the grid voltage, that is, threshold value
Voltage, this obtains method, that is, fixed current method of threshold voltage.Then, by the threshold voltage numerical value and standard threshold voltage
It is compared, if threshold voltage numerical value obtained is smaller (being less than standard threshold voltage), can determine whether do not have in corresponding storage position
There is storage electronics；If threshold voltage numerical value obtained is larger (being greater than standard threshold voltage), corresponding storage position can determine whether
In stored electronics.
Further, the standard threshold voltage and described second of the storage position setting of first enclosing structure 10 encloses grid knot
The standard threshold voltage of the storage position setting of structure 20 differs 3V to 4V.Magnitude range about standard threshold voltage numerical value can root
It is set according to the performance of flash memory structure.Specifically, the standard threshold voltage of the storage position setting of first enclosing structure 10
It is that the mean value that 50 threshold voltage normal samples are at least tested in position 52 is stored to the first storage position 51 or second.Second encloses grid knot
The standard threshold voltage of the storage position setting of structure 20 is the threshold at least testing third storage position 53 or the 4th storage position 54 50 times
The mean value of threshold voltage normal sample.
The case where applying voltage when being read out to aforementioned four storage position example is as follows.It is read when to the first storage position 51
When, make Vd (i.e. the voltage of drain terminal 42)=1.2V, Vs (i.e. the voltage of source 41)=0, to Vg1 (i.e. on first grid layer 14
The voltage of application) 0V to 3V voltage scanning is carried out, in specified current flow (such as 1*10-6A in the case where), if obtained threshold value
Voltage value is smaller then to store electronics if obtained threshold voltage numerical value is larger without storage electronics.
When reading to the second storage position 52, make Vs (i.e. the voltage of source 41)=1.2V, Vd (i.e. the voltage of drain terminal 42)
=0,0V to 3V voltage scanning is carried out to Vg1 (voltage applied on first grid layer 14), in the case where specified current flow,
It is then stored without storage electronics if obtained threshold voltage numerical value is larger if obtained threshold voltage numerical value is smaller
Electronics.
When reading to third storage position 53, make Vd (i.e. the voltage of drain terminal 42)=1.2V, Vs (i.e. the voltage of source 41)
=0,0V to 3V voltage scanning is carried out to Vg2 (voltage applied on second grid layer 24), in the case where specified current flow,
It is then stored without storage electronics if obtained threshold voltage numerical value is larger if obtained threshold voltage numerical value is smaller
Electronics.
When reading to the 4th storage position 54, make Vs (i.e. the voltage of source 41)=1.2V, Vd (i.e. the voltage of drain terminal 42)
=0,0V to 3V voltage scanning is carried out to Vg2 (voltage applied on second grid layer 24), in the case where specified current flow,
It is then stored without storage electronics if obtained threshold voltage numerical value is larger if obtained threshold voltage numerical value is smaller
Electronics.
Further, due in the first grid layer 14 and the second grid layer 24 impurity type on the contrary,
One is n-type doping polysilicon gate, and one is p-type doped polysilicon gate.The work function difference of the two grid layers is different, simultaneously
The thickness of charge storage layer has very big gap in two enclosing structures, causes the threshold voltage of two enclosing structures different
Sample, the threshold voltage of the second enclosing structure 20 can than high 3V to the 4V of the first enclosing structure 10, still described first can be enabled to enclose
The level threshold value of the storage position setting of the standard threshold voltage and second enclosing structure 20 of the storage position setting of grid structure 10
Voltage phase difference 3V to 4V, to distinguish the threshold value of the storage position of the first enclosing structure 10 and the storage position reading of the second enclosing structure 20
Voltage value.
As it can be seen that can be realized when the flash memory structure to the embodiment of the present invention is controlled using aforementioned four storage position
Four storages.Wherein, storage position each in this way can be there are two types of state, and such as " 0 " represents the state for storing electronics, and " 1 " represents
The state of electronics is not stored, then total available 16 kinds of assembled states, are from " 0000 " to " 1111 " respectively, it can storage
The information of 4bit.
To sum up, in flash memory structure provided by the present invention, including nano wire formed on a substrate and first grid are enclosed
Structure and the second enclosing structure are provided with channel region and are located at institute along the radial direction of the nano wire on the nano wire
State the source and drain terminal of channel region two sides, the source and the drain terminal respectively in the substrate source area and drain region connect
It connects, along the radial direction perpendicular to the nano wire, first enclosing structure and second enclosing structure are mutually isolated simultaneously
Enclose the two sides for being set to the channel region.Above-mentioned first enclosing structure and second enclosing structure are in a manner of semi-surrounding
(the encirclement mode partially surrounded and have part to expose) is formed on nano wire, and mutually isolated (is independent in electrical property
), it, can be in the first charge storage layer and the second charge storage layer respectively close to institute when controlling the flash memory structure
It states the region of source and forms four storage positions close to the region of the drain terminal, so as to realize four storages.Four storages
Design can greatly improve memory capacity (such as sharing combinations of states in 16 from " 0000 " to " 1111 "), therefore utilize this hair
The flush memory device of bright flash memory structure can be mentioned in terms of memory capacity compared with the flush memory device of dibit and unit storage mode
It is high.Simultaneously in flash memory structure of the invention, on the nano wire of channel region design on substrate, thus the first enclosing structure and/or
Second enclosing structure to channel region have good static control ability, be conducive to resist encountered in device dimensions shrink it is short
The problem of channelling effect and gate leakage.
The control method of above-mentioned flash memory structure provided by the invention, can be specified to any one in above-mentioned flash memory structure
Storage position be programmed operation, erasing operation or read operation, be conducive to include the flush memory device of above-mentioned flash memory structure popularization
Using.
Illustrate to being given for example only property of above-described embodiment the principles and effects of invention, and is not intended to limit the present invention.Appoint
What person of ordinary skill in the field, without violating the spirit and scope of the present invention, can to the invention discloses technology
Scheme and technology contents make the variation such as any type of equivalent replacement or modification, and still fall within protection scope of the present invention.
Claims (14)
1. a kind of flash memory structure characterized by comprising
Nano wire formed on a substrate, along the extending direction of the nano wire, be provided on the nano wire channel region and
Source and drain terminal positioned at the channel region two sides, the source and the drain terminal respectively in the substrate source area and leakage
Polar region connection；And
First enclosing structure and the second enclosing structure, along the extending direction perpendicular to the nano wire, first enclosing structure
And enclosing mutually isolated with second enclosing structure is set to the two sides of the channel region.
2. flash memory structure as described in claim 1, which is characterized in that first enclosing structure includes along the nano wire
First medium layer, the first charge storage layer, second dielectric layer and the first grid layer that surface is sequentially overlapped, described second encloses grid
Structure include the third dielectric layer being sequentially overlapped along the surface of the nano wire, the second charge storage layer, the 4th dielectric layer and
Second grid layer, wherein the thickness of second charge storage layer be greater than first charge storage layer thickness, described first
The type of impurity is opposite in grid layer and the second grid layer.
3. flash memory structure as claimed in claim 2, which is characterized in that include p-type impurity, institute in the first grid layer
Stating includes n-type doping impurity in second grid layer.
4. flash memory structure as claimed in claim 2, which is characterized in that the thickness range of first charge storage layer is 3nm
~5nm, the thickness range of second charge storage layer are 48nm~52nm.
5. flash memory structure as claimed in claim 2, which is characterized in that the thickness of the first medium layer and the third dielectric layer
Degree range is 2nm~4nm, and the thickness range of the second dielectric layer and the 4th dielectric layer is 5nm~7nm, described first
The thickness range of grid layer and the second grid layer is 80nm~100nm.
6. flash memory structure as described in claim 1, which is characterized in that the wire range of the nano wire is 4nm~6nm, long
Degree range is 27nm~33nm.
7. flash memory structure as described in claim 1, which is characterized in that the material of the nano wire includes germanium silicon.
8. flash memory structure as claimed in claim 7, which is characterized in that the material of the source area and the drain region includes germanium
Silicon or silicon, also, the Mole percent specific concentration of germanium is higher than rubbing for germanium in the source area and the drain region in the nano wire
That percent concentration.
9. flash memory structure as described in claim 1, which is characterized in that the material of the charge storage layer includes silicon nitride, institute
It states source area and the drain region includes n-type doping impurity.
10. a kind of control method of flash memory structure as described in any one of claim 1 to 9, which is characterized in that the flash memory
Any of four storage positions of structure are controlled, wherein and first charge storage layer includes two storage positions,
First charge storage layer is located at close to the region of the source and close to the region of the drain terminal, second electricity
Lotus accumulation layer also includes two storage positions, is located at second charge storage layer close to the region of the source and described
The region of drain terminal；The control method includes being programmed operation, erasing operation or reading to a specified storage position
Operation, the specified storage position is corresponding with a grid layer, and the grid layer is the first grid layer and the second gate
Close to the grid layer of the specified storage position in the layer of pole.
11. control method as claimed in claim 10, which is characterized in that the programming operation includes:
In the voltage of the source or drain terminal application 4.5V~5.5V close to the specified storage position, far from the finger
The source of fixed storage position or the drain terminal apply 0V voltage, and apply 6.5V~7.5V's in the corresponding grid layer
Voltage.
12. control method as claimed in claim 10, which is characterized in that the erasing operation includes:
In the voltage of the source or drain terminal application 4.5V~5.5V close to the specified storage position, far from the finger
The source of fixed storage position or the drain terminal apply 0V voltage, and in the corresponding grid layer application -4.5V~-5.5V
Voltage.
13. control method as claimed in claim 10, which is characterized in that the read operation includes:
In the voltage of the source or drain terminal application 1V~1.5V far from the specified storage position, close to described specified
Storage position the source or the drain terminal apply 0V voltage, and scan the voltage of the corresponding grid layer to obtain a threshold
Threshold voltage numerical value judges the storage state of the specified storage position according to the threshold voltage numerical value.
14. control method as claimed in claim 13, which is characterized in that set the corresponding electric current of the threshold voltage numerical value as
1*10-6A carries out 0V~3V voltage scanning to the corresponding grid layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811134024.0A CN109309096B (en) | 2018-09-27 | 2018-09-27 | Flash memory structure and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811134024.0A CN109309096B (en) | 2018-09-27 | 2018-09-27 | Flash memory structure and control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109309096A true CN109309096A (en) | 2019-02-05 |
| CN109309096B CN109309096B (en) | 2020-11-13 |
Family
ID=65225189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811134024.0A Active CN109309096B (en) | 2018-09-27 | 2018-09-27 | Flash memory structure and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109309096B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070090413A1 (en) * | 2005-10-24 | 2007-04-26 | Hynix Semiconductor Inc. | Nonvolatile ferroelectric memory device and method thereof |
| WO2009011450A1 (en) * | 2007-07-17 | 2009-01-22 | Sharp Kabushiki Kaisha | Core-shell-shell nanowire transistor and fabrication method thereof |
| CN103854971A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of nanowires and manufacturing method of nanowire field effect transistors |
| CN104733045A (en) * | 2015-03-23 | 2015-06-24 | 上海华力微电子有限公司 | Double-bit flash memory, and programming, erasing and reading method thereof |
| CN105393357A (en) * | 2013-03-05 | 2016-03-09 | 桑迪士克3D有限责任公司 | 3D non-volatile memory having low-current cells and fabrication thereof |
| US20170263615A1 (en) * | 2016-03-09 | 2017-09-14 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
-
2018
- 2018-09-27 CN CN201811134024.0A patent/CN109309096B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070090413A1 (en) * | 2005-10-24 | 2007-04-26 | Hynix Semiconductor Inc. | Nonvolatile ferroelectric memory device and method thereof |
| WO2009011450A1 (en) * | 2007-07-17 | 2009-01-22 | Sharp Kabushiki Kaisha | Core-shell-shell nanowire transistor and fabrication method thereof |
| CN103854971A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of nanowires and manufacturing method of nanowire field effect transistors |
| CN105393357A (en) * | 2013-03-05 | 2016-03-09 | 桑迪士克3D有限责任公司 | 3D non-volatile memory having low-current cells and fabrication thereof |
| CN104733045A (en) * | 2015-03-23 | 2015-06-24 | 上海华力微电子有限公司 | Double-bit flash memory, and programming, erasing and reading method thereof |
| US20170263615A1 (en) * | 2016-03-09 | 2017-09-14 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109309096B (en) | 2020-11-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4810712B2 (en) | Nonvolatile semiconductor memory device and reading method thereof | |
| JP5149539B2 (en) | Semiconductor device | |
| CN101388396B (en) | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus | |
| US7319618B2 (en) | Low-k spacer structure for flash memory | |
| CN100477226C (en) | Multi bits flash memory device and method for operating the same | |
| CN100527442C (en) | Double-fin type channel double-grid multifunction field effect transistor and producing method thereof | |
| US20110044110A1 (en) | Semiconductor memory having both volatile and non-volatile functionality and method of operating | |
| CN101438351B (en) | For wiping method and the multi-level programming memory devices of memory devices | |
| US11765907B2 (en) | Ferroelectric memory device and operation method thereof | |
| CN100356570C (en) | Floating gate of flash memory cell and method for making same and a flash memory cell | |
| Venkatesan et al. | Overview of 3D NAND technologies and outlook invited paper | |
| CN101548331B (en) | Programmable CSONOS logic element | |
| US7813180B2 (en) | Non-volatile memory devices and methods of operating the same | |
| CN116264869A (en) | Low voltage flash memory integrated with vertical field effect transistor | |
| US20070045719A1 (en) | Multi-purpose semiconductor device | |
| CN103972238A (en) | Memory unit structure | |
| CN109309096A (en) | Flash memory structure and its control method | |
| CN105470258B (en) | SONOS B4-flash memory | |
| US20220351785A1 (en) | Access operations in capacitive sense nand memory | |
| KR20160009299A (en) | Bandgap-engineered memory with multiple charge trapping layers storing charge | |
| Lorenzini et al. | A dual gate flash EEPROM cell with two-bit storage capacity | |
| CN104112474A (en) | Storage unit of single polycrystalline nonvolatile storage | |
| Miyaji et al. | Scaling trends and tradeoffs between short channel effect and channel boosting characteristics in sub-20 nm bulk/silicon-on-insulator NAND flash memory | |
| CN104425226A (en) | Floating gate and forming method thereof, and flash memory unit and forming method thereof | |
| CN108257638B (en) | Programming method suitable for split gate flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |