US20150031186A1 - Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics - Google Patents
Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics Download PDFInfo
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- US20150031186A1 US20150031186A1 US14/510,302 US201414510302A US2015031186A1 US 20150031186 A1 US20150031186 A1 US 20150031186A1 US 201414510302 A US201414510302 A US 201414510302A US 2015031186 A1 US2015031186 A1 US 2015031186A1
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- dielectric layer
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- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 36
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Images
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
Definitions
- Embodiments relate to a semiconductor device having a dielectric layer with improved electrical characteristics and associated methods.
- a dielectric layer may be formed between an upper electrode and a lower electrode of a capacitor.
- Diverse research is being conducted into improving characteristics of a dielectric layer, e.g., increasing the dielectric constant, improving crystallinity, and/or reducing defects, to thereby improve electrical characteristics of resultant semiconductor devices.
- the crystallinity of the dielectric layer may be improved by, e.g., depositing the dielectric layer at a high temperature or heat-treating the dielectric layer after deposition.
- defects in the dielectric layer may be removed by, e.g., oxygen curing after the dielectric layer is formed.
- Embodiments are directed to a semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, which substantially overcome one or more of the drawbacks, limitations, and/or disadvantages of the related art.
- a semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate, and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
- the insertion layer may be disposed between the dielectric layer and the lower metal layer.
- the insertion layer may be disposed between the dielectric layer and the upper metal layer.
- the insertion layer may be disposed between the dielectric layer and the lower metal layer and between the dielectric layer and the upper metal layer.
- the metal oxide film and the metallic material film may each independently include at least one of Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and Ac.
- the metal oxide film may be in the form of MO x , wherein M is a metal, O is oxygen, and x is about 0.5 to about 4.
- a metal used to form the metallic material film of the insertion layer may be the same as a metal used to form the metal oxide film of the dielectric layer.
- the metallic material film of the insertion layer may be a metal oxide film.
- the metallic material film of the insertion layer may be a metal nitride film.
- At least one of the above and other features and advantages may also be realized by providing a method of fabricating a semiconductor device including sequentially forming a lower metal layer, a dielectric layer, and an upper metal layer on a semiconductor substrate, and forming an insertion layer between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer is formed of a metal oxide film and the insertion layer is formed of a metallic material film.
- the forming the insertion layer may include forming the insertion layer between the dielectric layer and the lower metal layer.
- the forming the insertion layer may include forming the insertion layer between the dielectric layer and the upper metal layer.
- the forming the insertion layer may include forming the insertion layer between the dielectric layer and the lower metal layer and between the dielectric layer and the upper metal layer.
- the forming the insertion layer may include forming an insertion material layer on the lower metal layer, and converting the insertion material layer to the insertion layer while the dielectric layer is formed on the insertion material layer.
- the insertion material layer may include a metal film, a metal carbide film, or a metal nitride film.
- the insertion material layer may include a metal film, a metal carbide film, or a metal nitride film.
- FIG. 1 illustrates a cross-sectional view of a semiconductor device according to a first embodiment
- FIG. 2 illustrates a cross-sectional view of a semiconductor device according to a second embodiment
- FIG. 3 illustrates a cross-sectional view of a semiconductor device according to a third embodiment
- FIGS. 4 and 5 illustrate cross-sectional views of a semiconductor device according to a first comparative embodiment
- FIGS. 6 and 7 illustrate cross-sectional views of the semiconductor device according to the first embodiment
- FIGS. 8 and 9 illustrate views of the semiconductor device according to the first comparative embodiment
- FIGS. 10 and 11 illustrate views of the semiconductor device according to the first embodiment
- FIGS. 12 and 13 illustrate cross-sectional views of a semiconductor device according to a second comparative embodiment
- FIGS. 14 and 15 illustrate cross-sectional views of the semiconductor device according to the second embodiment
- FIG. 16 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first comparative embodiment
- FIG. 17 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first embodiment
- FIG. 18 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second comparative embodiment
- FIG. 19 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second embodiment
- FIG. 20 illustrates a circuit diagram of a unit cell of a dynamic random access memory (DRAM) device including a transistor, according to an embodiment
- FIG. 21 illustrates a plan view of a memory module using a DRAM chip, according to an embodiment
- FIG. 22 illustrates a block diagram of an electronic system using a DRAM chip, according to an embodiment.
- a semiconductor device may be fabricated by forming an insertion layer in a first position between a lower metal layer and a dielectric layer, a second position between the dielectric layer and an upper metal layer, or in both of the first and second positions.
- the first position may be an interface between the lower metal layer and the dielectric layer.
- the second position may be an interface between the dielectric layer and the upper metal layer.
- the lower metal layer may include, e.g., a metal nitride film.
- the dielectric layer may include, e.g., a metal oxide film.
- the insertion layer may include, e.g., a metallic material film.
- the insertion layer is formed between the lower metal layer and the dielectric layer, i.e., in the first position, formation of an undesirable interface layer due to oxidation of the lower metal layer during formation of the dielectric layer may be inhibited.
- the insertion layer may function as a seed layer during formation of the dielectric layer to, e.g., improve characteristics of the dielectric layer. If the insertion layer is formed between the dielectric layer and the upper metal layer, i.e., in the second position, the formation of an undesirable interface layer on the dielectric layer may be inhibited. Thus, the dielectric layer may not be damaged, thereby improving characteristics of the dielectric layer.
- FIG. 1 illustrates a cross-sectional view of a semiconductor device 200 according to the first embodiment.
- the semiconductor device 200 according to the first embodiment may include a lower structure, e.g., an insulating layer 12 , on a semiconductor substrate 10 .
- a material layer or a transistor may be formed on the semiconductor substrate 10 .
- a lower metal layer 14 may be formed on the semiconductor substrate 10 or on the insulating layer 12 .
- the lower metal layer 14 may include, e.g., a metal nitride film.
- the metal nitride film may include, e.g., a titanium nitride (TiN) film, a niobium nitride (NbN) film, or a tantalum nitride (TaN) film.
- TiN titanium nitride
- NbN niobium nitride
- TaN tantalum nitride
- a first insertion layer 16 a and a dielectric layer 18 may be formed sequentially on the lower metal layer 14 in the order stated.
- the first insertion layer 16 a may be formed in the first position between the lower metal layer 14 and the dielectric layer 18 .
- the first insertion layer 16 a may improve electrical characteristics of the dielectric layer 18 , advantageously reducing leakage current.
- the dielectric layer 18 may include, e.g., a metal oxide film.
- a metal M used to form the metal oxide film of the dielectric layer 18 may include, e.g., Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and/or Ac.
- the dielectric layer 18 may include, e.g., a single film including the metal M or multiple films including at least two films.
- the dielectric layer 18 may include the metal M in the form of MO x , wherein O is oxygen and x is about 0.5 to about 4.
- the dielectric layer 18 may include, e.g., a zirconium oxide (ZrO 2 ) film.
- the first insertion layer 16 a may include, e.g., a metallic material film.
- the metallic material film of the first insertion layer 16 a may include, e.g., a metal oxide film or a metal nitride film.
- the metal M used to form the metallic material film of the first insertion layer 16 a may be the same as the metal M used to form the metal oxide film of the dielectric layer 18 .
- the metal M used to form the metallic material film of the insertion layer 16 a may be different from the metal M used to form the metal oxide film of the dielectric layer 18 .
- the metal M used to form the metallic material film of the first insertion layer 16 a is the same as the metal M used to form the metal oxide film of the dielectric layer 18 , characteristics of the interface between the lower metal layer 14 and the dielectric layer 18 may be improved.
- the dielectric layer 18 may have excellent characteristics, improving electrical characteristics of the dielectric layer 18 .
- the first insertion layer 16 a may include, e.g., a ZrO 2 film. If the first insertion layer 16 a includes zirconium, and the dielectric layer 18 includes a ZrO 2 film, characteristics of the dielectric layer 18 may be improved, thereby improving electrical characteristics of the dielectric layer 18 .
- An upper metal layer 20 may be formed on the dielectric layer 18 .
- the upper metal layer 20 may be formed of the same material used to form the lower metal layer 14 .
- the semiconductor device 200 according to the first embodiment may include the lower metal layer 14 , the dielectric layer 18 , and the upper metal layer 20 , which may be sequentially formed on the semiconductor substrate 10 in the order stated.
- the first insertion layer 16 a may be formed in the first position between the lower metal layer 14 and the dielectric layer 18 .
- the dielectric layer 18 may include, e.g., a metal oxide film, and the first insertion layer 16 a may include, e.g., a metallic material film.
- the dielectric layer 18 of the semiconductor device 200 according to the first embodiment may have excellent electrical characteristics, thereby reducing leakage current.
- the semiconductor device 200 may include a capacitor including the lower metal layer 14 , the first insertion layer 16 a , the dielectric layer 18 , and the upper metal layer 20 .
- the capacitor may be used in various integrated circuit semiconductor devices, e.g., dynamic random access memory (DRAM) devices.
- DRAM dynamic random access memory
- FIG. 2 illustrates a cross-sectional view of a semiconductor device 220 fabricated according to the second embodiment.
- the semiconductor device 220 according to the second embodiment may be the same as the semiconductor device 200 according to the first embodiment, except that a second insertion layer 16 b may be formed between the upper metal layer 20 and the dielectric layer 18 , rather than forming the first insertion layer 16 a between the lower metal layer 14 and the dielectric layer 18 .
- the lower metal layer 14 may be formed on a semiconductor substrate 10 or on a insulating layer 12 .
- the lower metal layer 14 may include a metal nitride film, e.g., a TiN film, a NbN film, or a TaN film, as described above with reference to the first embodiment.
- the dielectric layer 18 may be formed on the lower metal layer 14 .
- the dielectric layer 18 may include a metal oxide film, as described above with reference to the first embodiment.
- the metal M used to form the metal oxide film of the dielectric layer 18 may be the same as the metal M described above with reference to the first embodiment.
- the dielectric layer 18 may include a metal oxide in the form of MO x , where M is the metal, O is oxygen, and x is about 0.5 to about 4.
- the dielectric layer 18 may include, e.g., a ZrO 2 film.
- the second insertion layer 16 b may be formed on the dielectric layer 18 .
- the second insertion layer 16 b may improve electrical characteristics of the dielectric layer 18 , thereby reducing leakage current.
- the second insertion layer 16 b may be formed of the same material used to form the first insertion layer 16 a of the first embodiment. That is, the second insertion layer 16 b may include, e.g., a metallic material film.
- the metallic material film of the second insertion layer 16 b may include, e.g., a metal oxide film or a metal nitride film.
- the metal M used to form the metallic material film of the second insertion layer 16 b may also be different from the metal used to form the metal oxide film of the dielectric layer 18 .
- the second insertion layer 16 b may include, e.g., a zirconium nitride (ZrN) film.
- the upper metal layer 20 may be formed on the second insertion layer 16 b .
- the upper metal layer 20 may be formed of the same material used to form the lower metal layer 14 .
- the semiconductor device 220 according to the second embodiment may include the second insertion layer 16 b formed in the second position between the dielectric layer 18 and the upper metal layer 20 .
- the dielectric layer 18 of the semiconductor device 220 according to the second embodiment may have improved electrical characteristics, thereby reducing leakage current.
- the semiconductor device 220 may include a capacitor including, e.g., the lower metal layer 14 , the dielectric layer 18 , the second insertion layer 16 b , and the upper metal layer 20 .
- the capacitor may be used in various integrated circuit semiconductor devices, e.g., DRAM devices.
- the lower metal layer 14 may be formed on the semiconductor substrate 10 or on the insulating layer 12 .
- the lower metal layer 14 may include a metal nitride film, e.g., a TiN film, a NbN film, or a TaN film, as described above with respect to the first and second embodiments.
- the first insertion layer 16 a may be formed on the lower metal layer 14 and the dielectric layer 18 may be formed on the first insertion layer 16 a .
- the first insertion layer 16 a may be the same as the insertion layer 16 a of the first embodiment.
- the dielectric layer 18 may include a metal oxide film, as described in the first and second embodiments.
- the metal M used to form the metal oxide film of the dielectric layer 18 may be the same as the metal M described with respect to the first and second embodiments.
- the dielectric layer 18 may include the metal oxide in the form of MO x , where M is the metal, O is oxygen, and x is about 0.5 to 4.
- the dielectric layer 18 may include, e.g., a ZrO 2 film.
- the first insertion layer 16 a may include a metallic material film.
- the metallic material film of the first insertion layer 16 a may include, e.g., a metal oxide film or a metal nitride film.
- the metal M used to form the metallic material film of the first insertion layer 16 a may be the same as or different from the metal M used to form the metal oxide film of the dielectric layer 18 .
- the first insertion layer 16 a may include, e.g., a ZrO 2 film. The first insertion layer 16 a may improve electrical characteristics of the dielectric layer 18 , thereby reducing leakage current.
- the second insertion layer 16 b and the upper metal layer 20 may be formed sequentially on the dielectric layer 18 in the order stated.
- the second insertion layer 16 b may be formed of the same material used to form the second insertion layer 16 b according to the second embodiment.
- the second insertion layer 16 b may improve electrical characteristics of the dielectric layer 18 , thereby reducing leakage current.
- the upper metal layer 20 may be formed of the same material used to form the lower metal layer 14 .
- the first insertion layer 16 a may be formed in the first position between the lower metal layer 14 and the dielectric layer 18 .
- the second insertion layer 16 b may be formed in the second position between the dielectric layer 18 and the upper metal layer 20 .
- the dielectric layer 18 of the semiconductor device 240 according to the third embodiment may have improved electrical characteristic, thereby reducing leakage current.
- the semiconductor device 240 may include a capacitor including the lower metal layer 14 , the first insertion layer 16 a , the dielectric layer 18 , the second insertion layer 16 b , and the upper metal layer 20 .
- the capacitor may be used in various integrated circuit semiconductor devices, e.g., DRAM devices.
- characteristics of the dielectric layer 18 of the semiconductor device 200 according to the first embodiment, in which the insertion layer 16 a may be formed between the lower metal layer 14 and the dielectric layer 18 will be compared with characteristics of the dielectric layer 18 of a semiconductor device according to the first comparative embodiment.
- the dielectric layer 18 may be formed directly on the lower metal layer 14 .
- a TiN film may be used as the lower metal layer 14
- a ZrO 2 film may be used as the insertion layer 16 a
- a ZrO 2 film may be used as the dielectric layer 18 .
- a TiN film may be used as the lower metal layer 14 and a ZrO 2 film may be used as the dielectric layer 18 .
- FIGS. 4 and 5 illustrate cross-sectional views of a semiconductor device according to the first comparative embodiment for comparison with the semiconductor device 200 according to the first embodiment.
- FIGS. 6 and 7 illustrate cross-sectional views of the semiconductor device 200 according to the first embodiment for comparison with the semiconductor device according to the first comparative embodiment.
- a dielectric layer 18 e.g., a ZrO 2 film
- a lower metal layer 14 e.g., a TiN film.
- the lower metal layer 14 may be oxidized by an ozone (O 3 ) oxidant, used to form the dielectric layer 18 , to form an interface layer 30 , e.g., a TiO x layer or a TiON layer, on the lower metal layer 14 .
- O 3 ozone
- the TiO x layer may have many defects, and the TiON layer may have a low bandgap, e.g., about 2.1 eV, electrical characteristics of the dielectric layer 18 may deteriorate.
- a first insertion material layer 15 a may first be formed on the lower metal layer 14 to fabricate the semiconductor device 200 .
- the first insertion material layer 15 a may be formed using, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
- the first insertion material layer 15 a may, e.g., a metal film, a metal carbide film, or a metal nitride film.
- the metal film may include, e.g., a zirconium film.
- the metal carbide film may include, e.g., a zirconium carbide (ZrC x ) film.
- the metal nitride film may include, e.g., a ZrN film.
- the dielectric layer 18 e.g., a ZrO 2 film, may be formed on the insertion material layer 15 a.
- the first insertion material layer 15 a may be converted to the first insertion layer 16 a , e.g., a ZrO 2 film, by an O 3 oxidant used during formation of the dielectric layer 18 .
- the undesirable interface layer 30 of the first comparative embodiment may be avoided.
- the first insertion material layer 15 a includes a metal nitride film or a metal carbide film
- the first insertion material layer 15 a may be converted to a metal oxide film, a metal nitride film, or a metal oxide nitride film by the O 3 oxidant.
- the first insertion material layer 15 a may be preferentially oxidized by the O 3 oxidant.
- the O 3 oxidant due to insufficient amount of free O 3 oxidant, undesirable formation of the interface layer 30 may be prevented.
- high activation energy may be required for the TiN film of the lower metal layer 14 to be oxidized to TiO x film or TiON film as described above with respect to the first comparative embodiment.
- the zirconium film of the first insertion material layer 15 a since low activation energy may be required for the zirconium film of the first insertion material layer 15 a to be converted to ZrO 2 film, the zirconium film may be preferentially oxidized by the O 3 gas, thereby preventing oxidation of the TiN film of the lower metal layer 14 .
- the first insertion material layer 15 a of the semiconductor device 200 according to the first embodiment may be oxidized, i.e., converted, to the first insertion layer 16 a .
- the metal oxide film, i.e., the ZrO 2 film of the dielectric layer 18 , and the metallic material film, i.e., the ZrO 2 film of the insertion layer 16 a are the same, a complete interface layer may be formed. Accordingly, characteristics of the dielectric layer 18 may be improved.
- FIGS. 8 and 9 illustrate cross-sectional views of a semiconductor device according to the first comparative embodiment for comparison with the semiconductor device 200 according to the first embodiment.
- FIGS. 10 and 11 illustrate cross-sectional views of the semiconductor device 200 according to the first embodiment for comparison with the semiconductor device according to the first comparative embodiment.
- the dielectric layer 18 e.g., a ZrO 2 film
- the dielectric layer 18 may be formed on the lower metal layer 14 , e.g., a TiN film.
- a lattice constant of the ZrO 2 film of the dielectric layer 18 may be about 5.09 ⁇ .
- a lattice constant of the TiN film of the lower metal layer 14 may be about 4.32 ⁇ , thereby exhibiting a large lattice constant difference between the dielectric layer 18 and the lower metal layer 14 .
- a crystal structure of the ZrO 2 film of the dielectric layer 18 may be different from the crystal structure of the TiN film of the lower metal layer 14 .
- a seed layer 32 may have low density and non-uniform grain size during an initial stage of deposition of the ZrO 2 film of the dielectric layer 18 . That is, as illustrated in FIG. 8 , the seed layer 32 having low density and non-uniform grain size may be formed on the lower metal layer 14 during the initial stage of deposition of the ZrO 2 film of the dielectric layer 18 .
- the upper diagram illustrates a plan view; and the lower diagram illustrates a cross-sectional view.
- the ZrO 2 film growing from the seed layer may have grains 34 with a non-uniform size; and grain boundaries formed by the grown grains 34 may not be densely formed.
- the seed layer 32 may not be densely formed on the lower metal layer 14 during the initial stage of deposition of the dielectric layer 18 , the size of the grains 34 may increase; and voids may exist in the grain boundaries.
- the dielectric layer 18 according to the first comparative embodiment may have poor characteristics. Accordingly, electrical characteristics of the dielectric layer 18 may deteriorate during operation of the semiconductor device.
- the first insertion material layer 15 a may be formed on the lower metal layer 14 in the semiconductor device 200 according to the first embodiment.
- the first insertion material layer 15 a may include a zirconium film as described with reference to FIG. 6 .
- the dielectric layer 18 e.g., a ZrO 2 film, may be formed on the first insertion material layer 15 a , converting the first insertion material layer 15 a to the first insertion layer 16 a as described with reference to FIG. 6 .
- the first insertion material layer 15 a e.g., the zirconium film
- the seed layer 36 may have high density and uniform size.
- the upper diagram illustrates a cross-sectional view; and the lower diagram illustrates a plan view.
- the ZrO 2 film growing from the seed layer may have grains 38 with a uniform and relatively small size; and grain boundaries formed by the grown grains 38 may be densely formed.
- the dielectric layer 18 is not limited to the TiN film and the ZrO 2 film, and most suitable metal nitride films and metal oxide film may be used.
- the method according to an embodiment may also be used when, e.g., a hafnium oxide (HfO 2 ) film is formed on a TiN film or a ZrO 2 film is formed on a TaN film.
- HfO 2 hafnium oxide
- characteristics of the dielectric layer 18 of the semiconductor device 220 according to the second embodiment, in which the second insertion layer 16 b may be formed between the upper metal layer 20 and the dielectric layer 18 will be compared with characteristics of the dielectric layer 18 of a semiconductor device according to the second comparative embodiment, in which the upper metal layer 20 may be formed directly on the dielectric layer 18 .
- a TiN film may be used as the upper metal layer 20
- a ZrO 2 film may be used as the second insertion layer 16 b
- a ZrO 2 film may be used as the dielectric layer 18 .
- a TiN film may be used as the upper metal layer 20
- a ZrO 2 film may be used as the dielectric layer 18
- FIGS. 12 and 13 illustrate cross-sectional views of the semiconductor device according to the second comparative embodiment for comparison with the semiconductor device 220 according to the second embodiment.
- FIGS. 14 and 15 illustrate cross-sectional views of the semiconductor device 220 according to the second embodiment for comparison with the semiconductor device according to the second comparative embodiment.
- an upper metal layer 20 e.g., a TiN film
- a dielectric layer 18 e.g., a ZrO 2 film
- an interface layer 30 a e.g., a ZrON film, a TiO x film, and a TiON film
- NH 3 ammonia
- the ZrON film may deteriorate interface characteristics with the upper metal layer 20 , the TiO x film may have many defects, and the TiON film may have a low bandgap of, e.g., about 2.1 eV. As a result, the interface layer 30 a may deteriorate electrical characteristics of the dielectric layer 18 .
- a second insertion material layer 15 b may be formed on the dielectric layer 18 to form the semiconductor device 220 according to the second embodiment.
- the second insertion material layer 15 b may be formed using, e.g., CVD, PVD, or ALD.
- the second insertion material layer 15 b may include, e.g., a metal film, a metal carbide film, or a metal nitride film.
- the metal film may include, e.g., a zirconium film.
- the metal carbide film may include, e.g., a zirconium carbide (ZrC x ) film.
- the metal nitride film may include, e.g., a ZrN film.
- An upper metal layer 20 may be formed on the second insertion material layer 15 b.
- the second insertion material layer 15 b may be converted to the second insertion layer 16 b , e.g., the ZrN film, by the NH 3 nitrating agent used during formation of the upper metal layer 20 .
- the second insertion layer 16 b may function as the upper metal layer 20 without adversely influencing the dielectric layer 18 , unlike in the second comparative embodiment. Since the dielectric layer 18 of the semiconductor device 220 according to the second embodiment may not be damaged while the upper metal layer 20 is formed, the interface between the dielectric layer 18 and the upper metal layer 20 may have excellent characteristics when compared with the second comparative embodiment. Thus, the dielectric layer 18 may have excellent electrical characteristics.
- FIG. 16 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first comparative embodiment.
- FIG. 17 illustrates a graph showing voltage and leakage current of the semiconductor device 200 according to the first embodiment.
- FIG. 16 illustrates a graph showing positive voltage and leakage current of a capacitor fabricated by forming a TiN film lower metal layer 14 on a semiconductor substrate 10 , forming a ZrO 2 film dielectric layer 18 on the lower metal layer 14 to a thickness of 70 ⁇ , and forming an upper metal layer 20 on the dielectric layer 18 .
- a reference leakage current is 10 ⁇ 7 ⁇ /cm 2 at 1 V
- characteristics of the dielectric layer 18 may be damaged after voltages ranging from 0 V to 3.3 V are applied 16 times to the dielectric layer 18 , and thus a low leakage current is not restored.
- FIG. 18 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second comparative embodiment.
- FIG. 19 illustrates a graph showing voltage and leakage current of the semiconductor device 220 according to the second embodiment.
- FIG. 18 illustrates a graph showing negative voltage and leakage current of a capacitor fabricated by forming a TiN film lower metal layer 14 on a semiconductor substrate 10 , forming a ZrO 2 film dielectric layer 18 on the lower metal layer 14 to a thickness of 70 ⁇ , and forming an upper metal layer 20 directly on the dielectric layer 18 .
- a reference leakage current is 10 ⁇ 7 ⁇ /cm 2 at ⁇ 1 V
- characteristics of the dielectric layer 18 are damaged after voltages ranging from 0 V to ⁇ 3.8 V are applied 25 times, and thus a low leakage current is not restored.
- FIG. 19 illustrates a graph showing negative voltage and leakage current of a capacitor fabricated by forming a TiN film lower metal layer 14 on a semiconductor substrate 10 , forming a ZrO 2 film dielectric layer 18 on the lower metal layer 14 to a thickness of 70 ⁇ , forming a ZrO 2 film second insertion layer 16 b on the dielectric layer 18 to a thickness of 10 ⁇ , and forming an upper metal layer 20 on the second insertion layer 16 b as in the second embodiment.
- a unit cell of a DRAM device may have various shapes.
- the unit cell according to an embodiment may include a transistor 110 and a capacitor 130 .
- the transistor 110 may be connected to a word line 170 .
- a bit line 150 may be connected to a source/drain region of the transistor 110 .
- the capacitor 130 according to Embodiments 1 to 3 described above may be connected to another source/drain region of the transistor 110 . That is, the capacitor fabricated according to Embodiments 1 to 3 may be applied to a DRAM device.
- the DRAM chips 50 to 58 may be fabricated by respectively packaging the semiconductor devices according to an embodiment.
- the DRAM chips 50 to 58 may be applied to the memory module 500 .
- the DRAM chips 50 to 58 may be attached to a module substrate 501 .
- the memory module 500 may include connectors 502 which may be inserted into sockets of a motherboard, at an end of the module substrate 501 and ceramic decoupling capacitors 59 on the module substrate 501 .
- the memory module 500 is not limited to the shape shown in FIG. 21 and thus may have various shapes.
- a semiconductor device may be fabricated by forming an insertion layer between a lower metal layer and a dielectric layer.
- the insertion layer is formed between the lower metal layer and the dielectric layer, the formation of an interface caused by the oxidation of the lower metal layer during the formation of the dielectric layer may be prevented.
- characteristics of the dielectric layer may be improved, since the insertion layer may function as a seed layer for the formation of the dielectric layer.
- the semiconductor device according to an embodiment may be fabricated by forming an insertion layer between the dielectric layer and an upper metal layer.
- an interface layer may not be formed on the dielectric layer, and the dielectric layer may not be damaged.
- characteristics of the dielectric layer of the semiconductor device including its electrical characteristics, may be improved.
- the dielectric layer is formed at a high temperature, the high temperature may adversely affect the resultant semiconductor devices. Additionally, if heat-treatment or the oxygen curing is performed after deposition of the dielectric layer, a plurality of interface layers may be formed on a lower film under the dielectric layer. The interface layers may deteriorate electrical characteristics of the dielectric layer during the operation of the semiconductor devices, thereby increasing undesirable leakage current.
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Abstract
A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
Description
- This is a continuation application based on pending application Ser. No. 13/424,825, filed Mar. 20, 2012, which in turn is a division of application Ser. No. 12/585,030, filed Sep. 1, 2009, abandoned; the entire contents of both is hereby incorporated by reference.
- 1. Field
- Embodiments relate to a semiconductor device having a dielectric layer with improved electrical characteristics and associated methods.
- 2. Description of the Related Art
- Various dielectric layers may be used during fabrication of semiconductor devices. A dielectric layer may be formed between an upper electrode and a lower electrode of a capacitor. Diverse research is being conducted into improving characteristics of a dielectric layer, e.g., increasing the dielectric constant, improving crystallinity, and/or reducing defects, to thereby improve electrical characteristics of resultant semiconductor devices.
- The crystallinity of the dielectric layer may be improved by, e.g., depositing the dielectric layer at a high temperature or heat-treating the dielectric layer after deposition. In addition, defects in the dielectric layer may be removed by, e.g., oxygen curing after the dielectric layer is formed.
- Embodiments are directed to a semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, which substantially overcome one or more of the drawbacks, limitations, and/or disadvantages of the related art.
- It is a feature of an embodiment to provide a semiconductor device having a dielectric layer with improved electrical characteristics.
- It is another feature of an embodiment to provide a semiconductor device that reduces a leakage current.
- At least one of the above and other features and advantages may be realized by providing a semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate, and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
- The insertion layer may be disposed between the dielectric layer and the lower metal layer.
- The insertion layer may be disposed between the dielectric layer and the upper metal layer.
- The insertion layer may be disposed between the dielectric layer and the lower metal layer and between the dielectric layer and the upper metal layer.
- The metal oxide film and the metallic material film may each independently include at least one of Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and Ac.
- The metal oxide film may be in the form of MOx, wherein M is a metal, O is oxygen, and x is about 0.5 to about 4.
- A metal used to form the metallic material film of the insertion layer may be the same as a metal used to form the metal oxide film of the dielectric layer.
- The metallic material film of the insertion layer may be a metal oxide film.
- The metallic material film of the insertion layer may be a metal nitride film.
- At least one of the above and other features and advantages may also be realized by providing a method of fabricating a semiconductor device including sequentially forming a lower metal layer, a dielectric layer, and an upper metal layer on a semiconductor substrate, and forming an insertion layer between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer is formed of a metal oxide film and the insertion layer is formed of a metallic material film.
- The forming the insertion layer may include forming the insertion layer between the dielectric layer and the lower metal layer.
- The forming the insertion layer may include forming the insertion layer between the dielectric layer and the upper metal layer.
- The forming the insertion layer may include forming the insertion layer between the dielectric layer and the lower metal layer and between the dielectric layer and the upper metal layer.
- The forming the insertion layer may include forming an insertion material layer on the lower metal layer, and converting the insertion material layer to the insertion layer while the dielectric layer is formed on the insertion material layer.
- The insertion material layer may include a metal film, a metal carbide film, or a metal nitride film.
- At least one of the above and other features and advantages may also be realized by providing a method of fabricating a semiconductor device including forming a lower metal layer on a semiconductor substrate, forming a dielectric layer on the lower metal layer using a metal oxide film, forming an insertion material layer on the dielectric layer, and forming an upper metal layer on the insertion material layer, wherein forming the upper metal layer includes converting the insertion material layer to an insertion layer.
- The insertion material layer may include a metal film, a metal carbide film, or a metal nitride film.
- The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
-
FIG. 1 illustrates a cross-sectional view of a semiconductor device according to a first embodiment; -
FIG. 2 illustrates a cross-sectional view of a semiconductor device according to a second embodiment; -
FIG. 3 illustrates a cross-sectional view of a semiconductor device according to a third embodiment; -
FIGS. 4 and 5 illustrate cross-sectional views of a semiconductor device according to a first comparative embodiment; -
FIGS. 6 and 7 illustrate cross-sectional views of the semiconductor device according to the first embodiment; -
FIGS. 8 and 9 illustrate views of the semiconductor device according to the first comparative embodiment; -
FIGS. 10 and 11 illustrate views of the semiconductor device according to the first embodiment; -
FIGS. 12 and 13 illustrate cross-sectional views of a semiconductor device according to a second comparative embodiment; -
FIGS. 14 and 15 illustrate cross-sectional views of the semiconductor device according to the second embodiment; -
FIG. 16 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first comparative embodiment; -
FIG. 17 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first embodiment; -
FIG. 18 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second comparative embodiment; -
FIG. 19 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second embodiment; -
FIG. 20 illustrates a circuit diagram of a unit cell of a dynamic random access memory (DRAM) device including a transistor, according to an embodiment; -
FIG. 21 illustrates a plan view of a memory module using a DRAM chip, according to an embodiment; and -
FIG. 22 illustrates a block diagram of an electronic system using a DRAM chip, according to an embodiment. - Korean Patent Application No. 10-2009-0009875, filed on Feb. 6, 2009, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device for Improving Electrical Characteristics of Dielectric Layer and Method of Fabricating the Same,” is incorporated by reference herein in its entirety.
- Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.
- In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
- A semiconductor device according to an embodiment may be fabricated by forming an insertion layer in a first position between a lower metal layer and a dielectric layer, a second position between the dielectric layer and an upper metal layer, or in both of the first and second positions. The first position may be an interface between the lower metal layer and the dielectric layer. The second position may be an interface between the dielectric layer and the upper metal layer.
- The lower metal layer may include, e.g., a metal nitride film. The dielectric layer may include, e.g., a metal oxide film. The insertion layer may include, e.g., a metallic material film.
- If the insertion layer is formed between the lower metal layer and the dielectric layer, i.e., in the first position, formation of an undesirable interface layer due to oxidation of the lower metal layer during formation of the dielectric layer may be inhibited. In addition, the insertion layer may function as a seed layer during formation of the dielectric layer to, e.g., improve characteristics of the dielectric layer. If the insertion layer is formed between the dielectric layer and the upper metal layer, i.e., in the second position, the formation of an undesirable interface layer on the dielectric layer may be inhibited. Thus, the dielectric layer may not be damaged, thereby improving characteristics of the dielectric layer. The semiconductor device and a method of fabricating the semiconductor device will be described with reference to the accompanying drawings, in which exemplary embodiments are shown.
-
FIG. 1 illustrates a cross-sectional view of asemiconductor device 200 according to the first embodiment. Thesemiconductor device 200 according to the first embodiment may include a lower structure, e.g., an insulatinglayer 12, on asemiconductor substrate 10. Instead of the insulatinglayer 12, a material layer or a transistor may be formed on thesemiconductor substrate 10. Alower metal layer 14 may be formed on thesemiconductor substrate 10 or on the insulatinglayer 12. Thelower metal layer 14 may include, e.g., a metal nitride film. The metal nitride film may include, e.g., a titanium nitride (TiN) film, a niobium nitride (NbN) film, or a tantalum nitride (TaN) film. - A
first insertion layer 16 a and adielectric layer 18 may be formed sequentially on thelower metal layer 14 in the order stated. Thefirst insertion layer 16 a may be formed in the first position between thelower metal layer 14 and thedielectric layer 18. Thefirst insertion layer 16 a may improve electrical characteristics of thedielectric layer 18, advantageously reducing leakage current. - The
dielectric layer 18 may include, e.g., a metal oxide film. A metal M used to form the metal oxide film of thedielectric layer 18 may include, e.g., Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and/or Ac. Thedielectric layer 18 may include, e.g., a single film including the metal M or multiple films including at least two films. Thedielectric layer 18 may include the metal M in the form of MOx, wherein O is oxygen and x is about 0.5 to about 4. Thedielectric layer 18 may include, e.g., a zirconium oxide (ZrO2) film. - The
first insertion layer 16 a may include, e.g., a metallic material film. The metallic material film of thefirst insertion layer 16 a may include, e.g., a metal oxide film or a metal nitride film. The metal M used to form the metallic material film of thefirst insertion layer 16 a may be the same as the metal M used to form the metal oxide film of thedielectric layer 18. Alternatively, the metal M used to form the metallic material film of theinsertion layer 16 a may be different from the metal M used to form the metal oxide film of thedielectric layer 18. - In particular, if the metal M used to form the metallic material film of the
first insertion layer 16 a is the same as the metal M used to form the metal oxide film of thedielectric layer 18, characteristics of the interface between thelower metal layer 14 and thedielectric layer 18 may be improved. Thus, thedielectric layer 18 may have excellent characteristics, improving electrical characteristics of thedielectric layer 18. - The
first insertion layer 16 a may include, e.g., a ZrO2 film. If thefirst insertion layer 16 a includes zirconium, and thedielectric layer 18 includes a ZrO2 film, characteristics of thedielectric layer 18 may be improved, thereby improving electrical characteristics of thedielectric layer 18. - An
upper metal layer 20 may be formed on thedielectric layer 18. Theupper metal layer 20 may be formed of the same material used to form thelower metal layer 14. - The
semiconductor device 200 according to the first embodiment may include thelower metal layer 14, thedielectric layer 18, and theupper metal layer 20, which may be sequentially formed on thesemiconductor substrate 10 in the order stated. In particular, in thesemiconductor device 200 of the first embodiment, thefirst insertion layer 16 a may be formed in the first position between thelower metal layer 14 and thedielectric layer 18. Thedielectric layer 18 may include, e.g., a metal oxide film, and thefirst insertion layer 16 a may include, e.g., a metallic material film. Thedielectric layer 18 of thesemiconductor device 200 according to the first embodiment may have excellent electrical characteristics, thereby reducing leakage current. - The
semiconductor device 200 according to the first embodiment may include a capacitor including thelower metal layer 14, thefirst insertion layer 16 a, thedielectric layer 18, and theupper metal layer 20. The capacitor may be used in various integrated circuit semiconductor devices, e.g., dynamic random access memory (DRAM) devices. -
FIG. 2 illustrates a cross-sectional view of asemiconductor device 220 fabricated according to the second embodiment. Thesemiconductor device 220 according to the second embodiment may be the same as thesemiconductor device 200 according to the first embodiment, except that asecond insertion layer 16 b may be formed between theupper metal layer 20 and thedielectric layer 18, rather than forming thefirst insertion layer 16 a between thelower metal layer 14 and thedielectric layer 18. - In particular, the
lower metal layer 14 may be formed on asemiconductor substrate 10 or on a insulatinglayer 12. Thelower metal layer 14 may include a metal nitride film, e.g., a TiN film, a NbN film, or a TaN film, as described above with reference to the first embodiment. Thedielectric layer 18 may be formed on thelower metal layer 14. Thedielectric layer 18 may include a metal oxide film, as described above with reference to the first embodiment. The metal M used to form the metal oxide film of thedielectric layer 18 may be the same as the metal M described above with reference to the first embodiment. Thedielectric layer 18 may include a metal oxide in the form of MOx, where M is the metal, O is oxygen, and x is about 0.5 to about 4. Thedielectric layer 18 may include, e.g., a ZrO2 film. - The
second insertion layer 16 b may be formed on thedielectric layer 18. Thesecond insertion layer 16 b may improve electrical characteristics of thedielectric layer 18, thereby reducing leakage current. Thesecond insertion layer 16 b may be formed of the same material used to form thefirst insertion layer 16 a of the first embodiment. That is, thesecond insertion layer 16 b may include, e.g., a metallic material film. - The metallic material film of the
second insertion layer 16 b may include, e.g., a metal oxide film or a metal nitride film. The metal M used to form the metallic material film of thesecond insertion layer 16 b may also be different from the metal used to form the metal oxide film of thedielectric layer 18. - If the metal M used to form the metallic material film of the
second insertion layer 16 b is the same as the metal M used to form the metal oxide film of thedielectric layer 18, characteristics of the interface between theupper metal layer 20 and thedielectric layer 18 may be improved. Thus, thedielectric layer 18 may have excellent characteristics. Accordingly, electrical characteristics of thedielectric layer 18 may also be improved. Thesecond insertion layer 16 b may include, e.g., a zirconium nitride (ZrN) film. Theupper metal layer 20 may be formed on thesecond insertion layer 16 b. Theupper metal layer 20 may be formed of the same material used to form thelower metal layer 14. - The
semiconductor device 220 according to the second embodiment may include thesecond insertion layer 16 b formed in the second position between thedielectric layer 18 and theupper metal layer 20. Thedielectric layer 18 of thesemiconductor device 220 according to the second embodiment may have improved electrical characteristics, thereby reducing leakage current. - The
semiconductor device 220 according to the second embodiment may include a capacitor including, e.g., thelower metal layer 14, thedielectric layer 18, thesecond insertion layer 16 b, and theupper metal layer 20. The capacitor may be used in various integrated circuit semiconductor devices, e.g., DRAM devices. -
FIG. 3 illustrates a cross-sectional view of asemiconductor device 240 fabricated according to the third embodiment. Thesemiconductor device 240 according to the third embodiment may be a combination of thesemiconductor device 200 according to the first embodiment and thesemiconductor device 220 according to the second embodiment. That is, thesemiconductor device 240 according to the third embodiment may include thefirst insertion layer 16 a formed in the first position between thelower metal layer 14 and thedielectric layer 18 and thesecond insertion layer 16 b formed in the second position between thedielectric layer 18 and theupper metal layer 20. - In particular, the
lower metal layer 14 may be formed on thesemiconductor substrate 10 or on the insulatinglayer 12. Thelower metal layer 14 may include a metal nitride film, e.g., a TiN film, a NbN film, or a TaN film, as described above with respect to the first and second embodiments. - The
first insertion layer 16 a may be formed on thelower metal layer 14 and thedielectric layer 18 may be formed on thefirst insertion layer 16 a. Thefirst insertion layer 16 a may be the same as theinsertion layer 16 a of the first embodiment. Thedielectric layer 18 may include a metal oxide film, as described in the first and second embodiments. The metal M used to form the metal oxide film of thedielectric layer 18 may be the same as the metal M described with respect to the first and second embodiments. Thedielectric layer 18 may include the metal oxide in the form of MOx, where M is the metal, O is oxygen, and x is about 0.5 to 4. Thedielectric layer 18 may include, e.g., a ZrO2 film. - The
first insertion layer 16 a may include a metallic material film. The metallic material film of thefirst insertion layer 16 a may include, e.g., a metal oxide film or a metal nitride film. The metal M used to form the metallic material film of thefirst insertion layer 16 a may be the same as or different from the metal M used to form the metal oxide film of thedielectric layer 18. Thefirst insertion layer 16 a may include, e.g., a ZrO2 film. Thefirst insertion layer 16 a may improve electrical characteristics of thedielectric layer 18, thereby reducing leakage current. - The
second insertion layer 16 b and theupper metal layer 20 may be formed sequentially on thedielectric layer 18 in the order stated. Thesecond insertion layer 16 b may be formed of the same material used to form thesecond insertion layer 16 b according to the second embodiment. Thesecond insertion layer 16 b may improve electrical characteristics of thedielectric layer 18, thereby reducing leakage current. Theupper metal layer 20 may be formed of the same material used to form thelower metal layer 14. - In the
semiconductor device 240 according to the third embodiment, thefirst insertion layer 16 a may be formed in the first position between thelower metal layer 14 and thedielectric layer 18. Thesecond insertion layer 16 b may be formed in the second position between thedielectric layer 18 and theupper metal layer 20. Thedielectric layer 18 of thesemiconductor device 240 according to the third embodiment may have improved electrical characteristic, thereby reducing leakage current. - The
semiconductor device 240 according to the third embodiment may include a capacitor including thelower metal layer 14, thefirst insertion layer 16 a, thedielectric layer 18, thesecond insertion layer 16 b, and theupper metal layer 20. The capacitor may be used in various integrated circuit semiconductor devices, e.g., DRAM devices. - Hereinafter, characteristics of the
dielectric layer 18 of thesemiconductor device 200 according to the first embodiment, in which theinsertion layer 16 a may be formed between thelower metal layer 14 and thedielectric layer 18, will be compared with characteristics of thedielectric layer 18 of a semiconductor device according to the first comparative embodiment. In the first comparative embodiment, thedielectric layer 18 may be formed directly on thelower metal layer 14. In thesemiconductor device 200 of the first embodiment, a TiN film may be used as thelower metal layer 14, a ZrO2 film may be used as theinsertion layer 16 a, and a ZrO2 film may be used as thedielectric layer 18. In the semiconductor device of the first comparative embodiment, a TiN film may be used as thelower metal layer 14 and a ZrO2 film may be used as thedielectric layer 18. -
FIGS. 4 and 5 illustrate cross-sectional views of a semiconductor device according to the first comparative embodiment for comparison with thesemiconductor device 200 according to the first embodiment.FIGS. 6 and 7 illustrate cross-sectional views of thesemiconductor device 200 according to the first embodiment for comparison with the semiconductor device according to the first comparative embodiment. - In particular, according to the first comparative embodiment as shown in
FIGS. 4 and 5 , adielectric layer 18, e.g., a ZrO2 film, may be formed on alower metal layer 14, e.g., a TiN film. According to the fabrication process, thelower metal layer 14 may be oxidized by an ozone (O3) oxidant, used to form thedielectric layer 18, to form aninterface layer 30, e.g., a TiOx layer or a TiON layer, on thelower metal layer 14. Since the TiOx layer may have many defects, and the TiON layer may have a low bandgap, e.g., about 2.1 eV, electrical characteristics of thedielectric layer 18 may deteriorate. - However, according to the first embodiment, a first
insertion material layer 15 a may first be formed on thelower metal layer 14 to fabricate thesemiconductor device 200. The firstinsertion material layer 15 a may be formed using, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The firstinsertion material layer 15 a may, e.g., a metal film, a metal carbide film, or a metal nitride film. The metal film may include, e.g., a zirconium film. The metal carbide film may include, e.g., a zirconium carbide (ZrCx) film. The metal nitride film may include, e.g., a ZrN film. Thedielectric layer 18, e.g., a ZrO2 film, may be formed on theinsertion material layer 15 a. - According to the first embodiment, the first
insertion material layer 15 a may be converted to thefirst insertion layer 16 a, e.g., a ZrO2 film, by an O3 oxidant used during formation of thedielectric layer 18. Thus, theundesirable interface layer 30 of the first comparative embodiment may be avoided. Furthermore, when the firstinsertion material layer 15 a includes a metal nitride film or a metal carbide film, the firstinsertion material layer 15 a may be converted to a metal oxide film, a metal nitride film, or a metal oxide nitride film by the O3 oxidant. - In the
semiconductor device 200 according to the first embodiment, the firstinsertion material layer 15 a may be preferentially oxidized by the O3 oxidant. Thus, due to insufficient amount of free O3 oxidant, undesirable formation of theinterface layer 30 may be prevented. From a thermodynamic point of view, high activation energy may be required for the TiN film of thelower metal layer 14 to be oxidized to TiOx film or TiON film as described above with respect to the first comparative embodiment. However, since low activation energy may be required for the zirconium film of the firstinsertion material layer 15 a to be converted to ZrO2 film, the zirconium film may be preferentially oxidized by the O3 gas, thereby preventing oxidation of the TiN film of thelower metal layer 14. - The first
insertion material layer 15 a of thesemiconductor device 200 according to the first embodiment may be oxidized, i.e., converted, to thefirst insertion layer 16 a. In particular, if the metal oxide film, i.e., the ZrO2 film of thedielectric layer 18, and the metallic material film, i.e., the ZrO2 film of theinsertion layer 16 a, are the same, a complete interface layer may be formed. Accordingly, characteristics of thedielectric layer 18 may be improved. -
FIGS. 8 and 9 illustrate cross-sectional views of a semiconductor device according to the first comparative embodiment for comparison with thesemiconductor device 200 according to the first embodiment.FIGS. 10 and 11 illustrate cross-sectional views of thesemiconductor device 200 according to the first embodiment for comparison with the semiconductor device according to the first comparative embodiment. - In particular, according to the first comparative embodiment, the
dielectric layer 18, e.g., a ZrO2 film, may be formed on thelower metal layer 14, e.g., a TiN film. A lattice constant of the ZrO2 film of thedielectric layer 18 may be about 5.09 Å. A lattice constant of the TiN film of thelower metal layer 14 may be about 4.32 Å, thereby exhibiting a large lattice constant difference between thedielectric layer 18 and thelower metal layer 14. Furthermore, a crystal structure of the ZrO2 film of thedielectric layer 18 may be different from the crystal structure of the TiN film of thelower metal layer 14. - Accordingly, as illustrated in
FIG. 8 , aseed layer 32 may have low density and non-uniform grain size during an initial stage of deposition of the ZrO2 film of thedielectric layer 18. That is, as illustrated inFIG. 8 , theseed layer 32 having low density and non-uniform grain size may be formed on thelower metal layer 14 during the initial stage of deposition of the ZrO2 film of thedielectric layer 18. InFIG. 8 , the upper diagram illustrates a plan view; and the lower diagram illustrates a cross-sectional view. In addition, as illustrated inFIG. 9 , the ZrO2 film growing from the seed layer may havegrains 34 with a non-uniform size; and grain boundaries formed by the growngrains 34 may not be densely formed. - In other words, since the
seed layer 32 may not be densely formed on thelower metal layer 14 during the initial stage of deposition of thedielectric layer 18, the size of thegrains 34 may increase; and voids may exist in the grain boundaries. Thus, thedielectric layer 18 according to the first comparative embodiment may have poor characteristics. Accordingly, electrical characteristics of thedielectric layer 18 may deteriorate during operation of the semiconductor device. - On the other hand, the first
insertion material layer 15 a may be formed on thelower metal layer 14 in thesemiconductor device 200 according to the first embodiment. The firstinsertion material layer 15 a may include a zirconium film as described with reference toFIG. 6 . Then, thedielectric layer 18, e.g., a ZrO2 film, may be formed on the firstinsertion material layer 15 a, converting the firstinsertion material layer 15 a to thefirst insertion layer 16 a as described with reference toFIG. 6 . - According to the fabrication process, the first
insertion material layer 15 a, e.g., the zirconium film, may be oxidized during the deposition of thedielectric layer 18 to form thefirst insertion layer 16 a and aseed layer 36 as illustrated inFIG. 10 . Thus, theseed layer 36 may have high density and uniform size. InFIG. 10 , the upper diagram illustrates a cross-sectional view; and the lower diagram illustrates a plan view. As illustrated inFIG. 11 , the ZrO2 film growing from the seed layer may havegrains 38 with a uniform and relatively small size; and grain boundaries formed by the growngrains 38 may be densely formed. - The
dielectric layer 18 is not limited to the TiN film and the ZrO2 film, and most suitable metal nitride films and metal oxide film may be used. For example, the method according to an embodiment may also be used when, e.g., a hafnium oxide (HfO2) film is formed on a TiN film or a ZrO2 film is formed on a TaN film. - Hereinafter, characteristics of the
dielectric layer 18 of thesemiconductor device 220 according to the second embodiment, in which thesecond insertion layer 16 b may be formed between theupper metal layer 20 and thedielectric layer 18, will be compared with characteristics of thedielectric layer 18 of a semiconductor device according to the second comparative embodiment, in which theupper metal layer 20 may be formed directly on thedielectric layer 18. In the second embodiment, a TiN film may be used as theupper metal layer 20, a ZrO2 film may be used as thesecond insertion layer 16 b, and a ZrO2 film may be used as thedielectric layer 18. In the second comparative embodiment, a TiN film may be used as theupper metal layer 20; and a ZrO2 film may be used as thedielectric layer 18 -
FIGS. 12 and 13 illustrate cross-sectional views of the semiconductor device according to the second comparative embodiment for comparison with thesemiconductor device 220 according to the second embodiment.FIGS. 14 and 15 illustrate cross-sectional views of thesemiconductor device 220 according to the second embodiment for comparison with the semiconductor device according to the second comparative embodiment. - In particular, according to the second comparative embodiment as illustrated in
FIGS. 12 and 13 , anupper metal layer 20, e.g., a TiN film, may be formed on adielectric layer 18, e.g., a ZrO2 film. According to the fabrication process, aninterface layer 30 a, e.g., a ZrON film, a TiOx film, and a TiON film, may be formed on thedielectric layer 18 by, e.g., an ammonia (NH3) nitrating agent, used during formation of theupper metal layer 20 or a reaction between theupper metal layer 20 and thedielectric layer 18. The ZrON film may deteriorate interface characteristics with theupper metal layer 20, the TiOx film may have many defects, and the TiON film may have a low bandgap of, e.g., about 2.1 eV. As a result, theinterface layer 30 a may deteriorate electrical characteristics of thedielectric layer 18. - On the other hand, a second
insertion material layer 15 b may be formed on thedielectric layer 18 to form thesemiconductor device 220 according to the second embodiment. The secondinsertion material layer 15 b may be formed using, e.g., CVD, PVD, or ALD. The secondinsertion material layer 15 b may include, e.g., a metal film, a metal carbide film, or a metal nitride film. The metal film may include, e.g., a zirconium film. The metal carbide film may include, e.g., a zirconium carbide (ZrCx) film. The metal nitride film may include, e.g., a ZrN film. Anupper metal layer 20 may be formed on the secondinsertion material layer 15 b. - According to the fabrication process, the second
insertion material layer 15 b may be converted to thesecond insertion layer 16 b, e.g., the ZrN film, by the NH3 nitrating agent used during formation of theupper metal layer 20. Thesecond insertion layer 16 b may function as theupper metal layer 20 without adversely influencing thedielectric layer 18, unlike in the second comparative embodiment. Since thedielectric layer 18 of thesemiconductor device 220 according to the second embodiment may not be damaged while theupper metal layer 20 is formed, the interface between thedielectric layer 18 and theupper metal layer 20 may have excellent characteristics when compared with the second comparative embodiment. Thus, thedielectric layer 18 may have excellent electrical characteristics. - As described above, the
semiconductor device 240 according to the third embodiment may be a combination of thesemiconductor device 200 according to the first embodiment and thesemiconductor device 220 according to the second embodiment. Thus, thesemiconductor device 240 according to the third embodiment may have the beneficial effects of both the first and second embodiments. Thesemiconductor device 240 according to the third embodiment may have better electrical characteristics than those of the first and second comparative embodiments. - Hereinafter, electrical characteristics of the
dielectric layer 18 according to the embodiments will be compared with those according to the first and second comparative embodiments. -
FIG. 16 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first comparative embodiment.FIG. 17 illustrates a graph showing voltage and leakage current of thesemiconductor device 200 according to the first embodiment. - Particularly,
FIG. 16 illustrates a graph showing positive voltage and leakage current of a capacitor fabricated by forming a TiN filmlower metal layer 14 on asemiconductor substrate 10, forming a ZrO2film dielectric layer 18 on thelower metal layer 14 to a thickness of 70 Å, and forming anupper metal layer 20 on thedielectric layer 18. In the capacitor of the first comparative embodiment, when a reference leakage current is 10−7 Å/cm2 at 1 V, characteristics of thedielectric layer 18 may be damaged after voltages ranging from 0 V to 3.3 V are applied 16 times to thedielectric layer 18, and thus a low leakage current is not restored. -
FIG. 17 illustrates a graph showing voltage and leakage current of a capacitor fabricated by forming a TiN filmlower metal layer 14 on asemiconductor substrate 10, forming a ZrO2 filmfirst insertion layer 16 a on thelower metal layer 14 to a thickness of 10 Å, forming a ZrO2film dielectric layer 18 on thefirst insertion layer 16 a to a thickness of 70 Å, and forming anupper metal layer 20 on thedielectric layer 18 as in the first embodiment. In the capacitor of the first embodiment, when a reference leakage current is 10−7 Å/cm2 at 1 V, characteristics of thedielectric layer 18 are maintained after voltages of about 0 V to about 3.3 V are applied 50 times to thedielectric layer 18; and thus the leakage current remains in a normal range. When comparing the results ofFIGS. 16 and 17 , it may be seen that electrical characteristics of thedielectric layer 18 of the capacitor according to the first embodiment are better than those according to the first comparative embodiment. -
FIG. 18 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second comparative embodiment.FIG. 19 illustrates a graph showing voltage and leakage current of thesemiconductor device 220 according to the second embodiment. - Particularly,
FIG. 18 illustrates a graph showing negative voltage and leakage current of a capacitor fabricated by forming a TiN filmlower metal layer 14 on asemiconductor substrate 10, forming a ZrO2film dielectric layer 18 on thelower metal layer 14 to a thickness of 70 Å, and forming anupper metal layer 20 directly on thedielectric layer 18. In the capacitor of the second comparative embodiment, when a reference leakage current is 10−7 Å/cm2 at −1 V, characteristics of thedielectric layer 18 are damaged after voltages ranging from 0 V to −3.8 V are applied 25 times, and thus a low leakage current is not restored. -
FIG. 19 . illustrates a graph showing negative voltage and leakage current of a capacitor fabricated by forming a TiN filmlower metal layer 14 on asemiconductor substrate 10, forming a ZrO2film dielectric layer 18 on thelower metal layer 14 to a thickness of 70 Å, forming a ZrO2 filmsecond insertion layer 16 b on thedielectric layer 18 to a thickness of 10 Å, and forming anupper metal layer 20 on thesecond insertion layer 16 b as in the second embodiment. In the capacitor of the second embodiment, when a reference leakage current is 10−7 Å/cm2 at −1 V, characteristics of thedielectric layer 18 are maintained after voltages ranging from 0 V to −3.8 V are applied 48 times to thedielectric layer 18; and thus the leakage current remains in a normal range. When comparing the results ofFIGS. 18 and 19 , it may be seen that electrical characteristics of thedielectric layer 18 of the capacitor according to the second embodiment are better than those according to the second comparative embodiment. - The capacitors fabricated according to the first, second, and/or third embodiments may be applied to semiconductor devices, e.g., DRAM devices. A DRAM device will be briefly described herein.
-
FIG. 20 illustrates a circuit diagram of a unit cell of a DRAM device including a transistor according to an embodiment. - A unit cell of a DRAM device may have various shapes. For example, the unit cell according to an embodiment may include a
transistor 110 and acapacitor 130. Thetransistor 110 may be connected to aword line 170. A bit line 150 may be connected to a source/drain region of thetransistor 110. Thecapacitor 130 according toEmbodiments 1 to 3 described above may be connected to another source/drain region of thetransistor 110. That is, the capacitor fabricated according toEmbodiments 1 to 3 may be applied to a DRAM device. - The semiconductor device, e.g., the DRAM device, according to an embodiment may be applied to various fields. A DRAM chip may be fabricated by packaging the semiconductor device, e.g., the DRAM device, according to an embodiment. The DRAM chip may be applied to various fields, and examples will be described herein.
-
FIG. 21 illustrates a plan view of amemory module 500 usingDRAM chips 50 to 58, according to an embodiment. - In particular, the DRAM chips 50 to 58 may be fabricated by respectively packaging the semiconductor devices according to an embodiment. The DRAM chips 50 to 58 may be applied to the
memory module 500. In thememory module 500, the DRAM chips 50 to 58 may be attached to amodule substrate 501. Thememory module 500 may includeconnectors 502 which may be inserted into sockets of a motherboard, at an end of themodule substrate 501 andceramic decoupling capacitors 59 on themodule substrate 501. However, thememory module 500 is not limited to the shape shown inFIG. 21 and thus may have various shapes. -
FIG. 22 illustrates a block diagram of anelectronic system 600 using aDRAM chip 512 according to an embodiment. - In particular, the
electronic system 600 may be a computer. Theelectronic system 600 may include a central processing unit (CPU) 505, a peripheral device, e.g., afloppy disc drive 507 and/or a compact disc read-only memory (CD-ROM)drive 509, input andoutput devices DRAM chip 512, aROM chip 514, etc. Control signals or data may be transferred among the elements via acommunication channel 511. TheDRAM chip 512 may be replaced by thememory module 500 including the DRAM chips 50 to 58 as described with reference toFIG. 21 . - A semiconductor device according to an embodiment may be fabricated by forming an insertion layer between a lower metal layer and a dielectric layer. When the insertion layer is formed between the lower metal layer and the dielectric layer, the formation of an interface caused by the oxidation of the lower metal layer during the formation of the dielectric layer may be prevented. Thus, characteristics of the dielectric layer may be improved, since the insertion layer may function as a seed layer for the formation of the dielectric layer.
- Furthermore, the semiconductor device according to an embodiment may be fabricated by forming an insertion layer between the dielectric layer and an upper metal layer. When the insertion layer is formed between the dielectric layer and the upper metal layer, an interface layer may not be formed on the dielectric layer, and the dielectric layer may not be damaged. As a result, characteristics of the dielectric layer of the semiconductor device, including its electrical characteristics, may be improved.
- As for drawbacks of other semiconductor devices and their fabrication processes, if the dielectric layer is formed at a high temperature, the high temperature may adversely affect the resultant semiconductor devices. Additionally, if heat-treatment or the oxygen curing is performed after deposition of the dielectric layer, a plurality of interface layers may be formed on a lower film under the dielectric layer. The interface layers may deteriorate electrical characteristics of the dielectric layer during the operation of the semiconductor devices, thereby increasing undesirable leakage current.
- Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Claims (20)
1-17. (canceled)
18. A method of fabricating a semiconductor device, the method comprising:
forming a lower metal layer on a semiconductor substrate;
forming an insertion material layer on the lower metal layer, the insertion material layer being substantially oxygen-free as deposited;
forming a dielectric layer on the insertion material layer; and
forming an upper metal layer on the dielectric layer,
wherein the insertion material layer is converted to an insertion layer including a metal oxide, a metal nitride, or a metal oxynitride during the forming of the dielectric layer.
19. The method as claimed in claim 18 , wherein the insertion material layer has a lower activation energy than the lower metal layer.
20. The method as claimed in claim 19 , wherein the insertion material layer includes a metal film, a metal carbide film, or a metal nitride film.
21. The method as claimed in claim 19 , wherein the insertion material layer includes a zirconium film, a zirconium carbide film, or a zirconium nitride film.
22. The method as claimed in claim 18 , wherein the lower metal layer includes a metal nitride.
23. The method as claimed in claim 18 , wherein the insertion layer is formed by an oxidation of the insertion material layer by an O3 oxidant during the forming of the dielectric layer.
24. The method as claimed in claim 23 , wherein the insertion material layer prevents oxidation of the lower metal layer during forming the dielectric layer.
25. The method as claimed in claim 18 , wherein the dielectric layer includes a metal oxide in the form of MOx, where M is a metal, O is oxygen, and x is about 0.5 to 4.
26. The method as claimed in claim 18 , wherein the dielectric layer includes a metal of the insertion material layer.
27. The method as claimed in claim 18 , wherein the insertion layer has a thickness of up to about 10 Å.
28. A method of fabricating a semiconductor device, the method comprising:
forming a lower metal layer on a semiconductor substrate;
forming a dielectric layer on the lower metal layer;
forming an insertion material layer on the dielectric layer, the insertion material layer being substantially oxygen-free as deposited; and
forming an upper metal layer on the insertion material layer,
wherein the insertion material layer is converted to an insertion layer including a metal oxide, a metal oxynitride, or a metal nitride during the forming of the upper metal layer.
29. The method as claimed in claim 28 , wherein the insertion material layer includes a metal film, a metal carbide film, or a metal nitride film.
30. The method as claimed in claim 28 , wherein the insertion material layer includes a zirconium film.
31. The method as claimed in claim 28 , wherein the insertion layer is formed by nitrating the insertion material layer by a nitrating agent used during the forming of the upper metal layer.
32. The method as claimed in claim 28 , wherein the upper metal layer includes a metal nitride.
33. The method as claimed in claim 32 , wherein the dielectric layer includes a metal oxide in the form of MOx, where M is a metal, O is oxygen, and x is about 0.5 to 4.
34. The method as claimed in claim 33 , wherein the insertion material layer substantially prevents oxidation of the upper metal layer during the forming of the upper metal layer.
35. The method as claimed in claim 28 , wherein the dielectric layer includes a metal of the insertion material layer.
36. The method as claimed in claim 28 , wherein the insertion layer has a thickness of up to about 10 Å.
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US12/585,030 US20100200950A1 (en) | 2009-02-06 | 2009-09-01 | Semiconductor device having dielectric layer with improved electrical characteristics and associated methods |
US13/424,825 US8859383B2 (en) | 2009-02-06 | 2012-03-20 | Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics |
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Cited By (5)
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KR20180120308A (en) * | 2017-04-26 | 2018-11-06 | 삼성전자주식회사 | Capacitor and method for manufacturing the same |
KR20190031402A (en) * | 2017-09-15 | 2019-03-26 | 삼성전자주식회사 | Method for manufacturing Capacitor and Semiconductor device |
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KR101607263B1 (en) * | 2009-02-06 | 2016-03-30 | 삼성전자주식회사 | Methods for fabricating semicondcutor devices capable of incresing electrical characteristics of dielectric layer |
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KR20180120308A (en) * | 2017-04-26 | 2018-11-06 | 삼성전자주식회사 | Capacitor and method for manufacturing the same |
US10453913B2 (en) * | 2017-04-26 | 2019-10-22 | Samsung Electronics Co., Ltd. | Capacitor, semiconductor device and methods of manufacturing the capacitor and the semiconductor device |
US20200013853A1 (en) * | 2017-04-26 | 2020-01-09 | Samsung Electronics Co., Ltd. | Capacitor, semiconductor device and methods of manufacturing the capacitor and the semiconductor device |
US10658454B2 (en) * | 2017-04-26 | 2020-05-19 | Samsung Electronics Co., Ltd. | Capacitor, semiconductor device and methods of manufacturing the capacitor and the semiconductor device |
KR102466330B1 (en) * | 2017-04-26 | 2022-11-15 | 삼성전자주식회사 | Capacitor and method for manufacturing the same |
DE102018108206B4 (en) | 2017-04-26 | 2023-01-19 | Samsung Electronics Co., Ltd. | Capacitor with a seed layer between electrode and dielectric layer |
KR20190031402A (en) * | 2017-09-15 | 2019-03-26 | 삼성전자주식회사 | Method for manufacturing Capacitor and Semiconductor device |
KR102428322B1 (en) * | 2017-09-15 | 2022-08-03 | 삼성전자주식회사 | Method for manufacturing Capacitor and Semiconductor device |
US20220115380A1 (en) * | 2019-06-14 | 2022-04-14 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of fabricating the same |
US11641730B2 (en) * | 2019-06-14 | 2023-05-02 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of fabricating the same |
US11778805B2 (en) | 2019-06-14 | 2023-10-03 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of fabricating the same |
Also Published As
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KR20100090534A (en) | 2010-08-16 |
KR101607263B1 (en) | 2016-03-30 |
US20100200950A1 (en) | 2010-08-12 |
US20120178254A1 (en) | 2012-07-12 |
US8859383B2 (en) | 2014-10-14 |
CN101800220A (en) | 2010-08-11 |
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