US20100200950A1 - Semiconductor device having dielectric layer with improved electrical characteristics and associated methods - Google Patents

Semiconductor device having dielectric layer with improved electrical characteristics and associated methods Download PDF

Info

Publication number
US20100200950A1
US20100200950A1 US12585030 US58503009A US2010200950A1 US 20100200950 A1 US20100200950 A1 US 20100200950A1 US 12585030 US12585030 US 12585030 US 58503009 A US58503009 A US 58503009A US 2010200950 A1 US2010200950 A1 US 2010200950A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
layer
dielectric layer
semiconductor device
film
insertion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12585030
Inventor
Youn-Soo Kim
Jae-Hyoung Choi
Kyu-Ho Cho
Wan-Don Kim
Jae-soon Lim
Sang-Yeol Kang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/75Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto

Abstract

A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.

Description

    BACKGROUND
  • 1. Field
  • Embodiments relate to a semiconductor device having a dielectric layer with improved electrical characteristics and associated methods.
  • 2. Description of the Related Art
  • Various dielectric layers may be used during fabrication of semiconductor devices. A dielectric layer may be formed between an upper electrode and a lower electrode of a capacitor. Diverse research is being conducted into improving characteristics of a dielectric layer, e.g., increasing the dielectric constant, improving crystallinity, and/or reducing defects, to thereby improve electrical characteristics of resultant semiconductor devices.
  • The crystallinity of the dielectric layer may be improved by, e.g., depositing the dielectric layer at a high temperature or heat-treating the dielectric layer after deposition. In addition, defects in the dielectric layer may be removed by, e.g., oxygen curing after the dielectric layer is formed.
  • SUMMARY
  • Embodiments are directed to a semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, which substantially overcome one or more of the drawbacks, limitations, and/or disadvantages of the related art.
  • It is a feature of an embodiment to provide a semiconductor device having a dielectric layer with improved electrical characteristics.
  • It is another feature of an embodiment to provide a semiconductor device that reduces a leakage current.
  • At least one of the above and other features and advantages may be realized by providing a semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate, and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
  • The insertion layer may be disposed between the dielectric layer and the lower metal layer.
  • The insertion layer may be disposed between the dielectric layer and the upper metal layer.
  • The insertion layer may be disposed between the dielectric layer and the lower metal layer and between the dielectric layer and the upper metal layer.
  • The metal oxide film and the metallic material film may each independently include at least one of Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and Ac.
  • The metal oxide film may be in the form of MO, wherein M is a metal, O is oxygen, and x is about 0.5 to about 4.
  • A metal used to form the metallic material film of the insertion layer may be the same as a metal used to form the metal oxide film of the dielectric layer.
  • The metallic material film of the insertion layer may be a metal oxide film.
  • The metallic material film of the insertion layer may be a metal nitride film.
  • At least one of the above and other features and advantages may also be realized by providing a method of fabricating a semiconductor device including sequentially forming a lower metal layer, a dielectric layer, and an upper metal layer on a semiconductor substrate, and forming an insertion layer between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer is formed of a metal oxide film and the insertion layer is formed of a metallic material film.
  • The forming the insertion layer may include forming the insertion layer between the dielectric layer and the lower metal layer.
  • The forming the insertion layer may include forming the insertion layer between the dielectric layer and the upper metal layer.
  • The forming the insertion layer may include forming the insertion layer between the dielectric layer and the lower metal layer and between the dielectric layer and the upper metal layer.
  • The forming the insertion layer may include forming an insertion material layer on the lower metal layer, and converting the insertion material layer to the insertion layer while the dielectric layer is formed on the insertion material layer.
  • The insertion material layer may include a metal film, a metal carbide film, or a metal nitride film.
  • At least one of the above and other features and advantages may also be realized by providing a method of fabricating a semiconductor device including forming a lower metal layer on a semiconductor substrate, forming a dielectric layer on the lower metal layer using a metal oxide film, forming an insertion material layer on the dielectric layer, and forming an upper metal layer on the insertion material layer, wherein forming the upper metal layer includes converting the insertion material layer to an insertion layer.
  • The insertion material layer may include a metal film, a metal carbide film, or a metal nitride film.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
  • FIG. 1 illustrates a cross-sectional view of a semiconductor device according to a first embodiment;
  • FIG. 2 illustrates a cross-sectional view of a semiconductor device according to a second embodiment;
  • FIG. 3 illustrates a cross-sectional view of a semiconductor device according to a third embodiment;
  • FIGS. 4 and 5 illustrate cross-sectional views of a semiconductor device according to a first comparative embodiment;
  • FIGS. 6 and 7 illustrate cross-sectional views of the semiconductor device according to the first embodiment;
  • FIGS. 8 and 9 illustrate views of the semiconductor device according to the first comparative embodiment;
  • FIGS. 10 and 11 illustrate views of the semiconductor device according to the first embodiment;
  • FIGS. 12 and 13 illustrate cross-sectional views of a semiconductor device according to a second comparative embodiment;
  • FIGS. 14 and 15 illustrate cross-sectional views of the semiconductor device according to the second embodiment;
  • FIG. 16 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first comparative embodiment;
  • FIG. 17 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first embodiment;
  • FIG. 18 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second comparative embodiment;
  • FIG. 19 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second embodiment;
  • FIG. 20 illustrates a circuit diagram of a unit cell of a dynamic random access memory (DRAM) device including a transistor, according to an embodiment;
  • FIG. 21 illustrates a plan view of a memory module using a DRAM chip, according to an embodiment; and
  • FIG. 22 illustrates a block diagram of an electronic system using a DRAM chip, according to an embodiment.
  • DETAILED DESCRIPTION
  • Korean Patent Application No. 10-2009-0009875, filed on Feb. 6, 2009, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device for Improving Electrical Characteristics of Dielectric Layer and Method of Fabricating the Same,” is incorporated by reference herein in its entirety.
  • Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.
  • In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
  • A semiconductor device according to an embodiment may be fabricated by forming an insertion layer in a first position between a lower metal layer and a dielectric layer, a second position between the dielectric layer and an upper metal layer, or in both of the first and second positions. The first position may be an interface between the lower metal layer and the dielectric layer. The second position may be an interface between the dielectric layer and the upper metal layer.
  • The lower metal layer may include, e.g., a metal nitride film. The dielectric layer may include, e.g., a metal oxide film. The insertion layer may include, e.g., a metallic material film.
  • If the insertion layer is formed between the lower metal layer and the dielectric layer, i.e., in the first position, formation of an undesirable interface layer due to oxidation of the lower metal layer during formation of the dielectric layer may be inhibited. In addition, the insertion layer may function as a seed layer during formation of the dielectric layer to, e.g., improve characteristics of the dielectric layer. If the insertion layer is formed between the dielectric layer and the upper metal layer, i.e., in the second position, the formation of an undesirable interface layer on the dielectric layer may be inhibited. Thus, the dielectric layer may not be damaged, thereby improving characteristics of the dielectric layer. The semiconductor device and a method of fabricating the semiconductor device will be described with reference to the accompanying drawings, in which exemplary embodiments are shown.
  • First Embodiment
  • FIG. 1 illustrates a cross-sectional view of a semiconductor device 200 according to the first embodiment. The semiconductor device 200 according to the first embodiment may include a lower structure, e.g., an insulating layer 12, on a semiconductor substrate 10. Instead of the insulating layer 12, a material layer or a transistor may be formed on the semiconductor substrate 10. A lower metal layer 14 may be formed on the semiconductor substrate 10 or on the insulating layer 12. The lower metal layer 14 may include, e.g., a metal nitride film. The metal nitride film may include, e.g., a titanium nitride (TiN) film, a niobium nitride (NbN) film, or a tantalum nitride (TaN) film.
  • A first insertion layer 16 a and a dielectric layer 18 may be formed sequentially on the lower metal layer 14 in the order stated. The first insertion layer 16 a may be formed in the first position between the lower metal layer 14 and the dielectric layer 18. The first insertion layer 16 a may improve electrical characteristics of the dielectric layer 18, advantageously reducing leakage current.
  • The dielectric layer 18 may include, e.g., a metal oxide film. A metal M used to form the metal oxide film of the dielectric layer 18 may include, e.g., Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and/or Ac. The dielectric layer 18 may include, e.g., a single film including the metal M or multiple films including at least two films. The dielectric layer 18 may include the metal M in the form of MOx, wherein O is oxygen and x is about 0.5 to about 4. The dielectric layer 18 may include, e.g., a zirconium oxide (ZrO2) film.
  • The first insertion layer 16 a may include, e.g., a metallic material film. The metallic material film of the first insertion layer 16 a may include, e.g., a metal oxide film or a metal nitride film. The metal M used to form the metallic material film of the first insertion layer 16 a may be the same as the metal M used to form the metal oxide film of the dielectric layer 18. Alternatively, the metal M used to form the metallic material film of the insertion layer 16 a may be different from the metal M used to form the metal oxide film of the dielectric layer 18.
  • In particular, if the metal M used to form the metallic material film of the first insertion layer 16 a is the same as the metal M used to form the metal oxide film of the dielectric layer 18, characteristics of the interface between the lower metal layer 14 and the dielectric layer 18 may be improved. Thus, the dielectric layer 18 may have excellent characteristics, improving electrical characteristics of the dielectric layer 18.
  • The first insertion layer 16 a may include, e.g., a ZrO2 film. If the first insertion layer 16 a includes zirconium, and the dielectric layer 18 includes a ZrO2 film, characteristics of the dielectric layer 18 may be improved, thereby improving electrical characteristics of the dielectric layer 18.
  • An upper metal layer 20 may be formed on the dielectric layer 18. The upper metal layer 20 may be formed of the same material used to form the lower metal layer 14.
  • The semiconductor device 200 according to the first embodiment may include the lower metal layer 14, the dielectric layer 18, and the upper metal layer 20, which may be sequentially formed on the semiconductor substrate 10 in the order stated. In particular, in the semiconductor device 200 of the first embodiment, the first insertion layer 16 a may be formed in the first position between the lower metal layer 14 and the dielectric layer 18. The dielectric layer 18 may include, e.g., a metal oxide film, and the first insertion layer 16 a may include, e.g., a metallic material film. The dielectric layer 18 of the semiconductor device 200 according to the first embodiment may have excellent electrical characteristics, thereby reducing leakage current.
  • The semiconductor device 200 according to the first embodiment may include a capacitor including the lower metal layer 14, the first insertion layer 16 a, the dielectric layer 18, and the upper metal layer 20. The capacitor may be used in various integrated circuit semiconductor devices, e.g., dynamic random access memory (DRAM) devices.
  • Second Embodiment
  • FIG. 2 illustrates a cross-sectional view of a semiconductor device 220 fabricated according to the second embodiment. The semiconductor device 220 according to the second embodiment may be the same as the semiconductor device 200 according to the first embodiment, except that a second insertion layer 16 b may be formed between the upper metal layer 20 and the dielectric layer 18, rather than forming the first insertion layer 16 a between the lower metal layer 14 and the dielectric layer 18.
  • In particular, the lower metal layer 14 may be formed on a semiconductor substrate 10 or on a insulating layer 12. The lower metal layer 14 may include a metal nitride film, e.g., a TiN film, a NbN film, or a TaN film, as described above with reference to the first embodiment. The dielectric layer 18 may be formed on the lower metal layer 14. The dielectric layer 18 may include a metal oxide film, as described above with reference to the first embodiment. The metal M used to form the metal oxide film of the dielectric layer 18 may be the same as the metal M described above with reference to the first embodiment. The dielectric layer 18 may include a metal oxide in the form of MOx, where M is the metal, O is oxygen, and x is about 0.5 to about 4. The dielectric layer 18 may include, e.g., a ZrO2 film.
  • The second insertion layer 16 b may be formed on the dielectric layer 18. The second insertion layer 16 b may improve electrical characteristics of the dielectric layer 18, thereby reducing leakage current. The second insertion layer 16 b may be formed of the same material used to form the first insertion layer 16 a of the first embodiment. That is, the second insertion layer 16 b may include, e.g., a metallic material film.
  • The metallic material film of the second insertion layer 16 b may include, e.g., a metal oxide film or a metal nitride film. The metal M used to form the metallic material film of the second insertion layer 16 b may also be different from the metal used to form the metal oxide film of the dielectric layer 18.
  • If the metal M used to form the metallic material film of the second insertion layer 16 b is the same as the metal M used to form the metal oxide film of the dielectric layer 18, characteristics of the interface between the upper metal layer 20 and the dielectric layer 18 may be improved. Thus, the dielectric layer 18 may have excellent characteristics. Accordingly, electrical characteristics of the dielectric layer 18 may also be improved. The second insertion layer 16 b may include, e.g., a zirconium nitride (ZrN) film. The upper metal layer 20 may be formed on the second insertion layer 16 b. The upper metal layer 20 may be formed of the same material used to form the lower metal layer 14.
  • The semiconductor device 220 according to the second embodiment may include the second insertion layer 16 b formed in the second position between the dielectric layer 18 and the upper metal layer 20. The dielectric layer 18 of the semiconductor device 220 according to the second embodiment may have improved electrical characteristics, thereby reducing leakage current.
  • The semiconductor device 220 according to the second embodiment may include a capacitor including, e.g., the lower metal layer 14, the dielectric layer 18, the second insertion layer 16 b, and the upper metal layer 20. The capacitor may be used in various integrated circuit semiconductor devices, e.g., DRAM devices.
  • Third Embodiment
  • FIG. 3 illustrates a cross-sectional view of a semiconductor device 240 fabricated according to the third embodiment. The semiconductor device 240 according to the third embodiment may be a combination of the semiconductor device 200 according to the first embodiment and the semiconductor device 220 according to the second embodiment. That is, the semiconductor device 240 according to the third embodiment may include the first insertion layer 16 a formed in the first position between the lower metal layer 14 and the dielectric layer 18 and the second insertion layer 16 b formed in the second position between the dielectric layer 18 and the upper metal layer 20.
  • In particular, the lower metal layer 14 may be formed on the semiconductor substrate 10 or on the insulating layer 12. The lower metal layer 14 may include a metal nitride film, e.g., a TiN film, a NbN film, or a TaN film, as described above with respect to the first and second embodiments.
  • The first insertion layer 16 a may be formed on the lower metal layer 14 and the dielectric layer 18 may be formed on the first insertion layer 16 a. The first insertion layer 16 a may be the same as the insertion layer 16 a of the first embodiment. The dielectric layer 18 may include a metal oxide film, as described in the first and second embodiments. The metal M used to form the metal oxide film of the dielectric layer 18 may be the same as the metal M described with respect to the first and second embodiments. The dielectric layer 18 may include the metal oxide in the form of MOx, where M is the metal, O is oxygen, and x is about 0.5 to 4. The dielectric layer 18 may include, e.g., a ZrO2 film.
  • The first insertion layer 16 a may include a metallic material film. The metallic material film of the first insertion layer 16 a may include, e.g., a metal oxide film or a metal nitride film. The metal M used to form the metallic material film of the first insertion layer 16 a may be the same as or different from the metal M used to form the metal oxide film of the dielectric layer 18. The first insertion layer 16 a may include, e.g., a ZrO2 film. The first insertion layer 16 a may improve electrical characteristics of the dielectric layer 18, thereby reducing leakage current.
  • The second insertion layer 16 b and the upper metal layer 20 may be formed sequentially on the dielectric layer 18 in the order stated. The second insertion layer 16 b may be formed of the same material used to form the second insertion layer 16 b according to the second embodiment. The second insertion layer 16 b may improve electrical characteristics of the dielectric layer 18, thereby reducing leakage current. The upper metal layer 20 may be formed of the same material used to form the lower metal layer 14.
  • In the semiconductor device 240 according to the third embodiment, the first insertion layer 16 a may be formed in the first position between the lower metal layer 14 and the dielectric layer 18. The second insertion layer 16 b may be formed in the second position between the dielectric layer 18 and the upper metal layer 20. The dielectric layer 18 of the semiconductor device 240 according to the third embodiment may have improved electrical characteristic, thereby reducing leakage current.
  • The semiconductor device 240 according to the third embodiment may include a capacitor including the lower metal layer 14, the first insertion layer 16 a, the dielectric layer 18, the second insertion layer 16 b, and the upper metal layer 20. The capacitor may be used in various integrated circuit semiconductor devices, e.g., DRAM devices.
  • Comparison of the First Embodiment and the First Comparative Embodiment
  • Hereinafter, characteristics of the dielectric layer 18 of the semiconductor device 200 according to the first embodiment, in which the insertion layer 16 a may be formed between the lower metal layer 14 and the dielectric layer 18, will be compared with characteristics of the dielectric layer 18 of a semiconductor device according to the first comparative embodiment. In the first comparative embodiment, the dielectric layer 18 may be formed directly on the lower metal layer 14. In the semiconductor device 200 of the first embodiment, a TiN film may be used as the lower metal layer 14, a ZrO2 film may be used as the insertion layer 16 a, and a ZrO2 film may be used as the dielectric layer 18. In the semiconductor device of the first comparative embodiment, a TiN film may be used as the lower metal layer 14 and a ZrO2 film may be used as the dielectric layer 18.
  • FIGS. 4 and 5 illustrate cross-sectional views of a semiconductor device according to the first comparative embodiment for comparison with the semiconductor device 200 according to the first embodiment. FIGS. 6 and 7 illustrate cross-sectional views of the semiconductor device 200 according to the first embodiment for comparison with the semiconductor device according to the first comparative embodiment.
  • In particular, according to the first comparative embodiment as shown in FIGS. 4 and 5, a dielectric layer 18, e.g., a ZrO2 film, may be formed on a lower metal layer 14, e.g., a TiN film. According to the fabrication process, the lower metal layer 14 may be oxidized by an ozone (O3) oxidant, used to form the dielectric layer 18, to form an interface layer 30, e.g., a TiOx layer or a TiON layer, on the lower metal layer 14. Since the TiOx layer may have many defects, and the TiON layer may have a low bandgap, e.g., about 2.1 eV, electrical characteristics of the dielectric layer 18 may deteriorate.
  • However, according to the first embodiment, a first insertion material layer 15 a may first be formed on the lower metal layer 14 to fabricate the semiconductor device 200. The first insertion material layer 15 a may be formed using, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The first insertion material layer 15 a may, e.g., a metal film, a metal carbide film, or a metal nitride film. The metal film may include, e.g., a zirconium film. The metal carbide film may include, e.g., a zirconium carbide (ZrCx) film. The metal nitride film may include, e.g., a ZrN film. The dielectric layer 18, e.g., a ZrO2 film, may be formed on the insertion material layer 15 a.
  • According to the first embodiment, the first insertion material layer 15 a may be converted to the first insertion layer 16 a, e.g., a ZrO2 film, by an O3 oxidant used during formation of the dielectric layer 18. Thus, the undesirable interface layer 30 of the first comparative embodiment may be avoided. Furthermore, when the first insertion material layer 15 a includes a metal nitride film or a metal carbide film, the first insertion material layer 15 a may be converted to a metal oxide film, a metal nitride film, or a metal oxide nitride film by the O3 oxidant.
  • In the semiconductor device 200 according to the first embodiment, the first insertion material layer 15 a may be preferentially oxidized by the O3 oxidant. Thus, due to insufficient amount of free O3 oxidant, undesirable formation of the interface layer 30 may be prevented. From a thermodynamic point of view, high activation energy may be required for the TiN film of the lower metal layer 14 to be oxidized to TiOx film or TiON film as described above with respect to the first comparative embodiment. However, since low activation energy may be required for the zirconium film of the first insertion material layer 15 a to be converted to ZrO2 film, the zirconium film may be preferentially oxidized by the O3 gas, thereby preventing oxidation of the TiN film of the lower metal layer 14.
  • The first insertion material layer 15 a of the semiconductor device 200 according to the first embodiment may be oxidized, i.e., converted, to the first insertion layer 16 a. In particular, if the metal oxide film, i.e., the ZrO2 film of the dielectric layer 18, and the metallic material film, i.e., the ZrO2 film of the insertion layer 16 a, are the same, a complete interface layer may be formed. Accordingly, characteristics of the dielectric layer 18 may be improved.
  • FIGS. 8 and 9 illustrate cross-sectional views of a semiconductor device according to the first comparative embodiment for comparison with the semiconductor device 200 according to the first embodiment. FIGS. 10 and 11 illustrate cross-sectional views of the semiconductor device 200 according to the first embodiment for comparison with the semiconductor device according to the first comparative embodiment.
  • In particular, according to the first comparative embodiment, the dielectric layer 18, e.g., a ZrO2 film, may be formed on the lower metal layer 14, e.g., a TiN film. A lattice constant of the ZrO2 film of the dielectric layer 18 may be about 5.09 Å. A lattice constant of the TiN film of the lower metal layer 14 may be about 4.32 Å, thereby exhibiting a large lattice constant difference between the dielectric layer 18 and the lower metal layer 14. Furthermore, a crystal structure of the ZrO2 film of the dielectric layer 18 may be different from the crystal structure of the TiN film of the lower metal layer 14.
  • Accordingly, as illustrated in FIG. 8, a seed layer 32 may have low density and non-uniform grain size during an initial stage of deposition of the ZrO2 film of the dielectric layer 18. That is, as illustrated in FIG. 8, the seed layer 32 having low density and non-uniform grain size may be formed on the lower metal layer 14 during the initial stage of deposition of the ZrO2 film of the dielectric layer 18. In FIG. 8, the upper diagram illustrates a plan view; and the lower diagram illustrates a cross-sectional view. In addition, as illustrated in FIG. 9, the ZrO2 film growing from the seed layer may have grains 34 with a non-uniform size; and grain boundaries formed by the grown grains 34 may not be densely formed.
  • In other words, since the seed layer 32 may not be densely formed on the lower metal layer 14 during the initial stage of deposition of the dielectric layer 18, the size of the grains 34 may increase; and voids may exist in the grain boundaries. Thus, the dielectric layer 18 according to the first comparative embodiment may have poor characteristics. Accordingly, electrical characteristics of the dielectric layer 18 may deteriorate during operation of the semiconductor device.
  • On the other hand, the first insertion material layer 15 a may be formed on the lower metal layer 14 in the semiconductor device 200 according to the first embodiment. The first insertion material layer 15 a may include a zirconium film as described with reference to FIG. 6. Then, the dielectric layer 18, e.g., a ZrO2 film, may be formed on the first insertion material layer 15 a, converting the first insertion material layer 15 a to the first insertion layer 16 a as described with reference to FIG. 6.
  • According to the fabrication process, the first insertion material layer 15 a, e.g., the zirconium film, may be oxidized during the deposition of the dielectric layer 18 to form the first insertion layer 16 a and a seed layer 36 as illustrated in FIG. 10. Thus, the seed layer 36 may have high density and uniform size. In FIG. 10, the upper diagram illustrates a cross-sectional view; and the lower diagram illustrates a plan view. As illustrated in FIG. 11, the ZrO2 film growing from the seed layer may have grains 38 with a uniform and relatively small size; and grain boundaries formed by the grown grains 38 may be densely formed.
  • The dielectric layer 18 is not limited to the TiN film and the ZrO2 film, and most suitable metal nitride films and metal oxide film may be used. For example, the method according to an embodiment may also be used when, e.g., a hafnium oxide (HfO2) film is formed on a TiN film or a ZrO2 film is formed on a TaN film.
  • Comparison of the Second Embodiment and the Second Comparative Embodiment
  • Hereinafter, characteristics of the dielectric layer 18 of the semiconductor device 220 according to the second embodiment, in which the second insertion layer 16 b may be formed between the upper metal layer 20 and the dielectric layer 18, will be compared with characteristics of the dielectric layer 18 of a semiconductor device according to the second comparative embodiment, in which the upper metal layer 20 may be formed directly on the dielectric layer 18. In the second embodiment, a TiN film may be used as the upper metal layer 20, a ZrO2 film may be used as the second insertion layer 16 b, and a ZrO2 film may be used as the dielectric layer 18. In the second comparative embodiment, a TiN film may be used as the upper metal layer 20; and a ZrO2 film may be used as the dielectric layer 18
  • FIGS. 12 and 13 illustrate cross-sectional views of the semiconductor device according to the second comparative embodiment for comparison with the semiconductor device 220 according to the second embodiment. FIGS. 14 and 15 illustrate cross-sectional views of the semiconductor device 220 according to the second embodiment for comparison with the semiconductor device according to the second comparative embodiment.
  • In particular, according to the second comparative embodiment as illustrated in FIGS. 12 and 13, an upper metal layer 20, e.g., a TiN film, may be formed on a dielectric layer 18, e.g., a ZrO2 film. According to the fabrication process, an interface layer 30 a, e.g., a ZrON film, a TiOx film, and a TiON film, may be formed on the dielectric layer 18 by, e.g., an ammonia (NH3) nitrating agent, used during formation of the upper metal layer 20 or a reaction between the upper metal layer 20 and the dielectric layer 18. The ZrON film may deteriorate interface characteristics with the upper metal layer 20, the TiOx film may have many defects, and the TiON film may have a low bandgap of, e.g., about 2.1 eV. As a result, the interface layer 30 a may deteriorate electrical characteristics of the dielectric layer 18.
  • On the other hand, a second insertion material layer 15 b may be formed on the dielectric layer 18 to form the semiconductor device 220 according to the second embodiment. The second insertion material layer 15 b may be formed using, e.g., CVD, PVD, or ALD. The second insertion material layer 15 b may include, e.g., a metal film, a metal carbide film, or a metal nitride film. The metal film may include, e.g., a zirconium film. The metal carbide film may include, e.g., a zirconium carbide (ZrCx) film. The metal nitride film may include, e.g., a ZrN film. An upper metal layer 20 may be formed on the second insertion material layer 15 b.
  • According to the fabrication process, the second insertion material layer 15 b may be converted to the second insertion layer 16 b, e.g., the ZrN film, by the NH3 nitrating agent used during formation of the upper metal layer 20. The second insertion layer 16 b may function as the upper metal layer 20 without adversely influencing the dielectric layer 18, unlike in the second comparative embodiment. Since the dielectric layer 18 of the semiconductor device 220 according to the second embodiment may not be damaged while the upper metal layer 20 is formed, the interface between the dielectric layer 18 and the upper metal layer 20 may have excellent characteristics when compared with the second comparative embodiment. Thus, the dielectric layer 18 may have excellent electrical characteristics.
  • Comparison of the Third Embodiment and the First and Second Comparative Embodiments
  • As described above, the semiconductor device 240 according to the third embodiment may be a combination of the semiconductor device 200 according to the first embodiment and the semiconductor device 220 according to the second embodiment. Thus, the semiconductor device 240 according to the third embodiment may have the beneficial effects of both the first and second embodiments. The semiconductor device 240 according to the third embodiment may have better electrical characteristics than those of the first and second comparative embodiments.
  • Hereinafter, electrical characteristics of the dielectric layer 18 according to the embodiments will be compared with those according to the first and second comparative embodiments.
  • FIG. 16 illustrates a graph showing voltage and leakage current of the semiconductor device according to the first comparative embodiment. FIG. 17 illustrates a graph showing voltage and leakage current of the semiconductor device 200 according to the first embodiment.
  • Particularly, FIG. 16 illustrates a graph showing positive voltage and leakage current of a capacitor fabricated by forming a TiN film lower metal layer 14 on a semiconductor substrate 10, forming a ZrO2 film dielectric layer 18 on the lower metal layer 14 to a thickness of 70 Å, and forming an upper metal layer 20 on the dielectric layer 18. In the capacitor of the first comparative embodiment, when a reference leakage current is 10−7 A/cm2 at 1 V, characteristics of the dielectric layer 18 may be damaged after voltages ranging from 0 V to 3.3 V are applied 16 times to the dielectric layer 18, and thus a low leakage current is not restored.
  • FIG. 17 illustrates a graph showing voltage and leakage current of a capacitor fabricated by forming a TiN film lower metal layer 14 on a semiconductor substrate 10, forming a ZrO2 film first insertion layer 16 a on the lower metal layer 14 to a thickness of 10 Å, forming a ZrO2 film dielectric layer 18 on the first insertion layer 16 a to a thickness of 70 Å, and forming an upper metal layer 20 on the dielectric layer 18 as in the first embodiment. In the capacitor of the first embodiment, when a reference leakage current is 10−7 A/cm2 at 1 V, characteristics of the dielectric layer 18 are maintained after voltages of about 0 V to about 3.3 V are applied 50 times to the dielectric layer 18; and thus the leakage current remains in a normal range. When comparing the results of FIGS. 16 and 17, it may be seen that electrical characteristics of the dielectric layer 18 of the capacitor according to the first embodiment are better than those according to the first comparative embodiment.
  • FIG. 18 illustrates a graph showing voltage and leakage current of the semiconductor device according to the second comparative embodiment. FIG. 19 illustrates a graph showing voltage and leakage current of the semiconductor device 220 according to the second embodiment.
  • Particularly, FIG. 18 illustrates a graph showing negative voltage and leakage current of a capacitor fabricated by forming a TiN film lower metal layer 14 on a semiconductor substrate 10, forming a ZrO2 film dielectric layer 18 on the lower metal layer 14 to a thickness of 70 Å, and forming an upper metal layer 20 directly on the dielectric layer 18. In the capacitor of the second comparative embodiment, when a reference leakage current is 10−7 A/cm2 at −1 V, characteristics of the dielectric layer 18 are damaged after voltages ranging from 0 V to −3.8 V are applied 25 times, and thus a low leakage current is not restored.
  • FIG. 19. illustrates a graph showing negative voltage and leakage current of a capacitor fabricated by forming a TiN film lower metal layer 14 on a semiconductor substrate 10, forming a ZrO2 film dielectric layer 18 on the lower metal layer 14 to a thickness of 70 Å, forming a ZrO2 film second insertion layer 16 b on the dielectric layer 18 to a thickness of 10 Å, and forming an upper metal layer 20 on the second insertion layer 16 b as in the second embodiment. In the capacitor of the second embodiment, when a reference leakage current is 10−7 A/cm2 at −1 V, characteristics of the dielectric layer 18 are maintained after voltages ranging from 0 V to −3.8 V are applied 48 times to the dielectric layer 18; and thus the leakage current remains in a normal range. When comparing the results of FIGS. 18 and 19, it may be seen that electrical characteristics of the dielectric layer 18 of the capacitor according to the second embodiment are better than those according to the second comparative embodiment.
  • Application Embodiment
  • The capacitors fabricated according to the first, second, and/or third embodiments may be applied to semiconductor devices, e.g., DRAM devices. A DRAM device will be briefly described herein.
  • FIG. 20 illustrates a circuit diagram of a unit cell of a DRAM device including a transistor according to an embodiment.
  • A unit cell of a DRAM device may have various shapes. For example, the unit cell according to an embodiment may include a transistor 110 and a capacitor 130. The transistor 110 may be connected to a word line 170. A bit line 150 may be connected to a source/drain region of the transistor 110. The capacitor 130 according to Embodiments 1 to 3 described above may be connected to another source/drain region of the transistor 110. That is, the capacitor fabricated according to Embodiments 1 to 3 may be applied to a DRAM device.
  • The semiconductor device, e.g., the DRAM device, according to an embodiment may be applied to various fields. A DRAM chip may be fabricated by packaging the semiconductor device, e.g., the DRAM device, according to an embodiment. The DRAM chip may be applied to various fields, and examples will be described herein.
  • FIG. 21 illustrates a plan view of a memory module 500 using DRAM chips 50 to 58, according to an embodiment.
  • In particular, the DRAM chips 50 to 58 may be fabricated by respectively packaging the semiconductor devices according to an embodiment. The DRAM chips 50 to 58 may be applied to the memory module 500. In the memory module 500, the DRAM chips 50 to 58 may be attached to a module substrate 501. The memory module 500 may include connectors 502 which may be inserted into sockets of a motherboard, at an end of the module substrate 501 and ceramic decoupling capacitors 59 on the module substrate 501. However, the memory module 500 is not limited to the shape shown in FIG. 21 and thus may have various shapes.
  • FIG. 22 illustrates a block diagram of an electronic system 600 using a DRAM chip 512 according to an embodiment.
  • In particular, the electronic system 600 may be a computer. The electronic system 600 may include a central processing unit (CPU) 505, a peripheral device, e.g., a floppy disc drive 507 and/or a compact disc read-only memory (CD-ROM) drive 509, input and output devices 508 and 510, the DRAM chip 512, a ROM chip 514, etc. Control signals or data may be transferred among the elements via a communication channel 511. The DRAM chip 512 may be replaced by the memory module 500 including the DRAM chips 50 to 58 as described with reference to FIG. 21.
  • A semiconductor device according to an embodiment may be fabricated by forming an insertion layer between a lower metal layer and a dielectric layer. When the insertion layer is formed between the lower metal layer and the dielectric layer, the formation of an interface caused by the oxidation of the lower metal layer during the formation of the dielectric layer may be prevented. Thus, characteristics of the dielectric layer may be improved, since the insertion layer may function as a seed layer for the formation of the dielectric layer.
  • Furthermore, the semiconductor device according to an embodiment may be fabricated by forming an insertion layer between the dielectric layer and an upper metal layer. When the insertion layer is formed between the dielectric layer and the upper metal layer, an interface layer may not be formed on the dielectric layer, and the dielectric layer may not be damaged. As a result, characteristics of the dielectric layer of the semiconductor device, including its electrical characteristics, may be improved.
  • As for drawbacks of other semiconductor devices and their fabrication processes, if the dielectric layer is formed at a high temperature, the high temperature may adversely affect the resultant semiconductor devices. Additionally, if heat-treatment or the oxygen curing is performed after deposition of the dielectric layer, a plurality of interface layers may be formed on a lower film under the dielectric layer. The interface layers may deteriorate electrical characteristics of the dielectric layer during the operation of the semiconductor devices, thereby increasing undesirable leakage current.
  • Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims (10)

  1. 1. A semiconductor device, comprising:
    a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate; and
    an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer,
    wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
  2. 2. The semiconductor device as claimed in claim 1, wherein the insertion layer is disposed between the dielectric layer and the lower metal layer.
  3. 3. The semiconductor device as claimed in claim 1, wherein the insertion layer is disposed between the dielectric layer and the upper metal layer.
  4. 4. The semiconductor device as claimed in claim 1, wherein the insertion layer is disposed between the dielectric layer and the lower metal layer and between the dielectric layer and the upper metal layer.
  5. 5. The semiconductor device as claimed in claim 1, wherein the metal oxide film and the metallic material film each independently include at least one of Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and Ac.
  6. 6. The semiconductor device as claimed in claim 5, wherein the metal oxide film is in the form of MOx, wherein M is a metal, O is oxygen, and x is about 0.5 to about 4.
  7. 7. The semiconductor device as claimed in claim 1, wherein a metal used to form the metallic material film of the insertion layer is the same as a metal used to form the metal oxide film of the dielectric layer.
  8. 8. The semiconductor device as claimed in claim 1, wherein the metallic material film of the insertion layer is a metal oxide film.
  9. 9. The semiconductor device as claimed in claim 1, wherein the metallic material film of the insertion layer is a metal nitride film.
  10. 10-17. (canceled)
US12585030 2009-02-06 2009-09-01 Semiconductor device having dielectric layer with improved electrical characteristics and associated methods Abandoned US20100200950A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR20090009875A KR101607263B1 (en) 2009-02-06 2009-02-06 Methods for fabricating semicondcutor devices capable of incresing electrical characteristics of dielectric layer
KR10-2009-0009875 2009-02-06

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13424825 US8859383B2 (en) 2009-02-06 2012-03-20 Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics
US14510302 US20150031186A1 (en) 2009-02-06 2014-10-09 Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13424825 Division US8859383B2 (en) 2009-02-06 2012-03-20 Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics

Publications (1)

Publication Number Publication Date
US20100200950A1 true true US20100200950A1 (en) 2010-08-12

Family

ID=42539728

Family Applications (3)

Application Number Title Priority Date Filing Date
US12585030 Abandoned US20100200950A1 (en) 2009-02-06 2009-09-01 Semiconductor device having dielectric layer with improved electrical characteristics and associated methods
US13424825 Active 2029-10-07 US8859383B2 (en) 2009-02-06 2012-03-20 Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics
US14510302 Abandoned US20150031186A1 (en) 2009-02-06 2014-10-09 Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics

Family Applications After (2)

Application Number Title Priority Date Filing Date
US13424825 Active 2029-10-07 US8859383B2 (en) 2009-02-06 2012-03-20 Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics
US14510302 Abandoned US20150031186A1 (en) 2009-02-06 2014-10-09 Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics

Country Status (3)

Country Link
US (3) US20100200950A1 (en)
KR (1) KR101607263B1 (en)
CN (1) CN101800220A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8815695B2 (en) 2012-12-27 2014-08-26 Intermolecular, Inc. Methods to improve leakage for ZrO2 based high K MIM capacitor
US20160043088A1 (en) * 2014-08-06 2016-02-11 International Business Machines Corporation Non-volatile memory device employing a deep trench capacitor
US20170316952A1 (en) * 2016-04-29 2017-11-02 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Transition metal-bearing capping film for group iii-nitride devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101607263B1 (en) * 2009-02-06 2016-03-30 삼성전자주식회사 Methods for fabricating semicondcutor devices capable of incresing electrical characteristics of dielectric layer
US8410535B2 (en) * 2011-04-25 2013-04-02 Nanya Technology Corporation Capacitor and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5702970A (en) * 1995-06-26 1997-12-30 Hyundai Electronics Industries Co., Ltd. Method for fabricating a capacitor of a semiconductor device
US20060006449A1 (en) * 2004-07-06 2006-01-12 Jeong Yong-Kuk Semiconductor integrated circuit devices having a hybrid dielectric layer and methods of fabricating the same
US20060124987A1 (en) * 2002-12-30 2006-06-15 Samsung Electronics Co., Ltd Capacitor of semiconductor device and method for manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100360150B1 (en) 1995-06-30 2002-10-25 주식회사 하이닉스반도체 Method for forming capacitor of semiconductor device
US6201276B1 (en) * 1998-07-14 2001-03-13 Micron Technology, Inc. Method of fabricating semiconductor devices utilizing in situ passivation of dielectric thin films
JP2004079931A (en) 2002-08-22 2004-03-11 Hitachi Kokusai Electric Inc Manufacturing method for semiconductor device
JP2004119832A (en) 2002-09-27 2004-04-15 Toshiba Corp Semiconductor device
CN1624869A (en) 2003-04-17 2005-06-08 国际商业机器公司 Semiconductor device and forming method thereof
US6940117B2 (en) 2002-12-03 2005-09-06 International Business Machines Corporation Prevention of Ta2O5 mim cap shorting in the beol anneal cycles
KR100604845B1 (en) * 2004-04-12 2006-07-26 삼성전자주식회사 Metal-Insulator-Metal capacitor having insulating layer with nitrogen and method for manufacturing the same
KR100631949B1 (en) 2004-07-23 2006-10-04 주식회사 하이닉스반도체 Method for forming capacitor of semiconductor device
KR101607263B1 (en) * 2009-02-06 2016-03-30 삼성전자주식회사 Methods for fabricating semicondcutor devices capable of incresing electrical characteristics of dielectric layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5702970A (en) * 1995-06-26 1997-12-30 Hyundai Electronics Industries Co., Ltd. Method for fabricating a capacitor of a semiconductor device
US20060124987A1 (en) * 2002-12-30 2006-06-15 Samsung Electronics Co., Ltd Capacitor of semiconductor device and method for manufacturing the same
US20060006449A1 (en) * 2004-07-06 2006-01-12 Jeong Yong-Kuk Semiconductor integrated circuit devices having a hybrid dielectric layer and methods of fabricating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8815695B2 (en) 2012-12-27 2014-08-26 Intermolecular, Inc. Methods to improve leakage for ZrO2 based high K MIM capacitor
US20160043088A1 (en) * 2014-08-06 2016-02-11 International Business Machines Corporation Non-volatile memory device employing a deep trench capacitor
US9754945B2 (en) * 2014-08-06 2017-09-05 Globalfoundries Inc. Non-volatile memory device employing a deep trench capacitor
US20170316952A1 (en) * 2016-04-29 2017-11-02 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Transition metal-bearing capping film for group iii-nitride devices

Also Published As

Publication number Publication date Type
KR101607263B1 (en) 2016-03-30 grant
CN101800220A (en) 2010-08-11 application
US20150031186A1 (en) 2015-01-29 application
US20120178254A1 (en) 2012-07-12 application
US8859383B2 (en) 2014-10-14 grant
KR20100090534A (en) 2010-08-16 application

Similar Documents

Publication Publication Date Title
US6787413B2 (en) Capacitor structure forming methods
US5882946A (en) High-permittivity thin film capacitor for a semiconductor integrated circuit and a fabrication method thereof
US6461931B1 (en) Thin dielectric films for DRAM storage capacitors
US6958265B2 (en) Semiconductor device with nanoclusters
US20030234417A1 (en) Dielectric layers and methods of forming the same
US20040141390A1 (en) Capacitor of semiconductor device and method for manufacturing the same
US20020093046A1 (en) Semiconductor device and its production process
EP0821415A2 (en) A capacitor and method of manufacture thereof
US20060263977A1 (en) Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities
US20040018747A1 (en) Deposition method of a dielectric layer
US20020190294A1 (en) Semiconductor device having a thin film capacitor and method for fabricating the same
US6743681B2 (en) Methods of Fabricating Gate and Storage Dielectric Stacks having Silicon-Rich-Nitride
US7217643B2 (en) Semiconductor structures and methods for fabricating semiconductor structures comprising high dielectric constant stacked structures
US7091089B2 (en) Method of forming a nanocluster charge storage device
US20050280069A1 (en) Semiconductor device and method of manufacturing the same
US6403441B1 (en) Method for fabricating storage capacitor using high dielectric constant material
US20070004154A1 (en) Dielectric structure in nonvolatile memory device and method for fabricating the same
US20010024853A1 (en) High charge storage density integrated circuit capacitor
US20040157391A1 (en) Capacitor of semiconductor memory device that has composite Al2O3/HfO2 dielectric layer and method of manufacturing the same
US20060244084A1 (en) Semiconductor devices having polymetal gate electrodes and methods of manufacturing the same
JP2006005006A (en) Nonvolatile semiconductor memory
US20010015453A1 (en) Capacitor forming methods
US20090309187A1 (en) Semiconductor Device and Method of Fabricating the Same
JP2001267566A (en) Multilayered dielectric stack and its method
US20080164582A1 (en) Semiconductor devices and methods of manufacture thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, YOUN-SOO;CHOI, JAE-HYOUNG;CHO, KYU-HO;AND OTHERS;REEL/FRAME:023222/0398

Effective date: 20090819