US20150008519A1 - Power integrated device having surface corrugations - Google Patents
Power integrated device having surface corrugations Download PDFInfo
- Publication number
- US20150008519A1 US20150008519A1 US14/492,243 US201414492243A US2015008519A1 US 20150008519 A1 US20150008519 A1 US 20150008519A1 US 201414492243 A US201414492243 A US 201414492243A US 2015008519 A1 US2015008519 A1 US 2015008519A1
- Authority
- US
- United States
- Prior art keywords
- depressions
- region
- projections
- conduction region
- conduction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 abstract description 24
- 230000008569 process Effects 0.000 abstract description 21
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000012545 processing Methods 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- 210000003323 beak Anatomy 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0869—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Definitions
- the present invention relates to a process for manufacturing integrated power devices having surface corrugations and to an integrated power device having surface corrugations.
- the corrugations can be defined by projections and depressions that extend parallel to one another in a direction parallel to a line that joins the source regions and the drain regions. Projections and depressions are hence parallel also to the direction of flow of the current.
- the corrugations are made as follows.
- a semiconductor wafer in which the devices are to be formed is selectively etched with a mask to form parallel trenches, in a direction that joins a first region, intended to accommodate source regions, and a second region, intended to accommodate drain regions.
- Parallel projections are defined between adjacent trenches.
- a channel region, designed for conduction, extends in a band that traverses the projections and the trenches.
- the surface of the wafer in the channel region is defined by a succession of parallel portions and of oblique portions.
- the profile of a section transversely to the projections and to the trenches is hence corrugated, and its development is greater than that of a plane surface without corrugations.
- An aim is to provide a process for manufacturing integrated power devices and an integrated power device that enables the limitations described to be overcome, in particular preserving the quality of the semiconductor material and offering an accurate control of the surface conformation.
- a process for manufacturing a power integrated device comprising, in a semiconductor body, forming projections and depressions which extend in a first direction and are arranged alternated in succession in a second direction, transverse to the first direction, forming at least a first conduction region and a second conduction region, so as to define a current flow direction between the first conduction region and the second conduction region parallel to the first direction, along the projections and the depressions, wherein forming projections and depressions comprises selectively oxidizing first portions of the semiconductor body which extend in the first direction and correspond to respective depressions.
- a power integrated device comprising, a semiconductor body, having projections and depressions, which extend in a first direction and are arranged alternated in succession in a second direction, transverse to the first direction, a first conduction region and a second conduction region, arranged so as to define a current flow direction between the first conduction region and the second conduction region parallel to the first direction, along the projections and the depressions; wherein ridges of the projections and a bottom of adjacent depressions are connected through walls having a rounded profile.
- FIG. 1 is a top plan view of a semiconductor wafer in an initial step of a process for manufacturing integrated power devices according to one embodiment of the present invention
- FIG. 2 is a cross section through the wafer of FIG. 1 , taken along the line II-II of FIG. 1 ;
- FIGS. 3-5 show the wafer of FIG. 2 in subsequent steps of the manufacturing process
- FIG. 6 is a top plan view of the wafer of FIG. 5 ;
- FIG. 7 is a cross section through the wafer of FIG. 6 , taken along the line VII-VII of FIG. 6 , in a subsequent processing step;
- FIG. 8 is a cross section through the wafer of FIG. 6 , taken along the line VIII-VIII of FIG. 6 , in the processing step of FIG. 7 ;
- FIG. 9 is a cross section through the wafer of FIG. 6 , taken along the line IX-IX of FIG. 6 , in the processing step of FIG. 7 ;
- FIG. 10 is a cross section through the wafer of FIG. 6 , taken along the line X-X of FIG. 6 , in the processing step of FIG. 7 ;
- FIG. 11 is a perspective view three quarters from above of a portion of the wafer of FIGS. 7-10 , in a subsequent processing step;
- FIG. 12 is a top plan view of the wafer of FIG. 11 , in a subsequent processing step;
- FIG. 13 is a cross section through the wafer of FIG. 12 , taken along the line XIII-XIII of FIG. 12 , in a subsequent processing step;
- FIG. 14 is a cross section through the wafer of FIG. 12 , taken along the line XIV-XIV of FIG. 12 , in the processing step of FIG. 13 ;
- FIG. 15 shows the view of FIG. 13 in a subsequent processing step
- FIG. 16 shows the view of FIG. 14 in a subsequent processing step
- FIG. 17 is a perspective view three quarters from above of a portion of the wafer of FIGS. 15 and 16 , in a subsequent processing step;
- FIG. 18 shows the view of FIG. 15 , which represents an integrated power device according to one embodiment
- FIG. 19 shows the view of FIG. 16 , which represents an integrated power device according to a further embodiment
- FIG. 20 is a top plan view of a die obtained by dicing the wafer of FIGS. 18 and 19 and incorporating the device of FIG. 18 and the device of FIG. 19 ;
- FIG. 21 is a simplified block diagram of an electronic system incorporating an integrated device according to one embodiment.
- a semiconductor wafer designated by 1 , comprises a substrate 2 of semiconductor material (for example, monocrystalline silicon of a P type), in which a low-voltage region 3 , a first power region 4 , and a second power region 5 are defined.
- semiconductor material for example, monocrystalline silicon of a P type
- low-voltage insulating structures 7 a of a STI (Shallow-Trench-Insulation) type, which delimit low-power active areas 6 a, are initially made in the low-voltage region 3 .
- insulating power structures 7 b are made, once again of an STI type, which delimit active power areas 6 b.
- a first pad-oxide layer 8 is then grown on the wafer 1 and a first silicon-nitride layer 9 is subsequently laid ( FIG. 2 ).
- a resist mask 10 is formed on the first silicon-nitride layer 9 and presents, on the first power region 4 and on the second power region 5 , elongated windows 12 , which extend mutually parallel in a direction perpendicular to the plane of FIG. 1 , in a first direction L (see in particular FIG. 1 ).
- the windows 12 are adjacent to one another and are arranged in succession in a second direction W, perpendicular to the first direction L, so as to form a grid.
- the low-voltage region 3 is internally protected by the resist mask 10 .
- the first silicon-nitride layer 9 and the first pad-oxide layer 8 are selectively etched through the resist mask 10 to form a shaping hard mask 14 having apertures 13 that correspond to respective windows 12 .
- a surface 2 a of the substrate 2 thus remains exposed through the windows 12 of the resist mask 10 and the apertures 13 in the first silicon-nitride layer 9 and in the first pad-oxide layer 8 .
- the resist mask 10 is then removed.
- LOCOS sacrificial structures 15 are obtained selectively in the exposed regions of the substrate 2 .
- the LOCOS sacrificial structures 15 grow in part on top of and in part inside the substrate 2 .
- Surface portions of the substrate 2 (designated by 2 b in FIG. 1 ) are hence converted into silicon oxide.
- the LOCOS sacrificial structures 15 penetrate, with characteristic lateral beaks, in part underneath the first silicon-nitride layer 9 at the margins of the apertures 13 .
- the LOCOS sacrificial structures 15 may have, for example, a thickness of between 300 nm and 400 nm.
- the surface 2 a of the substrate 2 is modified because part of the silicon surface exposed through the apertures 13 is converted into oxide.
- the surface 2 a has depressions 18 , where the LOCOS sacrificial structures 15 are present, and projections 17 , between adjacent depressions 18 .
- the projections 17 and the depressions 18 extend in the first direction L and alternate with one another in the second direction W.
- the shape of the depressions and the profile of the surface 2 a in the second direction W are determined by the shape of the LOCOS sacrificial structures 15 and can be controlled precisely.
- the depth of the depressions 18 with respect to the projections 17 is determined by the degree of penetration of the LOCOS sacrificial regions 15 within the substrate 2 .
- the thickness of the LOCOS sacrificial structures 15 and the extension and inclination of the lateral beaks are determined by the initial thickness of the first pad-oxide layer 8 , by the duration of the LOCOS step, and by the temperature.
- the ridges 17 a of the projections 17 , and the bottom 18 a of the adjacent depressions 18 are connected through walls 19 having a rounded profile.
- the LOCOS sacrificial structures 15 , the first silicon-nitride layer 9 and the first pad-oxide layer 8 are then removed from the first power region 4 and the second power region 5 .
- the LOCOS sacrificial structures 15 are etched with hydrofluoric acid so as to be removed completely.
- the structure shown in FIG. 4 is thus obtained, where the corrugations formed by the succession of projections 17 and depressions 18 are evident.
- a second pad-oxide layer 20 and a second silicon-nitride layer 21 are deposited in succession on the entire wafer 1 .
- the second pad-oxide layer 20 and the second silicon-nitride layer 21 are then selectively etched to provide a second field hard mask 24 having apertures 23 on the first power region 4 .
- the etch with which the field hard mask 24 is defined proceeds so as to form recesses in the substrate 2 . In this way, where necessary, it is possible to exploit the so-called “recessed LOCOS” technique and obtain LOCOS structures for field insulation, which extend prevalently within the substrate 2 and have a reduced projecting portion.
- the apertures 23 are elongated in shape and extend parallel to one another in the second direction W.
- the apertures 23 thus extend transversely to the projections 17 and to the depressions 18 and expose underlying portions of the surface 2 a of the substrate 2 . In this step, the low-voltage region 3 and the second power region 5 remain protected.
- a new LOCOS thermal oxidation is carried out to form, through the apertures 23 of the second field hard mask 24 , LOCOS field-oxide structures 25 that run mutually parallel, transversely to the projections 17 and depressions 18 .
- portions 2 c of the substrate 2 ( FIG. 6 ) exposed through the apertures 23 are converted into oxide, which moreover grows in part on top of the substrate 2 .
- the first power region 4 which is the only one to be modified in this step, assumes the appearance illustrated in FIG. 11 .
- body, source, and drain implantations are carried out in the substrate 2 using masks (not shown).
- body wells 27 (of a P type), source regions 28 (of an N type), source-contact regions 29 (of an N+ type), and drain-contact regions 30 (of an N+ type) are made in the first power region 4 and in the second power region 5 ; and body wells 31 (of a P type), source regions 32 (of an N type), source-contact regions 33 (of an N+ type), and drain-contact regions 34 (of an N+ type) are made in the second power region 5 .
- the source region 28 is defined centrally between adjacent LOCOS field-oxide structures 25 , at a distance there from, and extends in the second direction W, transversely to the projections 17 and depressions 18 .
- the source-contact region 29 is nested in the source region 28 .
- the drain-contact regions 30 are provided alongside the LOCOS field-oxide structures 25 , on the side opposite to the source region 28 .
- the source region 32 extends in the second direction W, transversely to the projections 17 and depressions 18 , and the drain-contact regions 34 are made alongside the source region 28 .
- the source-contact region 33 is nested in the source region 32 .
- CMOS circuit components 24 are carried out where required also in the low-voltage region 3 to provide CMOS circuit components 24 , which, however, are for simplicity illustrated only schematically, through circuit symbols.
- the sacrificial oxide layer 26 is then removed, as shown in FIGS. 15 and 16 , and in its place a thin gate-oxide layer 35 is grown, on which a polysilicon layer 36 is deposited.
- the polysilicon layer 36 and the gate-oxide layer 35 are defined to form, respectively, gate-oxide regions 37 and gate regions 38 , in the first power region 4 , and to form, respectively, gate-oxide regions 39 and gate regions 40 , in the second power region 5 .
- the gate regions 38 and the gate regions 40 enable selective coupling and decoupling of the source region 28 and the drain regions 30 and, respectively, the source region 32 and the drain regions 34 .
- the gate-oxide regions 37 extend directly on the substrate 2 between the source region 28 , which they slightly overlap, and respective LOCOS field-oxide structures 25 .
- the gate regions 38 lie in part on respective gate-oxide regions 37 until they come to be arranged on top of the source region 28 and, in part, on respective LOCOS field-oxide structures 25 .
- the portions of the gate regions 37 that extend on the LOCOS field-oxide structures 25 form so-called “field plates”, which in use modify the biasing conditions in the substrate 2 , increasing the reverse breakdown voltage of the junction between the source region 28 and the body region 27 .
- the process is completed by standard manufacturing steps, as shown in FIGS. 18 and 19 .
- the following are provided: a dielectric layer 43 ; source contacts 45 , gate contacts 46 , and drain contacts 47 in the first power region 4 ; source contacts 50 , gate contacts 51 , and drain contacts 52 in the second power region 5 ; metallization lines (not illustrated); and a passivation layer 53 .
- the CMOS components 24 are completed.
- a power device 55 ( FIG. 18 ), which in the embodiment described is a lateral N-channel DMOS transistor arranged in part on the active area and in part on the field insulation (field plates on the LOCOS field-oxide structures 25 ).
- a power device 57 is formed fully on the active area ( FIG. 19 , also in this case a lateral N-channel DMOS transistor).
- the wafer 1 is cut into dice 60 , each of which comprises low-voltage CMOS devices 24 , a power device 55 in the first power region 5 , and a power device 57 in the second power region 5 .
- the process described advantageously enables provision of surface corrugations in conduction regions of integrated power devices and an increase in the section available for conduction, without, however, degrading the quality of the semiconductor material and hence the levels of performance.
- the corrugations are defined by the succession of projections 17 and depressions 18 in the first power region 4 and in the second power region 5 .
- the current flows in use from the respective source region to the respective drain regions in the first direction L, parallel to the corrugations, when the source region and the drain regions are coupled as a result of the biasing of the respective gate regions.
- the cross section useful for conduction is greater than in the case of planar devices.
- the use of the LOCOS technique to form the corrugations enables to preserve the quality of the semiconductor material at the surface of the substrate 1 .
- Thermally oxidizing in fact, converts the semiconductor material gradually and penetrates in depth in a uniform way.
- the LOCOS sacrificial structures are selectively removed, without damaging the semiconductor material, which remains substantially unaltered.
- Direct removal of semiconductor material is instead aggressive and produces irregularities and imperfections, so much so that an oxidation is frequently necessary subsequent to etching in order to restore the surface of the semiconductor material. In the process described, it is not necessary to carry out an oxidation after formation of the corrugations.
- LOCOS oxidation enables precise determination of the shape and extension of the LOCOS sacrificial structures and hence also of the profile of the corrugations.
- the desired profile can be obtained by controlling the thickness of the initial pad-oxide layer and the temperature and duration of the thermally oxidizing.
- the process described enables making both fully-on-active power devices and devices with gate regions that extend on the field oxide (field plates).
- the process is compatible with the preliminary provision of insulating structures of an STI type, but does not necessarily call for such structures.
- the process can be exploited for integrating power devices and low-voltage devices with any type of CMOS technology.
- CMOS devices obtained with process sub-0.35- ⁇ m technology as a rule require an insulation of an STI type for low-voltage devices.
- the process flow is substantially the one already described. Initially, the STI structures are formed in the low-voltage region and in the power regions, where necessary. Once the STI structures have been completed, the LOCOS technique is used to create the corrugations in the power regions and, if necessary, field-insulation structures.
- CMOS devices obtained with process technology equal to or higher than 0.35 ⁇ m use, also in the low-power region, insulating structures of a LOCOS type instead of an STI type. In this case, the process is simplified.
- the creation of LOCOS insulating structures does not in fact entail steps of planarization, which are instead necessary to provide STI insulating structures and should necessarily be carried out before forming the corrugations, for obvious reasons.
- the low-voltage LOCOS insulating structures are formed together with the power LOCOS insulating structures, after formation of the corrugations, as described previously.
- the system 100 may comprise a controller 110 , an input/output (I/O) device 120 (for example, a keyboard or a screen), a microelectromechanical device 130 , a wireless interface 140 , and a memory 160 , of a volatile or non-volatile type, coupled together through a bus 150 .
- I/O input/output
- a microelectromechanical device 130 for example, a keyboard or a screen
- a wireless interface 140 for example, a keyboard or a screen
- a memory 160 of a volatile or non-volatile type, coupled together through a bus 150 .
- a battery 180 can be used for supplying the system 100 . It is to be noted that the scope of the present invention is not necessarily limited to the embodiments having one or all of the devices listed.
- the microelectromechanical device 130 comprises a microstructure 133 and an ASIC (application-specific integrated circuit) device 135 , dedicated to driving and control of the microstructure 133 and, possibly, to detection of quantities that can be measured by means of the microstructure 133 .
- the integrated device 135 comprises low-voltage CMOS components and power components integrated in one and the same semiconductor die and is provided according to what has been described with reference to FIGS. 1-19 .
- the microelectromechanical device 130 is a microelectromechanical sensor, such as, for example, an accelerometer, a gyroscope, a pressure sensor, a microphone.
- the microelectromechanical device 130 is a micro-actuator.
- the controller 110 may comprise, for example, one or more microprocessors, microcontrollers, and the like.
- the I/O device 120 can be used for generating a message.
- the system 100 can use the wireless interface 140 for transmitting and receiving messages to and from a wireless communications network with a radiofrequency (RF) signal.
- wireless interface may comprise an antenna, or a wireless transceiver, such as a dipole antenna, even though the scope of the present invention is not limited from this point of view.
- the I/O device 120 can provide a voltage representing what is stored either in the form of digital output (if digital information has been stored) or in the form of analog output (if analog information has been stored).
- the system 100 can be used in apparatuses such as, for example, a palmtop computer (personal digital assistant, PDA), a laptop computer or portable computer, possibly with wireless capacity, a cell phone, a messaging device, a digital music player, a digital camera, or other devices.
- a palmtop computer personal digital assistant, PDA
- PDA personal digital assistant
- laptop computer laptop computer or portable computer, possibly with wireless capacity
- cell phone a cell phone
- messaging device a digital music player
- digital camera a digital camera
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.
Description
- This application is a divisional from U.S. patent application Ser. No. 13/162,951 filed Jun. 17, 2011, which claims the priority benefit of Italian Application for Patent No. TO2010A000521, filed on Jun. 17, 2010, which are hereby incorporated by reference to the maximum extent allowable by law.
- 1. Field of the Invention
- The present invention relates to a process for manufacturing integrated power devices having surface corrugations and to an integrated power device having surface corrugations.
- 2. Discussion of the Related Art
- As is known, integrated power devices should frequently meet severe requirements as regards both the maximum current and the reverse breakdown voltage. These requirements necessitate providing devices of considerable dimensions, which contrasts with the increasingly felt need to reduce the area occupied. The dimensions of power devices are particularly critical when also low-voltage devices are integrated in one and the same die. In these cases, in fact, more than 70% of the area available can be occupied by power devices.
- For power devices there is hence posed the problem of obtaining a large area available for conduction, without sacrificing the overall dimensions.
- It has been proposed to provide surface corrugations in the active areas so as to extend the conduction surface with respect to a plane surface with the same footprint.
- In a lateral DMOS transistor, for example, the corrugations can be defined by projections and depressions that extend parallel to one another in a direction parallel to a line that joins the source regions and the drain regions. Projections and depressions are hence parallel also to the direction of flow of the current.
- The corrugations are made as follows.
- Before the body, source, and drain implantations are carried out, as well as that of the gate region, a semiconductor wafer in which the devices are to be formed is selectively etched with a mask to form parallel trenches, in a direction that joins a first region, intended to accommodate source regions, and a second region, intended to accommodate drain regions. Parallel projections are defined between adjacent trenches. A channel region, designed for conduction, extends in a band that traverses the projections and the trenches.
- The surface of the wafer in the channel region is defined by a succession of parallel portions and of oblique portions. The profile of a section transversely to the projections and to the trenches is hence corrugated, and its development is greater than that of a plane surface without corrugations.
- In known devices, however, the semiconductor surface in the electrically active region is deteriorated by the etches made to form the corrugations. Furthermore, the profile of the corrugations can be controlled only in a rather approximate way. Consequently, as a whole, the yield of the manufacturing processes is not satisfactory, and the effective levels of performance of the devices can easily depart from the nominal values.
- An aim is to provide a process for manufacturing integrated power devices and an integrated power device that enables the limitations described to be overcome, in particular preserving the quality of the semiconductor material and offering an accurate control of the surface conformation.
- According to an embodiment, there is provided a process for manufacturing a power integrated device comprising, in a semiconductor body, forming projections and depressions which extend in a first direction and are arranged alternated in succession in a second direction, transverse to the first direction, forming at least a first conduction region and a second conduction region, so as to define a current flow direction between the first conduction region and the second conduction region parallel to the first direction, along the projections and the depressions, wherein forming projections and depressions comprises selectively oxidizing first portions of the semiconductor body which extend in the first direction and correspond to respective depressions.
- According to another embodiment, there is provided a power integrated device comprising, a semiconductor body, having projections and depressions, which extend in a first direction and are arranged alternated in succession in a second direction, transverse to the first direction, a first conduction region and a second conduction region, arranged so as to define a current flow direction between the first conduction region and the second conduction region parallel to the first direction, along the projections and the depressions; wherein ridges of the projections and a bottom of adjacent depressions are connected through walls having a rounded profile.
- For a better understanding, some embodiments will now be described, purely by way of non-limiting example and with reference to the attached drawings, wherein:
-
FIG. 1 is a top plan view of a semiconductor wafer in an initial step of a process for manufacturing integrated power devices according to one embodiment of the present invention; -
FIG. 2 is a cross section through the wafer ofFIG. 1 , taken along the line II-II ofFIG. 1 ; -
FIGS. 3-5 show the wafer ofFIG. 2 in subsequent steps of the manufacturing process; -
FIG. 6 is a top plan view of the wafer ofFIG. 5 ; -
FIG. 7 is a cross section through the wafer ofFIG. 6 , taken along the line VII-VII ofFIG. 6 , in a subsequent processing step; -
FIG. 8 is a cross section through the wafer ofFIG. 6 , taken along the line VIII-VIII ofFIG. 6 , in the processing step ofFIG. 7 ; -
FIG. 9 is a cross section through the wafer ofFIG. 6 , taken along the line IX-IX ofFIG. 6 , in the processing step ofFIG. 7 ; -
FIG. 10 is a cross section through the wafer ofFIG. 6 , taken along the line X-X ofFIG. 6 , in the processing step ofFIG. 7 ; -
FIG. 11 is a perspective view three quarters from above of a portion of the wafer ofFIGS. 7-10 , in a subsequent processing step; -
FIG. 12 is a top plan view of the wafer ofFIG. 11 , in a subsequent processing step; -
FIG. 13 is a cross section through the wafer ofFIG. 12 , taken along the line XIII-XIII ofFIG. 12 , in a subsequent processing step; -
FIG. 14 is a cross section through the wafer ofFIG. 12 , taken along the line XIV-XIV ofFIG. 12 , in the processing step ofFIG. 13 ; -
FIG. 15 shows the view ofFIG. 13 in a subsequent processing step; -
FIG. 16 shows the view ofFIG. 14 in a subsequent processing step; -
FIG. 17 is a perspective view three quarters from above of a portion of the wafer ofFIGS. 15 and 16 , in a subsequent processing step; -
FIG. 18 shows the view ofFIG. 15 , which represents an integrated power device according to one embodiment; -
FIG. 19 shows the view ofFIG. 16 , which represents an integrated power device according to a further embodiment; -
FIG. 20 is a top plan view of a die obtained by dicing the wafer ofFIGS. 18 and 19 and incorporating the device ofFIG. 18 and the device ofFIG. 19 ; and -
FIG. 21 is a simplified block diagram of an electronic system incorporating an integrated device according to one embodiment. - With reference to
FIGS. 1 and 2 , a semiconductor wafer, designated by 1, comprises asubstrate 2 of semiconductor material (for example, monocrystalline silicon of a P type), in which a low-voltage region 3, afirst power region 4, and asecond power region 5 are defined. - By known manufacturing steps, low-
voltage insulating structures 7 a, of a STI (Shallow-Trench-Insulation) type, which delimit low-poweractive areas 6 a, are initially made in the low-voltage region 3. At the same time, in the second high-poweractive region 5insulating power structures 7 b are made, once again of an STI type, which delimitactive power areas 6 b. - A first pad-
oxide layer 8 is then grown on thewafer 1 and a first silicon-nitride layer 9 is subsequently laid (FIG. 2 ). - A
resist mask 10 is formed on the first silicon-nitride layer 9 and presents, on thefirst power region 4 and on thesecond power region 5,elongated windows 12, which extend mutually parallel in a direction perpendicular to the plane ofFIG. 1 , in a first direction L (see in particularFIG. 1 ). Thewindows 12 are adjacent to one another and are arranged in succession in a second direction W, perpendicular to the first direction L, so as to form a grid. - The low-
voltage region 3 is internally protected by theresist mask 10. - The first silicon-
nitride layer 9 and the first pad-oxide layer 8 are selectively etched through theresist mask 10 to form a shapinghard mask 14 havingapertures 13 that correspond torespective windows 12. Asurface 2 a of thesubstrate 2 thus remains exposed through thewindows 12 of theresist mask 10 and theapertures 13 in the first silicon-nitride layer 9 and in the first pad-oxide layer 8. - The
resist mask 10 is then removed. - As illustrated in
FIG. 3 , through wet LOCOS thermal oxidation, LOCOSsacrificial structures 15 are obtained selectively in the exposed regions of thesubstrate 2. In greater detail, during the LOCOS oxidation step the LOCOSsacrificial structures 15 grow in part on top of and in part inside thesubstrate 2. Surface portions of the substrate 2 (designated by 2 b inFIG. 1 ) are hence converted into silicon oxide. Furthermore, the LOCOSsacrificial structures 15 penetrate, with characteristic lateral beaks, in part underneath the first silicon-nitride layer 9 at the margins of theapertures 13. The LOCOSsacrificial structures 15 may have, for example, a thickness of between 300 nm and 400 nm. - During this step of the process, the
surface 2 a of thesubstrate 2 is modified because part of the silicon surface exposed through theapertures 13 is converted into oxide. In particular, thesurface 2 a has depressions 18, where the LOCOSsacrificial structures 15 are present, andprojections 17, betweenadjacent depressions 18. Theprojections 17 and thedepressions 18 extend in the first direction L and alternate with one another in the second direction W. - The shape of the depressions and the profile of the
surface 2 a in the second direction W are determined by the shape of the LOCOSsacrificial structures 15 and can be controlled precisely. In particular, the depth of thedepressions 18 with respect to theprojections 17 is determined by the degree of penetration of the LOCOSsacrificial regions 15 within thesubstrate 2. - In turn, the thickness of the LOCOS
sacrificial structures 15 and the extension and inclination of the lateral beaks are determined by the initial thickness of the first pad-oxide layer 8, by the duration of the LOCOS step, and by the temperature. - Furthermore, thanks to the progressive penetration of the lateral beaks underneath the shaping
hard mask 14, theridges 17 a of theprojections 17, and the bottom 18 a of the adjacent depressions 18 (which may be seen more clearly inFIG. 4 ) are connected throughwalls 19 having a rounded profile. - The LOCOS
sacrificial structures 15, the first silicon-nitride layer 9 and the first pad-oxide layer 8 are then removed from thefirst power region 4 and thesecond power region 5. In particular, the LOCOSsacrificial structures 15 are etched with hydrofluoric acid so as to be removed completely. The structure shown inFIG. 4 is thus obtained, where the corrugations formed by the succession ofprojections 17 anddepressions 18 are evident. - Then (
FIGS. 5 and 6 ), a second pad-oxide layer 20 and a second silicon-nitride layer 21 are deposited in succession on theentire wafer 1. Through a resist mask (not shown), the second pad-oxide layer 20 and the second silicon-nitride layer 21 are then selectively etched to provide a second fieldhard mask 24 havingapertures 23 on thefirst power region 4. In one embodiment (not shown), the etch with which the fieldhard mask 24 is defined proceeds so as to form recesses in thesubstrate 2. In this way, where necessary, it is possible to exploit the so-called “recessed LOCOS” technique and obtain LOCOS structures for field insulation, which extend prevalently within thesubstrate 2 and have a reduced projecting portion. - The
apertures 23 are elongated in shape and extend parallel to one another in the second direction W. Theapertures 23 thus extend transversely to theprojections 17 and to thedepressions 18 and expose underlying portions of thesurface 2 a of thesubstrate 2. In this step, the low-voltage region 3 and thesecond power region 5 remain protected. - As shown in
FIGS. 7-10 , a new LOCOS thermal oxidation is carried out to form, through theapertures 23 of the second fieldhard mask 24, LOCOS field-oxide structures 25 that run mutually parallel, transversely to theprojections 17 anddepressions 18. In this step,portions 2 c of the substrate 2 (FIG. 6 ) exposed through theapertures 23 are converted into oxide, which moreover grows in part on top of thesubstrate 2. - After thermal oxidation, the second silicon-nitride layer 22 and the second pad-
oxide layer 21 are removed. Thefirst power region 4, which is the only one to be modified in this step, assumes the appearance illustrated inFIG. 11 . - As shown in
FIGS. 12-14 , after forming asacrificial oxide layer 26, body, source, and drain implantations are carried out in thesubstrate 2 using masks (not shown). Thus, body wells 27 (of a P type), source regions 28 (of an N type), source-contact regions 29 (of an N+ type), and drain-contact regions 30 (of an N+ type) are made in thefirst power region 4 and in thesecond power region 5; and body wells 31 (of a P type), source regions 32 (of an N type), source-contact regions 33 (of an N+ type), and drain-contact regions 34 (of an N+ type) are made in thesecond power region 5. - In particular, in the
first power region 4 thesource region 28 is defined centrally between adjacent LOCOS field-oxide structures 25, at a distance there from, and extends in the second direction W, transversely to theprojections 17 anddepressions 18. The source-contact region 29 is nested in thesource region 28. The drain-contact regions 30 are provided alongside the LOCOS field-oxide structures 25, on the side opposite to thesource region 28. - In the
second power region 5, thesource region 32 extends in the second direction W, transversely to theprojections 17 anddepressions 18, and the drain-contact regions 34 are made alongside thesource region 28. The source-contact region 33 is nested in thesource region 32. - The implants are carried out where required also in the low-
voltage region 3 to provideCMOS circuit components 24, which, however, are for simplicity illustrated only schematically, through circuit symbols. - The
sacrificial oxide layer 26 is then removed, as shown inFIGS. 15 and 16 , and in its place a thin gate-oxide layer 35 is grown, on which apolysilicon layer 36 is deposited. - By a photolithographic process, the
polysilicon layer 36 and the gate-oxide layer 35 are defined to form, respectively, gate-oxide regions 37 andgate regions 38, in thefirst power region 4, and to form, respectively, gate-oxide regions 39 andgate regions 40, in thesecond power region 5. In use, thegate regions 38 and thegate regions 40 enable selective coupling and decoupling of thesource region 28 and thedrain regions 30 and, respectively, thesource region 32 and thedrain regions 34. - As shown also in
FIG. 17 , in thefirst power region 4 the gate-oxide regions 37 extend directly on thesubstrate 2 between thesource region 28, which they slightly overlap, and respective LOCOS field-oxide structures 25. Thegate regions 38 lie in part on respective gate-oxide regions 37 until they come to be arranged on top of thesource region 28 and, in part, on respective LOCOS field-oxide structures 25. The portions of thegate regions 37 that extend on the LOCOS field-oxide structures 25 form so-called “field plates”, which in use modify the biasing conditions in thesubstrate 2, increasing the reverse breakdown voltage of the junction between thesource region 28 and thebody region 27. - The process is completed by standard manufacturing steps, as shown in
FIGS. 18 and 19 . In particular, the following are provided: adielectric layer 43;source contacts 45,gate contacts 46, anddrain contacts 47 in thefirst power region 4;source contacts 50,gate contacts 51, anddrain contacts 52 in thesecond power region 5; metallization lines (not illustrated); and apassivation layer 53. Furthermore, in the low-voltage region 3 (here not illustrated), theCMOS components 24 are completed. - In the
first power region 4 there is thus defined a power device 55 (FIG. 18 ), which in the embodiment described is a lateral N-channel DMOS transistor arranged in part on the active area and in part on the field insulation (field plates on the LOCOS field-oxide structures 25). In thesecond power region 5, instead, apower device 57 is formed fully on the active area (FIG. 19 , also in this case a lateral N-channel DMOS transistor). - Finally (
FIG. 20 ), thewafer 1 is cut intodice 60, each of which comprises low-voltage CMOS devices 24, apower device 55 in thefirst power region 5, and apower device 57 in thesecond power region 5. - The process described advantageously enables provision of surface corrugations in conduction regions of integrated power devices and an increase in the section available for conduction, without, however, degrading the quality of the semiconductor material and hence the levels of performance.
- In particular, the corrugations are defined by the succession of
projections 17 anddepressions 18 in thefirst power region 4 and in thesecond power region 5. Both in thepower device 55 and in thepower device 57, the current flows in use from the respective source region to the respective drain regions in the first direction L, parallel to the corrugations, when the source region and the drain regions are coupled as a result of the biasing of the respective gate regions. Given the same occupation of area, the cross section useful for conduction is greater than in the case of planar devices. - The use of the LOCOS technique to form the corrugations enables to preserve the quality of the semiconductor material at the surface of the
substrate 1. Thermally oxidizing, in fact, converts the semiconductor material gradually and penetrates in depth in a uniform way. Furthermore, the LOCOS sacrificial structures are selectively removed, without damaging the semiconductor material, which remains substantially unaltered. Direct removal of semiconductor material is instead aggressive and produces irregularities and imperfections, so much so that an oxidation is frequently necessary subsequent to etching in order to restore the surface of the semiconductor material. In the process described, it is not necessary to carry out an oxidation after formation of the corrugations. - Furthermore, LOCOS oxidation enables precise determination of the shape and extension of the LOCOS sacrificial structures and hence also of the profile of the corrugations. In particular, the desired profile can be obtained by controlling the thickness of the initial pad-oxide layer and the temperature and duration of the thermally oxidizing.
- Another advantage derives from the fact that the process of LOCOS thermal oxidation tends to produce structures without sharp edges, with gradual transitions between surfaces with different inclinations. The maximum values of electrical field and the related risks are hence reduced.
- The process described enables making both fully-on-active power devices and devices with gate regions that extend on the field oxide (field plates).
- The process is compatible with the preliminary provision of insulating structures of an STI type, but does not necessarily call for such structures. In particular, the process can be exploited for integrating power devices and low-voltage devices with any type of CMOS technology. CMOS devices obtained with process sub-0.35-μm technology as a rule require an insulation of an STI type for low-voltage devices. In this case, the process flow is substantially the one already described. Initially, the STI structures are formed in the low-voltage region and in the power regions, where necessary. Once the STI structures have been completed, the LOCOS technique is used to create the corrugations in the power regions and, if necessary, field-insulation structures.
- The CMOS devices obtained with process technology equal to or higher than 0.35 μm use, also in the low-power region, insulating structures of a LOCOS type instead of an STI type. In this case, the process is simplified. The creation of LOCOS insulating structures does not in fact entail steps of planarization, which are instead necessary to provide STI insulating structures and should necessarily be carried out before forming the corrugations, for obvious reasons. In process technology equal to or larger than 0.35 μm, the low-voltage LOCOS insulating structures are formed together with the power LOCOS insulating structures, after formation of the corrugations, as described previously.
- The process described is moreover compatible with the production of conventional (planar) power devices, which can be integrated in one and the same die by simply protecting the corresponding portions of the
substrate 2 during formation of the corrugations. - A portion of a
system 100 in accordance with one embodiment is illustrated inFIG. 21 . Thesystem 100 may comprise acontroller 110, an input/output (I/O) device 120 (for example, a keyboard or a screen), amicroelectromechanical device 130, awireless interface 140, and amemory 160, of a volatile or non-volatile type, coupled together through abus 150. In one embodiment, abattery 180 can be used for supplying thesystem 100. It is to be noted that the scope of the present invention is not necessarily limited to the embodiments having one or all of the devices listed. - The
microelectromechanical device 130 comprises amicrostructure 133 and an ASIC (application-specific integrated circuit)device 135, dedicated to driving and control of themicrostructure 133 and, possibly, to detection of quantities that can be measured by means of themicrostructure 133. Theintegrated device 135 comprises low-voltage CMOS components and power components integrated in one and the same semiconductor die and is provided according to what has been described with reference toFIGS. 1-19 . In one embodiment, themicroelectromechanical device 130 is a microelectromechanical sensor, such as, for example, an accelerometer, a gyroscope, a pressure sensor, a microphone. In a different embodiment, themicroelectromechanical device 130 is a micro-actuator. - The
controller 110 may comprise, for example, one or more microprocessors, microcontrollers, and the like. - The I/
O device 120 can be used for generating a message. Thesystem 100 can use thewireless interface 140 for transmitting and receiving messages to and from a wireless communications network with a radiofrequency (RF) signal. Examples of wireless interface may comprise an antenna, or a wireless transceiver, such as a dipole antenna, even though the scope of the present invention is not limited from this point of view. Furthermore, the I/O device 120 can provide a voltage representing what is stored either in the form of digital output (if digital information has been stored) or in the form of analog output (if analog information has been stored). - The
system 100 can be used in apparatuses such as, for example, a palmtop computer (personal digital assistant, PDA), a laptop computer or portable computer, possibly with wireless capacity, a cell phone, a messaging device, a digital music player, a digital camera, or other devices. - Finally, it is evident that modifications and variations may be made to the process and to the device described herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.
Claims (13)
1. A power integrated device, comprising:
a semiconductor body, having projections and depressions, which extend in a first direction and are arranged alternated in succession in a second direction, transverse to the first direction;
a first conduction region and a second conduction region, arranged so as to define a current flow direction between the first conduction region and the second conduction region parallel to the first direction, along the projections and the depressions; wherein ridges of the projections and a bottom of adjacent depressions are connected through walls having a rounded profile.
2. The device according to claim 1 , further comprising at least a field insulation structure, arranged transversely to the projections and to the depressions, in the second direction, and a control region, arranged between the first conduction region and the second conduction region and lying in part on the field insulation structure.
3. The device according to claim 1 , further comprising a control region between the first conduction region and the second conduction region.
4. The device according to claim 3 , further comprising a field insulation structure arranged transversely to the projections and to the depressions and extending in the second direction.
5. The device according to claim 4 , wherein the control region lies in part on the field insulation structure.
6. The device according to claim 5 , wherein the first conduction region and the second conduction region are arranged at sides of the field insulation structure and extend in the second direction, transversely to the projections and to the depressions.
7. The device according to claim 1 , wherein the first conduction region and the second conduction region extend in the second direction, transversely to the projections and to the depressions.
8. A system comprising a control unit and a power integrated device according to claim 1 which is coupled to the control unit.
9. A device, comprising:
a semiconductor substrate having parallel alternating projections and depressions which are connected by walls having rounded profiles; and
first and second conduction regions formed in the semiconductor substrate and configured to define a current flow direction along the projections and the depressions.
10. The device as defined in claim 9 , further comprising a field insulation structure arranged transversely to the projections and the depressions, and a control region arranged between the first conduction region and the second conduction region.
11. The device according to claim 10 , wherein the control region lies in part on the field insulation structure.
12. The device according to claim 11 , wherein the first conduction region and the second conduction region are arranged at sides of the field insulation structure and extend in a direction transverse to the projections and to the depressions.
13. The device according to claim 9 , wherein the first conduction region and the second conduction region extend in a direction transverse to the projections and to the depressions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/492,243 US20150008519A1 (en) | 2010-06-17 | 2014-09-22 | Power integrated device having surface corrugations |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITTO2010A000521A IT1401729B1 (en) | 2010-06-17 | 2010-06-17 | PROCEDURE FOR THE MANUFACTURE OF INTEGRATED POWER DEVICES WITH SURFACE CORRUGATIONS AND INTEGRATED POWER DEVICE WITH SURFACE CORRUGATIONS |
ITTO2010A000521 | 2010-06-17 | ||
US13/162,951 US8871594B2 (en) | 2010-06-17 | 2011-06-17 | Process for manufacturing power integrated devices having surface corrugations, and power integrated device having surface corrugations |
US14/492,243 US20150008519A1 (en) | 2010-06-17 | 2014-09-22 | Power integrated device having surface corrugations |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/162,951 Division US8871594B2 (en) | 2010-06-17 | 2011-06-17 | Process for manufacturing power integrated devices having surface corrugations, and power integrated device having surface corrugations |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150008519A1 true US20150008519A1 (en) | 2015-01-08 |
Family
ID=43446452
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/162,951 Active 2032-11-09 US8871594B2 (en) | 2010-06-17 | 2011-06-17 | Process for manufacturing power integrated devices having surface corrugations, and power integrated device having surface corrugations |
US14/492,243 Abandoned US20150008519A1 (en) | 2010-06-17 | 2014-09-22 | Power integrated device having surface corrugations |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/162,951 Active 2032-11-09 US8871594B2 (en) | 2010-06-17 | 2011-06-17 | Process for manufacturing power integrated devices having surface corrugations, and power integrated device having surface corrugations |
Country Status (2)
Country | Link |
---|---|
US (2) | US8871594B2 (en) |
IT (1) | IT1401729B1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103943548A (en) * | 2013-01-23 | 2014-07-23 | 无锡华润上华半导体有限公司 | Manufacturing method of semiconductor device of discrete field oxide structure |
US10529812B1 (en) * | 2018-10-10 | 2020-01-07 | Texas Instruments Incorporated | Locos with sidewall spacer for transistors and other devices |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6677202B2 (en) * | 1999-04-30 | 2004-01-13 | Fairchild Semiconductor Corporation | Power MOS device with increased channel width and process for forming same |
US7170118B2 (en) * | 2003-08-01 | 2007-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor (FET) device having corrugated structure and method for fabrication thereof |
US20100001345A1 (en) * | 2008-07-03 | 2010-01-07 | Seiko Epson Corporation | Semiconductor device |
US20100270614A1 (en) * | 2009-04-22 | 2010-10-28 | Stmicroelectronics S.R.L. | Process for manufacturing devices for power applications in integrated circuits |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6191964A (en) * | 1984-10-12 | 1986-05-10 | Nec Ic Microcomput Syst Ltd | Mos field effect transistor |
US5466624A (en) * | 1994-09-30 | 1995-11-14 | Intel Corporation | Isolation between diffusion lines in a memory array |
-
2010
- 2010-06-17 IT ITTO2010A000521A patent/IT1401729B1/en active
-
2011
- 2011-06-17 US US13/162,951 patent/US8871594B2/en active Active
-
2014
- 2014-09-22 US US14/492,243 patent/US20150008519A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6677202B2 (en) * | 1999-04-30 | 2004-01-13 | Fairchild Semiconductor Corporation | Power MOS device with increased channel width and process for forming same |
US7170118B2 (en) * | 2003-08-01 | 2007-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor (FET) device having corrugated structure and method for fabrication thereof |
US20100001345A1 (en) * | 2008-07-03 | 2010-01-07 | Seiko Epson Corporation | Semiconductor device |
US20100270614A1 (en) * | 2009-04-22 | 2010-10-28 | Stmicroelectronics S.R.L. | Process for manufacturing devices for power applications in integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
IT1401729B1 (en) | 2013-08-02 |
US8871594B2 (en) | 2014-10-28 |
ITTO20100521A1 (en) | 2011-12-18 |
US20110309480A1 (en) | 2011-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI683439B (en) | Semiconductor devices in semiconductor substrate and fabrication method thereof | |
TWI392055B (en) | Method of forming a trench semiconductor device and structure therefor | |
US7508048B2 (en) | Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby | |
WO2011099047A1 (en) | Semiconductor device and method of manufacturing same | |
US9385049B2 (en) | Process for manufacturing integrated device incorporating low-voltage components and power components | |
JP2007088010A (en) | Semiconductor device and its manufacturing method | |
JP4221420B2 (en) | Manufacturing method of semiconductor device | |
JPH0870124A (en) | Fabrication of silicon carbide semiconductor device | |
JP2007200980A (en) | Semiconductor device, and method for manufacturing same | |
US20150008519A1 (en) | Power integrated device having surface corrugations | |
JP2002270685A (en) | Manufacturing method for semiconductor device | |
US9640614B2 (en) | Integrated device with raised locos insulation regions and process for manufacturing such device | |
KR20100050977A (en) | Semiconductor device and method for manufacturing the same | |
CN105405809A (en) | Method of manufacturing flash memory | |
KR100745939B1 (en) | Method for forming semiconductor device | |
KR100949269B1 (en) | Method for manufcturing semiconductor device | |
KR20070017655A (en) | Method for forming semiconductor device | |
CN107658341B (en) | Groove type power MOSFET and preparation method thereof | |
CN101939842A (en) | Semiconductor manufacturing method | |
KR100667908B1 (en) | Method for forming trench-type mos gate | |
KR100571413B1 (en) | Device Separator Formation Method of Semiconductor Device | |
EP2306509A1 (en) | Process for manufacturing an integrated device with "damascene" field insulation, and integrated device made by such process | |
CN105206530A (en) | Formation method of PMOS transistor | |
KR100774794B1 (en) | Mosfet structure and menufacturing method thereof | |
KR20090044482A (en) | Semiconductor device and method for manufacturing of the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |