US20150001722A1 - Semiconductor Device with Reduced Contact Resistance - Google Patents
Semiconductor Device with Reduced Contact Resistance Download PDFInfo
- Publication number
- US20150001722A1 US20150001722A1 US14/483,989 US201414483989A US2015001722A1 US 20150001722 A1 US20150001722 A1 US 20150001722A1 US 201414483989 A US201414483989 A US 201414483989A US 2015001722 A1 US2015001722 A1 US 2015001722A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor device
- copper
- electrode
- power
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/29124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/29166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/305—Material
- H01L2224/30505—Layer connectors having different materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73151—Location prior to the connecting process on different surfaces
- H01L2224/73153—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01088—Radium [Ra]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0133—Ternary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/047—Silicides composed of metals from groups of the periodic table
- H01L2924/0483—13th Group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/36—Material effects
- H01L2924/365—Metallurgical effects
- H01L2924/3651—Formation of intermetallics
Definitions
- Recent advances in silicon cell technologies have reduced the RA of, for example, a 30V device from 50 to 14 m Ohm-mm 2 . Advances in semiconductor device technology are likely to continue to reduce the RA. If this trend continues an active area of approximately 10 mm 2 can be expected to have an R dson of 630 ⁇ Ohm to 240 ⁇ Ohm depending on the fabrication process.
- a DirectFET® package (sold by the assignee of the present application), in simple terms, is a semiconductor package which includes a conductive can, and a semiconductor die disposed inside the can and electrically and mechanically connected to an interior surface of the can.
- U.S. Pat. No. 6,624,522 shows an example of such a package.
- top metal resistance of the semiconductor die which is directly connected by solder, conductive epoxy or the like to a conductive pad of a substrate such as a circuit board
- the top metal resistance is increased somewhat to between 0.2 and 0.7 mOhm depending on the model used.
- the top metallization can include current paths with up to 0.66 mOhm resistance. It is, therefore, desirable to reduce the resistance of the top metal of the semiconductor die in order to improve the overall resistance of a package such as a DirectFETTM package.
- a device includes a semiconductor die, having an electrode on a surface thereof, the electrode electrically and mechanically connected to the die being comprised of a first conductive material, and a conductive body, the conductive body being comprised of a second material having a resistivity that is lower than that of first conductive material.
- a barrier layer may be interposed between the conductive body and the electrode.
- the back electrode may also a conductive material of lower resistivity.
- a stress balancing metallic body may be applied to balance the stress on the die.
- FIG. 1 illustrates a top plan view of a semiconductor die according to the prior art.
- FIG. 2 shows a top plan view of a semiconductor device according to the present invention.
- FIG. 3 shows a cross-sectional view of a semiconductor device according to the present invention along line 3 - 3 and viewed in the direction of the arrows.
- FIG. 4 shows a top plan view of a semiconductor device according to the present invention having a passivation layer formed thereon.
- FIG. 5 shows a cross-sectional view of the device shown in FIG. 4 along line 5 - 5 and viewed in the direction of the arrows
- FIG. 6 show a top perspective view of a package which includes a semiconductor device according to the present invention.
- FIG. 7 shows a bottom perspective view of a package which includes a semiconductor device according to the present invention.
- FIG. 8 illustrates a cross-sectional view of the package shown in FIG. 7 along line 8 - 8 and viewed in the direction of the arrows.
- FIGS. 9-17 illustrate the steps in the fabrication of a semiconductor device according to an embodiment of the present invention.
- FIG. 18 shows a summary of a process for fabricating a device according to an embodiment of the present invention.
- FIG. 19 shows the effect of the thickness of a conductive body on the lowering of the electrical resistivity in a semiconductor device according to the present invention.
- FIG. 20A illustrates the top plan view of an example of the present invention, in which the conductive body having the lower resistivity covers the entire surface of the electrodes of a semiconductor device.
- FIG. 20B illustrates the top plan view of an example of the present invention, in which the conductive body having the lower resistivity covers not all but a substantial portion of the electrodes of a semiconductor device.
- FIG. 20C illustrates the top plan view of an example of the present invention, in which the conductive body having the lower resistivity covers not all but a lesser portion (less than that shown by FIG. 20B ) of the entire surface of the electrodes of a semiconductor device.
- FIG. 21 graphically illustrates the effect of a pattern of the conductive body on the lowering of electrical resistivity.
- FIG. 22A illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
- FIG. 22B illustrates a cross-sectional view of a semiconductor device according to an alternative embodiment of the present invention.
- FIG. 23 illustrates a cross-sectional view of a package containing a semiconductor device according to the present invention.
- FIG. 24A illustrates a top plan view of a semiconductor device disposed in an alternative package.
- FIG. 24B illustrates a cross-sectional view of the package of FIG. 24A along line 24 B- 24 B, viewed in the direction of the arrows.
- a semiconductor device such as a power MOSFET, according to the prior art includes a semiconductor body 10 , at least one power electrode 12 (i.e. source electrode), and a control electrode (i.e. gate electrode) 14 .
- the device shown in FIG. 1 is a vertical conduction type power device, and includes a second power electrode (i.e. drain electrode) (not shown) on a surface of semiconductor body 10 opposite first power electrodes 12 .
- the electrodes of a power device are made usually from Al, AlSi, or AlSiCu.
- a semiconductor device includes semiconductor body 10 , at least one first power electrode 12 , and a control electrode 14 .
- a device according to the present invention preferably includes second power electrode 16 disposed opposite on semiconductor body opposite power electrode 12 .
- a semiconductor device according to the preferred embodiment of the present invention is a vertical conduction type power MOSFET in which first power electrode 12 is the source electrode, the second power electrode 16 is the drain electrode and control electrode 14 is the gate electrode.
- FIG. 2 shows two first power electrodes 12 , the present invention does not require two first power electrodes.
- the preferred embodiment is a power MOSFET, the present invention is fully applicable to other power semiconductor devices including IGBTs, power diode, triacs, and power bipolar transistors, and the like.
- a semiconductor device includes barrier layer 18 which is disposed on and electrically connected to a first power electrode 12 , and conductive body 20 which is disposed on and electrically connected to barrier layer 18 .
- Conductive body 20 is preferably made from copper, but can be made from any material of lower resistivity than that of first power electrode 12 .
- Barrier layer 18 is preferably formed from titanium (Ti) and functions to a) to hinder and prevent contamination of first power electrode 12 by copper through diffusion, and b) ensure good adhesion of copper body 20 to first power electrode 12 .
- titanium barrier layer 18 is about 20 nanometers thick.
- the thickness of copper body 20 can be selected to attain the desired resistivity, and is preferably between 10 ⁇ m to 20 ⁇ m. It is believed, however, that in a process according to the present invention it may be possible to achieve copper bodies 20 of as thick as 100 ⁇ m and possibly thicker. It also should be noted that barrier layer 18 can be eliminated if conductive body 20 is made from such a material that a) adheres well to first power electrode 12 , and b) does not diffuse into first power electrode 12 , or otherwise harms the functionality of the semiconductor die.
- a device according to the present invention is preferably configured for flip-chip-type mounting.
- copper body 20 on each electrode is provided with solderable body 22 which enables copper body 20 to become electrically and mechanically connectable to a conductive pad directly by a conductive adhesive such as solder, or a conductive epoxy, such as silver loaded epoxy.
- solderable bodies 22 include a nickel (e.g. 1-6 microns thick, specifically, for example, about two microns thick) layer over copper body 20 and a lead tin layer (e.g. about one micron thick) formed over the nickel layer, a bimetal stack such as NiAg, or NiAu.
- the Au may be deposited using a flash or immersion process.
- first power electrodes 12 and control electrode 14 include barrier layer 18 , a copper body 20 and optionally a solderable body 22 to facilitate flip-chip mounting.
- a device according to the present invention may include a passivation body 24 (illustrated by slanted lines in FIG. 4 ).
- Passivation body 24 includes at least one opening 26 to expose a respective solderable body 22 whereby a conductive adhesive can reach the exposed solderable body at the bottom of each opening in passivation body 24 .
- Passivation body 24 is preferably composed of a suitable epoxy, polyimide, BCB (benzocyclobutene), or other organic material that can also function as a solder resist. As a result, solder or any other conductive adhesive is prevented from traveling and shorting a first power electrode 12 to control electrode 14 when the device is flip-chip mounted.
- a device according to the present invention can be disposed within a conductive can 28 or some other conductive clip according to the concepts disclosed in U.S. Pat. No. 6,624,522, which is assigned to the assignee of the present invention, and the disclosure of which is incorporated by reference.
- second power electrode 16 is electrically and mechanically attached to an interior surface of can 28 by a layer of conductive adhesive 30 such as solder or conductive epoxy.
- conductive can 28 which is preferably formed from copper or a copper alloy, can serve as an electrical connector for second power electrode 16 .
- can 28 includes connection surfaces 32 each for external electrical connection (by a conductive adhesive such as solder, or conductive epoxy) to a respective conductive pad 34 on a substrate 36 , such as a circuit board.
- control electrode 14 and each first power electrodes 12 (only one illustrated for clarity) is available for direct electrical connection to a respective conductive pad 34 by a conductive adhesive such as solder or conductive epoxy in that each includes a solderable body 22 disposed thereover.
- second power electrode 16 of a device according to the present invention can be electrically and mechanically attached by a conductive adhesive such as solder or conductive epoxy to the conductive pad of a lead frame or a substrate such as a circuit board.
- a conductive adhesive such as solder or conductive epoxy
- a device, according to the present invention is fabricated according to a method described hereafter.
- a semiconductor wafer 102 is prepared to have a plurality of semiconductor die each having at least one power electrode 100 .
- Power electrode 100 may be first power electrode 12 as seen in the preferred embodiment.
- each die may include a control electrode 104 , such as control electrode 14 as described above, which is processed simultaneously with the power electrode 100 .
- a blanket barrier layer 106 is formed over one face of wafer 102 covering electrodes 100 , 104 as well as areas of wafer 102 between the electrodes.
- Barrier layer 106 is preferably formed from titanium and may be about 20 nanometers thick. Titanium may be sputtered. Other suitable materials for forming blanket barrier layer 106 include tantalum or titanium tungsten.
- Blanket copper seed layer 108 is formed on barrier layer 106 , as seen in FIG. 11 .
- Blanket copper seed layer 108 may be about 200 nanometers thick and may be sputtered on as well. Alternatively, blanket copper seed layer 108 may be plated through electroless plating. Blanket copper seed layer 108 forms a low resistance path for the plating current and acts as a plating electrode.
- photoresist layer 110 is formed over blanket copper seed layer 108 , as seen in FIG. 12 .
- a shipley BPR 100 liquid photoresist was used to form photoresist layer 110 .
- This material is available from Rohm and Haas electronic materials, Marlborough, Mass., and was selected as it is capable of forming a layer of up to 100 ⁇ m in a single application.
- Photoresist layer 110 is then patterned through conventional photolithography to include openings 112 each exposing a portion of blanket copper seed layer 108 over each electrode 100 , or 104 as seen in FIG. 13 .
- the photoresist deposition, edge bead removal, and procure can be completed on a spin coater track system.
- the photoresist is then exposed in a mask aligner or similar photo tool.
- the exposed photoresist material is then developed in a suitable developer solution. If required, a post develop bake stage at elevated temperatures may be performed.
- a process for applying a photoresist is an example of a process for applying a photoresist:
- photoresist developing residual photoresist material may remain in opened apertures.
- the residual resist should be removed. This is done preferably using an oxygen plasma clean process (wafers are bombarded with O 2 ).
- an electrical contact 113 and seal clamp 114 is applied to the edges of wafer 102 .
- Electrical contact 113 and seal clamp 114 is provided to apply voltage to electrodes 100 , 104 in order to facilitate the electroplating process, as will be described later.
- wafer 102 is immersed in an electroplating solution, and the appropriate voltage is applied to electrical contact 113 whereby a copper body 20 is grown in each opening 112 on exposed copper seed layer 108 . Also, a solderable body 22 is formed over each respective copper body 20 as seen in FIG. 15 .
- the surface to be electroplated forms the cathode and is submerged in a plating solution.
- a plating solution Each manufacturer may offer its own plating solution. Manufacturers of these materials include Atotech, MacDermid, Rohm and Hass, and Cookson Electronics.
- the plating solution may be any one of the following:
- the plating solution is acid based.
- An example of such a plating solution may include the following chemicals:
- any copper seed material 108 and barrier material 106 that is not under copper bodies 20 is removed to obtain the structure shown in FIG. 17 .
- the wafer can then be processed according to any known method to obtain a device according to the present invention.
- back metal is applied to form second power electrode, and passivation 24 is applied and patterned to obtain a plurality of devices as described above.
- the wafer can be passivated through a screen printing process.
- the passivation material is preferably an aqueous developing, liquid photoimagable polymer. The following is an example of a procedure that can be followed in applying the passivation:
- the wafer may become warped. This is due to high stresses caused by the recrystallization of the fine grain structure of the electroplated copper.
- wafer 102 is diced to obtain individual semiconductor devices according to the present invention, which can be ready to be received in a conductive can 28 as described above, or packaged in any other package for example an SO8, TO-220, D2pak, Dpak and MLP packages.
- the first cut should be performed with a blade specially designed for copper dicing, followed by a standard blade suitable for cutting a semiconductor die at a standard speed.
- copper dicing may be necessary to penetrate the residual copper present on the perimeter of the wafer contact ring.
- the copper deposition can be avoided by correctly designing the perimeter plating contact to fit within the plating chuck seal, thereby eliminating the copper dicing step.
- the re-design may also help to reduce wafer warpage, as the plated copper on the contact ring can be one of the main contributors to the stress within the wafer.
- FIG. 18 summarizes a process for fabricating a semiconductor device according to the present invention.
- a device will include a copper body 20 formed over a harrier layer 18 .
- copper bodies may be applied to a MOSFET die using a process of seed layer deposition, electroplating, photoresist, copper etch/strip or alternatively by pattern plating.
- the photoresist is applied after electroplating.
- applying photoresist prior to electroplating is preferred in that only minimal copper etching is required and tighter tolerances are often achievable on the thick copper films.
- the metal finish required on the top surface of the copper is determined by the required interconnection between the die and the package or the die and the circuit board.
- a Nickel barrier is typically required followed by a thin gold film.
- the nickel acts as a solderable layer and acts to prevent solder forming intermetallics with the underlying copper.
- the gold layer prevents oxidation of the nickel and is consumed during the soldering process.
- Typical recommended nickel thickness is in the range of 1 to 8 ⁇ m, or preferably 4 to 8 ⁇ m.
- a copper body 20 need not cover the entire surface of the electrode over which it resides. Rather, the device covered by a copper body can be varied to obtain the desired reduction in the resistivity for the device.
- FIGS. 20A-20C which show respectively a first pattern, a second pattern, and a third pattern, for copper bodies 20 , it has been observed through experimentation that pattern variation may affect the resistivity obtained.
- ANSYS solid models were set up and refined to include contributions from die, substrate, die attach adhesive and the copper can. Using this model as a baseline a copper layer was added to the model. The thickness of this layer was then modified to investigate the effect of metal thickness upon device R dson .
- FIG. 19 shows the effect upon device R dson of increasing the metal thickness. Note that models of copper under just the source pads and all over the die were investigated. For example, with zero copper thickness and 4 ⁇ m aluminum the device R dson is approx 1.9 mOhm. As the thickness of copper is increased to 20 ⁇ m the R dson drops to 1.67 m Ohm. This represents a reduction of over 200 ⁇ Ohm.
- a die having a thick copper body formed on a power electrode thereof exhibits a significantly reduced resistance.
- the addition of 1 to 20 ⁇ m of copper has shown reductions in R dson in the range of 180 to 200 ⁇ Ohm.
- models predict that similar, if not greater, absolute shifts in Rdson are possible with smaller die, and some models predict significant reductions in Rdson are possible by combining thick copper with thinned die. It is expected, therefore, that a semiconductor device according to the present invention when assembled in a DirectFFT or a conventional package such as a TO-220 package will reduce the overall resistance of the package.
- FIGS. 20A-20C show the dimensions of the test patterns. The design rules used on each pattern are listed below.
- Pattern 1 full surface coverage ( FIG. 20A );
- Pattern 3 (copper under source pads only) ( FIG. 20C ):
- FIG. 21 illustrates the effect that a pattern may have on the resistivity of the device.
- copper patterns 1 and 2 FIGS. 20A and 20B ), which cover respectively, all of and a substantial part of the area of the power electrode contribute the most to the reduction of the resistivity of the device.
- Plating copper is advantageous in that it may be applied to selective regions of the die, may be applied during the die fabrication process or even during the packaging. Plating is commonly used in the circuit board industry and advantageously is a low temperature process. Plated copper also has the benefit of having electrical resistivity very close to that of pure copper.
- copper is plated using electroplating.
- Electroplating is advantageous specially when a copper thickness of more than a few microns is required in a relatively reasonable time in that electroplating offers relatively fast deposition rates.
- Copper may also be plated using electroless plating if time is not an issue.
- lamination techniques may be used for forming thick copper layers.
- Lamination based techniques of applying thick copper are commonly used in the circuit board industry. While copper or resin films can be applied to wafers using a lamination technique, making electrical connection between the film and the electrodes is likely to require laser or conventional drilling, plating and possibly via filling. Thus, lamination may be more expensive than plating the wafer surface, but can be used to practice the present invention.
- a semiconductor device includes a barrier layer 18 over second power electrode 16 , a copper body 20 over barrier layer 18 .
- Barrier Layer 18 serves to protect second power electrode from contamination due to diffusion of copper.
- a device includes a solderable body 22 formed over copper body 20 .
- stress balancing bodies 128 are formed over copper body 20 in order to even out the stress on die 10 .
- a stress balancing body 128 is formed on each side of the die to even out the stress.
- a suitable material for forming a stress balancing body 128 is nickel.
- the copper and solderable layers may be applied to the front and back side of die 10 simultaneously using the steps described for the front side metallization.
- die 10 is reduced in thickness to further reduce the resistance thereof.
- die 10 may be reduced in thickness to 1.00 ⁇ m or less.
- a semiconductor device according to the present invention can be disposed in a conductive can 28 as described above with reference to FIG. 8 .
- a semiconductor device according to FIG. 22B may be used in combination with a can 28 in the manner described above with reference to FIG. 8 .
- a semiconductor device may be packaged in a conventional package, such as SO-8.
- a package may include a drain lead 116 , which is integrated with a drain pad 118 , a source lead 120 , and a gate lead 122 .
- Drain pad 118 is electrically and mechanically coupled to copper body 20 that is over drain electrode 16 using a conductive adhesive 30 such as solder, or a conductive epoxy.
- Wire bond 124 can be used to connect source lead 120 to copper body 20 over source electrode 12 , and copper body 20 over gate electrode 14 .
- Mold compound 126 can be molded over at least the semiconductor device to form a housing (rendered transparent in FIGS. 24A , 24 B for better illustration) For the package as is well known.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
- This application is a continuation-in-part of U.S. application Ser. No. 11/144,483, filed Jun. 2, 2005, entitled Semiconductor Device With Reduced Contact Resistance which claims the benefit of U.S. Provisional Application No. 60/576,767, filed on Jun. 3, 2004, entitled Semiconductor Die Contact with Reduced Resistance, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference. This application is also based on and claims benefit of U.S. Provisional Application No. 60/821,831, filed on Aug. 9, 2006, entitled Double Sided Copper Plating On Die to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.
- Recent advances in silicon cell technologies have reduced the RA of, for example, a 30V device from 50 to 14 m Ohm-mm2. Advances in semiconductor device technology are likely to continue to reduce the RA. If this trend continues an active area of approximately 10 mm2 can be expected to have an Rdson of 630 μOhm to 240 μOhm depending on the fabrication process.
- If semiconductor device technologies are able to meet these target specifications packaging technologies will have to improve significantly. The introduction of DirectFET® technology has enabled significant reductions in die free package resistance compared to conventional 8 lead SOIC power packages. A DirectFET® package (sold by the assignee of the present application), in simple terms, is a semiconductor package which includes a conductive can, and a semiconductor die disposed inside the can and electrically and mechanically connected to an interior surface of the can. U.S. Pat. No. 6,624,522 shows an example of such a package. Using the packaging concept embodied in a DirectFET® package, package resistance, excluding top metal resistance (the resistance associated with the power electrode, e.g. source electrode, of the semiconductor die which is directly connected by solder, conductive epoxy or the like to a conductive pad of a substrate such as a circuit board) is now
sub 100 μOhm. However, when one considers the top metal resistance this is increased somewhat to between 0.2 and 0.7 mOhm depending on the model used. For example, through modeling it has been found that the top metallization can include current paths with up to 0.66 mOhm resistance. It is, therefore, desirable to reduce the resistance of the top metal of the semiconductor die in order to improve the overall resistance of a package such as a DirectFET™ package. - According to one aspect of the present invention, the electrical resistance of a power electrode of a semiconductor device is reduced by forming a thick, and highly conductive metal such as copper to the top metal. Thus, a device according to the present invention includes a semiconductor die, having an electrode on a surface thereof, the electrode electrically and mechanically connected to the die being comprised of a first conductive material, and a conductive body, the conductive body being comprised of a second material having a resistivity that is lower than that of first conductive material.
- In one embodiment, a barrier layer may be interposed between the conductive body and the electrode.
- In another embodiment, the back electrode may also a conductive material of lower resistivity.
- In yet another embodiment, a stress balancing metallic body may be applied to balance the stress on the die.
- Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
-
FIG. 1 illustrates a top plan view of a semiconductor die according to the prior art. -
FIG. 2 shows a top plan view of a semiconductor device according to the present invention. -
FIG. 3 shows a cross-sectional view of a semiconductor device according to the present invention along line 3-3 and viewed in the direction of the arrows. -
FIG. 4 shows a top plan view of a semiconductor device according to the present invention having a passivation layer formed thereon. -
FIG. 5 shows a cross-sectional view of the device shown inFIG. 4 along line 5-5 and viewed in the direction of the arrows -
FIG. 6 show a top perspective view of a package which includes a semiconductor device according to the present invention. -
FIG. 7 shows a bottom perspective view of a package which includes a semiconductor device according to the present invention. -
FIG. 8 illustrates a cross-sectional view of the package shown inFIG. 7 along line 8-8 and viewed in the direction of the arrows. -
FIGS. 9-17 illustrate the steps in the fabrication of a semiconductor device according to an embodiment of the present invention. -
FIG. 18 shows a summary of a process for fabricating a device according to an embodiment of the present invention. -
FIG. 19 shows the effect of the thickness of a conductive body on the lowering of the electrical resistivity in a semiconductor device according to the present invention. -
FIG. 20A illustrates the top plan view of an example of the present invention, in which the conductive body having the lower resistivity covers the entire surface of the electrodes of a semiconductor device. -
FIG. 20B illustrates the top plan view of an example of the present invention, in which the conductive body having the lower resistivity covers not all but a substantial portion of the electrodes of a semiconductor device. -
FIG. 20C illustrates the top plan view of an example of the present invention, in which the conductive body having the lower resistivity covers not all but a lesser portion (less than that shown byFIG. 20B ) of the entire surface of the electrodes of a semiconductor device. -
FIG. 21 graphically illustrates the effect of a pattern of the conductive body on the lowering of electrical resistivity. -
FIG. 22A illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present invention. -
FIG. 22B illustrates a cross-sectional view of a semiconductor device according to an alternative embodiment of the present invention. -
FIG. 23 illustrates a cross-sectional view of a package containing a semiconductor device according to the present invention. -
FIG. 24A illustrates a top plan view of a semiconductor device disposed in an alternative package. -
FIG. 24B illustrates a cross-sectional view of the package ofFIG. 24A alongline 24B-24B, viewed in the direction of the arrows. - Referring to
FIG. 1 , a semiconductor device, such as a power MOSFET, according to the prior art includes asemiconductor body 10, at least one power electrode 12 (i.e. source electrode), and a control electrode (i.e. gate electrode) 14. The device shown inFIG. 1 is a vertical conduction type power device, and includes a second power electrode (i.e. drain electrode) (not shown) on a surface ofsemiconductor body 10 oppositefirst power electrodes 12. - The electrodes of a power device are made usually from Al, AlSi, or AlSiCu.
- Referring next to
FIGS. 2 and 3 , a semiconductor device according to the present invention includessemiconductor body 10, at least onefirst power electrode 12, and acontrol electrode 14. Referring specifically toFIG. 3 , a device according to the present invention preferably includessecond power electrode 16 disposed opposite on semiconductor body oppositepower electrode 12. A semiconductor device according to the preferred embodiment of the present invention is a vertical conduction type power MOSFET in whichfirst power electrode 12 is the source electrode, thesecond power electrode 16 is the drain electrode andcontrol electrode 14 is the gate electrode. It should be noted that althoughFIG. 2 shows twofirst power electrodes 12, the present invention does not require two first power electrodes. Furthermore, it should be noted that although the preferred embodiment is a power MOSFET, the present invention is fully applicable to other power semiconductor devices including IGBTs, power diode, triacs, and power bipolar transistors, and the like. - Referring now specifically to
FIG. 3 , a semiconductor device according to the preferred embodiment of the present invention includesbarrier layer 18 which is disposed on and electrically connected to afirst power electrode 12, andconductive body 20 which is disposed on and electrically connected tobarrier layer 18.Conductive body 20 is preferably made from copper, but can be made from any material of lower resistivity than that offirst power electrode 12.Barrier layer 18 is preferably formed from titanium (Ti) and functions to a) to hinder and prevent contamination offirst power electrode 12 by copper through diffusion, and b) ensure good adhesion ofcopper body 20 tofirst power electrode 12. In the preferred embodiment of the present inventiontitanium barrier layer 18 is about 20 nanometers thick. The thickness ofcopper body 20 can be selected to attain the desired resistivity, and is preferably between 10 μm to 20 μm. It is believed, however, that in a process according to the present invention it may be possible to achievecopper bodies 20 of as thick as 100 μm and possibly thicker. It also should be noted thatbarrier layer 18 can be eliminated ifconductive body 20 is made from such a material that a) adheres well tofirst power electrode 12, and b) does not diffuse intofirst power electrode 12, or otherwise harms the functionality of the semiconductor die. - A device according to the present invention is preferably configured for flip-chip-type mounting. Specifically,
copper body 20 on each electrode is provided withsolderable body 22 which enablescopper body 20 to become electrically and mechanically connectable to a conductive pad directly by a conductive adhesive such as solder, or a conductive epoxy, such as silver loaded epoxy. - Examples of suitable
solderable bodies 22 include a nickel (e.g. 1-6 microns thick, specifically, for example, about two microns thick) layer overcopper body 20 and a lead tin layer (e.g. about one micron thick) formed over the nickel layer, a bimetal stack such as NiAg, or NiAu. The Au may be deposited using a flash or immersion process. - It should be noted that in the preferred embodiment both
first power electrodes 12 andcontrol electrode 14 includebarrier layer 18, acopper body 20 and optionally asolderable body 22 to facilitate flip-chip mounting. - Referring next to
FIGS. 4 and 5 , a device according to the present invention may include a passivation body 24 (illustrated by slanted lines inFIG. 4 ).Passivation body 24 includes at least oneopening 26 to expose a respectivesolderable body 22 whereby a conductive adhesive can reach the exposed solderable body at the bottom of each opening inpassivation body 24. -
Passivation body 24 is preferably composed of a suitable epoxy, polyimide, BCB (benzocyclobutene), or other organic material that can also function as a solder resist. As a result, solder or any other conductive adhesive is prevented from traveling and shorting afirst power electrode 12 to controlelectrode 14 when the device is flip-chip mounted. - Referring next to
FIGS. 6 , 7 and 8, a device according to the present invention can be disposed within aconductive can 28 or some other conductive clip according to the concepts disclosed in U.S. Pat. No. 6,624,522, which is assigned to the assignee of the present invention, and the disclosure of which is incorporated by reference. - Referring specifically to
FIG. 8 ,second power electrode 16 is electrically and mechanically attached to an interior surface ofcan 28 by a layer of conductive adhesive 30 such as solder or conductive epoxy. Thus,conductive can 28, which is preferably formed from copper or a copper alloy, can serve as an electrical connector forsecond power electrode 16. Specifically, can 28 includes connection surfaces 32 each for external electrical connection (by a conductive adhesive such as solder, or conductive epoxy) to a respectiveconductive pad 34 on asubstrate 36, such as a circuit board. In addition,control electrode 14 and each first power electrodes 12 (only one illustrated for clarity) is available for direct electrical connection to a respectiveconductive pad 34 by a conductive adhesive such as solder or conductive epoxy in that each includes asolderable body 22 disposed thereover. - Alternatively,
second power electrode 16 of a device according to the present invention can be electrically and mechanically attached by a conductive adhesive such as solder or conductive epoxy to the conductive pad of a lead frame or a substrate such as a circuit board. - A device, according to the present invention is fabricated according to a method described hereafter.
- Referring first to
FIG. 9 , asemiconductor wafer 102 is prepared to have a plurality of semiconductor die each having at least onepower electrode 100.Power electrode 100 may befirst power electrode 12 as seen in the preferred embodiment. Also, each die may include acontrol electrode 104, such ascontrol electrode 14 as described above, which is processed simultaneously with thepower electrode 100. - Referring next to
FIG. 1.0 , ablanket barrier layer 106 is formed over one face ofwafer 102 coveringelectrodes wafer 102 between the electrodes.Barrier layer 106 is preferably formed from titanium and may be about 20 nanometers thick. Titanium may be sputtered. Other suitable materials for formingblanket barrier layer 106 include tantalum or titanium tungsten. - Thereafter, a blanket
copper seed layer 108 is formed onbarrier layer 106, as seen inFIG. 11 . Blanketcopper seed layer 108 may be about 200 nanometers thick and may be sputtered on as well. Alternatively, blanketcopper seed layer 108 may be plated through electroless plating. Blanketcopper seed layer 108 forms a low resistance path for the plating current and acts as a plating electrode. - Next,
photoresist layer 110 is formed over blanketcopper seed layer 108, as seen inFIG. 12 . In one embodiment ashipley BPR 100 liquid photoresist was used to formphotoresist layer 110. This material is available from Rohm and Haas electronic materials, Marlborough, Mass., and was selected as it is capable of forming a layer of up to 100 μm in a single application.Photoresist layer 110 is then patterned through conventional photolithography to includeopenings 112 each exposing a portion of blanketcopper seed layer 108 over eachelectrode FIG. 13 . - The photoresist deposition, edge bead removal, and procure can be completed on a spin coater track system. The photoresist is then exposed in a mask aligner or similar photo tool. The exposed photoresist material is then developed in a suitable developer solution. If required, a post develop bake stage at elevated temperatures may be performed. The following is an example of a process for applying a photoresist:
-
- 1. Pre-clean: Iso-propyl Alcohol (IpA) 30 seconds at 50 rpm followed by
nitrogen 2 min at 500 rpm. - 2. Dispense: 5.5 ml of
BPR 100 dispensed within 20 seconds on a wafer spinning at 50 rpm. - 3. Spread cycle: ramp to 500 rpm at 100 rpm/sec acceleration, followed by 10 sec spin.
- 4. Spin cycle: ramp to 1000 rpm (100 rpm/sec acceleration) followed by 30 sec spin.
- 5. Dry cycle: 30 sec at 300 rpm.
- 6. Edge Bead Removal: IPA to remove photoresist from 2 mm perimeter.
- 7. Soft Bake: 3 min 65° C. in a convection oven ramped up to 90° C. to cure for 30 minutes.
- 8. Exposure: coated wafers were exposed to UV light at 5 mJ for 3 minutes.
- 9. Post bake: 10 minutes at 110° C.
- 10. Development: photoresist was developed using BPR developer; bath was made up of 96% v/v deionized water and 4% v/v developer.
- 11. Final rinse and dry: with deionized water followed by nitrogen on the spin coater.
- 1. Pre-clean: Iso-propyl Alcohol (IpA) 30 seconds at 50 rpm followed by
- During photoresist developing residual photoresist material may remain in opened apertures. In order to enable uniform plating into these apertures the residual resist should be removed. This is done preferably using an oxygen plasma clean process (wafers are bombarded with O2).
- Thereafter, as illustrated by
FIG. 14 , anelectrical contact 113 and sealclamp 114 is applied to the edges ofwafer 102.Electrical contact 113 and sealclamp 114 is provided to apply voltage toelectrodes - Next,
wafer 102 is immersed in an electroplating solution, and the appropriate voltage is applied toelectrical contact 113 whereby acopper body 20 is grown in eachopening 112 on exposedcopper seed layer 108. Also, asolderable body 22 is formed over eachrespective copper body 20 as seen inFIG. 15 . - For example, the following procedure can be followed to carry out the electroplating step:
-
- 1. Put wafer on a chuck. The chuck is a mechanical fixture which also provides electrical contact.
- 2. Leak test to assure tight seal.
- 3. Wet wafer.
- 4. Remove oxide layer on copper with 10% Sulphuric acid.
- 5. Rinse with deionized water.
- 6. Dry with nitrogen.
- 7. Copper plate in a commercial copper plating solution. The solution may be agitated. In certain systems the wafer is rotated to aid deposition.
- 8. Rinse with deionized water.
- 9. Dry with nitrogen.
- 10. Nickel plate in a commercial nickel plating solution.
- 11. Rinse with deionized water.
- 12. Dry with nitrogen.
- 13. SnPb plate in commercial plating bath.
- 14. Rinse with deionized water.
- 15. Dry with nitrogen.
- In a typical electroplating process, the surface to be electroplated forms the cathode and is submerged in a plating solution. Each manufacturer may offer its own plating solution. Manufacturers of these materials include Atotech, MacDermid, Rohm and Hass, and Cookson Electronics. The plating solution may be any one of the following:
-
- 1. Alkaline—several modifications of cyanide and non-cyanide.
- 2. Mildly alkaline—pyro phosphate
- 3. Acid—sulfate and fiuorobate.
- More typically the plating solution is acid based. An example of such a plating solution may include the following chemicals:
-
- 1. H2SO4 contributes to the overall solution conductivity, reduced anode and cathode polarization (e.g. 60 g/ltr).
- 2. CuSO4 medium for plating (e.g. 200 g/ltr).
- 3. HCL, which helps to corrode anode (e.g. ppm level).
- 4. Brightener/Grain refiner.
- 5. Carrier/polarizer, which helps with crystal deposition and organization.
- 6. Leveller, which helps with crystal deposition and organization.
- The last three ingredients are typically organic materials. During the plating the following chemical reactions occur at each electrode:
-
- At Anode (+Ve charged): Oxidation of the copper Cu→Cu2++2e−
- At Cathode/Wafer (−Ve charged): Reduction of Copper Cu2++2e−→Cu
- As a rule of thumb and from
Faradays laws 2×96,485 coulombs of charge are usually required to produce one mole of copper from copper (II) ion (Cu2+). The rate of plating is determined by the current applied to the electrodes and can be determined using the relationship Q=current (I)×time (t) in conjunction with Faradays law. - Next, the remaining
photoresist 110 is removed as seen inFIG. 16 . Thereafter, anycopper seed material 108 andbarrier material 106 that is not undercopper bodies 20 is removed to obtain the structure shown inFIG. 17 . - For example, the following procedure can be carried out:
-
- 1. Strip the remaining photoresist with stripper with BPR Stripper
- 2. Etch copper with a copper etchant. Both alkaline and acid chemistries are suitable for etching copper. Two of the most common etchant chemistries are ammoniacal etchant and cupric chloride etchant.
- 3. Rinse with deionized water.
- 4. Dry with nitrogen.
- 5. Etch titanium with titanium etchant, for example, Hydrogen Peroxide or dilute Hydrofloric acid.
- 6. Rinse with deionized water.
- 7. Dry with nitrogen.
- 8. Take the wafer out of the chuck.
- The wafer can then be processed according to any known method to obtain a device according to the present invention. For example, back metal is applied to form second power electrode, and
passivation 24 is applied and patterned to obtain a plurality of devices as described above. - For example, the wafer can be passivated through a screen printing process. The passivation material is preferably an aqueous developing, liquid photoimagable polymer. The following is an example of a procedure that can be followed in applying the passivation:
-
- 1. Mix the passivation material: 100 parts paste part to 19 parts hardener by weight.
- 2. Screen print the mixture.
- 3. Tack dry in convection oven at 80° C. for 20 minutes.
- 4. Expose the passivation for 25 seconds at 5 mJ.
- 5. Develop the passivation.
- 6. Apply Final cure for 60 minutes at 150° C. in a convection oven.
- It should be noted that in some cases the wafer may become warped. This is due to high stresses caused by the recrystallization of the fine grain structure of the electroplated copper.
- Thereafter,
wafer 102 is diced to obtain individual semiconductor devices according to the present invention, which can be ready to be received in aconductive can 28 as described above, or packaged in any other package for example an SO8, TO-220, D2pak, Dpak and MLP packages. - To perform the dicing step it may be preferable to use a dual step cutting process. The first cut should be performed with a blade specially designed for copper dicing, followed by a standard blade suitable for cutting a semiconductor die at a standard speed. Although the wafer can be fabricated without any copper in the wafer streets, copper dicing may be necessary to penetrate the residual copper present on the perimeter of the wafer contact ring. The copper deposition can be avoided by correctly designing the perimeter plating contact to fit within the plating chuck seal, thereby eliminating the copper dicing step. The re-design may also help to reduce wafer warpage, as the plated copper on the contact ring can be one of the main contributors to the stress within the wafer.
-
FIG. 18 summarizes a process for fabricating a semiconductor device according to the present invention. - It should be noted that any material left from copper seed layer merges with the electroplated
copper bodies 20. Thus, a device according to the preferred embodiment of the present invention will include acopper body 20 formed over aharrier layer 18. - Alternatively, copper bodies may be applied to a MOSFET die using a process of seed layer deposition, electroplating, photoresist, copper etch/strip or alternatively by pattern plating. In the alternative process, the photoresist is applied after electroplating. However, applying photoresist prior to electroplating is preferred in that only minimal copper etching is required and tighter tolerances are often achievable on the thick copper films.
- The metal finish required on the top surface of the copper is determined by the required interconnection between the die and the package or the die and the circuit board. For solderable contacts to a copper surface a Nickel barrier is typically required followed by a thin gold film. The nickel acts as a solderable layer and acts to prevent solder forming intermetallics with the underlying copper. The gold layer prevents oxidation of the nickel and is consumed during the soldering process. Typical recommended nickel thickness is in the range of 1 to 8 μm, or preferably 4 to 8 μm.
- It should also be noted that a
copper body 20 need not cover the entire surface of the electrode over which it resides. Rather, the device covered by a copper body can be varied to obtain the desired reduction in the resistivity for the device. - Referring for example to
FIGS. 20A-20C which show respectively a first pattern, a second pattern, and a third pattern, forcopper bodies 20, it has been observed through experimentation that pattern variation may affect the resistivity obtained. - Relatively simple models based upon using the relationship R=ρL/A show that top metal resistance can add significant resistance to current flowing along the top surface of a die. In practice these models are flawed in that they only consider current flowing in one direction and do not include the parallel current paths that surround the device source pads connected to a circuit board. In order to obtain more accurate estimates of the benefits of adding thick copper to the power electrode of a die, finite element analysis (FEA) was performed. As is well known, the finite element method operates on the theory that any continuous function over a global domain can be approximated by a series of functions operating over a finite number of small sub-domains. ANSYS, available from ANSYS, Inc., Canonsburg, Pa., is a software which can be used for performing final element analyses. ANSYS solid models were set up and refined to include contributions from die, substrate, die attach adhesive and the copper can. Using this model as a baseline a copper layer was added to the model. The thickness of this layer was then modified to investigate the effect of metal thickness upon device Rdson.
- FEA models of devices with thick copper showed less voltage dropped across the source region compared to devices with Aluminum front metal only.
-
FIG. 19 shows the effect upon device Rdson of increasing the metal thickness. Note that models of copper under just the source pads and all over the die were investigated. For example, with zero copper thickness and 4 μm aluminum the device Rdson is approx 1.9 mOhm. As the thickness of copper is increased to 20 μm the Rdson drops to 1.67 m Ohm. This represents a reduction of over 200 μOhm. - Also models were developed to examine the effect of adding thick copper as the die size is reduced, keeping the die resistivity the same as the larger die. In both cases it appears possible to reduce Rdson by over 0.5 mOhm by adding about 20 μm of copper.
- Interestingly, the absolute reduction in Rdson by adding thick copper appeared more significant in the smaller die sizes. It is believed that this result is due to the aspect ratio of the source areas being higher in smaller die, resulting in higher initial top metal resistance.
- Thus, through experiments and models the inventors have discovered that a die having a thick copper body formed on a power electrode thereof exhibits a significantly reduced resistance. In both cases, for example, the addition of 1 to 20 μm of copper has shown reductions in Rdson in the range of 180 to 200 μOhm. Furthermore models predict that similar, if not greater, absolute shifts in Rdson are possible with smaller die, and some models predict significant reductions in Rdson are possible by combining thick copper with thinned die. It is expected, therefore, that a semiconductor device according to the present invention when assembled in a DirectFFT or a conventional package such as a TO-220 package will reduce the overall resistance of the package.
- To examine the effect of area coverage on the resistivity of the device, a test mask was designed with three different die test patterns.
FIGS. 20A-20C show the dimensions of the test patterns. The design rules used on each pattern are listed below. - Pattern 1 (full surface coverage) (
FIG. 20A ); -
- Min 220 μm clearance,
-
Min 50 μm clearance to nearest Al feature, - Area of feature on source: 2×4.34 mm2,
- Area of feature on gate: 0.77 mm2,
- Pattern 2 (reduced coverage) (
FIG. 20B ): -
- Min 300 μm clearance,
-
Min 50 μm clearance to the nearest Al feature, - Area of feature on source: 2×3.80 mm2
- Area of feature on gate: 0.77 mm2
- Pattern 3 (copper under source pads only) (
FIG. 20C ): -
- identical to Passivation opening,
- Area of feature on source: 2×1.79 mm2
- Area of feature on gate: 0.71 min2
-
FIG. 21 illustrates the effect that a pattern may have on the resistivity of the device. As seencopper patterns 1 and 2 (FIGS. 20A and 20B ), which cover respectively, all of and a substantial part of the area of the power electrode contribute the most to the reduction of the resistivity of the device. - Plating copper is advantageous in that it may be applied to selective regions of the die, may be applied during the die fabrication process or even during the packaging. Plating is commonly used in the circuit board industry and advantageously is a low temperature process. Plated copper also has the benefit of having electrical resistivity very close to that of pure copper.
- In the preferred embodiment copper is plated using electroplating. Electroplating is advantageous specially when a copper thickness of more than a few microns is required in a relatively reasonable time in that electroplating offers relatively fast deposition rates.
- Copper may also be plated using electroless plating if time is not an issue.
- Other methods can also be used for forming a conductive body on an electrode of the device according to the present invention.
- For example, thick film screen-printing is a low cost method available for forming a thick copper layer on an electrode of a power device. However, the processing temperatures for thick screen printing is relatively high (e.g. 500° C.+), and may in some cases cause wafer warpage (depending on the wafer). Nevertheless, such a process can be used to practice the present invention. Low temperature pastes may be used to overcome the problems associated with the high temperatures as long as the paste that is used is of lower resistance.
- In addition, lamination techniques may be used for forming thick copper layers. Lamination based techniques of applying thick copper are commonly used in the circuit board industry. While copper or resin films can be applied to wafers using a lamination technique, making electrical connection between the film and the electrodes is likely to require laser or conventional drilling, plating and possibly via filling. Thus, lamination may be more expensive than plating the wafer surface, but can be used to practice the present invention.
- In summary, for the reasons stated above, electroplating is preferred over other methods, although other methods are considered to be within the scope and the spirit of the present invention.
- Referring to
FIG. 22A , in which like numerals identify like features, a semiconductor device according to the present invention includes abarrier layer 18 oversecond power electrode 16, acopper body 20 overbarrier layer 18.Barrier Layer 18 serves to protect second power electrode from contamination due to diffusion of copper. A device according to the preferred embodiment of the present invention includes asolderable body 22 formed overcopper body 20. - The stack of
barrier layer 18, andcopper body 20 can be formed according to the process set forth above. In the preferred process, after deposition ofcopper seed layer 108 onbarrier layer 18 onelectrodes front electrodes back electrode 16 at the same time. - Referring now to
FIG. 22B , in which like numerals identify like features, in another embodiment of the present invention,stress balancing bodies 128 are formed overcopper body 20 in order to even out the stress ondie 10. Specifically, astress balancing body 128 is formed on each side of the die to even out the stress. A suitable material for forming astress balancing body 128 is nickel. Thus, the application of the nickel on both sides of die 10 counterbalances the stress created on the active side of the device. - Applying thick metallization to both sides of die 10 evens out the stress between front and backside metallization on
die 10. Ideally equal areas and thickness of nickel should be applied on the front and rear side ofdie 10. For example, with reference toFIG. 22B on the total area of thefront side copper 20 should equal the area ofcopper 20 on the rear of the die. - Note that the copper and solderable layers may be applied to the front and back side of
die 10 simultaneously using the steps described for the front side metallization. - According to one aspect of the present invention, die 10 is reduced in thickness to further reduce the resistance thereof. Thus, die 10 may be reduced in thickness to 1.00 μm or less.
- Referring now to
FIG. 23 , in which like numerals identify like features, a semiconductor device according to the present invention can be disposed in aconductive can 28 as described above with reference toFIG. 8 . Alternatively, a semiconductor device according toFIG. 22B may be used in combination with acan 28 in the manner described above with reference toFIG. 8 . - Referring now to
FIGS. 24A-24B , a semiconductor device according to the present invention may be packaged in a conventional package, such as SO-8. Such a package may include adrain lead 116, which is integrated with adrain pad 118, asource lead 120, and agate lead 122.Drain pad 118 is electrically and mechanically coupled tocopper body 20 that is overdrain electrode 16 using a conductive adhesive 30 such as solder, or a conductive epoxy.Wire bond 124 can be used to connect source lead 120 tocopper body 20 oversource electrode 12, andcopper body 20 overgate electrode 14.Mold compound 126 can be molded over at least the semiconductor device to form a housing (rendered transparent inFIGS. 24A , 24B for better illustration) For the package as is well known. - Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/483,989 US20150001722A1 (en) | 2004-06-03 | 2014-09-11 | Semiconductor Device with Reduced Contact Resistance |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US57676704P | 2004-06-03 | 2004-06-03 | |
US11/144,483 US7678680B2 (en) | 2004-06-03 | 2005-06-02 | Semiconductor device with reduced contact resistance |
US82183106P | 2006-08-09 | 2006-08-09 | |
US11/890,965 US8390131B2 (en) | 2004-06-03 | 2007-08-08 | Semiconductor device with reduced contact resistance |
US13/780,161 US8836145B2 (en) | 2004-06-03 | 2013-02-28 | Power semiconductor device with reduced contact resistance |
US14/483,989 US20150001722A1 (en) | 2004-06-03 | 2014-09-11 | Semiconductor Device with Reduced Contact Resistance |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/780,161 Continuation US8836145B2 (en) | 2004-06-03 | 2013-02-28 | Power semiconductor device with reduced contact resistance |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150001722A1 true US20150001722A1 (en) | 2015-01-01 |
Family
ID=38970669
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/890,965 Active US8390131B2 (en) | 2004-06-03 | 2007-08-08 | Semiconductor device with reduced contact resistance |
US13/780,161 Active US8836145B2 (en) | 2004-06-03 | 2013-02-28 | Power semiconductor device with reduced contact resistance |
US14/483,989 Abandoned US20150001722A1 (en) | 2004-06-03 | 2014-09-11 | Semiconductor Device with Reduced Contact Resistance |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/890,965 Active US8390131B2 (en) | 2004-06-03 | 2007-08-08 | Semiconductor device with reduced contact resistance |
US13/780,161 Active US8836145B2 (en) | 2004-06-03 | 2013-02-28 | Power semiconductor device with reduced contact resistance |
Country Status (1)
Country | Link |
---|---|
US (3) | US8390131B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160235953A1 (en) * | 2015-02-16 | 2016-08-18 | Cenefom Corp. | Hemostatic equipment |
EP4369393A1 (en) * | 2022-11-10 | 2024-05-15 | Siemens Aktiengesellschaft | Semiconductor device comprising a switchable semiconductor element and method of obtaining the same |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011046517A1 (en) | 2009-10-16 | 2011-04-21 | Empire Technology Development Llc | Apparatus and method of applying a film to a semiconductor wafer and method of processing a semiconductor wafer |
DE112012003228B4 (en) * | 2011-08-04 | 2021-08-12 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US8698293B2 (en) * | 2012-05-25 | 2014-04-15 | Infineon Technologies Ag | Multi-chip package and method of manufacturing thereof |
JP5726215B2 (en) * | 2013-01-11 | 2015-05-27 | 株式会社豊田中央研究所 | Cooling type switching element module |
JP2015005623A (en) * | 2013-06-20 | 2015-01-08 | 株式会社東芝 | Semiconductor device |
US9536800B2 (en) | 2013-12-07 | 2017-01-03 | Fairchild Semiconductor Corporation | Packaged semiconductor devices and methods of manufacturing |
US9328418B2 (en) * | 2014-09-16 | 2016-05-03 | Eastman Kodak Company | Method of forming a patterned polymer layer |
JP2022044549A (en) * | 2020-09-07 | 2022-03-17 | ロバート ボッシュ (オーストラリア) ピーティーワイ リミテッド | Packaging method for rectifying element and rectifying element |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5038195A (en) * | 1990-02-09 | 1991-08-06 | Ibm | Composition and coating to prevent current induced electrochemical dendrite formation between conductors on dielectric substrate |
US6164523A (en) * | 1998-07-01 | 2000-12-26 | Semiconductor Components Industries, Llc | Electronic component and method of manufacture |
US20010034083A1 (en) * | 2000-01-26 | 2001-10-25 | Coyle Anthony L. | Method of fabricating a molded package for micromechanical devices |
US20020079459A1 (en) * | 2000-12-21 | 2002-06-27 | Ralf Dorscheid | Detector for the detection of electromagnetic radiation |
US20020167082A1 (en) * | 2001-05-09 | 2002-11-14 | Hans Weber | Compensation component, circuit configuration, and method |
US20020185710A1 (en) * | 1999-09-13 | 2002-12-12 | Vishay Intertechnology, Inc. | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US20050151233A1 (en) * | 2004-01-13 | 2005-07-14 | Halliburton Energy Services, Inc. | Conductive material compositions, apparatus, systems, and methods |
US20060145319A1 (en) * | 2004-12-31 | 2006-07-06 | Ming Sun | Flip chip contact (FCC) power package |
US7508077B2 (en) * | 2004-07-09 | 2009-03-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing same |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2332822B2 (en) * | 1973-06-28 | 1978-04-27 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Process for the production of diffused, contacted and surface-passivated semiconductor components from semiconductor wafers made of silicon |
US4408216A (en) * | 1978-06-02 | 1983-10-04 | International Rectifier Corporation | Schottky device and method of manufacture using palladium and platinum intermetallic alloys and titanium barrier for low reverse leakage over wide temperature range |
EP0332254B1 (en) * | 1988-03-07 | 1994-01-19 | Koninklijke Philips Electronics N.V. | Multilayer capacitor |
GB8807729D0 (en) * | 1988-03-31 | 1988-05-05 | British Telecomm | Device mounting |
US5015803A (en) * | 1989-05-31 | 1991-05-14 | Olin Corporation | Thermal performance package for integrated circuit chip |
JPH07101736B2 (en) * | 1990-06-28 | 1995-11-01 | 日本電装株式会社 | Semiconductor device and manufacturing method thereof |
JP3193100B2 (en) | 1992-03-13 | 2001-07-30 | 富士通株式会社 | Semiconductor device |
US5451544A (en) * | 1993-10-15 | 1995-09-19 | International Rectifier Corporation | Method of manufacturing a back contact for semiconductor die |
US5532512A (en) * | 1994-10-03 | 1996-07-02 | General Electric Company | Direct stacked and flip chip power semiconductor device structures |
JP2725611B2 (en) | 1994-10-19 | 1998-03-11 | 株式会社デンソー | Semiconductor device |
US5468984A (en) * | 1994-11-02 | 1995-11-21 | Texas Instruments Incorporated | ESD protection structure using LDMOS diodes with thick copper interconnect |
JP3136390B2 (en) * | 1994-12-16 | 2001-02-19 | 株式会社日立製作所 | Solder joining method and power semiconductor device |
US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
JPH09260645A (en) | 1996-03-19 | 1997-10-03 | Sanyo Electric Co Ltd | Semiconductor device |
AU705177B1 (en) * | 1997-11-26 | 1999-05-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP3406817B2 (en) * | 1997-11-28 | 2003-05-19 | 株式会社東芝 | Method for marking metal layer and semiconductor device |
JP4085536B2 (en) * | 1998-11-09 | 2008-05-14 | 株式会社日本自動車部品総合研究所 | ELECTRIC DEVICE, ITS MANUFACTURING METHOD, AND PRESSURE SEMICONDUCTOR DEVICE |
US6376910B1 (en) * | 1999-06-23 | 2002-04-23 | International Rectifier Corporation | Solder-on back metal for semiconductor die |
US6180526B1 (en) * | 1999-09-17 | 2001-01-30 | Industrial Technology Research Institute | Method for improving conformity of a conductive layer in a semiconductor device |
JP3630070B2 (en) | 2000-03-30 | 2005-03-16 | 株式会社デンソー | Semiconductor chip and semiconductor device |
JP2001217275A (en) | 2000-02-03 | 2001-08-10 | Matsushita Electric Works Ltd | Flip-chip mounting structure for semiconductor device |
US6624522B2 (en) | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
JP3650008B2 (en) * | 2000-09-04 | 2005-05-18 | 三洋電機株式会社 | Protection circuit device using MOSFET and manufacturing method thereof |
JP3745213B2 (en) * | 2000-09-27 | 2006-02-15 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP3655181B2 (en) | 2000-09-28 | 2005-06-02 | 株式会社東芝 | Semiconductor device and its package |
CN1173411C (en) * | 2000-11-21 | 2004-10-27 | 松下电器产业株式会社 | Semiconductor device and its manufacturing method |
US6566164B1 (en) * | 2000-12-07 | 2003-05-20 | Amkor Technology, Inc. | Exposed copper strap in a semiconductor package |
JP3526291B2 (en) * | 2001-04-25 | 2004-05-10 | 三菱電機株式会社 | Capacitor module and semiconductor device using the same |
US6413851B1 (en) * | 2001-06-12 | 2002-07-02 | Advanced Interconnect Technology, Ltd. | Method of fabrication of barrier cap for under bump metal |
US6372619B1 (en) * | 2001-07-30 | 2002-04-16 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for fabricating wafer level chip scale package with discrete package encapsulation |
JP2003045877A (en) | 2001-08-01 | 2003-02-14 | Sharp Corp | Semiconductor device and its manufacturing method |
JP2004047622A (en) | 2002-07-10 | 2004-02-12 | Fujitsu Ltd | Method for electrically connecting electrodes |
US6946740B2 (en) * | 2002-07-15 | 2005-09-20 | International Rectifier Corporation | High power MCM package |
US7804131B2 (en) * | 2006-04-28 | 2010-09-28 | International Rectifier Corporation | Multi-chip module |
-
2007
- 2007-08-08 US US11/890,965 patent/US8390131B2/en active Active
-
2013
- 2013-02-28 US US13/780,161 patent/US8836145B2/en active Active
-
2014
- 2014-09-11 US US14/483,989 patent/US20150001722A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5038195A (en) * | 1990-02-09 | 1991-08-06 | Ibm | Composition and coating to prevent current induced electrochemical dendrite formation between conductors on dielectric substrate |
US6164523A (en) * | 1998-07-01 | 2000-12-26 | Semiconductor Components Industries, Llc | Electronic component and method of manufacture |
US20020185710A1 (en) * | 1999-09-13 | 2002-12-12 | Vishay Intertechnology, Inc. | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US20010034083A1 (en) * | 2000-01-26 | 2001-10-25 | Coyle Anthony L. | Method of fabricating a molded package for micromechanical devices |
US20020079459A1 (en) * | 2000-12-21 | 2002-06-27 | Ralf Dorscheid | Detector for the detection of electromagnetic radiation |
US20020167082A1 (en) * | 2001-05-09 | 2002-11-14 | Hans Weber | Compensation component, circuit configuration, and method |
US20050151233A1 (en) * | 2004-01-13 | 2005-07-14 | Halliburton Energy Services, Inc. | Conductive material compositions, apparatus, systems, and methods |
US7508077B2 (en) * | 2004-07-09 | 2009-03-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing same |
US20060145319A1 (en) * | 2004-12-31 | 2006-07-06 | Ming Sun | Flip chip contact (FCC) power package |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160235953A1 (en) * | 2015-02-16 | 2016-08-18 | Cenefom Corp. | Hemostatic equipment |
EP4369393A1 (en) * | 2022-11-10 | 2024-05-15 | Siemens Aktiengesellschaft | Semiconductor device comprising a switchable semiconductor element and method of obtaining the same |
WO2024099822A1 (en) * | 2022-11-10 | 2024-05-16 | Siemens Aktiengesellschaft | Semiconductor arrangement with a switchable semiconductor element and method for producing same |
Also Published As
Publication number | Publication date |
---|---|
US8836145B2 (en) | 2014-09-16 |
US20130175690A1 (en) | 2013-07-11 |
US20080017987A1 (en) | 2008-01-24 |
US8390131B2 (en) | 2013-03-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7678680B2 (en) | Semiconductor device with reduced contact resistance | |
US8836145B2 (en) | Power semiconductor device with reduced contact resistance | |
US7759777B2 (en) | Semiconductor module | |
KR100454381B1 (en) | Semiconductor device and manufacturing method thereof | |
US8716063B2 (en) | Wafer level chip scale package and process of manufacture | |
JP2015167257A (en) | Compact electronic apparatus, formation method thereof, and system | |
US7755190B2 (en) | Electronic device including a nickel-palladium alloy layer | |
JP4058619B2 (en) | Semiconductor wafer | |
US20120211884A1 (en) | Wafer chip scale package connection scheme | |
KR101132825B1 (en) | A semiconductor device including a die region designed for aluminum-free solder bump connection and a test structure designed for aluminum-free wire bonding | |
KR20190142102A (en) | Semiconductor device | |
KR100753006B1 (en) | Fabrication method for an interconnect on a substrate and a corresponding interconnect | |
US20200365483A1 (en) | Plating for thermal management | |
CN100508147C (en) | Method for galvanization and forming a contact boss | |
US20090168380A1 (en) | Package substrate embedded with semiconductor component | |
US11876040B2 (en) | Semiconductor devices and methods of manufacturing semiconductor devices | |
JP3506686B2 (en) | Method for manufacturing semiconductor device | |
JP2002237517A (en) | Wafer holder | |
JP3308882B2 (en) | Method for manufacturing electrode structure of semiconductor device | |
JP2023172178A (en) | Semiconductor device and method for manufacturing the same | |
JPH0846042A (en) | Formation of viahole | |
JP2022071925A (en) | Semiconductor device and method for manufacturing semiconductor device | |
JP3726529B2 (en) | Semiconductor device | |
JP2002339078A (en) | Wafer fixture for plating | |
JP2004158656A (en) | Semiconductor device and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL RECTIFIER CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUCHS, SVEN;PAVIER, MARK;REEL/FRAME:033724/0662 Effective date: 20050526 |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AMERICAS CORP., CALIFORNIA Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:INTERNATIONAL RECTIFIER CORPORATION;INFINEON TECHNOLOGIES AMERICAS CORP.;REEL/FRAME:038187/0421 Effective date: 20150929 |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AMERICAS CORP., CALIFORNIA Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:INFINEON TECHNOLOGIES NORTH AMERICA CORP.;INTERNATIONAL RECTIFIER CORPORATION;REEL/FRAME:038463/0859 Effective date: 20150929 Owner name: INFINEON TECHNOLOGIES AMERICAS CORP., CALIFORNIA Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:INFINEON TECHNOLOGIES NORTH AMERICA CORP.;INTERNATIONAL RECTIFIER CORPORATION;INTERNATIONAL RECTIFIER CORPORATION;REEL/FRAME:038463/0859 Effective date: 20150929 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |