US20140353817A1 - Heat dissipation device embedded within a microelectronic die - Google Patents
Heat dissipation device embedded within a microelectronic die Download PDFInfo
- Publication number
- US20140353817A1 US20140353817A1 US13/904,169 US201313904169A US2014353817A1 US 20140353817 A1 US20140353817 A1 US 20140353817A1 US 201313904169 A US201313904169 A US 201313904169A US 2014353817 A1 US2014353817 A1 US 2014353817A1
- Authority
- US
- United States
- Prior art keywords
- microelectronic die
- microelectronic
- conductive material
- heat dissipation
- thermally conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004377 microelectronic Methods 0.000 title claims abstract description 137
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 55
- 239000004020 conductor Substances 0.000 claims abstract description 58
- 241001133184 Colletotrichum agaves Species 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000010849 ion bombardment Methods 0.000 claims description 3
- 238000000608 laser ablation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000001816 cooling Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- -1 poly(methyl methacrylate) Polymers 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000005679 Peltier effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/38—Cooling arrangements using the Peltier effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N19/00—Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10271—Silicon-germanium [SiGe]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
- Embodiments of the present description generally relate to the field of heat dissipation from a microelectronic die, and, more specifically, to a heat dissipation device embedded within the microelectronic die.
- The microelectronic industry is continually striving to produce ever faster and smaller microelectronic dice for use in various mobile electronic products, such as portable computers, electronic tablets, cellular phones, digital cameras, and the like. As these goals are achieved, the density of power consumption of integrated circuit components within the microelectronic dice has increased, which, in turn, increases the average junction temperature of the microelectronic die. If the temperature of the microelectronic die becomes too high, the integrated circuits within the microelectronic die may be damaged or destroyed. In typical microelectronic dice, such as flip-chip type dice, heat is generally removed convectively with a heat spreader/heat sink attached to a back surface of the microelectronic die. However, when microelectronic dice are used in thin products, such as smart phones, tablets, ultrabook computers, and the like, space for the incorporation of such heat removal solutions is limited. Therefore, there is an ongoing effort to design ever more efficient, cost-effective, and lower profile heat dissipation devices for microelectronic dice.
- The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
-
FIG. 1 illustrates a side cross-sectional view of a microelectronic die, according to one embodiment of the present description. -
FIGS. 2 a and 2 b illustrate a side cross-sectional view and a top plan view, respectively, of at least one trench formed in a back surface of the microelectronic die ofFIG. 1 , according to one embodiment of the present description. -
FIGS. 3 a-3 d illustrate side cross-sectional views of various embodiments of trench shapes, according to embodiments of the present description. -
FIG. 4 illustrates a side cross-sectional view of a seed/barrier layer deposited on the microelectronic die back surface and within the trenches of the structure illustrated inFIG. 2 , according to an embodiment of the present description. -
FIG. 5 illustrates a side cross-sectional view of a mask patterned on the microelectronic die back surface with at least one opening corresponding to at least one of the trenches of the structure illustrated inFIG. 4 , according to an embodiment of the present description. -
FIG. 6 illustrates a side cross-sectional view of the trenches ofFIG. 5 filled with a thermally conductive material to form at least one heat transfer device, according to an embodiment of the present description. -
FIG. 7 illustrates a side cross-sectional view of the structure ofFIG. 6 after the removal of the mask, according to an embodiment of the present description. -
FIGS. 8 a and 8 b illustrates a side cross-sectional view and a top plan view, respectively, of a microelectronic die having embedded heat dissipation devices located in specific regions of the microelectronic die, according to another embodiment of the present description. -
FIGS. 9 a and 9 b illustrates a side cross-sectional view and a top plan view, respectively, of a microelectronic die having an embedded thermoelectric cooling device, according to yet another embodiment of the present description. -
FIG. 10 illustrates a side cross-sectional view of a microelectronic die, having an embedded heat dissipation device, attached to a microelectronic structure and having an integrated heat spreading in thermal contract therewith, according to an embodiment of the present description. -
FIG. 11 is a flow chart of a process of forming a heat dissipation device within a microelectronic die, according to an embodiment of the present description. -
FIG. 12 illustrates an electronic system, according to one embodiment of the present description. - In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
- Embodiments of the present description relate to a heat dissipation device that is embedded within a microelectronic die. The heat dissipation device may be fabricated by forming at least one trench extending into the microelectronic die from a microelectronic die back surface, which opposes an active surface thereof, and filling the trenches with at least one layer of thermally conductive material.
- As shown in
FIG. 1 , amicroelectronic die 110 may be fabricated or provided, wherein themicroelectronic die 110 may include anactive surface 112 and anopposing back surface 114. As will be understood to those skilled in the art, themicroelectronic die 110 may include anactive region 116 proximate the microelectronic dieactive surface 112, wherein the integrated circuitry (not shown) of themicroelectronic die 110 is formed in and/or on the microelectronic dieactive region 116. Themicroelectronic die 110 may be formed from any appropriate material, including, but not limited to silicon, germanium, silicon-germanium or III-V compound semiconductor material, and may include a silicon-on-insulator substrate. Themicroelectronic die 110 may be any appropriate microelectronic device, including, but not limited to a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit device, and the like. - As shown in
FIGS. 2 a and 2 b, at least onetrench 120 may be formed to extend into themicroelectronic die 110 from the microelectronicdie back surface 114. Thetrenches 120 may be formed by any technique known in the art, including, but not limited to, lithography with wet or dry etching, ion bombardment, laser ablation, and the like. Although thetrenches 120 ofFIGS. 2 a and 2 b are illustrated to run substantially parallel to one another, it is understood that thetrenches 120 could form any appropriate pattern. Furthermore, although thetrenches 120 are shown inFIG. 2 as having a substantially square shaped in cross-section, it is understood that thetrenches 120 may have any appropriate cross-sectional shape including V-shaped (FIG. 3 a), trapezoidal (FIG. 3 b), rectangular (FIG. 3 c), U-shaped (FIG. 3 d), and the like. As will be understood to those skilled in the art, the cross-sectional shape of thetrenches 120 may be a function of the technique used to form thetrenches 120, as well as the operating parameters used with those techniques. - As shown in
FIG. 4 , at least one seed and/or abarrier layer 130 may be optionally deposited on the microelectronicdie back surface 114 and within thetrenches 120. The seed/barrier layer 130 may be formed from any appropriate material and may be deposited by any technique known in the art, including but not limited to, sputtering processes and electro-less plating processes. As will be understood to those skilled in the art, a barrier layer may be utilized to prevent migration of a subsequently deposited material, and a seed layer may be utilized assist in the subsequent plating of a material. - As shown in
FIG. 5 , amask 140 may be patterned on the microelectronicdie back surface 114 with at least oneopening 142 corresponding to at least one of thetrenches 120. Themask 140 may be any appropriate material, including but not limited to photoresist materials, such as poly(methyl methacrylate), poly(methyl glutarimide), phenol formaldehyde resin, and the like, and may be patterned by any known technique, including but not limited to, lithographic techniques. - As shown in
FIG. 6 , the trenches 120 (seeFIG. 5 ) may be filled with an appropriate thermallyconductive material 152 to form at least oneheat dissipation device 150, and thereby forming amicroelectronic device 155 comprising themicroelectronic die 110 and theheat dissipation device 150. The filling of the trenches 120 (seeFIG. 5 ) may be achieved by any technique known in the art, including but not limited to electrolytic plating. The thermallyconductive material 152 may be any appropriate material including but not limited to metals, such as copper, silver, alloys thereof, and the like. As shown inFIG. 7 , the mask 140 (seeFIG. 6 ) may be removed by any appropriate technique known in the art. It is understood that after the removal of the mask 140 (seeFIG. 6 ), the microelectronicdie back surface 114 and/or the thermallyconductive material 152 may be planarized. - As will be understood to those skilled in the art, the formation of the
heat dissipation device 150 may increase the cross-section contact area for heat transfer, thereby enhancing the removal of heat from themicroelectronic die 110, without substantially changing a thickness T (seeFIG. 2 a), of themicroelectronic die 110. It is understood, that trench depth D (seeFIG. 2 a), trench spacing S (seeFIG. 2 a), and the cross-sectional shape of the trenches 120 (e.g. seeFIGS. 2 a and 3 a-3 d) may be varied depending on thermal performance requirements. It is further understood that the trench depth D should not encroach into the active region 116 (e.g. such that no transition performance would be detected). Additionally, it is understood that the thermally conductive material 152 (seeFIG. 7 ) could be selected to have a coefficient of thermal expansion that substantially counteracts warpage during subsequent reflow processes, as will be understood to those skilled in the art. - Although the
heat dissipation device 150 is shown to extend substantially across the entire microelectronicdie back surface 114 inFIG. 2 b, one of more heat dissipation devices (shown aselements FIGS. 8 a and 8 b) may be selectively formed over “hot spot regions” (shown aselements FIGS. 8 a and 8 b).Hot spot regions microelectronic die 110. The selective formation of theheat dissipation devices microelectronic die 110, as will be understood to those skilled in the art. - In another embodiment of the present description, as shown in
FIGS. 9 a and 9 b, the heat dissipation device may be a thermoelectric heat dissipation device (i.e., a Peltier effect device). A thermoelectric heat dissipation device is a solid-state electric heat pump which utilizes electric current to induce a Peltier effect creating a heat flux between an interface between two different conductive materials, thereby transferring heat from one side of the thermoelectric heat dissipation device to the other side thereof. The thermoelectric heat dissipation device (illustrated as element 170) may comprise a firstconductive material layer 172 and a secondconductive material layer 174 abutting the firstconductive material layer 172, both of which are disposed within atrench 120. The firstconductive material layer 172 may be electrically connected to afirst terminal 182 of a current generatingelectrical device 180 and the secondconductive material layer 174 may be electrically connected to asecond terminal 184 of the current generatingelectrical device 180. Thetrench 120, the firstconductive material layer 172, and the secondconductive material layer 174 may be formed by any known techniques including those discussed with regard toFIGS. 1-8 b. - As shown in
FIG. 10 , the microelectronic die 110 may be attached to afirst surface 204 of themicroelectronic substrate 202 with a plurality ofinterconnects 212. The die-to-substrate interconnects 212, such as soldered interconnects, may extend betweenbond pads 118 formed in or on the microelectronic dieactive surface 112 of themicroelectronic die 110 and substantially mirror-image bond pads 206 in or on the microelectronic substratefirst surface 204. Anunderfill material 224, such as an epoxy material, may be disposed between the microelectronic dieactive surface 112 and the microelectronic substratefirst surface 204. - As further shown in
FIG. 10 , themicroelectronic substrate 202 may provide electrical communication routes (illustrated as dashed lines 208) between themicroelectronic die 110 and external components (not shown). As will be understood to those skilled in the art, the microelectronicdie bond pads 118 are in electrical communication with integrated circuitry (not shown) within themicroelectronic die 110. - As still further illustrated in
FIG. 10 , anintegrated heat spreader 220 may be in thermal contact with themicroelectronic die 110, to form amicroelectronic system 260. Theintegrated heat spreader 220 may have afirst surface 222 and an opposingsecond surface 224 in thermal contact with theheat dissipation device 150 embedded in themicroelectronic die 110. Athermal interface material 232, such as a thermally conductive grease or polymer, may be disposed between the integrated heat spreadersecond surface 224 and theheat dissipation device 150 to facilitate heat transfer therebetween. Theintegrated heat spreader 220 may include at least onefooting 242 extending between the integrated heat spreadersecond surface 224 and themicroelectronic substrate 202, wherein the integratedheat spreader footing 242 may be attached to the microelectronic substratefirst surface 204 with anadhesive material 252, such as an epoxy material. Theintegrated heat spreader 220 may be made of any appropriate thermally conductive material, such a metals and alloys, including, but not limited to, copper, aluminum, and the like. It is understood that theintegrated heat spreader 220 may be utilized as a load mechanism. -
FIG. 11 is a flow chart of aprocess 300 of fabricating a microelectronic structure according to the various embodiments of the present description. As set forth inblock 310, a microelectronic die may be formed having an active surface and an opposing back surface. At least one trench may be formed extending into the microelectronic die from the microelectronic die back surface, as set forth inblock 320. As set forth inblock 330, the at least one trench may be filled with at least one layer of thermally conductive material. -
FIG. 12 illustrates an embodiment of an electronic system/device 400, such as a portable computer, a desktop computer, a mobile telephone, a digital camera, a digital music player, a web tablet/pad device, a personal digital assistant, a pager, an instant messaging device, or other devices. The electronic system/device 400 may be adapted to transmit and/or receive information wirelessly, such as through a wireless local area network (DYLAN) system, a wireless personal area network (WAN) system, and/or a cellular network. The electronic system/device 400 may include a microelectronic motherboard orsubstrate 410 disposed within adevice housing 420. The microelectronic motherboard/substrate 410 may have various electronic components electrically coupled thereto, including a microelectronic device including a microelectronic die and a heat dissipation device disposed therein, as described in the present description (seeFIGS. 1-10 ), and optionally the integrated heat spreader ofFIG. 11 , all of which are shown generically aselement 430. Themicroelectronic motherboard 410 may be attached to various peripheral devices including aninput device 450, such as keypad, and adisplay device 460, such an LCD display. It is understood that thedisplay device 460 may also function as the input device, if thedisplay device 460 is touch sensitive. - The following examples pertain to further embodiments, wherein Example 1 is a microelectronic device, comprising a microelectronic die having an active surface and an opposing back surface; and at least one heat dissipation device extending into the microelectronic die from the microelectronic die back surface.
- In Example 2, the subject matter of Example 1 can optionally include the heat dissipation device comprising at least one layer of thermally conductive material within the at least one trench extending into the microelectronic die.
- In Example 3, the subject matter of Example 2 can optionally include the at least one layer of thermally conductive material within the at least one trench comprises a first thermally conductive material layer abutting a second thermally conductive material layer.
- In Example 4, the subject matter of Example 3 can optionally include the first thermally conductive material layer in electrical contact with a first terminal of a current generating electrical device and the second thermally conductive material layer in electrical contact with a second terminal of the current generating electronic device.
- In Example 5, the subject matter of any of Examples 1 to 4 can optionally include the at least one heat dissipation device positioned proximate a hot spot location in the microelectronic die.
- In Example 6, the subject matter of any of Examples 1 to 4 can optionally include the at least one heat dissipation device comprising a thermally conductive material selected from a group consisting of copper and silver.
- In Example 7, the subject matter of any of Examples 1 to 4 can optionally include the microelectronic die active surface electrically connected to a microelectronic substrate.
- In Example 8, the subject matter of any of Examples 1 to 4 can optionally include an integrated heat spreader in thermal contact with the at least one heat dissipation device.
- In Example 9, the subject matter of any of Examples 1 to 4 can optionally include at least one of a seed layer and a barrier layer disposed between the microelectronic die and the at least one heat dissipation device.
- The following examples pertain to further embodiments, wherein Example 10 is a method of fabricating a heat dissipation device within a microelectronic die, comprising forming a microelectronic die having an active surface and an opposing back surface; forming at least one trench extending into the microelectronic die from the microelectronic die back surface; and disposing at least one layer of thermally conductive material within the at least one trench.
- In Example 11, the subject matter of Example 10 can optionally include the step of disposing at least one layer of thermally conductive material within the at least one trench comprising disposing a first thermally conductive material layer within the at least one trench and disposing a second thermally conductive material layer abutting the first thermally conductive material layer within the at least one trench.
- In Example 12, the subject matter of Example 11 can optionally include the electrically contacting the first thermally conductive material layer with a first terminal of a current generating electrical device and electrically contacting the second thermally conductive material layer with a second terminal of the current generating electronic device.
- In Example 13, the subject matter of Example 10 can optionally include forming at the least one trench extending into the microelectronic die from the microelectronic die back surface by a technique selected from the group consisting of etching, ion bombardment, and laser ablation.
- In Example 14, the subject matter of any of Examples 10 to 13 can optionally include forming at least one of a seed layer and a barrier layer disposed between the at least one trench and the at least one thermally conductive material layer.
- In Example 15, the subject matter of any of Examples 10 to 13 can optionally include the step of disposing at least one layer of thermally conductive material within the at least one trench comprising patterning a mask with at least one opening corresponding to the at least one trench; and plating the thermally conductive material within the at least one trench.
- In Example 16, the subject matter of Example 15 can optionally include removing the mask.
- In Example 17, the subject matter of any of Examples 10 to 13 can optionally include connecting the microelectronic die active surface to a microelectronic substrate.
- In Example 18, the subject matter of any of Examples 10 to 13 can optionally include thermally contacting an integrated heat spreader with the heat dissipation device.
- In Example 19, the subject matter of any of Examples 10 to 13 can optionally include disposing at least one layer of thermally conductive material selected from a group consisting of copper and silver.
- In Example 20, the subject matter of any of Examples 10 to 13 can optionally include forming the at least one heat dissipation device proximate a hot spot location in the microelectronic die.
- The following examples pertain to further embodiments, wherein Example 21 is an electronic system, comprising a housing; a microelectronic substrate disposed within the housing; and a microelectronic device comprising: a microelectronic die having an active surface and an opposing back surface electrically attached to the microelectronic surface by the microelectronic die first surface; and a heat dissipation device extending into the microelectronic die from the microelectronic die back surface.
- In Example 22, the subject matter of Example 21 can optionally include the heat dissipation device comprising at least one layer of thermally conductive material within the at least one trench extending into the microelectronic die.
- In Example 23, the subject matter of Example 22 can optionally include the at least one layer of thermally conductive material within the at least one trench comprising a first thermally conductive material layer abutting a second thermally conductive material layer.
- In Example 24, the subject matter Examples 23 can optionally include the first thermally conductive material layer in electrical contact with a first terminal of a current generating electrical device and the second thermally conductive material layer in electrical contact with a second terminal of the current generating electronic device.
- In Example 25, the subject matter of any of Examples 21 to 24 can optionally include the at least one heat dissipation device positioned proximate a hot spot location in the microelectronic die.
- In Example 26, the subject matter of any of Examples 21 to 24 can optionally include the at least one heat dissipation device comprising a thermally conductive material selected from a group consisting of copper and silver.
- In Example 27, the subject matter of any of Examples 21 to 24 can optionally include an integrated heat spreader in thermal contact with the at least one heat dissipation device.
- In Example 28, the subject matter of any of Examples 21 to 24 can optionally include at least one of a seed layer and a barrier layer disposed between the microelectronic die and the at least one heat dissipation device.
- It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in
FIGS. 1-12 . The subject matter may be applied to other microelectronic device applications, as well as applications outside of the microelectronic industry, as will be understood to those skilled in the art. - Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
Claims (28)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/904,169 US8907461B1 (en) | 2013-05-29 | 2013-05-29 | Heat dissipation device embedded within a microelectronic die |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/904,169 US8907461B1 (en) | 2013-05-29 | 2013-05-29 | Heat dissipation device embedded within a microelectronic die |
Publications (2)
Publication Number | Publication Date |
---|---|
US20140353817A1 true US20140353817A1 (en) | 2014-12-04 |
US8907461B1 US8907461B1 (en) | 2014-12-09 |
Family
ID=51984217
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/904,169 Active US8907461B1 (en) | 2013-05-29 | 2013-05-29 | Heat dissipation device embedded within a microelectronic die |
Country Status (1)
Country | Link |
---|---|
US (1) | US8907461B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108269772A (en) * | 2017-01-03 | 2018-07-10 | 意法半导体(格勒诺布尔2)公司 | Include the electronic device for chip of slotting |
US11289395B2 (en) * | 2019-04-18 | 2022-03-29 | Western Digital Technologies, Inc. | Aperture structure on semiconductor component backside to alleviate delamination in stacked packaging |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7527090B2 (en) * | 2003-06-30 | 2009-05-05 | Intel Corporation | Heat dissipating device with preselected designed interface for thermal interface materials |
US7029951B2 (en) * | 2003-09-12 | 2006-04-18 | International Business Machines Corporation | Cooling system for a semiconductor device and method of fabricating same |
US7122891B2 (en) * | 2003-12-23 | 2006-10-17 | Intel Corporation | Ceramic embedded wireless antenna |
US7286359B2 (en) * | 2004-05-11 | 2007-10-23 | The U.S. Government As Represented By The National Security Agency | Use of thermally conductive vias to extract heat from microelectronic chips and method of manufacturing |
US20050257821A1 (en) * | 2004-05-19 | 2005-11-24 | Shriram Ramanathan | Thermoelectric nano-wire devices |
US7523098B2 (en) * | 2004-09-15 | 2009-04-21 | International Business Machines Corporation | Systems and methods for efficient data searching, storage and reduction |
US8259451B2 (en) * | 2008-11-25 | 2012-09-04 | Intel Corporation | Metal injection molded heat dissipation device |
US8552554B2 (en) * | 2010-08-12 | 2013-10-08 | Industrial Technology Research Institute | Heat dissipation structure for electronic device and fabrication method thereof |
US8772817B2 (en) * | 2010-12-22 | 2014-07-08 | Cree, Inc. | Electronic device submounts including substrates with thermally conductive vias |
-
2013
- 2013-05-29 US US13/904,169 patent/US8907461B1/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108269772A (en) * | 2017-01-03 | 2018-07-10 | 意法半导体(格勒诺布尔2)公司 | Include the electronic device for chip of slotting |
US11289395B2 (en) * | 2019-04-18 | 2022-03-29 | Western Digital Technologies, Inc. | Aperture structure on semiconductor component backside to alleviate delamination in stacked packaging |
Also Published As
Publication number | Publication date |
---|---|
US8907461B1 (en) | 2014-12-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10616992B2 (en) | Circuit board and method for manufacturing the same | |
US9837383B2 (en) | Interconnect structure with improved conductive properties and associated systems and methods | |
KR100865595B1 (en) | Thermoelectric nano-wire devices | |
TWI528504B (en) | Wafer level stack die package | |
US9685421B2 (en) | Methods for high precision microelectronic die integration | |
US11756856B2 (en) | Package architecture including thermoelectric cooler structures | |
KR20160021752A (en) | Integrated thermoelectric cooling | |
US20220240370A1 (en) | Package substrate inductor having thermal interconnect structures | |
US9099427B2 (en) | Thermal energy dissipation using backside thermoelectric devices | |
CN103187372A (en) | Chip packaging structure | |
US9847272B2 (en) | Three-dimensional integrated circuit structures providing thermoelectric cooling and methods for cooling such integrated circuit structures | |
TWI306381B (en) | Printed circuit board with improved thermal dissipating structure and electronic device with the same | |
CN114730746A (en) | Thermally conductive pillar/active die for improved cooling of stacked bottom die | |
US8907461B1 (en) | Heat dissipation device embedded within a microelectronic die | |
US20200312741A1 (en) | Thermoelectric cooler to enhance thermal-mechanical package performance | |
US20190206836A1 (en) | Stacked semiconductor architecture including semiconductor dies and thermal spreaders on a base die | |
US10644140B2 (en) | Integrated circuit die having back-end-of-line transistors | |
US20180226322A1 (en) | Thermoelectric bonding for integrated circuits | |
US11664293B2 (en) | Solid state thermoelectric cooler in silicon backend layers for fast cooling in turbo scenarios | |
US11462457B2 (en) | Using a thermoelectric cooler to reduce heat transfer between heat-conducting plates | |
Chau et al. | Feasibility study of using solid state refrigeration technologies for electronic cooling | |
TWI360241B (en) | Chip with thermoelectric function | |
US20220208628A1 (en) | Chip packaging structure | |
WO2017116527A2 (en) | Thermoelectric cooler having a solderless electrode | |
TW201731056A (en) | Dielectric buffer layer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: INTEL CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KONCHADY, MANOHAR S.;ROY, MIHIR K.;REEL/FRAME:033014/0920 Effective date: 20130528 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |