TW201731056A - Dielectric buffer layer - Google Patents

Abstract

Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the passivation layer, a patternable dielectric material layer; processing the patternable dielectric material layer to expose a portion of the passivation layer covering the RDL; processing the portion of the passivation layer covering the RDL to expose a portion of the RDL; and forming, on the exposed portion of the RDL, an LMI landing pad. The resulting wafer can include a redistribution line having a top portion and a sidewall portion; a passivation layer covering the sidewall portion; a dielectric layer covering the passivation layer; and a metal interface covering the top portion of the redistribution line.

Description

Dielectric buffer layer

Embodiments disclosed herein relate to semiconductor processing, and more particularly to the use of a spin-on dielectric to increase the buffer layer as a logical memory interface to protect from plating through the passivation layer seam.

After the redistribution layer (RDL) plating process, a passivation layer is deposited on the logic memory interface (LMI) layer as a dielectric to prevent RDL line-to-line leakage and short circuits. Due to the high topography of the RDL line, such a passivation layer has seams that open during LMI plating and cause plating in the joints, resulting in a line to line short circuit. Again, the fragile zone in the seam after the manufacturing process causes copper extrusion in the seam during thermal cycling and will result in early failure of the device. 1 is a schematic diagram of a germanium wafer including a metal plated from a passivation layer joint.

According to an embodiment of the present invention, a device is specifically provided, comprising: a substrate; a redistribution line having a top portion and a side wall portion; a passivation layer at least partially covering the side wall portion; at least partially covering the a dielectric layer of the passivation layer; and a metal interface covering the top of the redistribution line and in electrical contact with the redistribution line.

200, 240, 250, 260, 270, 280, 290 ‧ ‧ 矽 wafer

202‧‧‧ base

204, 604‧‧‧metal wire

206, 606, 658‧‧ ‧ passivation layer

208, 608‧‧‧ seams

209‧‧‧ top

210‧‧‧ trench

211‧‧‧ side wall

212‧‧‧patternable dielectric materials

214‧‧‧LMI opening

216‧‧‧cured patterned dielectric materials

218‧‧‧ openings in the passivation layer

300‧‧‧ Method flow chart

302-316‧‧‧ square

400‧‧‧Intermediary

402‧‧‧First substrate

404‧‧‧Second substrate

406‧‧‧ Ball Grid Array (BGA)

408‧‧‧Metal interconnects

410‧‧‧through hole

412‧‧‧through through hole (TSV)

414‧‧‧ embedded devices

500‧‧‧ computing device

501‧‧‧ front side

502‧‧‧Integrated circuit die

503, 552‧‧‧ Redistribution Layer (RDL)

504‧‧‧CPU

506‧‧‧ on-die memory

508‧‧‧Communication logic unit

510‧‧‧Electrical memory

512‧‧‧ Non-electrical memory

514‧‧‧Graphical Processing Unit (GPU)

516‧‧‧Digital Signal Processor (DSP)

520‧‧‧ chipsets

522‧‧‧Antenna

524‧‧‧Display or touch screen display

526‧‧‧Touch Screen Controller

528‧‧‧Global Positioning System (GPS) devices

530‧‧‧Battery

532‧‧‧Sports coprocessor or sensor

534‧‧‧Speakers

536‧‧‧Video Recorder

538‧‧‧User input device

540‧‧‧ Mass storage device

550, 601‧‧‧ back side

600‧‧‧ Schematic

602‧‧‧矽 device wafer

603‧‧‧ device side

616‧‧‧patternable dielectric material layer

620‧‧‧Logical/Memory Interface (LMI) Landing Pad

652‧‧‧ Temporary 矽 carrier wafer

656‧‧‧ Front-end and back-end layers (FE/BE layer)

662‧‧‧Bumps, through-holes (TSV)

1 is a schematic diagram of a germanium wafer including a metal plated from a passivation layer joint.

2A is a cross-sectional view of a germanium wafer including a redistribution layer and a passivation layer in accordance with embodiments disclosed herein.

2B is a cross-sectional view of a germanium wafer with a patternable dielectric material in accordance with an embodiment disclosed herein.

2C is a cross-sectional view of a wafer with a patterned dielectric material that has been processed in accordance with embodiments disclosed herein.

2D is a cross-sectional view of a wafer with a cured and patternable dielectric material in accordance with an embodiment disclosed herein.

2E is a cross-sectional view of a wafer with a treated passivation layer and an exposed redistribution layer in accordance with an embodiment disclosed herein.

2F is a cross-sectional view of a wafer that has been cleaned in accordance with embodiments disclosed herein.

2G is a cross-sectional view of a germanium wafer with a patternable dielectric material in accordance with an embodiment disclosed herein.

3 is a flow diagram of a method of forming a passivation layer seam barrier layer on a germanium wafer using a patternable dielectric material in accordance with embodiments disclosed herein.

4 is a schematic block diagram of an interposer embodying embodiments disclosed herein.

Figure 5 is a calculation established in accordance with an embodiment disclosed herein A schematic block diagram of the device.

Figure 6 is a schematic illustration of the back side of a germanium wafer attached to a germanium carrier wafer.

Described herein is the formation of a protective layer over the passivation layer to protect against seam attack and precipitation during electroless deposition of, for example, a logic/memory interface landing pad.

Disclosed herein is the fabrication of a patternable buffer layer after deposition of an LMI passivation layer. The patternable buffer layer will prevent the LMI plating solution from contacting the LMI passivation layer seam and thus protecting the seam from attack by the LMI plating chemical solution.

2A is a cross-sectional view of a germanium wafer 200 including a redistribution layer and a passivation layer in accordance with embodiments disclosed herein. In some embodiments, Figures 2A-2G illustrate the front side of the germanium wafer; in several embodiments, Figures 2A-2G illustrate the back side of the germanium wafer. The back side of the wafer is described in further detail in Figure 6. The germanium wafer 200 includes a substrate 202. The substrate can be tantalum, niobium oxide, or other materials. The germanium wafer 200 shows that a metal plating process has been performed to form the separate metal lines 204. For example, the split metal line can be a metal line used in a redistribution layer (RDL). The split metal wire can include a top 209 and a side wall 211 (or two side walls 211). Adjacent separate metal lines 204 are separated by gaps that define trenches 210. Prior to forming the passivation layer 206, the substrate 202 separating the metal lines 204 is exposed at the bottom of the trenches 210. In several embodiments, the separate metal lines are formed using a metal plating process. The separate wires may include copper, aluminum, or other conductive metals.

The germanium wafer 200 also includes a passivation layer 206 that covers the top 209, sidewalls 211, and the exposed substrate 202 inside the trenches 210. The passivation layer 206 may include tantalum nitride, tantalum carbide, tantalum carbonitride, hafnium oxynitride, and niobium doped lanthanum oxynitride. The passivation layer 206 can act to protect copper or other metals from spreading across the trench 210 that would cause leakage or shorting of the lines in the RDL.

Passivation layer 206 can be generated in a known manner. Often, seam 208 will be formed between the surfaces of the passivation layer due to the relatively high topography of the separate metal lines 204. The seam 208 is susceptible to the short circuit of the RDL across the wire 204 by exposing the separate metal wires to the electroless deposition of metal introduced to create a logic/memory interface (LMI) landing pad.

To address the short circuit problem caused by the fragile seam of the seam, the patterned dielectric material 212 can be directed to the trench, which prevents the electroless plating bath solution from attacking the seam and plating through the seam. 2B is a cross-sectional view of a germanium wafer 240 with a patternable dielectric material in accordance with an embodiment disclosed herein. The patternable dielectric material 212 can be a photodefinable, photoimageable, or photopatternable dielectric material or other dielectric that can be patterned using photolithographic techniques or other known techniques. In some embodiments, the patternable dielectric material 212 can be a positive photoimageable dielectric material. In some embodiments, the patternable dielectric material can be a spin exposure development (SED) patternable material. In some embodiments, the patternable dielectric material 212 can be processed to form a permanent film (eg, the patternable dielectric material 212 can be cured to form a permanent film).

Examples of electrically photodefinable dielectric materials include, but are not limited to: available from Dow (Dow Chemical) is InterVideo ^{TM (InterVia TM)} 8000 series photodefinable dielectric material; available from Dow mosaic Borodin ^TM (Clyclotene ^TM ) 4000 series photo-definable dielectric materials; SU-8 photo-definable epoxy materials from Microchem; WL-5000 series photo-definable dielectric materials from Dow Chemical Avatrel® from Promerus is a light-definable dielectric material; SINR series light-definable dielectric materials from ShinEtsuMicroSi; from Sumitomo Berkeley SUMITESIN EXCEL® CRC-8600 series of light-definable dielectric materials (Sumitomo Bakelite Co, Ltd.); photodefinable polyimine and PBO materials from Fujifilm; from Toray Nice light ^TM (Photoneece ^TM) series photodefinable polyimide materials; available from Asahi Kasei Electronics materials (Asahi Kasei E-materials Corp.) Pim ^{TM (Pimel TM)} photodefinable polyimide materials and PBO Light-definable polyimine materials from HD Microsystems; available from JS R Micro Corporation (. JSR Micro, Inc) is WPR series photodefinable dielectric materials; and available from DuPont (Dupont) a series of optical PerMX ^TM 3000 dielectric dry film adhesive.

The patternable dielectric material 212 can be directed to the tantalum wafer 240 by spin coating, dry film lamination, extrusion coating, or by other known techniques. A patterned dielectric material 212 over the passivation layer 206 is included in the passivation layer 206 in the trench 210 to form a patternable dielectric material. More specifically, the patternable dielectric material 212 covers the seams 208 and other locations 208 formed by the passivation layers in the trenches. Patternable dielectric material 212 can resist non-electricity The degradation of the chemical in the deplating solution serves to protect the passivation layer seam 208 from the electroless plating solution.

The patternable dielectric material can include one or more of the following characteristics: the patternable dielectric material is compatible with the plating solution, and the plating is allowed without affecting the composition of the coating.

The patterned dielectric material prevents the LMI plating solution from contacting the LMI passivation layer seam, and the seam is protected from attack by the LMI plating chemical solution.

The applied patternable dielectric material can be patterned and compatible with existing tool sets.

The curing process is used for the patternable dielectric material, which is performed at the low temperatures required for the through-pass via process steps.

The patternable dielectric material does not react with the plating solution and does not alter the plating chemistry or composition of the coating.

The patternable dielectric material has low stress that prevents excessive bending of the wafer during processing and prevents additional stress on the wafer at the end of the line.

The patternable dielectric material has good dielectric properties and acts as a dielectric barrier to prevent line-to-line shorts.

The patternable dielectric material can survive the downstream assembly process.

2C is a cross-sectional view of a wafer 250 with a processed patternable dielectric material in accordance with an embodiment disclosed herein. to In FIG. 2C, the patternable dielectric material 212 can be processed to form a pattern on the passivation layer 206. For a patterned dielectric material 212 comprising a positive photoimageable or photopatternable dielectric material, as is well known in the art, a mask can be used on top of the separate metal line 204 and on top of the passivation layer 206, but not The regions above the trench 201 where the LMI opening 214 is desired are exposed to UV light; and the patternable dielectric material of the positive photoimageable or photopatternable dielectric material in the exposed regions is developed It is removed during the process. The exposed portion of such a passivation layer 206 is shown in Figure 2C as an LMI opening 214 that is created during patterning of the patternable dielectric. It is noted that after the patternable dielectric material is developed, the patternable dielectric material 212 still covers the seam 208.

2D is a cross-sectional view of a wafer 260 with a cured and patternable dielectric material in accordance with an embodiment disclosed herein. In some embodiments, the germanium wafer 260 can be cured to cure the patterned dielectric material 212 to form a permanent film (shown as cured patterned dielectric material 216 in FIG. 2D). The cured patternable dielectric material 216 can withstand the etching technique used to remove the passivation layer 206 such that the seam 208 is still covered by the cured patternable dielectric material 216. The temperature and time of curing depend on the type of patterned dielectric material used.

2E is a cross-sectional view of a wafer 270 with a treated passivation layer and an exposed redistribution layer in accordance with an embodiment disclosed herein. The separate metal lines 204 that make up the RDL are exposed such that metal can be deposited onto the separate metal lines 204 to form electrical contacts (i.e., LMI landing pads). Developing the exposed passivation layer 206 from the patternable dielectric material 212 can Etching is performed using known techniques, such as dry or wet etching techniques. The result of the etch is an opening 218 in the passivation layer that exposes the separate metal lines 204 (eg, separating the tops of the metal lines) without exposing the trenches 210, or more specifically, the seams 208.

2F is a cross-sectional view of a wafer 280 that has been subjected to a passivation layer post-etch cleanup process in accordance with embodiments disclosed herein. The etched polymer or other contaminants are removed from the wafer surface during the cleaning process.

2G is a cross-sectional view of a germanium wafer 290 with a patternable dielectric material in accordance with an embodiment disclosed herein. A logic/memory interface (LMI) landing pad can be deposited onto the exposed separate metal line 204 by electroless plating (electroless plating). In Figure 2G, the landing pad is shown as an electroless plated surface finish 220. The electroless plated surface finish 220 includes a metal that is in electrical contact with the exposed separate wire 204 after deposition. Suitable electroless plating surface finishing includes, but is not limited to, electroless CoP/immersion Au, electroless CoWP/immersion Au, electroless NiP/immersion Au, electroless NiP/electrolytic Pd/immersion Au, electroless Sn , electroless NiP / electroless Sn, electroless CoP / immersion Au, electroless CoWP / non-electrolytic Sn, electroless Cu / electroless CoP / immersion Au, non-electrolytic Cu / electroless CoWP / immersion Au, non-electrolytic Cu / Non-electrolytic NiP/immersion Au, electroless Cu/electroless NiP/electrolytic Pd/immersion Au, electroless Cu/electrolytic Sn, electroless Cu/electroless NiP/electrolytic Sn, electroless Cu/electrolytic CoP/ Immersion of Au, electroless Cu/electrolytic CoWP/non-electrolytic Sn. Other surface finishing may also be desirable depending on the wafer-to-wafer solder material and/or wafer-to-wafer attach method employed. The passivation layer 206 and the cured patternable dielectric material 216 prevent the electroless plating solution from contacting the separate metal inside the trench 210 Line 204 (i.e., by plating through seam 208). As such, the cured patternable dielectric material isolates the electroless metal deposition to the top exposed portions of the respective separate metal lines 204. In other words, each of the separate metal lines 204 includes an LMI landing pad and is electrically insulated from the other separate metal lines 204.

In an alternate embodiment, a C4 or flip chip bump is fabricated on top of the landing pad opening rather than surface finishing. The C4 or flip chip bumps are fabricated using techniques known in the art and may include materials such as PbSn, Sn, SnAg, Cu, In, SnAgCu, SnCu, Au, and the like.

3 is a flow diagram 300 of a method of forming a passivation layer seam barrier layer on a germanium wafer using a patternable dielectric material in accordance with embodiments disclosed herein. In some embodiments, a passivation layer seam barrier layer can be formed on the front side of the crucible; and in several embodiments, a passivation layer seam barrier layer can be formed on the dorsal aspect. On the wafer, a redistribution layer (302) can be formed. The redistribution layer can include a plurality of separate (e.g., insulated from each other) metal lines formed by plating, such as electrolytic or electroless deposition or other known techniques. The separate metal wires can be copper, aluminum, or other metals.

A passivation layer can be formed over the RDL (304). The passivation layer can cover the sidewalls and the exposed germanium substrate on top of each of the separate metal lines and between the metal lines. The passivation layer may form a seam at the joint or form a seam from a deposition process (eg, a chemical vapor deposition technique) where the passivation layers meet each other. For example, a seam is formed in the groove between the separate wires. The resulting seam is vulnerable to chemical attack in the electroless deposition process used to form the logic/memory interface landing pad. The result of such an attack may result in the electroless deposition solution contacting the metal separating the wires and causing the electroless plating through the seam. The joints in the metal trenches are plated to cause short circuits between adjacent separate metal lines.

A layer of patterned dielectric material can be formed over the passivation layer (306). In particular, a layer of patterned dielectric material can be formed to cover the passivation layer including the seam. The patterned dielectric material layer can be formed by spin coating, dry film lamination, extrusion coating, or by other known techniques. The patternable dielectric material layer can include a patternable dielectric material, such as a positive photoimageable or photopatternable dielectric material, or a rotational exposure development (SED) patternable dielectric.

The patternable dielectric material can be treated to expose the top of the passivation layer (308). The patternable dielectric material can be processed by photolithography to remove portions of the patternable dielectric material overlying the passivation layer (eg, separating the passivation layer on top of the metal lines). The processing of the patternable dielectric should not remove the patternable dielectric material that covers the seam of the passivation layer. As part of the processing of the patternable dielectric material, the patternable dielectric material can be cured (310). Curing the patternable dielectric material can form a permanent film that can withstand etching of the passivation layer, cleaning of the substrate and other layers, and electroless plating of the LMI landing pad.

A passivation layer covering the separate metal lines can be treated to expose portions of the separate metal lines (312). The passivation layer can be etched, such as by dry etching, wet etching, or by other known techniques. The etching process should not affect the patternable dielectric material.

The cleaning process can be used to remove etched polymer or other contaminants, or otherwise prepare the exposed metal surface for subsequent processing.

LMI landing pads can be formed on exposed separate wires Upper (316). LMI landing pads can be formed using electroless deposition. Electroless deposition can deposit metal to metal lines, such as the aforementioned metals. The non-electrolytic deposition chemistry is prevented from attacking the seam because the seam is covered by the cured patternable dielectric material. Non-electrolytic deposition of chemicals by preventing non-electrolytic deposition chemicals from attacking the seam.

In the description herein, various embodiments of the specific embodiments are intended to convey the substance of their work to those skilled in the art. However, it will be apparent to those skilled in the art that the disclosure herein may be practiced only in the part of the description. The specific number, materials, and configurations are set forth to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that the disclosure herein can be practiced without the specific details. In other instances, well-known features are deleted or simplified to avoid obscuring the embodiments.

In turn, the description of the operations in a manner that is most helpful in understanding the teachings herein is a plurality of separate operations, however, the described ordering should not be interpreted as implying that such operations are necessarily sequential dependencies. In particular, such operations need not be performed in the order presented.

As used herein, the terms "above", "below", "between", and "on", mean the relative position of a layer or layer of material relative to other layers or components. For example, a layer disposed above or below another layer may directly contact another layer, or may have one or more interposers. Furthermore, a layer disposed between the two layers may directly contact the two layers, or may have one or more interposers. Conversely, the first layer is in direct contact with the second layer on the "upper" layer of the second layer. Similarly, unless you understand Chen In addition, a feature disposed between two features may directly contact the adjacent features, or may have one or more interposers.

Embodiments disclosed herein can be formed or performed on a substrate such as a semiconductor substrate. In one embodiment, the semiconductor substrate can be a crystalline substrate formed using a bulk germanium or insulator-on-raft structure. In other embodiments, the semiconductor substrate may be fabricated using other materials that may or may not be combined, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, arsenic. Indium gallium, gallium antimonide, or other combinations of III-V or Group IV materials. Although a number of material examples from which a substrate can be formed are described herein, any material on which the semiconductor device can be built as a basis is within the spirit and scope of the disclosure herein.

A plurality of transistors such as a gold oxide half field effect transistor (MOSFET or MOS transistor for short) may be fabricated on the substrate. In various embodiments disclosed herein, the MOS transistor can be a planar transistor, a non-planar transistor, or a combination of both. Non-planar transistors include fin-type FinFET transistors such as double-gate transistors and triple-gate transistors, and wrapped or fully encapsulated gate transistors such as nanowires or nanowire transistors. While the embodiments described herein may exemplify only planar transistors, it is noted that the disclosure herein may also be performed using non-planar transistors.

Each of the MOS transistors includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer can include a layer or a stack. One or more layers may include yttrium oxide, cerium oxide (SiO ₂ ), and/or a high-k dielectric material. The high-k dielectric material may include elements such as lanthanum, cerium, oxygen, titanium, lanthanum, cerium, aluminum, zirconium, hafnium, tantalum, niobium, lead, lanthanum, cerium, and zinc. Examples of high-k materials that can be used for the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium oxide, hafnium oxide, hafnium oxide, zirconium oxide, zirconium oxide hafnium oxide, hafnium oxide, titanium oxide, hafnium oxide. Titanium, titanium cerium oxide, titanium cerium oxide, cerium oxide, aluminum oxide, lead lanthanum oxide, and lead zinc citrate. In several embodiments, when a high-k material is used, an annealing process can be performed on the gate dielectric layer to improve its quality.

The gate electrode layer is formed on the gate dielectric layer and may be composed of at least one P-type work function metal or N-type work function metal depending on whether the transistor is a PMOS or NMOS transistor. In some embodiments, the gate electrode layer can be composed of a stacked two or more metal layers where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers, such as barrier layers, for other purposes may be included.

As for the PMOS transistor, the metal that can be used for the gate electrode includes, but is not limited to, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide such as ruthenium oxide. The P-type metal layer will enable it to form a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. As for the NMOS transistor, metals which can be used for the gate electrode include, but are not limited to, yttrium, zirconium, titanium, hafnium, aluminum, alloys of such metals, and carbides of such metals such as tantalum carbide, zirconium carbide, titanium carbide , strontium carbide, aluminum carbide. The N-type metal layer will enable it to form an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV.

In some embodiments, when viewed in the source-channel-dip diode direction as a cross-section of the transistor, the gate electrode may comprise a U-shaped structure comprising a bottom substantially parallel to the surface of the substrate and a substantially vertical substrate Two side wall portions of the top surface. In another embodiment, at least one of the metal layers forming the gate electrode can be simply a planar layer that is substantially parallel to the top surface of the substrate and does not include a sidewall portion that is substantially perpendicular to the top surface of the substrate. In a further embodiment disclosed herein, the gate electrode can be comprised of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be formed by forming one or more U-shaped metal layers on top of one or more planar non- U-shaped layers.

In several embodiments disclosed herein, a pair of sidewall spacers can be formed on opposite sides of the gate stack to enclose the gate stack. The sidewall spacers may be made of materials such as tantalum nitride, tantalum oxide, tantalum carbide, tantalum carbonitride, and hafnium oxynitride. The method of forming the sidewall spacers is well known in the art and generally includes deposition and etching processing steps. In alternative embodiments, multiple pairs of spacers may be used, for example two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

As is well known in the industry, the source and drain regions are formed in a gate stack adjacent to each MOS transistor within the substrate. The source and germanium regions are typically fabricated using an implant/diffusion method or an etch/deposition method. In the former method, a dopant such as boron, aluminum, bismuth, phosphorus, or arsenic may be ion implanted into the matrix to form a source and a germanium region. The activation of the dopant and the annealing treatment that causes the dopant to further diffuse into the matrix typically follows the ion implantation process. In the latter process, the substrate may be etched to form a recess at the source and the land. Then, an epitaxial deposition process can be performed to fill the recesses with the materials used to fabricate the source and the germanium regions. In several embodiments, the source and germanium regions can be fabricated using a tantalum alloy such as tantalum or tantalum carbide. In several embodiments, the epitaxially deposited tantalum alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorous. In a further embodiment, the source and The germanium region can be made using one or more alternative semiconductor materials such as germanium or III-V metals or alloys. In further embodiments, one or more layers of metal and/or alloy may be used to form the source and the germanium regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistor. The ILD layer can be made using a dielectric material known to be applicable to integrated circuit structures, such as low-k dielectric materials. Examples of useful dielectric materials include, but are not limited to, cerium oxide (SiO ₂ ), carbon-doped oxide (CDO), tantalum nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorine. Tellurite glass (FSG), and organic phthalates such as sesquiterpene oxide, decane, or organosilicate glass. The ILD layer can include an orifice or an air gap to further reduce its dielectric constant.

4 is a schematic block diagram of an interposer 1000 in accordance with an embodiment disclosed herein. The interposer 400 is an intermediate substrate for bridging the first substrate 402 to the second substrate 404. The first substrate 402 can be, for example, an integrated circuit die. The second substrate 404 can be, for example, a memory module, a computer motherboard, or other integrated circuit die. In general, the purpose of the interposer 400 is to unfold a link to a wider pitch or to rearrange a link to a different link. For example, the interposer 400 can couple the integrated circuit die to a ball grid array (BGA) 406, which can then be coupled to the second substrate 404. In several embodiments, the first and second substrates 402/404 are attached to opposite sides of the interposer 400. In other embodiments, the first and second substrates 402/404 are attached to the same side of the interposer 400. In further embodiments, three or more base systems are interconnected by an interposer 400.

The intermediate member 400 can be reinforced by epoxy resin or glass fiber. Made of epoxy resin, ceramic material, or polymer material such as polyimide. In further embodiments, the interposer may be made of other rigid or flexible materials, which may include the same materials previously described for semiconductor substrates, such as tantalum, niobium, and other III-V and Group IV materials.

The interposer can include metal interconnects 408 and vias 410 including, but not limited to, through via vias (TSV) 412. The interposer 400 can further include an embedded device 414, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, antennas, arrays, sensors, and MEMS devices can also be formed on the interposer 400.

In accordance with embodiments disclosed herein, the apparatus or method described herein can be used in the fabrication of the interposer 400.

FIG. 5 is a computing device 500 in accordance with an embodiment disclosed herein. Computing device 500 can include a front side 501 and a back side 550. The computing device 500 has a plurality of components, some of which reside on the front side 501. In one embodiment, the components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single single wafer system (SoC) die. Components in computing device 500 include, but are not limited to, integrated circuit die 502 and at least one communication logic unit 508. In some embodiments, the communication logic unit 508 is fabricated within the integrated circuit die 502, while in other embodiments, the communication logic unit 508 is fabricated in a separate integrated circuit die that can be coupled to the product. Body circuit die 502 Shared or electronically coupled base or motherboard. The integrated circuit die 502 can include a CPU 504 and on-die memory 506, which are often used as cache memory, such as embedded DRAM (eDRAM) or rotary transfer moment memory (STTM or STT-MRAM). ) Technology provided.

Computing device 500 can include other components that may or may not be physically and electrically coupled to a motherboard or fabricated within a SoC die. Such other components include, but are not limited to, electrical memory 510 (eg, DRAM), non-electrical memory 512 (eg, ROM or flash memory), graphics processing unit 514 (GPU), digital a signal processor 516, a cryptographic processor 542 (a specialized processor that performs cryptographic algorithms within the hardware), a chipset 520, an antenna 522, a display or touch screen display 524, a touch screen controller 526, a battery 530, or Other power supplies, power amplifiers (not shown), voltage regulators (not shown), global positioning system (GPS) devices 528, motion co-processors or sensors 532 (which may include accelerometers, gyro Instrument, and compass), speaker 534, video recorder 536, user input device 538 (such as keyboard, mouse, stylus, trackpad), and mass storage device 540 (such as hard disk drive, CD ( CD), digital audio and video discs (DVD) and so on).

Communication logic unit 508 enables wireless communication for transferring data to and from computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that communicate data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, but may not be included in several embodiments. Communication logic unit 508 can implement numerous Any of the wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols labeled 3G, 4G, 5G, and thereafter. Computing device 500 can include a plurality of communication logic units 508. For example, the first communication logic unit 508 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication logic unit 508 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, And others.

Processor 504 of computing device 500 includes one or more devices, such as a transistor or metal interconnect, formed in accordance with embodiments disclosed herein. The term "processor" may refer to any device or portion of a device that processes electronic data from a register and/or memory to transform the electronic data into other electronic data that can be stored in a register and/or memory.

Communication logic unit 508 can also include one or more devices formed in accordance with embodiments disclosed herein, such as a transistor or a metal interconnect.

In a further embodiment, another component of the housing inside the housing of computing device 500 can contain one or more devices, such as a transistor or metal interconnect, formed in accordance with embodiments disclosed herein.

In various embodiments, computing device 500 can be a laptop, a small notebook, a notebook, a laptop, a smart phone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a table. Upper computer, server, printer, scanner, monitor, set-top box, Entertainment control unit, digital video recorder, portable music player, or digital video recorder. In a further embodiment, computing device 500 can be any other electronic device that processes data.

The back side 550 can include a redistribution layer (RDL) 552. One or more of the components referenced above may be interconnected using metal wires forming RDL 552. In accordance with embodiments disclosed herein, each metal line can be accessed through a via or logic/memory interface landing pad formed on the back side 550 of the computing device. For example, the back side 550 can include a redistribution layer metal line having a top portion and a sidewall portion; a passivation layer at least partially covering the sidewall portion; a dielectric layer at least partially covering the passivation layer; and covering the top of the redistribution line and Metal interface for electrical contact. In some embodiments, front side 501 can also include RDL 503 and passivation layer seam cushioning in accordance with embodiments disclosed herein.

6 is a schematic diagram 600 of the back side of a germanium device wafer attached to a germanium carrier wafer. Figure 6 shows similar components as shown in Figures 2A-2G. In accordance with embodiments disclosed herein, germanium device wafer 602 includes features having a back side 601, such as a separate metal line 604, a passivation layer 606 (which may be a tantalum nitride layer), and a seam 608 in the passivation layer 606. A patterned dielectric material layer 616, and a logic/memory interface (LMI) landing pad 620.

The device wafer 602 also includes a device side 603. Features on the back side 601 can be electrically linked to features on the device side by through through vias (TSV) 662. On the device side, the germanium device wafer 602 can include front and back end layers (FE/BE layers) 656, a hard passivation layer 658, and one or more bumps 662. Bump 662 is electrically coupled to device side 603 of device wafer 602 The back end metal wiring layer 656. After the back side 601 process is completed, the thinned germanium device wafer 602 is detached from the temporary germanium carrier wafer 652, and the thinned germanium device wafer 602 is diced into individual wafers. Bumps 662 on each individual wafer are then electrically bonded to the chip package, for example by soldering.

Diagram 600 shows how germanium wafer 602 can be carried on germanium carrier wafer 652. The device wafer 602 can be secured to the tantalum carrier wafer by a layer of glue or other adhesive 654.

The following paragraphs present examples of each of the embodiments described herein.

Example 1 is a device comprising a substrate; a redistribution line having a top portion and a sidewall portion; a passivation layer at least partially covering the sidewall portion; a dielectric layer at least partially covering the passivation layer; and covering The top of the redistribution line and a metal interface in electrical contact therewith.

Example 2 can include the subject matter of Example 1, wherein the passivation layer comprises one or a combination of tantalum nitride, tantalum carbide, niobium carbonitride, hafnium oxynitride, or tantalum oxynitride.

Example 3 can include the subject matter of Example 1, wherein the dielectric layer comprises a patternable dielectric material.

Example 4 can include the subject matter of any of Examples 1 or 2 or 3, wherein the dielectric layer comprises a rotational exposure developing dielectric.

Example 5 can include the subject matter of any of Examples 1 or 2 or 3 or 4, wherein the dielectric layer comprises a permanent film.

Example 6 can include the subject matter of any of Examples 1 or 2 or 3 or 4 or 5, wherein the metal interface comprises a logic/memory interface (LMI).

Example 7 can include the subject matter of any of Examples 1 or 2 or 3 or 4 or 5 or 6, wherein the redistribution line comprises copper or aluminum.

Example 8 can include the subject matter of any of Examples 1 or 2 or 3 or 4 or 5 or 6 or 7, wherein the redistribution line, the passivation layer, the dielectric layer, and the metal interface are in a twin On the back side of the circle.

Example 9 is a method for forming a logic/memory interface (LMI) landing pad on a back side of a germanium wafer, the method comprising forming a redistribution layer on a substrate; Forming a passivation layer overlying the substrate and the redistribution layer; forming a patterned dielectric material layer on the passivation layer; treating the patterned dielectric material layer to expose the redistribution layer a portion of the passivation layer; treating the portion of the passivation layer overlying the redistribution layer to expose a portion of the redistribution layer; and forming a portion in electrical contact with the redistribution layer on the exposed portion of the redistribution layer LMI landing pad.

Example 10 can include the subject matter of Example 9, wherein forming the layer of patterned dielectric material comprises spinning on the layer of patterned dielectric material.

Example 11 can include the subject matter of any of Examples 9 or 10, wherein the layer of patterned dielectric material comprises a positive photoimageable dielectric material.

Example 12 can include any of example 9 or 10 or 11. The subject matter wherein the layer of patterned dielectric material comprises a spin exposure development (SED) material.

Example 13 may include the subject matter of any of examples 9 or 10 or 11 or 12, wherein processing the layer of patterned dielectric material comprises masking a first portion of the layer of patterned dielectric material; A second portion of the dielectric is exposed to a light source to remove the second portion from the passivation layer to expose the portion of the passivation layer.

Example 14 can include the subject matter of any of Examples 9 or 10 or 11 or 12 or 13, wherein processing the layer of patterned dielectric material further comprises curing the layer of patterned dielectric material to form a permanent film.

Example 15 can include the subject matter of any of Examples 9 or 10 or 11 or 12 or 13 or 14, wherein the redistribution layer is formed to comprise electrolytic or electroless plating of copper.

Example 16 can include the subject matter of any of Examples 9 or 10 or 11 or 12 or 13 or 14 or 15, wherein forming the LMI landing pad comprises depositing the LMI landing pad by electroless deposition.

Example 17 can include the subject matter of any of Examples 9 or 10 or 11 or 12 or 13 or 14 or 15 or 16, wherein processing the portion of the passivation layer comprises etching the portion of the passivation layer.

Example 18 can include the subject matter of any of Examples 9 or 10 or 11 or 12 or 13 or 14 or 15 or 16 or 17, wherein forming the layer of patterned dielectric material on the passivation layer comprises covering a layer formed thereon One or more seams in the passivation layer; and wherein the portion of the passivation layer that covers the redistribution layer comprises maintaining a layer of the patterned dielectric material layer formed on the blunt One or more seams in the layer.

Example 19 is a computing device that includes a substrate including a device side and a back side. The device side may include a processor; a communication logic unit inside the processor; a memory inside the processor; a graphics processing unit inside the computing device; and an antenna inside the computing device; a power amplifier internal to the processor; and a voltage regulator internal to the processor. The back side may include a redistribution line having a top portion and a sidewall portion; a passivation layer at least partially covering the sidewall portion; a dielectric layer at least partially covering the passivation layer; and covering the redistribution line The top and a metal interface in electrical contact therewith.

Example 20 can include the subject matter of Example 19, wherein the passivation layer comprises tantalum nitride.

Example 21 can include the subject matter of any of examples 19 or 20, wherein the dielectric layer comprises a patternable dielectric material.

Example 22 can include the subject matter of any of Examples 19 or 20 or 21, wherein the dielectric layer comprises a permanent film.

Example 23 can include the subject matter of any of Examples 19 or 20 or 21 or 22, wherein the metal interface comprises a logic/memory interface (LMI).

Example 24 can include the subject matter of any of Examples 9 or 10 or 11 or 12 or 13 or 14 or 15 or 16 or 17 or 18, wherein the LMI landing pad is formed on a back side of a wafer.

The description of the illustrative embodiments disclosed herein, including those described in the Summary of the Invention, are not intended to be exhaustive or The text is revealed in the precise form disclosed. While the invention has been described with respect to the specific embodiments and examples thereof, it is intended to be

202‧‧‧ base

204‧‧‧Laminated metal wire

206‧‧‧ Passivation layer

208‧‧‧Seams existing after the formation of the passivation layer

216‧‧‧ hardened patterned dielectric materials

220‧‧‧Electroless plating surface finishing

290‧‧‧矽 wafer

Claims (23)

A device comprising: a substrate; a redistribution line having a top portion and a sidewall portion; a passivation layer at least partially covering the sidewall portion; a dielectric layer at least partially covering the passivation layer; and covering the Redistributing the top of the line and a metal interface in electrical contact with the redistribution line. The device of claim 1, wherein the passivation layer comprises one or a combination of tantalum nitride, tantalum carbide, niobium carbonitride, hafnium oxynitride, or tantalum oxynitride. The device of claim 1 wherein the dielectric layer comprises a patternable dielectric material. The device of claim 1, wherein the dielectric layer comprises a rotational exposure developing dielectric. The device of claim 1 wherein the dielectric layer comprises a permanent film. The device of claim 1, wherein the metal interface comprises a logic/memory interface (LMI). The device of claim 1, wherein the redistribution line comprises copper or aluminum. The device of claim 1, wherein the redistribution line, the passivation layer, the dielectric layer, and the metal interface are on a back side of the wafer. One for forming a logic on the back side of one of the wafers a method of landing/memory interface (LMI) landing pad, the method comprising: forming a redistribution layer on a substrate; forming a passivation layer covering the substrate and the redistribution layer on the redistribution layer and the substrate; Forming a layer of patterned dielectric material on the passivation layer; treating the layer of patterned dielectric material to expose a portion of the passivation layer overlying the redistribution layer; treating the passivation layer covering the redistribution layer Partially exposing a portion of the redistribution layer; and forming an LMI landing pad in electrical contact with the redistribution layer on the exposed portion of the redistribution layer. The method of claim 9, wherein forming the layer of patterned dielectric material comprises spinning on the layer of patterned dielectric material. The method of claim 9 or 10, wherein the layer of patterned dielectric material comprises a positive photoimageable dielectric material. The method of claim 9, wherein the layer of patterned dielectric material comprises a spin exposure development (SED) material. The method of claim 9, wherein processing the layer of patterned dielectric material comprises: masking a first portion of the layer of patterned dielectric material; exposing a second portion of the patterned dielectric to a light source The second portion is removed from the passivation layer to expose the portion of the passivation layer. The method of claim 9, wherein processing the layer of patterned dielectric material further comprises curing the layer of patterned dielectric material to form A permanent film. The method of claim 9, wherein the redistribution layer is formed to comprise electrolytic or electroless plating of copper. The method of claim 9, wherein forming the LMI landing pad comprises depositing the LMI landing pad by electroless deposition. The method of claim 9, wherein processing the portion of the passivation layer comprises etching the portion of the passivation layer. The method of claim 9, wherein forming the layer of patterned dielectric material on the passivation layer comprises covering one or more seams formed in the passivation layer; and wherein the passivation layer covering the redistribution layer is processed The portion includes maintaining one or more seams formed in the passivation layer by the layer of the patternable dielectric material. A computing device comprising: a substrate comprising a device side and a back side; the device side comprising: a processor; a communication logic unit in the processor; a memory in the processor; a graphics processing unit in the computing device; an antenna in the computing device; a power amplifier in the processor; and a voltage regulator in the processor; the back side includes: a redistribution line having a top portion and a sidewall portion; a passivation layer at least partially covering the sidewall portion; a dielectric layer at least partially covering the passivation layer; and the top portion covering the redistribution line and A redistribution line is used as a metal interface for electrical contact. The device of claim 19, wherein the passivation layer comprises tantalum nitride. The device of claim 19, wherein the dielectric layer comprises a patternable dielectric material. The device of claim 19, wherein the dielectric layer comprises a permanent film. The device of claim 19, wherein the metal interface comprises a logic/memory interface (LMI).