US20140340142A1 - Multi-level stack voltage system for integrated circuits - Google Patents
Multi-level stack voltage system for integrated circuits Download PDFInfo
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- US20140340142A1 US20140340142A1 US13/896,019 US201313896019A US2014340142A1 US 20140340142 A1 US20140340142 A1 US 20140340142A1 US 201313896019 A US201313896019 A US 201313896019A US 2014340142 A1 US2014340142 A1 US 2014340142A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/613—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in parallel with the load as final control devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
- H02J1/08—Three-wire systems; Systems having more than three wires
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
- H02J1/08—Three-wire systems; Systems having more than three wires
- H02J1/082—Plural DC voltage, e.g. DC supply voltage with at least two different DC voltage levels
Definitions
- MOSFET metal-oxide-silicon field effect transistor
- a MOS transistor is four-terminal device with source, drain, gate and body terminals.
- the gate terminal is typically formed using a gate conductor layer (metal or polysilicon) that is insulated from the body by a gate dielectric layer.
- the gate dielectric layer is typically a silicon dioxide layer (referred to as “gate oxide layer”).
- the thickness of the gate oxide layer along with transistor geometry in a given process are some of the factors determining the speed of operation of a transistor device.
- the thickness of the gate oxide layer and transistor geometry also limit the amount of voltage that can be applied to the transistor device.
- Small geometry transistor devices In order to reduce the power consumption and achieve high speed, small geometry transistor devices are preferred. Small geometry transistor devices generally use a thinner gate oxide and require a lower power supply voltage to operate. However, many system applications have standard system power supply voltage, such as 3.3V, which is incompatible with integrated circuits using low voltage, thin oxide and small geometry transistor devices to achieve low power consumption and high speed.
- One example system application is a PON (Passive Optical Networks) optical module incorporating a laser diode driver and a receiver.
- the typical optical module requires 3.3V power source as a standard system power supply.
- the requirement for the standard 3.3V power supply precludes the use of integrated circuits incorporating thin oxide transistors devices to increase the speed of operation of the integrated circuits.
- a system application may use a linear regulator (such as an LDO) to generate a low power supply voltage to supply integrated circuits with thin gate oxide and small geometry devices in order to achieve high speed of operation.
- LDO linear regulator
- using an LDO to step down the standard system power supply voltage is not power efficient due to the wasted power drop across the LDO.
- a system application may use a switching regulator to generate a low power supply in order to increase power efficiency.
- such approach would require an external inductor that increase cost, and generate switching noise that could be detrimental to analog circuits in the system.
- FIG. 1 is a schematic diagram illustrating an integrated circuit incorporating a multi-level stack voltage system in embodiments of the present invention.
- FIG. 2 is a schematic diagram of a multi-level stack voltage generator which can be used to form the multi-level stack voltage system in embodiments of the present invention.
- FIG. 3 is a schematic diagram of an integrated circuit illustrating an example implementation of the multi-level stack voltage system in one embodiment of the present invention.
- FIG. 4 is a schematic diagram illustrating an integrated circuit incorporating a multi-level stack voltage system in alternate embodiments of the present invention.
- FIG. 5 is a schematic diagram further illustrating the core circuit in an integrated circuit utilizing reduced supply voltages and stacked circuit layer according to embodiments of the present invention
- the invention can be implemented in numerous ways, including as a process; an apparatus; a system; and/or a composition of matter.
- these implementations, or any other form that the invention may take, may be referred to as techniques.
- the order of the steps of disclosed processes may be altered within the scope of the invention.
- a multi-level stack voltage system for an integrated circuit includes a multi-level stack voltage generator configured to partition a system power supply voltage of the integrated circuit into one or more smaller supply voltages.
- the low power supply voltages are used to supply core circuit units arranged in a stack formation.
- an integrated circuit can be formed using low voltage, high speed transistor devices for the core circuitry while the integrated circuit receives a standard high power supply voltage from an external system power source.
- the multi-level stack voltage generator operates to apply the same current through multiple levels of circuitry to reduce the total current requirement.
- the integrated circuit thus formed can achieve high speed of operation while reducing power consumption.
- the reliability of the integrated circuit is also ensured by driving the low voltage transistor devices at the appropriate voltage levels.
- the integrated circuit may be constructed using thin gate oxide transistor devices for the core circuitry to achieve high speed of operation and reduced circuit area while reducing overall power consumption.
- the integrated circuit can be supplied by a high power supply voltage that would normally require thick gate oxide transistor devices which have lower speed of operation.
- the external system power source provides a 3.6V power supply voltage to the integrated circuit and the multi-level stack voltage system partitions the 3.6V power supply voltage into three 1.2V supply voltages. The 1.2V supply voltages are then used to drive circuitry formed using thin gate oxide transistors, such as 90 nm gate oxide transistors.
- FIG. 1 is a schematic diagram illustrating an integrated circuit incorporating a multi-level stack voltage system in embodiments of the present invention.
- an integrated circuit 10 receives a system power supply voltage including a positive power supply voltage V Rail+ (node 12 ) and a negative power supply voltage V Rail ⁇ (node 14 ) from an external system power source.
- the power supply voltage for an MOS integrated circuit is often referred to as the Vdd voltage and is also referred to as the rail-to-rail power supply voltage, or rail-to-rail power supply, in the present description.
- the rail-to-rail power supply voltage is a positive power supply voltage only and the negative power supply voltage (node 14 ) is ground or 0V.
- Integrated circuit 10 can be generalized as including an I/O circuit 16 and a core circuit 28 .
- the I/O circuit 16 is configured to receive input signals I/O_In on input terminals 17 and to provide output signals I/O_Out on output terminals 18 of the integrated circuit. Because the I/O circuit 16 interfaces with systems external to the integrated circuit 10 , the I/O circuit 16 is operated at the rail-to-rail power supply voltage so that the I/O circuit can receive input signals and can generate output signals at voltage levels that are compatible with external systems.
- the rail-to-rail power supply voltages V Rail+ and V Rail ⁇ are usually too high to allow the use of low voltage, high speed transistor devices.
- Integrated circuit 10 incorporates a multi-level stack voltage generator 30 configured to receive the rail-to-rail power supply voltage V Rail+ and V Rail ⁇ and to generate a series of one or more reduced supply voltages 32 having voltage values smaller than the voltage range of the rail-to-rail power supply voltage.
- multi-level stack voltage generator 30 generates a series of reduced supply voltages V 1 to V n .
- the reduced supply voltages 32 together with the rail-to-rail power supply voltage V Rail+ and V Rail ⁇ , are used to supply the core circuit 28 . More specifically, the core circuit 28 is divided into core circuit units 36 and the core circuit units 36 are supplied by the reduced supply voltages 32 in a stack formation.
- a core circuit unit 36 may include a combination of active or passive circuit elements.
- the reduced supply voltages 32 and the rail-to-rail power supply voltage V Rail+ and V Rail ⁇ are arranged in a stack formation or in series so that a pair of adjacent supply voltages forms a circuit layer 34 .
- Core circuit units 36 are arranged within the circuit layers 34 so that each core circuit unit 36 is supplied by two adjacent supply voltages having a reduced voltage range than the rail-to-rail power supply voltage. That is, a first core circuit unit 36 may be supplied by reduced supply voltage V1 and the negative power supply voltage V Rail ⁇ while a second core circuit unit 36 may be supplied by reduced supply voltage V n and V n ⁇ 1 . Meanwhile a third core circuit unit may be supplied by the positive power supply voltage V Rail+ and a reduced supply voltage V n .
- the core circuit units 36 use the reduced supply voltages as the internal power source to process signals or to operate the circuit within the unit.
- the core circuit units 36 are supplied by smaller power supply voltages, the core circuit units 36 can be formed using low voltage, high speed transistors devices so that the core circuit 28 of the integrated circuit 10 can achieve a high speed of operation. As a result, the integrated circuit 10 can achieve a high operation speed while being supplied by a standard power supply voltage where the standard power supply voltage may have a voltage value too large to be compatible with the low voltage, high speed transistors used in the core circuit 28 .
- the core circuit units 36 are arranged in a stack formation or in series between the largest supply voltage value (the positive power supply voltage V Rail+ ) and the smallest supply voltage value (the negative power supply voltage V Rail ⁇ ) with the core circuit units 36 being supplied by the reduced supply voltages V 1 to V n disposed between the rail-to-rail power supply voltage.
- the multi-level stack voltage generator 30 is configured to maintain the voltage levels of the reduced supply voltages 32 and adjust the power flow through the core circuit units 36 . Since the same current is applied to multiple levels of circuit layers 34 , efficient power consumption is realized.
- Integrated circuit 10 receives input signals that are referenced to the rail-to-rail power supply voltage V Rail+ and V Rail ⁇ and also needs to generate output signals that are referenced to the rail-to-rail power supply voltage V Rail+ and V Rail ⁇ .
- the core circuit 28 includes core circuit units 36 for processing signals that are referenced to the reduced supply voltages having a smaller voltage range.
- the I/O circuit 16 in the integrated circuit 10 incorporates the level shifters or level translators to translate signal levels of signals between the I/O circuit 16 and the core circuit 28 .
- I/O circuit 16 includes input I/O circuits 20 receiving input signals 17 .
- the input signals 17 are coupled to level shifters 22 to be translated to level-translated input signals 24 .
- Each of the level-translated input signals 24 has a voltage range matching the supply voltage range of the core circuit unit 36 receiving that input signal.
- the core circuit units 36 process signals, including the input signals, and some of the core circuit units 36 may generate level-shifted output signals 26 to be outputted out of the integrated circuit 10 .
- the I/O circuit 16 further includes level shifters 23 receiving the level-shifted output signals 26 from the core circuit 28 .
- the level shifters 23 translate the level-shifted output signals 26 to level-translated output signals having a voltage range of the rail-to-rail power supply voltage.
- the level-translated output signals are then provided to output I/O circuits 21 to generate the output signals 18 .
- FIG. 2 is a schematic diagram of a multi-level stack voltage generator which can be used to form the multi-level stack voltage system in embodiments of the present invention.
- a multi-level stack voltage generator 30 includes a reference voltage generator 40 generating a set of reference voltages V refi between the rail-to-rail power supply voltage V Rail+ and V Rail ⁇ .
- the reference voltages V refi are used by the multi-level stack voltage generator to regulate the reduced supply voltages being generated, as will be explained in more detail below.
- the reference voltage generator 40 is a resistor string including resistors R 1 to R n+1 to divide down the rail-to-rail power supply voltage to generate n reference voltages V ref1 to V refn .
- the reference voltage generator 40 may be formed on the same integrated circuit as the multi-level stack voltage generator 30 .
- the reference voltage generator 40 may be formed external to the integrated circuit as the multi-level stack voltage generator 30 and the set of reference voltages is provided to the voltage generator. The exact circuit or method used to generate the set of reference voltages is not critical to the practice of the present invention.
- the multi-level stack voltage generator 30 further includes a power-voltage controller 42 configured to generate a series of reduced supply voltages V 1 to V n on nodes 32 a to 32 n.
- the reduced supply voltages V 1 to V n together with the rail-to-rail power supply voltage V Rail+ and V Rail ⁇ , are used to supply the core circuit units 36 coupled between a pair of adjacent supply voltages.
- each pair of adjacent supply voltages form a circuit layer 34 for housing a core circuit unit and biasing the core circuit unit within the voltage range of the adjacent supply voltages.
- the reduced supply voltages V 1 to V n and the rail-to-rail power supply voltage V Rail+ and V Rail ⁇ form circuit layers 34 a to 34 n where each circuit layer 34 i may house one or more core circuit units.
- the power-voltage controller 42 operates to regulate the voltage levels of each reduced supply voltages V 1 to V n so that reduced supply voltages maintain substantially stable voltage values during operation of the voltage generator 30 .
- power-voltage controller 42 includes a sense amplifier 44 i, a power control unit 46 i, and a power adjust unit 48 i for each reduced supply voltage V i being generated.
- the sense amplifier 44 i compares the reduced supply voltage V i to the associated reference voltage V refi . The error signal thus generated is provided to the power control unit 46 i.
- the power control unit 46 i generates a control signal to control the power adjust unit 48 i so as to regulate the voltage level of the reduced supply voltage V i to the reference voltage V refi .
- the power control unit 46 i generates the control signal to the power adjust unit 48 i to adjust the voltage level of the voltage V i to stabilize the voltage level of voltage V i .
- a power adjust unit 48 i is coupled between two adjacent reduced supply voltages V i ⁇ 1 and V i .
- the power adjust unit 48 adjusts the reduced supply voltage V i by sinking or sourcing a current from voltage V i ⁇ 1 to voltage V i .
- the power adjust unit 48 i provides a low impedance output for both voltages V i ⁇ 1 to V i .
- the sense amplifier 44 compares the reference voltage V refn ⁇ 1 to voltage V n ⁇ 1 and generates an error signal.
- the error signal is provided to power control unit 46 which generates a control signal to control the power adjust unit 48 .
- the power adjust unit 48 is connected between the reduced supply voltage V n (node 32 n ) and voltage V n ⁇ 1 (node 32 m ).
- the power control unit 46 controls the power adjust unit 48 to sink or source current between nodes 32 n and 32 m so as to stabilize the reduced supply voltage V n ⁇ 1 .
- the power-voltage controller 42 includes power adjust units 48 connected to each circuit layer 34 and connected in series between the rail-to-rail power supply voltages V Rail+ and V Rail ⁇ .
- the power adjust unit 48 for each circuit layer 34 adjusts its current flows so as to maintain the voltage value for each reduced supply voltage. For example, when the core circuit unit(s) in circuit layer 34 m is not drawing as much current as the core circuit unit(s) in circuit layer 34 n, the power adjust unit for circuit layer 34 m routes the excess current through the power adjust unit so that the current flow in both circuit layers is balanced. In other words, the core circuit units in the circuit layers share the same current while the power adjust unit adjusts the shared current flowing through each circuit layer to maintain stable reduced supply voltages V 1 to V n .
- FIG. 3 is a schematic diagram of an integrated circuit illustrating an example implementation of the multi-level stack voltage system in one embodiment of the present invention.
- an integrated circuit 60 receives a positive power supply voltage V Rail+ (node 62 ) and a negative power supply voltage V Rail ⁇ (node 64 ).
- the positive power supply voltage V Rail+ is 3.3V and the negative power supply voltage V Rail ⁇ is 0V or ground.
- the integrated circuit 60 includes a multi-level stack voltage generator 80 to generate a reduced supply voltage V m (node 82 ).
- the reduced supply voltage V m is 1.65V.
- the integrated circuit 60 is configured to include two core circuit units 86 to be supplied by the rail-to-rail power supply voltage V Rail+ /V Rail ⁇ and the reduced supply voltage V m . More specifically, core circuit unit 1 is coupled between the positive power supply voltage V Rail+ (node 62 ) and the reduced supply voltage V m (node 82 ). Meanwhile, core circuit unit 2 is coupled between the reduced supply voltage V m (node 82 ) and the negative power supply voltage V Rail ⁇ (node 64 ). Accordingly, the transistor devices in core circuit units 1 and 2 are biased to a reduced voltage range (e.g., 1.65V), less than the rail-to-rail power supply voltage of the integrated circuit 60 .
- a reduced voltage range e.g., 1.65V
- the integrated circuit 60 includes I/O circuit units 70 receiving incoming input signals and providing outgoing output signals on node 66 .
- the I/O circuit units 70 are biased between the rail-to-rail power supply voltages to enable the integrated circuit 60 to interface with external systems. Because the I/O circuit units 70 and the core circuit units 1 and 2 are biased to different supply voltage ranges, integrated circuit 60 includes level shifters 72 coupled between the core circuit units 1 and 2 and the I/O circuit units 70 .
- Level shifters 72 level translate signals intended for the core circuit unit 1 or 2 from the rail-to-rail power supply voltage to the reduced voltage range (e.g. from 3.3V to 1.65V) and vice versa.
- integrated circuit 60 While integrated circuit 60 interfaces with external systems at the rail-to-rail power supply voltage, integrated circuit 60 operates the core circuit using lower supply voltages.
- the lower supply voltage provided by the multi-level stack voltage generator 80 enables the use of low voltage, high speed transistor devices for the core circuitry.
- the I/O circuit units 70 , the level shifters 72 and the multi-level stack voltage generator 80 are powered by the rail-to-rail power supply voltage and are therefore formed using thick gate oxide MOS devices that can withstand high supply voltages.
- the core circuit units 1 and 2 are powered by the reduced supply voltage and can therefore be formed using thin gate oxide MOS devices that can be operated at high speed.
- Multi-level stack voltage generator 80 sinks or sources current at the power supply nodes 62 , 64 and 82 so as to maintain a stable reduced supply voltage V m .
- the integrated circuit 60 uses 0.35 ⁇ thick-oxide MOS transistor devices for circuitry being operated using the rail-to-rail power supply voltage, that is, the I/O circuit units 70 , the level shifters 72 and the multi-level stack voltage generator 80 .
- the integrated circuit 60 further uses 0.15 ⁇ thin-oxide MOS transistor devices for core circuitry being operated using the reduced supply voltage V m , that is, the core circuit units 1 and 2.
- FIG. 4 is a schematic diagram illustrating an integrated circuit incorporating a multi-level stack voltage system in alternate embodiments of the present invention.
- an integrated circuit 100 includes I/O circuit 106 for receiving input signals 110 and I/O circuit 108 for providing output signals 120 .
- the I/O circuits 106 and 108 are biased by the rail-to-rail power supply voltage, including positive power supply voltage V Rail+ (node 102 ) and negative power supply voltage V Rail ⁇ (node 104 ).
- I/O circuit 106 includes input circuits 112 for receiving input signals 110 and one or more level shifter circuits 114 for generating level translated signals on nodes 126 and 126 for the core circuit 128 .
- I/O circuit 108 includes one or more level shifter circuits 116 for receiving level shifted signals from the core circuit 128 and level translating the signals for output circuits 118 .
- the output circuits 118 provides the output signals 120 to systems outside of integrated circuit 100 .
- the multi-level stack voltage generator 130 generates reduced supply voltages V 1 to V 3 .
- core circuit 128 includes four stacked circuit layers for supplying core circuit units 136 .
- the core circuit units can process signals within a circuit layer and then the processed signals may be level-translated to be further processed by another circuit layer.
- level translated signal 124 is provided to a core circuit unit 136 a coupled to the supply voltage V Rail+ and V 3 .
- the core circuit unit 136 a processes the signal and provides the processed signal to another core circuit unit 136 b which then provides the processed signal to the I/O circuit 108 to generate the output signals 120 .
- the core circuit unit 136 a may provide the processed signal to a core circuit unit 136 c in a different circuit layer.
- a down level shifter 150 is used to shift the processed signal from the voltage domain of core circuit unit 136 a to the voltage domain of core circuit unit 136 c.
- Core circuit unit 136 c processes the signal and provides the processed signal to the I/O circuit 108 to generate the output signals 120 .
- the level translated signal 126 is provided to a core circuit unit 136 d coupled to the supply voltage V 1 and V Rail ⁇ .
- the core circuit unit 136 d processes the signal and provides the processed signal to a core circuit unit in another voltage domain.
- an up lever shifted 152 level translates the signal from core circuit unit 136 d to the voltage domain of core circuit unit 136 e.
- Core circuit unit 136 e processes the signal and provides the processed signal to the I/O circuit 108 to generate the output signals 120 .
- the core circuit units 136 in the core circuit 128 can be arranged within the stacked circuit layers to make use of the reduced supply voltages.
- Each core circuit unit processes the signals and the signals may be transferred between different circuit layers as long as the signals are properly level translated.
- FIG. 5 is a schematic diagram further illustrating the core circuit in an integrated circuit utilizing reduced supply voltages and stacked circuit layer according to embodiments of the present invention.
- an integrated circuit incorporates a multi-level stack voltage generator (not shown) to generate a series of reduced supply voltages V 1 to V 3 .
- core circuit 228 may configure the core circuit units in any circuit layers or between two or more circuit layers. The core circuit units may assume different configurations to utilize the reduced supply voltages efficiently and optimally.
- a core circuit unit 230 is coupled across two adjacent supply voltages V Rail+ and V 3 .
- a core circuit unit 248 is coupled across two circuit layers, between supply voltages V Rail+ and V 2 .
- Level shifters are used to convert signals between one voltage domain to another voltage domain.
- the core circuit unit 230 receives a level-shifted input signal LS_I/O1 210 .
- the core circuit unit 230 may process the signal and provide the signal further to a core circuit unit 232 which generates a level-shifted output signal LS_I/O3 213 .
- a down level shifter 242 may receive the signal from the core circuit unit 230 and convert the signal to the voltage domain of core circuit unit 244 which is coupled between supply voltages V 2 and V 3 .
- Core circuit unit 244 may process the signal and then the signal is level translated by up lever shifter 246 into the voltage domain of core circuit unit 248 .
- the core circuit unit 248 may process the signal and provide the signal as a level-shifted output signal LS_I/O5 215 .
- the core circuit unit 234 receives an input signal LS_I/O2 211 and processes the signal.
- An up level shifter converts the signal to the voltage domain of core circuit unit 254 .
- Core circuit unit 254 processes the signal and the signal may further be level shifted by up level shifter 256 to the voltage domain of core circuit unit 232 .
- the core circuit unit 232 processes the signal to generate the output signal LS_IO3 213 .
- the multi-level stack voltage generator partitions the rail-to-rail power supply voltage evenly into the one or more reduced supply voltages. In other embodiments, the multi-level stack voltage generator partitions the rail-to-rail power supply voltage in other proportions into the one or more reduced supply voltages. For example, a 3.6V rail-to-rail power supply voltage may be partitioned into 1.2V and 2.4V reduced supply voltages. Alternately, the 3.6V rail-to-rail power supply voltage may be partitioned into 0.8V and 1.5V reduced supply voltages.
- the multi-level stack voltage system of the present invention improves the power efficiency of the integrated circuit in which the voltage system is incorporated.
- power consumption is reduced as the same current flows through all the core circuit units.
- the multi-level stack voltage generator operates to maintain the stability of the reduced supply voltages by routing excess current in a circuit layer through the power adjust unit.
- the power consumption of the core circuit is determined by the core circuit unit drawing the largest amount of current.
Abstract
Description
- Electronic systems are formed using integrated circuits or semiconductor chips commonly fabricated using metal-oxide-silicon field effect transistor (MOSFET) devices. A MOS transistor is four-terminal device with source, drain, gate and body terminals. The gate terminal is typically formed using a gate conductor layer (metal or polysilicon) that is insulated from the body by a gate dielectric layer. The gate dielectric layer is typically a silicon dioxide layer (referred to as “gate oxide layer”). The thickness of the gate oxide layer along with transistor geometry in a given process are some of the factors determining the speed of operation of a transistor device. The thickness of the gate oxide layer and transistor geometry also limit the amount of voltage that can be applied to the transistor device.
- Electronic systems with integrated circuits that are operated at high speed often consume large amount of power and generate large amount of heat. In order to reduce the power consumption and achieve high speed, small geometry transistor devices are preferred. Small geometry transistor devices generally use a thinner gate oxide and require a lower power supply voltage to operate. However, many system applications have standard system power supply voltage, such as 3.3V, which is incompatible with integrated circuits using low voltage, thin oxide and small geometry transistor devices to achieve low power consumption and high speed.
- One example system application is a PON (Passive Optical Networks) optical module incorporating a laser diode driver and a receiver. The typical optical module requires 3.3V power source as a standard system power supply. The requirement for the standard 3.3V power supply precludes the use of integrated circuits incorporating thin oxide transistors devices to increase the speed of operation of the integrated circuits. In some cases, a system application may use a linear regulator (such as an LDO) to generate a low power supply voltage to supply integrated circuits with thin gate oxide and small geometry devices in order to achieve high speed of operation. However, using an LDO to step down the standard system power supply voltage is not power efficient due to the wasted power drop across the LDO. In other cases, a system application may use a switching regulator to generate a low power supply in order to increase power efficiency. However such approach would require an external inductor that increase cost, and generate switching noise that could be detrimental to analog circuits in the system.
- Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings.
-
FIG. 1 is a schematic diagram illustrating an integrated circuit incorporating a multi-level stack voltage system in embodiments of the present invention. -
FIG. 2 is a schematic diagram of a multi-level stack voltage generator which can be used to form the multi-level stack voltage system in embodiments of the present invention. -
FIG. 3 is a schematic diagram of an integrated circuit illustrating an example implementation of the multi-level stack voltage system in one embodiment of the present invention. -
FIG. 4 is a schematic diagram illustrating an integrated circuit incorporating a multi-level stack voltage system in alternate embodiments of the present invention. -
FIG. 5 is a schematic diagram further illustrating the core circuit in an integrated circuit utilizing reduced supply voltages and stacked circuit layer according to embodiments of the present invention - The invention can be implemented in numerous ways, including as a process; an apparatus; a system; and/or a composition of matter. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention.
- A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.
- In embodiments of the present invention, a multi-level stack voltage system for an integrated circuit includes a multi-level stack voltage generator configured to partition a system power supply voltage of the integrated circuit into one or more smaller supply voltages. The low power supply voltages are used to supply core circuit units arranged in a stack formation. In this manner, an integrated circuit can be formed using low voltage, high speed transistor devices for the core circuitry while the integrated circuit receives a standard high power supply voltage from an external system power source. In particular, the multi-level stack voltage generator operates to apply the same current through multiple levels of circuitry to reduce the total current requirement. The integrated circuit thus formed can achieve high speed of operation while reducing power consumption. The reliability of the integrated circuit is also ensured by driving the low voltage transistor devices at the appropriate voltage levels.
- When an MOS integrated circuit incorporates the multi-level stack voltage system of the present invention, the integrated circuit may be constructed using thin gate oxide transistor devices for the core circuitry to achieve high speed of operation and reduced circuit area while reducing overall power consumption. The integrated circuit can be supplied by a high power supply voltage that would normally require thick gate oxide transistor devices which have lower speed of operation. In one embodiment, the external system power source provides a 3.6V power supply voltage to the integrated circuit and the multi-level stack voltage system partitions the 3.6V power supply voltage into three 1.2V supply voltages. The 1.2V supply voltages are then used to drive circuitry formed using thin gate oxide transistors, such as 90 nm gate oxide transistors.
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FIG. 1 is a schematic diagram illustrating an integrated circuit incorporating a multi-level stack voltage system in embodiments of the present invention. Referring toFIG. 1 , anintegrated circuit 10 receives a system power supply voltage including a positive power supply voltage VRail+ (node 12) and a negative power supply voltage VRail− (node 14) from an external system power source. The power supply voltage for an MOS integrated circuit is often referred to as the Vdd voltage and is also referred to as the rail-to-rail power supply voltage, or rail-to-rail power supply, in the present description. In some examples, the rail-to-rail power supply voltage is a positive power supply voltage only and the negative power supply voltage (node 14) is ground or 0V. -
Integrated circuit 10 can be generalized as including an I/O circuit 16 and acore circuit 28. The I/O circuit 16 is configured to receive input signals I/O_In oninput terminals 17 and to provide output signals I/O_Out onoutput terminals 18 of the integrated circuit. Because the I/O circuit 16 interfaces with systems external to theintegrated circuit 10, the I/O circuit 16 is operated at the rail-to-rail power supply voltage so that the I/O circuit can receive input signals and can generate output signals at voltage levels that are compatible with external systems. The rail-to-rail power supply voltages VRail+ and VRail− are usually too high to allow the use of low voltage, high speed transistor devices. -
Integrated circuit 10 incorporates a multi-levelstack voltage generator 30 configured to receive the rail-to-rail power supply voltage VRail+ and VRail− and to generate a series of one or more reducedsupply voltages 32 having voltage values smaller than the voltage range of the rail-to-rail power supply voltage. In the present embodiment, multi-levelstack voltage generator 30 generates a series of reduced supply voltages V1 to Vn. The reducedsupply voltages 32, together with the rail-to-rail power supply voltage VRail+ and VRail−, are used to supply thecore circuit 28. More specifically, thecore circuit 28 is divided intocore circuit units 36 and thecore circuit units 36 are supplied by the reducedsupply voltages 32 in a stack formation. In some embodiments, acore circuit unit 36 may include a combination of active or passive circuit elements. - In embodiments of the present invention, the reduced
supply voltages 32 and the rail-to-rail power supply voltage VRail+ and VRail− are arranged in a stack formation or in series so that a pair of adjacent supply voltages forms acircuit layer 34.Core circuit units 36 are arranged within thecircuit layers 34 so that eachcore circuit unit 36 is supplied by two adjacent supply voltages having a reduced voltage range than the rail-to-rail power supply voltage. That is, a firstcore circuit unit 36 may be supplied by reduced supply voltage V1 and the negative power supply voltage VRail− while a secondcore circuit unit 36 may be supplied by reduced supply voltage Vn and Vn−1. Meanwhile a third core circuit unit may be supplied by the positive power supply voltage VRail+ and a reduced supply voltage Vn. Thecore circuit units 36 use the reduced supply voltages as the internal power source to process signals or to operate the circuit within the unit. - Because the
core circuit units 36 are supplied by smaller power supply voltages, thecore circuit units 36 can be formed using low voltage, high speed transistors devices so that thecore circuit 28 of the integratedcircuit 10 can achieve a high speed of operation. As a result, the integratedcircuit 10 can achieve a high operation speed while being supplied by a standard power supply voltage where the standard power supply voltage may have a voltage value too large to be compatible with the low voltage, high speed transistors used in thecore circuit 28. - With the
core circuit units 36 arranged in thestacked circuit layers 34, thecore circuit units 36 are arranged in a stack formation or in series between the largest supply voltage value (the positive power supply voltage VRail+) and the smallest supply voltage value (the negative power supply voltage VRail−) with thecore circuit units 36 being supplied by the reduced supply voltages V1 to Vn disposed between the rail-to-rail power supply voltage. The multi-levelstack voltage generator 30 is configured to maintain the voltage levels of the reducedsupply voltages 32 and adjust the power flow through thecore circuit units 36. Since the same current is applied to multiple levels of circuit layers 34, efficient power consumption is realized. - Integrated
circuit 10 receives input signals that are referenced to the rail-to-rail power supply voltage VRail+ and VRail− and also needs to generate output signals that are referenced to the rail-to-rail power supply voltage VRail+ and VRail−. Meanwhile, thecore circuit 28 includescore circuit units 36 for processing signals that are referenced to the reduced supply voltages having a smaller voltage range. In embodiments of the present invention, the I/O circuit 16 in theintegrated circuit 10 incorporates the level shifters or level translators to translate signal levels of signals between the I/O circuit 16 and thecore circuit 28. In the present embodiment, I/O circuit 16 includes input I/O circuits 20 receiving input signals 17. The input signals 17 are coupled tolevel shifters 22 to be translated to level-translated input signals 24. Each of the level-translated input signals 24 has a voltage range matching the supply voltage range of thecore circuit unit 36 receiving that input signal. Insidecore circuit 28, thecore circuit units 36 process signals, including the input signals, and some of thecore circuit units 36 may generate level-shiftedoutput signals 26 to be outputted out of theintegrated circuit 10. To that end, the I/O circuit 16 further includeslevel shifters 23 receiving the level-shiftedoutput signals 26 from thecore circuit 28. The level shifters 23 translate the level-shiftedoutput signals 26 to level-translated output signals having a voltage range of the rail-to-rail power supply voltage. The level-translated output signals are then provided to output I/O circuits 21 to generate the output signals 18. -
FIG. 2 is a schematic diagram of a multi-level stack voltage generator which can be used to form the multi-level stack voltage system in embodiments of the present invention. Referring toFIG. 2 , a multi-levelstack voltage generator 30 includes areference voltage generator 40 generating a set of reference voltages Vrefi between the rail-to-rail power supply voltage VRail+ and VRail −. The reference voltages Vrefi are used by the multi-level stack voltage generator to regulate the reduced supply voltages being generated, as will be explained in more detail below. - In the present embodiment, the
reference voltage generator 40 is a resistor string including resistors R1 to Rn+1 to divide down the rail-to-rail power supply voltage to generate n reference voltages Vref1to Vrefn. In other embodiments, thereference voltage generator 40 may be formed on the same integrated circuit as the multi-levelstack voltage generator 30. Alternately, in some embodiments, thereference voltage generator 40 may be formed external to the integrated circuit as the multi-levelstack voltage generator 30 and the set of reference voltages is provided to the voltage generator. The exact circuit or method used to generate the set of reference voltages is not critical to the practice of the present invention. - The multi-level
stack voltage generator 30 further includes a power-voltage controller 42 configured to generate a series of reduced supply voltages V1 to Vn onnodes 32 a to 32 n. The reduced supply voltages V1 to Vn, together with the rail-to-rail power supply voltage VRail+ and VRail−, are used to supply thecore circuit units 36 coupled between a pair of adjacent supply voltages. In particular, each pair of adjacent supply voltages form acircuit layer 34 for housing a core circuit unit and biasing the core circuit unit within the voltage range of the adjacent supply voltages. As thus configured, the reduced supply voltages V1 to Vn and the rail-to-rail power supply voltage VRail+ and VRail− form circuit layers 34 a to 34 n where each circuit layer 34 i may house one or more core circuit units. - Because loading at the circuit layers 34 a to 34 n may not be exactly the same, the power-
voltage controller 42 operates to regulate the voltage levels of each reduced supply voltages V1 to Vn so that reduced supply voltages maintain substantially stable voltage values during operation of thevoltage generator 30. To that end, power-voltage controller 42 includes a sense amplifier 44 i, a power control unit 46 i, and a power adjust unit 48 i for each reduced supply voltage Vi being generated. For each reduced supply voltage Vi, the sense amplifier 44 i compares the reduced supply voltage Vi to the associated reference voltage Vrefi. The error signal thus generated is provided to the power control unit 46 i. The power control unit 46 i generates a control signal to control the power adjust unit 48 i so as to regulate the voltage level of the reduced supply voltage Vi to the reference voltage Vrefi. The power control unit 46 i generates the control signal to the power adjust unit 48 i to adjust the voltage level of the voltage Vi to stabilize the voltage level of voltage Vi. - In particular, a power adjust unit 48 i is coupled between two adjacent reduced supply voltages Vi−1 and Vi. In one embodiment, the power adjust
unit 48 adjusts the reduced supply voltage Vi by sinking or sourcing a current from voltage Vi−1 to voltage Vi. At the same time, the power adjust unit 48 i provides a low impedance output for both voltages Vi−1 to Vi. For example, for reduced supply voltage Vn−1, thesense amplifier 44 compares the reference voltage Vrefn−1 to voltage Vn−1 and generates an error signal. The error signal is provided topower control unit 46 which generates a control signal to control the power adjustunit 48. the power adjustunit 48 is connected between the reduced supply voltage Vn (node 32 n) and voltage Vn−1 (node 32 m). Thepower control unit 46 controls the power adjustunit 48 to sink or source current betweennodes - As thus configured, the power-
voltage controller 42 includes power adjustunits 48 connected to eachcircuit layer 34 and connected in series between the rail-to-rail power supply voltages VRail+ and VRail−. In operation, the power adjustunit 48 for eachcircuit layer 34 adjusts its current flows so as to maintain the voltage value for each reduced supply voltage. For example, when the core circuit unit(s) in circuit layer 34 m is not drawing as much current as the core circuit unit(s) incircuit layer 34 n, the power adjust unit for circuit layer 34 m routes the excess current through the power adjust unit so that the current flow in both circuit layers is balanced. In other words, the core circuit units in the circuit layers share the same current while the power adjust unit adjusts the shared current flowing through each circuit layer to maintain stable reduced supply voltages V1 to Vn. -
FIG. 3 is a schematic diagram of an integrated circuit illustrating an example implementation of the multi-level stack voltage system in one embodiment of the present invention. Referring toFIG. 3 , anintegrated circuit 60 receives a positive power supply voltage VRail+ (node 62) and a negative power supply voltage VRail− (node 64). In one embodiment, the positive power supply voltage VRail+ is 3.3V and the negative power supply voltage VRail− is 0V or ground. Theintegrated circuit 60 includes a multi-levelstack voltage generator 80 to generate a reduced supply voltage Vm (node 82). In one embodiment, the reduced supply voltage Vm is 1.65V. Theintegrated circuit 60 is configured to include twocore circuit units 86 to be supplied by the rail-to-rail power supply voltage VRail+/VRail− and the reduced supply voltage Vm. More specifically,core circuit unit 1 is coupled between the positive power supply voltage VRail+ (node 62) and the reduced supply voltage Vm (node 82). Meanwhile, core circuit unit 2 is coupled between the reduced supply voltage Vm (node 82) and the negative power supply voltage VRail− (node 64). Accordingly, the transistor devices incore circuit units 1 and 2 are biased to a reduced voltage range (e.g., 1.65V), less than the rail-to-rail power supply voltage of theintegrated circuit 60. - The
integrated circuit 60 includes I/O circuit units 70 receiving incoming input signals and providing outgoing output signals onnode 66. The I/O circuit units 70 are biased between the rail-to-rail power supply voltages to enable theintegrated circuit 60 to interface with external systems. Because the I/O circuit units 70 and thecore circuit units 1 and 2 are biased to different supply voltage ranges, integratedcircuit 60 includeslevel shifters 72 coupled between thecore circuit units 1 and 2 and the I/O circuit units 70.Level shifters 72 level translate signals intended for thecore circuit unit 1 or 2 from the rail-to-rail power supply voltage to the reduced voltage range (e.g. from 3.3V to 1.65V) and vice versa. - In this manner, while integrated
circuit 60 interfaces with external systems at the rail-to-rail power supply voltage, integratedcircuit 60 operates the core circuit using lower supply voltages. The lower supply voltage provided by the multi-levelstack voltage generator 80 enables the use of low voltage, high speed transistor devices for the core circuitry. For example, inintegrated circuit 60, the I/O circuit units 70, thelevel shifters 72 and the multi-levelstack voltage generator 80 are powered by the rail-to-rail power supply voltage and are therefore formed using thick gate oxide MOS devices that can withstand high supply voltages. Meanwhile, thecore circuit units 1 and 2 are powered by the reduced supply voltage and can therefore be formed using thin gate oxide MOS devices that can be operated at high speed. Furthermore, by stacking thecore circuit 1 and core circuit 2 between the rail-to-rail power supply voltage, power consumption is reduced as thecore circuit unit 1 and core circuit unit 2 share the current flowing from the rail-to-rail power supply (nodes 62 to 64). Multi-levelstack voltage generator 80 sinks or sources current at thepower supply nodes - In one embodiment, the
integrated circuit 60 uses 0.35μ thick-oxide MOS transistor devices for circuitry being operated using the rail-to-rail power supply voltage, that is, the I/O circuit units 70, thelevel shifters 72 and the multi-levelstack voltage generator 80. Theintegrated circuit 60 further uses 0.15μ thin-oxide MOS transistor devices for core circuitry being operated using the reduced supply voltage Vm, that is, thecore circuit units 1 and 2. -
FIG. 4 is a schematic diagram illustrating an integrated circuit incorporating a multi-level stack voltage system in alternate embodiments of the present invention. Referring toFIG. 4 , anintegrated circuit 100 includes I/O circuit 106 for receiving input signals 110 and I/O circuit 108 for providing output signals 120. The I/O circuits O circuit 106 includesinput circuits 112 for receiving input signals 110 and one or morelevel shifter circuits 114 for generating level translated signals onnodes core circuit 128. I/O circuit 108 includes one or morelevel shifter circuits 116 for receiving level shifted signals from thecore circuit 128 and level translating the signals foroutput circuits 118. Theoutput circuits 118 provides the output signals 120 to systems outside ofintegrated circuit 100. - In the present embodiment, the multi-level
stack voltage generator 130 generates reduced supply voltages V1 to V3. As thus configured,core circuit 128 includes four stacked circuit layers for supplying core circuit units 136. In operation, the core circuit units can process signals within a circuit layer and then the processed signals may be level-translated to be further processed by another circuit layer. For example, level translatedsignal 124 is provided to acore circuit unit 136 a coupled to the supply voltage VRail+ and V3. Thecore circuit unit 136 a processes the signal and provides the processed signal to anothercore circuit unit 136 b which then provides the processed signal to the I/O circuit 108 to generate the output signals 120. - At the same time, the
core circuit unit 136 a may provide the processed signal to acore circuit unit 136 c in a different circuit layer. A downlevel shifter 150 is used to shift the processed signal from the voltage domain ofcore circuit unit 136 a to the voltage domain ofcore circuit unit 136 c.Core circuit unit 136 c processes the signal and provides the processed signal to the I/O circuit 108 to generate the output signals 120. - In another case, the level translated
signal 126 is provided to acore circuit unit 136 d coupled to the supply voltage V1 and VRail−. Thecore circuit unit 136 d processes the signal and provides the processed signal to a core circuit unit in another voltage domain. For example, an up lever shifted 152 level translates the signal fromcore circuit unit 136 d to the voltage domain ofcore circuit unit 136 e.Core circuit unit 136 e processes the signal and provides the processed signal to the I/O circuit 108 to generate the output signals 120. - With the multi-level
stack voltage generator 130 providing reduced supply voltages, the core circuit units 136 in thecore circuit 128 can be arranged within the stacked circuit layers to make use of the reduced supply voltages. Each core circuit unit processes the signals and the signals may be transferred between different circuit layers as long as the signals are properly level translated. -
FIG. 5 is a schematic diagram further illustrating the core circuit in an integrated circuit utilizing reduced supply voltages and stacked circuit layer according to embodiments of the present invention. Referring toFIG. 5 , an integrated circuit incorporates a multi-level stack voltage generator (not shown) to generate a series of reduced supply voltages V1 to V3. With the provision of the series of reduced supply voltages,core circuit 228 may configure the core circuit units in any circuit layers or between two or more circuit layers. The core circuit units may assume different configurations to utilize the reduced supply voltages efficiently and optimally. - For example, in
FIG. 5 , acore circuit unit 230 is coupled across two adjacent supply voltages VRail+ and V3. Meanwhile, acore circuit unit 248, on the other hand, is coupled across two circuit layers, between supply voltages VRail+ and V2. Many other configurations of the core circuit units are possible. Level shifters are used to convert signals between one voltage domain to another voltage domain. - In
integrated circuit 200, thecore circuit unit 230 receives a level-shifted input signal LS_I/O1 210. Thecore circuit unit 230 may process the signal and provide the signal further to acore circuit unit 232 which generates a level-shifted output signal LS_I/O3 213. A downlevel shifter 242 may receive the signal from thecore circuit unit 230 and convert the signal to the voltage domain ofcore circuit unit 244 which is coupled between supply voltages V2 and V3.Core circuit unit 244 may process the signal and then the signal is level translated by uplever shifter 246 into the voltage domain ofcore circuit unit 248. Thecore circuit unit 248 may process the signal and provide the signal as a level-shifted output signal LS_I/O5 215. - In another example, the
core circuit unit 234 receives an input signal LS_I/O2 211 and processes the signal. An up level shifter converts the signal to the voltage domain ofcore circuit unit 254.Core circuit unit 254 processes the signal and the signal may further be level shifted by uplevel shifter 256 to the voltage domain ofcore circuit unit 232. Thecore circuit unit 232 processes the signal to generate theoutput signal LS_IO3 213. - In embodiments of the present invention, the multi-level stack voltage generator partitions the rail-to-rail power supply voltage evenly into the one or more reduced supply voltages. In other embodiments, the multi-level stack voltage generator partitions the rail-to-rail power supply voltage in other proportions into the one or more reduced supply voltages. For example, a 3.6V rail-to-rail power supply voltage may be partitioned into 1.2V and 2.4V reduced supply voltages. Alternately, the 3.6V rail-to-rail power supply voltage may be partitioned into 0.8V and 1.5V reduced supply voltages.
- The multi-level stack voltage system of the present invention improves the power efficiency of the integrated circuit in which the voltage system is incorporated. By connecting the core circuit units in a stack configuration between a series of supply voltages, power consumption is reduced as the same current flows through all the core circuit units. The multi-level stack voltage generator operates to maintain the stability of the reduced supply voltages by routing excess current in a circuit layer through the power adjust unit. The power consumption of the core circuit is determined by the core circuit unit drawing the largest amount of current.
- Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.
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