US20140332757A1 - Graphene photodetector - Google Patents
Graphene photodetector Download PDFInfo
- Publication number
- US20140332757A1 US20140332757A1 US13/891,940 US201313891940A US2014332757A1 US 20140332757 A1 US20140332757 A1 US 20140332757A1 US 201313891940 A US201313891940 A US 201313891940A US 2014332757 A1 US2014332757 A1 US 2014332757A1
- Authority
- US
- United States
- Prior art keywords
- electrode
- buried
- upper electrode
- electrodes
- graphene layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 68
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 62
- 239000002800 charge carrier Substances 0.000 claims abstract description 25
- 238000005259 measurement Methods 0.000 claims abstract description 20
- 239000012212 insulator Substances 0.000 claims description 32
- 230000005670 electromagnetic radiation Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 81
- 239000004020 conductor Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 238000009429 electrical wiring Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004299 exfoliation Methods 0.000 description 1
- -1 i.e. Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000001995 intermetallic alloy Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000000527 sonication Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/09—Devices sensitive to infrared, visible or ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/108—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the Schottky type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Definitions
- the present invention relates to an optoelectronic device, and particularly to a photodetector employing a sheet of graphene and methods of manufacturing and operating the same.
- Two-dimensional carbon lattice structures include sp 2 -bonded carbon atoms that are densely packed in a hexagonal lattice structure. If the two-dimensional carbon lattice structure is topologically planar, the two-dimensional carbon lattice structure constitutes a graphene layer. A graphene layer absorbs and emits light across the entire range of the electromagnetic spectrum, and sustains high electrical current densities and extreme temperatures.
- a photodetector based on a graphene layer can provide high efficiency by geometrically arranging a plurality of electrodes to minimize travel distances for charge carriers generated by photons.
- the photodetector utilizes both photovoltaic effects and photo-thermo-electric (PTE) effects to enhance the photoresponse of a graphene-based photodetector.
- PTE photo-thermo-electric
- a set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type is formed thereupon.
- a first upper electrode is formed over a center portion of each buried electrode.
- Second upper electrodes are formed in regions that do not overlie the buried electrodes.
- a bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.
- the response of the photodetector of the present invention is due to the photovoltaic and photothermoelectric effect at the p-n junctions in the graphene layer. These two effects produces a photocurrent in the same direction. The three effects result in electrical currents that flow along a same direction, thereby proving a greater photocurrent than a component of the electrical current due to the photovoltaic effect only.
- the location of the p-n junctions can be optimized by adjusting the magnitude of electrical bias applied to the buried electrodes.
- the lengths of the first and second upper electrodes and the buried electrodes can also be optimized to enhance the photoresponse of the device.
- the device of the present invention can be integrated into standard semiconductor manufacturing schemes to provide low cost electromagnetic radiation detectors.
- an electromagnetic radiation detector which includes at least one buried electrode embedded in an insulator layer, a graphene layer overlying the insulator layer, and at least one first upper electrode.
- Each of the at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of the at least one buried electrode.
- the electromagnetic radiation detector further includes at least one second upper electrode that does not overlie, and is laterally offset from sidewalls of, the at least one buried electrode.
- a measurement circuitry is configured to measure an electrical current between, or an electrical voltage across, the at least one first upper electrode and the at least one second upper electrode.
- a method of forming an electromagnetic radiation detector is provided. At least one buried electrode is formed in an insulator layer. A graphene layer is formed over the insulator layer. At least one first upper electrode is formed. Each of the at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of the at least one buried electrode. At least one second upper electrode is formed. The at least one second upper electrode does not overlie, and is laterally offset from sidewalls of, the at least one buried electrode.
- a measurement circuitry is formed, which is configured to measure an electrical current between, or an electrical voltage across, the at least one first upper electrode and the at least one second upper electrode.
- FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of trenches in an insulator layer according to an embodiment of the present invention.
- FIG. 2 is a vertical cross-sectional view of the exemplary structure after formation of buried electrodes according to an embodiment of the present invention.
- FIG. 3 is a vertical cross-sectional view of the exemplary structure after placement of a graphene layer on the top surface of the insulator layer according to an embodiment of the present invention.
- FIG. 4 is a vertical cross-sectional view of the exemplary structure after forming of first upper electrodes and second upper electrodes according to an embodiment of the present invention.
- FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement circuitry according to an embodiment of the present invention.
- FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement circuitry according to an embodiment of the present invention.
- the present invention relates to a photodetector employing a sheet of graphene and methods of manufacturing and operating the same. Aspects of the present invention are now described in detail with accompanying figures. It is noted that like reference numerals refer to like elements across different embodiments. As used herein, ordinals such as “first” and “second” are employed merely to distinguish similar elements, and different ordinals may be employed to designate a same element in the specification and/or claims.
- an exemplary structure includes a substrate 8 , which includes a stack of a handle substrate 10 and an insulator layer 20 .
- the handle substrate 10 can include a semiconductor material, a dielectric material, or a conductive material, and provides mechanical support to the insulator layer 20 and the structures to be formed thereupon.
- the insulator layer 20 includes a dielectric material such as silicon oxide, silicon nitride, or another dielectric material. The thickness of the insulator layer 20 can be in a range from 100 nm to 1,000 nm, although lesser and greater thicknesses can also be employed.
- Trenches 31 are formed in the insulator layer 20 , for example, by application of a photoresist layer 27 , formation of line-shaped openings within the photoresist layer 27 , and transfer of the pattern into the insulator layer 20 by an etch that employs the photoresist layer 27 as an etch mask.
- a “line-shaped opening” refers to an opening defined by a periphery including a pair of lengthwise edges that are parallel to each other.
- a “lengthwise edge” refers to an edge that is parallel to a longest edge of a shape.
- the etch can be an anisotropic etch such as a reactive ion etch, or can be an isotropic etch such as a wet etch.
- the etch can be an anisotropic etch.
- the depth of the trenches 31 can be in a range from 30 nm to 1,000 nm, although lesser and greater depths can also be employed.
- the peripheries of the trenches 31 coincide with the peripheries of the openings in the photoresist layer 27 .
- Each trench 31 can have a pair of sidewalls that are laterally spaced by a width, which is herein referred to as a third width w 3 .
- the third width w 3 can be in a range from 50 nm to 5,000 nm, although lesser and greater third widths can also be employed.
- the distance between neighboring trenches 31 can be in a range from 50 nm to 2,000 nm, although lesser and greater distances can also be employed.
- the horizontal direction along which the lengthwise sidewalls of the trenches 31 extend is herein referred to as a lengthwise direction of the trenches 31 .
- the photoresist layer 27 is subsequently removed, for example, by ashing.
- buried electrodes 30 are formed by filling the trenches 31 with at least one conductive material and by removing portions of the at least one conductive material from above the horizontal plane including the top surface of the insulator layer 20 .
- a metallic layer and a metallic fill material layer can be sequentially deposited in the trenches 31 and over the top surface of the insulator layer 20 , and can be planarized to remove portions of the metallic fill material layer and the metallic layer from above a horizontal plane including the top surface of the insulator layer 20 .
- the planarization of the metallic fill material layer and the metallic layer can be performed, for example, by chemical mechanical planarization (CMP).
- CMP chemical mechanical planarization
- Remaining portions of the at least one conductive material constitute the buried electrodes 30 .
- the remaining portions of the metallic layer constitute metallic liners 32 , and the remaining portions of the metallic fill material layer constitute conductive fill material portions 34 .
- Each buried electrode 30 can include a metallic liner 32 and a conductive fill material portion 34 .
- the metallic liner 32 and the conductive fill material portion 34 in each buried electrode 32 can have top surfaces that are coplanar with the top surface of the insulator layer 20 .
- Each buried electrode 30 is embedded in the insulator layer 20 .
- the metallic liners 32 can include a metallic material that promotes adhesion to the surfaces of the insulator layer 20 .
- the metallic liners 32 can include a metallic nitride such as TiN, TaN, and WN.
- the thickness of the metallic liners 32 can be in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed.
- the conductive fill material portions 34 can include any metallic material.
- the conductive fill material portions 34 can include an elemental metal or an intermetallic alloy such as Au, Ag, Ti, Ta, Al, Cu, Pt, and alloys thereof.
- Each buried electrode 30 includes a pair of sidewalls that extends along the lengthwise direction of the buried electrode 30 .
- the lengthwise direction is a horizontal direction that is perpendicular to the spacing between neighboring buried electrodes 30 .
- a metallic liner 32 in each buried electrode 30 contacts sidewalls and a recessed surface of the insulator layer 20 .
- a conductive fill material portion 34 in each buried electrode 30 has a top surface that is coplanar with the top surface of the insulator layer 20 .
- a graphene layer 40 is placed on the top surface of the insulator layer 20 .
- the graphene layer 40 can be provided by any known method in the art.
- the graphene layer 40 can be provided by exfoliation, sonication of graphite, reduction of graphite oxide, or epitaxial growth on a single crystalline substrate and separation.
- the graphene layer 40 thus provided is subsequently disposed on the top surface of the insulator layer 20 .
- the graphene layer 40 as provided is doped with electrical dopants at a dopant concentration in a range from 1.0 ⁇ 10 14 /m 2 to 1.0 ⁇ 10 18 /m 2 .
- the conductivity type of the electrical dopants in the graphene layer 40 is herein referred to as a first conductivity type, which can be p-type or n-type.
- the graphene layer 40 as a doping of the first conductivity type.
- the graphene layer 40 can be a single layer of a graphene sheet. The graphene layer 40 can contact the entirety of the top surfaces of the buried electrodes 30 and the top surface of the insulator layer 20 .
- first upper electrodes 50 and second upper electrodes 60 are formed on the graphene layer 40 .
- the first upper electrodes 50 are formed within areas of the buried electrodes 30
- the second upper electrodes 60 are formed outside areas of the buried electrodes 30 .
- Each first upper electrode 50 has a pair of sidewalls that overlie a top surface of a buried electrode 30 .
- an element “overlies” a surface if the entirety of the element is located above a two-dimensional plane including the surface and if the entirety of the element is present within an area defined by the periphery of the surface.
- Each second upper electrode 60 does not overlie, and is laterally offset from sidewalls of, the buried electrodes. In other words, the areas of the second upper electrodes 60 do not overly with any area of the buried electrodes 60 .
- the first upper electrodes 50 and the second upper electrodes 60 include a metallic material, which can be, for example, Au, Ag, Ti, Ta, Al, Cu, Pt, and alloys thereof.
- the first upper electrodes 50 and the second upper electrodes 60 can be simultaneously formed by a masked directional deposition of a conductive material.
- a “masked directional deposition” refers to a directional deposition of a material employing a patterned mask. Methods for the directional deposition of a conductive material include vacuum evaporation, sputtering, molecular beam deposition, or any other deposition method that provides a directional path for a beam of conductive molecules or conductive particles.
- the mask employed to block the directional path of the beam determines the areas in which the first upper electrodes 50 and the second upper electrodes 60 are formed.
- the mask can have openings in areas corresponding to the areas of the first upper electrodes 50 and the second upper electrodes 60 .
- the first upper electrodes 50 and the second upper electrodes 60 can include different conductive materials.
- the first upper electrodes 50 and the second upper electrodes 60 can be formed by separate masked deposition processes.
- the first upper electrodes 50 and the second upper electrodes 60 can be formed by deposition of a metallic material and subsequent patterning of the metallic material.
- an etch chemistry employed to pattern the deposited metallic material can be selective to carbon in order to avoid damaging the graphene layer 40 .
- Each first upper electrode 50 can have a pair of parallel sidewalls separated by a first width w 1 , i.e., can have a uniform width that is the same as the first width w 1 .
- the first width w 1 can be in a range from 25 nm to 1,000 nm, although lesser and greater first widths can also be employed.
- Each second upper electrode 60 can have a pair of sidewalls separated by a second width w 2 , i.e., can have a uniform width that is the same as the second width w 2 .
- the second width w 2 can be in a range from 25 nm to 1,000 nm, although lesser and greater second widths can also be employed.
- the parallel sidewalls of the first upper electrodes 50 can extend along the lengthwise direction, i.e., the horizontal direction along which the buried electrodes 30 laterally extend.
- the parallel sidewalls of the second upper electrodes 60 can extend along the lengthwise direction.
- a plurality of first upper electrodes 50 and a plurality of second upper electrodes 60 can be interlaced to provide an alternating arrangement of first and second upper electrodes ( 50 , 60 ) along a horizontal direction.
- the first upper electrodes 50 and the second upper electrodes 60 can alternate along the horizontal direction that is perpendicular to the lengthwise direction.
- a vertical plane including a sidewall of a buried electrode 30 can exist between each neighboring pair of a first upper electrode 50 and a second upper electrode 60 .
- the parallel sidewalls of the first and second upper electrodes ( 50 , 60 ) can be perpendicular to spacings between neighboring pairs of a first upper electrode 50 and a second upper electrode 60 .
- various contact structures are formed on the buried electrodes 30 , the first upper electrodes 50 , and the second upper electrodes 60 .
- the various contact structures include buried electrode contact structures 38 that are formed directly on the buried electrodes 30 , first electrode contact structures 58 that are formed directly on first upper electrodes 50 , and second electrode contact structures 68 that are formed directly on second upper electrodes 60 .
- Holes 37 can be made through the graphene layer 40 to prevent electrical shorts between the buried electrode contact structures 38 and the graphene layer 40 .
- the various contact structures ( 38 , 58 , 68 ) can be solder balls, patterned metallic pads, or contact via structures formed within a dielectric material layer that is deposited over the first and second upper electrodes ( 50 , 60 ) and the graphene layer 40 .
- the electrical wiring can include buried-electrode-side electrical wiring 39 that is electrically connected (i.e., electrically shorted) to the buried electrodes 30 through the buried electrode contact structures 38 , first-electrode-side electrical wiring 59 that is electrically connected to the first upper electrodes 50 through the first electrode contact structures 58 , and second-electrode-side electrical wiring 69 that is electrically connected to the second upper electrodes 60 through the second electrode contact structures 68 .
- the bias circuitry is configured to electrically bias the buried electrodes 30 relative to the first upper electrodes 50 or relative to the second upper electrodes 60 .
- the node relative to which an electrical bias voltage V B is applied to the buried electrodes 30 is herein referred to as a reference node.
- the reference node may be electrically grounded.
- Application of the electrical bias voltage V B to the buried electrodes 30 can be performed by a battery or any other constant voltage source known in the art.
- Charge carriers are formed in regions of the graphene layer 40 that overlie the buried electrodes by applying an electrical bias to the buried electrodes.
- the polarity and the magnitude of the electrical bias voltage V B can be selected such that minority charge carriers are provided in regions of the graphene layer 40 that overlie the buried electrodes 30 .
- the induced charge carriers have a conductivity type that is the opposite of the conductivity type of the dopants in the graphene layer 40 as provided on the insulator layer 20 prior to application of the electrical bias.
- the graphene layer 40 is doped with dopants of the first conductivity type, and thus, predominant charge carriers in the graphene layer 40 are charge carriers of the first conductivity type. If the first conductivity type is p-type, the majority charge carriers in the graphene layer 40 are p-type charge carriers, i.e., holes, and if the first conductivity type is n-type, the majority charge carriers in the graphene layer 40 are n-type charge carriers, i.e., electrons.
- the conductivity type that is the opposite of the first conductivity type is herein referred to as a second conductivity type. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa.
- the minority charge carriers provided in regions of the graphene layer 40 that overlie the buried electrodes 30 are holes if the graphene layer 40 as provided at the step of FIG. 3 is n-doped, or electrons if the graphene layer 40 as provided at the step of FIG. 3 is p-doped.
- P-n junctions 41 are formed within the graphene layer 40 by the application of the electrical bias voltage V B to the buried electrodes 30 . Each p-n junction 41 does not overlie any of the buried electrodes 30 . Each p-n junction 41 is laterally offset from a sidewall of a most proximate buried electrode among the buried electrodes 30 .
- a depletion region is formed around each p-n junction 40 , in which free charge carriers are not present and electrical field is present. Photogeneration of a pair of an electron and a hole occurs upon illumination of the graphene layer 40 . If the photogeneration of the electron-hole pair occurs in regions in which the electrical field is non-zero, the electron and the hole are separated without recombination. One of the electron and the hole is pulled toward a most proximate first upper electrode 50 , and the other of the electron and the hole is puller toward a most proximate second upper electrode 60 . The direction of the electrical field in the depletion region determines the direction along which the electron or the hole is transported.
- a measurement circuitry is provided to measure the electrical current or the electrical voltage across the first upper electrodes 50 and the second upper electrodes 60 .
- the measurement circuitry can be configured to measure an electrical current between, or an electrical voltage across, the first upper electrodes 50 and the second upper electrodes 60 .
- a plurality of first upper electrodes 50 can be electrically shorted to provide a first node, and a plurality of second upper electrodes 60 can be electrically shorted to provide a second node.
- Any measurement circuitry configured to measure an electrical current between the first node and the second node may be employed.
- the measurement circuitry can include a series connection of an ammeter and a load (such as a resistor R) as illustrated in FIG. 5 .
- Any of the first node and the second node can be the reference node, which may be electrically shorted.
- the measurement circuitry can include a voltmeter.
- the measurement circuitry can be configured to measure the open circuit voltage as illustrated in FIG. 6 , or a finite electrical load (not shown) such as a resistor may be added across the first node and the second node. Any of the first node and the second node can be the reference node, which may be electrically shorted.
- the magnitude of the bias voltage across the buried electrodes 30 and the reference node can be selected such that the lateral offset of p-n junctions 41 from a most proximate sidewall of the buried electrodes 30 can be in a range of 3 nm to 30 nm.
- An electrical bias voltage in a range from 0.5 V to 5 V can be employed, although lesser and greater electrical bias voltages can also be employed.
- the first upper electrodes 50 and the second upper electrodes 60 are geometrically arranged to minimize travel distances for charge carriers generated by photons. Further, the photodetector utilizes both photovoltaic effects and photo-thermo-electric (PTE) effects to enhance the photoresponse of a graphene-based photodetector.
- PTE photo-thermo-electric
- Charge carriers generated at the p-n junctions 41 are collected by the first upper electrodes 50 and the second upper electrodes 60 , and are subsequently measured by a current measurement device or a voltage measurement device.
- Multiple p-n junctions 41 are formed in the graphene layer 40 such that the p-n junctions 41 are located within multiple pair of metallic fingers of different types, i.e., metallic fingers of a first type that include the first upper electrodes 50 and metallic fingers of a second type that include the second upper electrodes 60 .
- the response of the photodetector of the present invention is due to the photovoltaic effect at the p-n junctions 41 in the graphene layer 40 , the photo-thermo-electric effect at the material junctions between each first upper electrode 50 and an underlying region of the graphene layer 40 including charge carriers of the second conductivity type (which are induced by the electrical bias applied to the buried electrodes 30 ), and the photo-thermo-electric effect at the material junctions between each second upper electrode 60 and an underlying region of the graphene layer 40 including charge carriers of the first conductivity type (i.e., the majority charge carriers).
- the three effects result in electrical currents that flow along a same direction, thereby proving a greater photocurrent than a component of the electrical current due to the photovoltaic effect only.
- the location of the p-n junctions 41 can be optimized by adjusting the magnitude of electrical bias applied to the buried electrodes 50 .
- the lengths of the first and second upper electrodes ( 50 , 60 ) and the buried electrodes 30 can also be optimized to enhance the photoresponse of the device.
- the device of the present invention can be integrated into standard semiconductor manufacturing schemes to provide low cost electromagnetic radiation detectors.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Light Receiving Elements (AREA)
- Manufacturing & Machinery (AREA)
Abstract
Description
- The present invention relates to an optoelectronic device, and particularly to a photodetector employing a sheet of graphene and methods of manufacturing and operating the same.
- Two-dimensional carbon lattice structures include sp2-bonded carbon atoms that are densely packed in a hexagonal lattice structure. If the two-dimensional carbon lattice structure is topologically planar, the two-dimensional carbon lattice structure constitutes a graphene layer. A graphene layer absorbs and emits light across the entire range of the electromagnetic spectrum, and sustains high electrical current densities and extreme temperatures. Despite the superior performance potential of a graphene relative to silicon and group III-V semiconductor compounds in terms of such properties, formation of a compact optoelectronic device based on a graphene is a significant challenge because coupling between electromagnetic radiation and charge carriers of the graphene layer is relatively weak and because the charge carrier lifetime in a graphene layer is relatively short.
- A photodetector based on a graphene layer can provide high efficiency by geometrically arranging a plurality of electrodes to minimize travel distances for charge carriers generated by photons. The photodetector utilizes both photovoltaic effects and photo-thermo-electric (PTE) effects to enhance the photoresponse of a graphene-based photodetector.
- A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type is formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.
- Multiple p-n junctions are formed in a graphene layer such that the p-n junctions are located within multiple pairs of metallic fingers of different types. The response of the photodetector of the present invention is due to the photovoltaic and photothermoelectric effect at the p-n junctions in the graphene layer. These two effects produces a photocurrent in the same direction. The three effects result in electrical currents that flow along a same direction, thereby proving a greater photocurrent than a component of the electrical current due to the photovoltaic effect only. The location of the p-n junctions can be optimized by adjusting the magnitude of electrical bias applied to the buried electrodes. The lengths of the first and second upper electrodes and the buried electrodes can also be optimized to enhance the photoresponse of the device. Further, the device of the present invention can be integrated into standard semiconductor manufacturing schemes to provide low cost electromagnetic radiation detectors.
- According to an aspect of the present invention, an electromagnetic radiation detector is provided, which includes at least one buried electrode embedded in an insulator layer, a graphene layer overlying the insulator layer, and at least one first upper electrode. Each of the at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of the at least one buried electrode. The electromagnetic radiation detector further includes at least one second upper electrode that does not overlie, and is laterally offset from sidewalls of, the at least one buried electrode. In addition, a measurement circuitry is configured to measure an electrical current between, or an electrical voltage across, the at least one first upper electrode and the at least one second upper electrode.
- According to another aspect of the present invention, a method of forming an electromagnetic radiation detector is provided. At least one buried electrode is formed in an insulator layer. A graphene layer is formed over the insulator layer. At least one first upper electrode is formed. Each of the at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of the at least one buried electrode. At least one second upper electrode is formed. The at least one second upper electrode does not overlie, and is laterally offset from sidewalls of, the at least one buried electrode. A measurement circuitry is formed, which is configured to measure an electrical current between, or an electrical voltage across, the at least one first upper electrode and the at least one second upper electrode.
-
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of trenches in an insulator layer according to an embodiment of the present invention. -
FIG. 2 is a vertical cross-sectional view of the exemplary structure after formation of buried electrodes according to an embodiment of the present invention. -
FIG. 3 is a vertical cross-sectional view of the exemplary structure after placement of a graphene layer on the top surface of the insulator layer according to an embodiment of the present invention. -
FIG. 4 is a vertical cross-sectional view of the exemplary structure after forming of first upper electrodes and second upper electrodes according to an embodiment of the present invention. -
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement circuitry according to an embodiment of the present invention. -
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement circuitry according to an embodiment of the present invention. - As stated above, the present invention relates to a photodetector employing a sheet of graphene and methods of manufacturing and operating the same. Aspects of the present invention are now described in detail with accompanying figures. It is noted that like reference numerals refer to like elements across different embodiments. As used herein, ordinals such as “first” and “second” are employed merely to distinguish similar elements, and different ordinals may be employed to designate a same element in the specification and/or claims.
- Referring to
FIG. 1 , an exemplary structure according to an embodiment of the present invention includes asubstrate 8, which includes a stack of ahandle substrate 10 and aninsulator layer 20. Thehandle substrate 10 can include a semiconductor material, a dielectric material, or a conductive material, and provides mechanical support to theinsulator layer 20 and the structures to be formed thereupon. Theinsulator layer 20 includes a dielectric material such as silicon oxide, silicon nitride, or another dielectric material. The thickness of theinsulator layer 20 can be in a range from 100 nm to 1,000 nm, although lesser and greater thicknesses can also be employed. -
Trenches 31 are formed in theinsulator layer 20, for example, by application of aphotoresist layer 27, formation of line-shaped openings within thephotoresist layer 27, and transfer of the pattern into theinsulator layer 20 by an etch that employs thephotoresist layer 27 as an etch mask. As used herein, a “line-shaped opening” refers to an opening defined by a periphery including a pair of lengthwise edges that are parallel to each other. As used herein, a “lengthwise edge” refers to an edge that is parallel to a longest edge of a shape. The etch can be an anisotropic etch such as a reactive ion etch, or can be an isotropic etch such as a wet etch. In one embodiment, the etch can be an anisotropic etch. The depth of thetrenches 31 can be in a range from 30 nm to 1,000 nm, although lesser and greater depths can also be employed. In one embodiment, the peripheries of thetrenches 31 coincide with the peripheries of the openings in thephotoresist layer 27. - Each
trench 31 can have a pair of sidewalls that are laterally spaced by a width, which is herein referred to as a third width w3. The third width w3 can be in a range from 50 nm to 5,000 nm, although lesser and greater third widths can also be employed. The distance between neighboringtrenches 31 can be in a range from 50 nm to 2,000 nm, although lesser and greater distances can also be employed. The horizontal direction along which the lengthwise sidewalls of thetrenches 31 extend is herein referred to as a lengthwise direction of thetrenches 31. Thephotoresist layer 27 is subsequently removed, for example, by ashing. - Referring to
FIG. 2 , buriedelectrodes 30 are formed by filling thetrenches 31 with at least one conductive material and by removing portions of the at least one conductive material from above the horizontal plane including the top surface of theinsulator layer 20. For example, a metallic layer and a metallic fill material layer can be sequentially deposited in thetrenches 31 and over the top surface of theinsulator layer 20, and can be planarized to remove portions of the metallic fill material layer and the metallic layer from above a horizontal plane including the top surface of theinsulator layer 20. - The planarization of the metallic fill material layer and the metallic layer can be performed, for example, by chemical mechanical planarization (CMP). Remaining portions of the at least one conductive material constitute the buried
electrodes 30. The remaining portions of the metallic layer constitutemetallic liners 32, and the remaining portions of the metallic fill material layer constitute conductivefill material portions 34. Each buriedelectrode 30 can include ametallic liner 32 and a conductivefill material portion 34. Themetallic liner 32 and the conductivefill material portion 34 in each buriedelectrode 32 can have top surfaces that are coplanar with the top surface of theinsulator layer 20. Each buriedelectrode 30 is embedded in theinsulator layer 20. - The
metallic liners 32 can include a metallic material that promotes adhesion to the surfaces of theinsulator layer 20. For example, themetallic liners 32 can include a metallic nitride such as TiN, TaN, and WN. The thickness of themetallic liners 32 can be in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed. The conductivefill material portions 34 can include any metallic material. For example, the conductivefill material portions 34 can include an elemental metal or an intermetallic alloy such as Au, Ag, Ti, Ta, Al, Cu, Pt, and alloys thereof. - Each buried
electrode 30 includes a pair of sidewalls that extends along the lengthwise direction of the buriedelectrode 30. The lengthwise direction is a horizontal direction that is perpendicular to the spacing between neighboring buriedelectrodes 30. Ametallic liner 32 in each buriedelectrode 30 contacts sidewalls and a recessed surface of theinsulator layer 20. A conductivefill material portion 34 in each buriedelectrode 30 has a top surface that is coplanar with the top surface of theinsulator layer 20. - Referring to
FIG. 3 , agraphene layer 40 is placed on the top surface of theinsulator layer 20. Thegraphene layer 40 can be provided by any known method in the art. For example, thegraphene layer 40 can be provided by exfoliation, sonication of graphite, reduction of graphite oxide, or epitaxial growth on a single crystalline substrate and separation. Thegraphene layer 40 thus provided is subsequently disposed on the top surface of theinsulator layer 20. - In one embodiment, the
graphene layer 40 as provided is doped with electrical dopants at a dopant concentration in a range from 1.0×1014/m2 to 1.0×1018/m2. The conductivity type of the electrical dopants in thegraphene layer 40 is herein referred to as a first conductivity type, which can be p-type or n-type. Thus, thegraphene layer 40 as a doping of the first conductivity type. Thegraphene layer 40 can be a single layer of a graphene sheet. Thegraphene layer 40 can contact the entirety of the top surfaces of the buriedelectrodes 30 and the top surface of theinsulator layer 20. - Referring to
FIG. 4 , firstupper electrodes 50 and secondupper electrodes 60 are formed on thegraphene layer 40. The firstupper electrodes 50 are formed within areas of the buriedelectrodes 30, and the secondupper electrodes 60 are formed outside areas of the buriedelectrodes 30. Each firstupper electrode 50 has a pair of sidewalls that overlie a top surface of a buriedelectrode 30. As used herein, an element “overlies” a surface if the entirety of the element is located above a two-dimensional plane including the surface and if the entirety of the element is present within an area defined by the periphery of the surface. Each secondupper electrode 60 does not overlie, and is laterally offset from sidewalls of, the buried electrodes. In other words, the areas of the secondupper electrodes 60 do not overly with any area of the buriedelectrodes 60. - The first
upper electrodes 50 and the secondupper electrodes 60 include a metallic material, which can be, for example, Au, Ag, Ti, Ta, Al, Cu, Pt, and alloys thereof. The firstupper electrodes 50 and the secondupper electrodes 60 can be simultaneously formed by a masked directional deposition of a conductive material. As used herein, a “masked directional deposition” refers to a directional deposition of a material employing a patterned mask. Methods for the directional deposition of a conductive material include vacuum evaporation, sputtering, molecular beam deposition, or any other deposition method that provides a directional path for a beam of conductive molecules or conductive particles. The mask employed to block the directional path of the beam determines the areas in which the firstupper electrodes 50 and the secondupper electrodes 60 are formed. For example, the mask can have openings in areas corresponding to the areas of the firstupper electrodes 50 and the secondupper electrodes 60. - In one embodiment, the first
upper electrodes 50 and the secondupper electrodes 60 can include different conductive materials. In this case, the firstupper electrodes 50 and the secondupper electrodes 60 can be formed by separate masked deposition processes. - Alternately, the first
upper electrodes 50 and the secondupper electrodes 60 can be formed by deposition of a metallic material and subsequent patterning of the metallic material. In this case, an etch chemistry employed to pattern the deposited metallic material can be selective to carbon in order to avoid damaging thegraphene layer 40. - Each first
upper electrode 50 can have a pair of parallel sidewalls separated by a first width w1, i.e., can have a uniform width that is the same as the first width w1. The first width w1 can be in a range from 25 nm to 1,000 nm, although lesser and greater first widths can also be employed. Each secondupper electrode 60 can have a pair of sidewalls separated by a second width w2, i.e., can have a uniform width that is the same as the second width w2. The second width w2 can be in a range from 25 nm to 1,000 nm, although lesser and greater second widths can also be employed. The parallel sidewalls of the firstupper electrodes 50 can extend along the lengthwise direction, i.e., the horizontal direction along which the buriedelectrodes 30 laterally extend. Likewise, the parallel sidewalls of the secondupper electrodes 60 can extend along the lengthwise direction. - In one embodiment, a plurality of first
upper electrodes 50 and a plurality of secondupper electrodes 60 can be interlaced to provide an alternating arrangement of first and second upper electrodes (50, 60) along a horizontal direction. In other words, the firstupper electrodes 50 and the secondupper electrodes 60 can alternate along the horizontal direction that is perpendicular to the lengthwise direction. In this case, a vertical plane including a sidewall of a buriedelectrode 30 can exist between each neighboring pair of a firstupper electrode 50 and a secondupper electrode 60. The parallel sidewalls of the first and second upper electrodes (50, 60) can be perpendicular to spacings between neighboring pairs of a firstupper electrode 50 and a secondupper electrode 60. - Referring to
FIG. 5 , various contact structures are formed on the buriedelectrodes 30, the firstupper electrodes 50, and the secondupper electrodes 60. The various contact structures include buriedelectrode contact structures 38 that are formed directly on the buriedelectrodes 30, firstelectrode contact structures 58 that are formed directly on firstupper electrodes 50, and secondelectrode contact structures 68 that are formed directly on secondupper electrodes 60.Holes 37 can be made through thegraphene layer 40 to prevent electrical shorts between the buriedelectrode contact structures 38 and thegraphene layer 40. The various contact structures (38, 58, 68) can be solder balls, patterned metallic pads, or contact via structures formed within a dielectric material layer that is deposited over the first and second upper electrodes (50, 60) and thegraphene layer 40. - Electrical wirings are attached to the various contact structures (38, 58, 68) to provide a bias circuitry and a measurement circuitry. The electrical wiring can include buried-electrode-side
electrical wiring 39 that is electrically connected (i.e., electrically shorted) to the buriedelectrodes 30 through the buriedelectrode contact structures 38, first-electrode-sideelectrical wiring 59 that is electrically connected to the firstupper electrodes 50 through the firstelectrode contact structures 58, and second-electrode-sideelectrical wiring 69 that is electrically connected to the secondupper electrodes 60 through the secondelectrode contact structures 68. - The bias circuitry is configured to electrically bias the buried
electrodes 30 relative to the firstupper electrodes 50 or relative to the secondupper electrodes 60. The node relative to which an electrical bias voltage VB is applied to the buriedelectrodes 30 is herein referred to as a reference node. In one embodiment, the reference node may be electrically grounded. Application of the electrical bias voltage VB to the buriedelectrodes 30 can be performed by a battery or any other constant voltage source known in the art. - Charge carriers are formed in regions of the
graphene layer 40 that overlie the buried electrodes by applying an electrical bias to the buried electrodes. Specifically, the polarity and the magnitude of the electrical bias voltage VB can be selected such that minority charge carriers are provided in regions of thegraphene layer 40 that overlie the buriedelectrodes 30. The induced charge carriers have a conductivity type that is the opposite of the conductivity type of the dopants in thegraphene layer 40 as provided on theinsulator layer 20 prior to application of the electrical bias. - As discussed above, the
graphene layer 40 is doped with dopants of the first conductivity type, and thus, predominant charge carriers in thegraphene layer 40 are charge carriers of the first conductivity type. If the first conductivity type is p-type, the majority charge carriers in thegraphene layer 40 are p-type charge carriers, i.e., holes, and if the first conductivity type is n-type, the majority charge carriers in thegraphene layer 40 are n-type charge carriers, i.e., electrons. The conductivity type that is the opposite of the first conductivity type is herein referred to as a second conductivity type. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. Thus, the minority charge carriers provided in regions of thegraphene layer 40 that overlie the buriedelectrodes 30 are holes if thegraphene layer 40 as provided at the step ofFIG. 3 is n-doped, or electrons if thegraphene layer 40 as provided at the step ofFIG. 3 is p-doped. -
P-n junctions 41 are formed within thegraphene layer 40 by the application of the electrical bias voltage VB to the buriedelectrodes 30. Eachp-n junction 41 does not overlie any of the buriedelectrodes 30. Eachp-n junction 41 is laterally offset from a sidewall of a most proximate buried electrode among the buriedelectrodes 30. - A depletion region is formed around each
p-n junction 40, in which free charge carriers are not present and electrical field is present. Photogeneration of a pair of an electron and a hole occurs upon illumination of thegraphene layer 40. If the photogeneration of the electron-hole pair occurs in regions in which the electrical field is non-zero, the electron and the hole are separated without recombination. One of the electron and the hole is pulled toward a most proximate firstupper electrode 50, and the other of the electron and the hole is puller toward a most proximate secondupper electrode 60. The direction of the electrical field in the depletion region determines the direction along which the electron or the hole is transported. - A measurement circuitry is provided to measure the electrical current or the electrical voltage across the first
upper electrodes 50 and the secondupper electrodes 60. The measurement circuitry can be configured to measure an electrical current between, or an electrical voltage across, the firstupper electrodes 50 and the secondupper electrodes 60. A plurality of firstupper electrodes 50 can be electrically shorted to provide a first node, and a plurality of secondupper electrodes 60 can be electrically shorted to provide a second node. Any measurement circuitry configured to measure an electrical current between the first node and the second node may be employed. For example, the measurement circuitry can include a series connection of an ammeter and a load (such as a resistor R) as illustrated inFIG. 5 . Any of the first node and the second node can be the reference node, which may be electrically shorted. - Alternately, the measurement circuitry can include a voltmeter. The measurement circuitry can be configured to measure the open circuit voltage as illustrated in
FIG. 6 , or a finite electrical load (not shown) such as a resistor may be added across the first node and the second node. Any of the first node and the second node can be the reference node, which may be electrically shorted. - The magnitude of the bias voltage across the buried
electrodes 30 and the reference node can be selected such that the lateral offset ofp-n junctions 41 from a most proximate sidewall of the buriedelectrodes 30 can be in a range of 3 nm to 30 nm. An electrical bias voltage in a range from 0.5 V to 5 V can be employed, although lesser and greater electrical bias voltages can also be employed. - The first
upper electrodes 50 and the secondupper electrodes 60 are geometrically arranged to minimize travel distances for charge carriers generated by photons. Further, the photodetector utilizes both photovoltaic effects and photo-thermo-electric (PTE) effects to enhance the photoresponse of a graphene-based photodetector. - Charge carriers generated at the
p-n junctions 41 are collected by the firstupper electrodes 50 and the secondupper electrodes 60, and are subsequently measured by a current measurement device or a voltage measurement device. Multiplep-n junctions 41 are formed in thegraphene layer 40 such that thep-n junctions 41 are located within multiple pair of metallic fingers of different types, i.e., metallic fingers of a first type that include the firstupper electrodes 50 and metallic fingers of a second type that include the secondupper electrodes 60. The response of the photodetector of the present invention is due to the photovoltaic effect at thep-n junctions 41 in thegraphene layer 40, the photo-thermo-electric effect at the material junctions between each firstupper electrode 50 and an underlying region of thegraphene layer 40 including charge carriers of the second conductivity type (which are induced by the electrical bias applied to the buried electrodes 30), and the photo-thermo-electric effect at the material junctions between each secondupper electrode 60 and an underlying region of thegraphene layer 40 including charge carriers of the first conductivity type (i.e., the majority charge carriers). The three effects result in electrical currents that flow along a same direction, thereby proving a greater photocurrent than a component of the electrical current due to the photovoltaic effect only. The location of thep-n junctions 41 can be optimized by adjusting the magnitude of electrical bias applied to the buriedelectrodes 50. The lengths of the first and second upper electrodes (50, 60) and the buriedelectrodes 30 can also be optimized to enhance the photoresponse of the device. Further, the device of the present invention can be integrated into standard semiconductor manufacturing schemes to provide low cost electromagnetic radiation detectors. - While the invention has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Each of the various embodiments of the present invention can be implemented alone, or in combination with any other embodiments of the present invention unless expressly disclosed otherwise or otherwise impossible as would be known to one of ordinary skill in the art. Accordingly, the invention is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the invention and the following claims.
Claims (13)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/891,940 US8901689B1 (en) | 2013-05-10 | 2013-05-10 | Graphene photodetector |
US14/027,322 US8987740B2 (en) | 2013-05-10 | 2013-09-16 | Graphene photodetector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/891,940 US8901689B1 (en) | 2013-05-10 | 2013-05-10 | Graphene photodetector |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/027,322 Continuation US8987740B2 (en) | 2013-05-10 | 2013-09-16 | Graphene photodetector |
Publications (2)
Publication Number | Publication Date |
---|---|
US20140332757A1 true US20140332757A1 (en) | 2014-11-13 |
US8901689B1 US8901689B1 (en) | 2014-12-02 |
Family
ID=51864151
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/891,940 Active US8901689B1 (en) | 2013-05-10 | 2013-05-10 | Graphene photodetector |
US14/027,322 Active US8987740B2 (en) | 2013-05-10 | 2013-09-16 | Graphene photodetector |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/027,322 Active US8987740B2 (en) | 2013-05-10 | 2013-09-16 | Graphene photodetector |
Country Status (1)
Country | Link |
---|---|
US (2) | US8901689B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3070741A1 (en) * | 2015-03-18 | 2016-09-21 | Nokia Technologies OY | An apparatus comprising a sensor arrangement and associated fabrication methods |
US10056513B2 (en) | 2016-02-12 | 2018-08-21 | Nokia Technologies Oy | Apparatus and method of forming an apparatus comprising a two dimensional material |
WO2018223068A1 (en) * | 2017-06-01 | 2018-12-06 | The Regents Of The University Of California | Metallo-graphene nanocomposites and methods for using metallo-graphene nanocomposites for electromagnetic energy conversion |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9202945B2 (en) * | 2011-12-23 | 2015-12-01 | Nokia Technologies Oy | Graphene-based MIM diode and associated methods |
US9812604B2 (en) * | 2014-05-30 | 2017-11-07 | Klaus Y. J. Hsu | Photosensing device with graphene |
US10020300B2 (en) | 2014-12-18 | 2018-07-10 | Agilome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
EP3235010A4 (en) | 2014-12-18 | 2018-08-29 | Agilome, Inc. | Chemically-sensitive field effect transistor |
US9859394B2 (en) | 2014-12-18 | 2018-01-02 | Agilome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
US10006910B2 (en) | 2014-12-18 | 2018-06-26 | Agilome, Inc. | Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same |
US9857328B2 (en) | 2014-12-18 | 2018-01-02 | Agilome, Inc. | Chemically-sensitive field effect transistors, systems and methods for manufacturing and using the same |
US9618474B2 (en) | 2014-12-18 | 2017-04-11 | Edico Genome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
KR102395776B1 (en) | 2015-05-18 | 2022-05-09 | 삼성전자주식회사 | Semiconductor device including two-dimensional material and method of manufacturing the same |
WO2017201081A1 (en) | 2016-05-16 | 2017-11-23 | Agilome, Inc. | Graphene fet devices, systems, and methods of using the same for sequencing nucleic acids |
US10374106B2 (en) | 2017-04-13 | 2019-08-06 | Globalfoundaries Inc. | Integrated graphene detectors with waveguides |
CN108155267B (en) * | 2017-12-08 | 2019-09-13 | 浙江大学 | A kind of photo negative-resistance device based on Schottky-MOS mixed structure |
GB201815847D0 (en) * | 2018-09-28 | 2018-11-14 | Cambridge Entpr Ltd | Photodetector |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5525828A (en) | 1991-10-31 | 1996-06-11 | International Business Machines Corporation | High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields |
NL1010635C2 (en) | 1998-11-23 | 2000-05-24 | Stichting Energie | A method of manufacturing a metallization pattern on a photovoltaic cell. |
US6239422B1 (en) | 1999-03-10 | 2001-05-29 | Trw Inc. | Variable electrode traveling wave metal-semiconductor-metal waveguide photodetector |
US8110883B2 (en) * | 2007-03-12 | 2012-02-07 | Nantero Inc. | Electromagnetic and thermal sensors using carbon nanotubes and methods of making same |
US8053782B2 (en) | 2009-08-24 | 2011-11-08 | International Business Machines Corporation | Single and few-layer graphene based photodetecting devices |
US8969779B2 (en) | 2011-02-11 | 2015-03-03 | Nokia Corporation | Photodetecting structure with photon sensing graphene layer(s) and vertically integrated graphene field effect transistor |
CN103081109B (en) * | 2011-07-22 | 2015-08-05 | 松下电器产业株式会社 | Self-spining device, its driving method and manufacture method thereof |
CN103022347B (en) * | 2011-09-27 | 2016-03-09 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and manufacture method thereof |
-
2013
- 2013-05-10 US US13/891,940 patent/US8901689B1/en active Active
- 2013-09-16 US US14/027,322 patent/US8987740B2/en active Active
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3070741A1 (en) * | 2015-03-18 | 2016-09-21 | Nokia Technologies OY | An apparatus comprising a sensor arrangement and associated fabrication methods |
WO2016146884A1 (en) * | 2015-03-18 | 2016-09-22 | Nokia Technologies Oy | An apparatus comprising a sensor arrangement and associated fabrication methods |
JP2018509768A (en) * | 2015-03-18 | 2018-04-05 | エンベリオン オイEmberion Oy | Device with sensor array and method of manufacturing the same |
US10566425B2 (en) | 2015-03-18 | 2020-02-18 | Emberion Oy | Apparatus comprising a sensor arrangement and associated fabrication methods |
US10056513B2 (en) | 2016-02-12 | 2018-08-21 | Nokia Technologies Oy | Apparatus and method of forming an apparatus comprising a two dimensional material |
WO2018223068A1 (en) * | 2017-06-01 | 2018-12-06 | The Regents Of The University Of California | Metallo-graphene nanocomposites and methods for using metallo-graphene nanocomposites for electromagnetic energy conversion |
US11456392B2 (en) | 2017-06-01 | 2022-09-27 | The Regents Of The University Of California | Metallo-graphene nanocomposites and methods for using metallo-graphene nanocomposites for electromagnetic energy conversion |
Also Published As
Publication number | Publication date |
---|---|
US8901689B1 (en) | 2014-12-02 |
US8987740B2 (en) | 2015-03-24 |
US20140335650A1 (en) | 2014-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8901689B1 (en) | Graphene photodetector | |
US8368159B2 (en) | Photon counting UV-APD | |
EP3518292B1 (en) | Method for manufacturing a photodiode detector | |
US20160035876A1 (en) | Fin end spacer for preventing merger of raised active regions | |
US7235832B2 (en) | Self-aligned rear electrode for diode array element | |
JP6388707B2 (en) | Hybrid all-back contact solar cell and manufacturing method thereof | |
JP6878338B2 (en) | Light receiving device and manufacturing method of light receiving device | |
Wu et al. | Recent advances in processing and characterization of edgeless detectors | |
US20140231951A1 (en) | Silicon photomultiplier and method of manufacturing silicon photomultiplier | |
US9343565B2 (en) | Semiconductor device having a dense trench transistor cell array | |
US20130147003A1 (en) | Photovoltaic device | |
KR101711087B1 (en) | Silicon photomultiplier and method for fabricating the same | |
US9685511B2 (en) | Semiconductor device and method for manufacturing a semiconductor device | |
TWI585982B (en) | Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode | |
US10177258B2 (en) | Semiconductor device comprising a diode and electrostatic discharge protection device | |
US9202829B2 (en) | Light sensors with infrared photocurrent suppression | |
US20100224237A1 (en) | Solar cell with backside contact network | |
CN111584656A (en) | Drift detector and processing method thereof | |
US8569813B2 (en) | Inductive load driving circuit | |
US10361321B2 (en) | Method of forming a contact for a photovoltaic cell | |
KR101768704B1 (en) | photo multiplier and manufacturing method for the same | |
US11152410B2 (en) | Image sensor with reduced capacitance transfer gate | |
Sun et al. | Novel silicon photomultiplier with vertical bulk-Si quenching resistors | |
US20120073634A1 (en) | Solar Cells and Solar Cell Arrays | |
CN117476485A (en) | Test structure, forming method thereof and test method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVOURIS, PHAEDON;LOW, TONY A.;XIA, FENGNIAN;REEL/FRAME:030396/0873 Effective date: 20130423 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |