CN117476485A

CN117476485A - Test structure, forming method thereof and test method

Info

Publication number: CN117476485A
Application number: CN202210868699.8A
Authority: CN
Inventors: 王丙泉; 张斯日古楞; 阎大勇; 王志高; 陈星�
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2022-07-22
Filing date: 2022-07-22
Publication date: 2024-01-30

Abstract

A test structure and a forming method thereof, a test method, the test structure comprises: a test body portion including a first face and a second face facing away from the first face, the test body portion including a substrate having first dopant ions and a deep trench isolation structure extending through the substrate, the substrate including an interconnect region, the deep trench isolation structure including a first deep trench isolation structure for testing, a sidewall of the first deep trench isolation structure being contiguous with a boundary of the interconnect region; a first interconnect structure located on a first side of the test body portion and electrically connected to the substrate of the interconnect region, the first interconnect structure being configured to serve as a first test signal loading terminal; the second interconnection structure is positioned on the second surface of the test main body part, is electrically connected with the first deep groove isolation structure and is used as a second test signal loading end. The invention improves the test accuracy of the test structure.

Description

Test structure, forming method thereof and test method

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a test structure, a forming method thereof and a testing method thereof.

Background

In the semiconductor field, adjacent device regions are typically isolated by deep trench isolation (Deep Trench Isolation, DTI) structures, which are filled with a material for isolation, however, the contact surface between the DTI structure and the film layers in the adjacent device regions is prone to some defects. Particularly in the construction of photosensors.

A photosensor is a device that converts an optical signal into an electrical signal. The working principle is based on the photoelectric effect, which is the effect that electrons of substances absorb photon energy to generate free carrier pairs when light irradiates on certain substances, and current is generated under the action of an electric field, so that optical signals are converted into electrical signals. The photosensors each have an area of pixel (pixel) area for receiving the optical signal and performing photoelectric conversion.

In a single photon avalanche diode (Single Photon Avalanche Diode, SPAD) sensor, a pixel area is usually a plurality of pixel units arranged in an array, each pixel unit is provided with a SPAD device, adjacent SPAD devices are isolated through a DTI structure, materials for optical and electrical isolation are filled in the DTI structure, however, the contact surface of the DTI structure and the pixel units is easy to generate defects, and the optical and electrical performances of the SPAD are affected.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a test structure, a forming method and a testing method thereof, and improves the testing accuracy of the test structure.

To solve the above problems, an embodiment of the present invention provides a test structure, including: a test body portion including a first face and a second face facing away from the first face, the test body portion including a substrate having first dopant ions and a deep trench isolation structure extending through the substrate, the substrate including an interconnect region, the deep trench isolation structure including a first deep trench isolation structure for testing, a sidewall of the first deep trench isolation structure being contiguous with a boundary of the interconnect region; a first interconnect structure located on a first side of the test body portion and electrically connected to the substrate of the interconnect region, the first interconnect structure being configured to serve as a first test signal loading terminal; the second interconnection structure is positioned on the second surface of the test main body part, is electrically connected with the first deep groove isolation structure and is used as a second test signal loading end.

Correspondingly, the embodiment of the invention also provides a method for forming the test structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with first doping ions, the substrate comprises a first surface and a second surface which is away from the first surface, and the substrate comprises an interconnection area along the direction parallel to the surface of the substrate; forming a first dielectric layer on a first side of the substrate and a first interconnection structure in the first dielectric layer, wherein the first interconnection structure is electrically connected with the substrate of the interconnection area and is used as a first test signal loading end; forming a deep trench isolation structure penetrating through the substrate in the substrate from the second face of the substrate, wherein the deep trench isolation structure comprises a first deep trench isolation structure used for testing, and the side wall of the first deep trench isolation structure is adjacent to the boundary of the interconnection area; after the deep trench isolation structure is formed, a second dielectric layer and a second interconnection structure are formed on the second surface of the substrate, wherein the second interconnection structure is electrically connected with the first deep trench isolation structure and is used as a second test signal loading end.

Correspondingly, the embodiment of the invention also provides a testing method, which comprises the following steps: providing the test structure provided by the embodiment of the invention; loading corresponding test signals to the first test signal loading end and the second test signal loading end, wherein the test signals are used for enabling the first interconnection structure, the substrate, the first deep groove isolation structure and the second interconnection structure to form a test path; acquiring corresponding capacitance values of the test path under different test signals; and obtaining the electrical thickness and the charge distribution of the corresponding side wall charge layer of the first deep groove isolation structure according to the capacitance value.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the test structure provided by the embodiment of the invention, the side wall of the first deep groove isolation structure used for testing is adjacent to the boundary of the interconnection area of the substrate, the first interconnection structure used as the first test signal loading end is electrically connected with the substrate of the interconnection area, and the second interconnection structure used as the second test signal loading end is electrically connected with the first deep groove isolation structure, so that the first interconnection structure, the substrate, the first deep groove isolation structure and the second interconnection structure form a test path through the loading of the test signal by the first test signal loading end and the second test signal loading end, the test path is electrically tested to obtain the electrical signal of the test path, and the electrical thickness and the charge distribution condition of a charge layer adsorbed by the side wall of the first deep groove isolation structure in the test path are represented.

Drawings

FIGS. 1 to 2 are schematic structural views of a first embodiment of the test structure of the present invention;

FIG. 3 is a schematic diagram of a second embodiment of a test structure according to the present invention;

FIG. 4 is a schematic diagram of a third embodiment of a test structure according to the present invention;

FIGS. 5 to 11 are schematic structural views corresponding to the steps in the first embodiment of the method for forming a test structure according to the present invention;

FIG. 12 is a schematic diagram of the structure corresponding to each step in the second embodiment of the method for forming a test structure according to the present invention;

FIG. 13 is a schematic diagram showing the structure corresponding to each step in the third embodiment of the method for forming a test structure according to the present invention;

FIG. 14 is a flow chart of steps of an embodiment of the testing method of the present invention.

Detailed Description

As known from the background art, a photoelectric sensor has a pixel area with a certain area for receiving an optical signal, the pixel area generally includes a plurality of sub-pixel areas arranged in an array, in order to obtain a device with better quality, the sub-pixel areas are usually manufactured in a substrate with lower doping concentration, a DTI structure is formed between adjacent sub-pixel areas, under the existing process conditions, due to factors such as plasma electrification required by the process and heterogeneous interface atomic level defects during material deposition, the interface of the processed DTI structure close to the substrate is easy to carry stable positive charges or negative charges, in general, when the DTI structure filling material is silicon oxide, the DTI side wall is positively charged, and when the DTI structure filling material is high-K material, the DTI side wall is negatively charged, wherein the high-K material is a material with K value greater than or equal to 7, for example, hafnium oxide or aluminum oxide. When the charge carriers of the doped ions in the substrate are the same as the charge of the side wall of the DTI structure, the charge carriers of the side wall of the substrate are repelled due to the principle of like polarity repulsion, and correspondingly, the charge carriers with opposite charges are sucked out to the side wall of the substrate, so that concentrated inversion charge accumulation is easily generated at the position of the substrate contacted with the side wall of the DTI structure, and the working performance of the photoelectric sensor is influenced by an inversion layer formed by the concentrated inversion charge; when the charge of the charge carrier of the doped ions in the substrate is opposite to that of the side wall of the DTI structure, the charge carrier of the side wall of the substrate is attracted due to the principle of opposite attraction, and correspondingly, the charge carrier with opposite charge carriers is repelled to the side wall of the substrate, so that the substrate is easy to generate concentrated homotype charge aggregation at the position contacted with the side wall of the DTI structure, and the homotype layer formed by the concentrated homotype charge can influence the working performance of the photoelectric sensor.

In order to detect the distribution of the inversion charges or the homotype charges in the substrate of the photoelectric sensor, a test structure with the same DTI structure and substrate in the photoelectric sensor is formed, and the distribution of the inversion charges or the homotype charges in the substrate of the photoelectric sensor is characterized by testing the test structure.

In the prior art, a scanning capacitance microscope (Scanning Capacitance Microscope, SCM) or a scanning extended resistance microscope (scanning spreading resistance microscopy, SSRM) is generally used for detecting the morphology, the size, the characteristics and the like of an ion implantation distribution area of a cross section of a structure, however, the SCM and the SSRM are used for testing, the cross section of a device is required to be tested, therefore, the test structure is required to be cut to obtain the test structure with an exposed cross section, sample preparation errors are easy to cause, the test structure is damaged, process waste is also caused, meanwhile, when a probe is arranged on the cross section, the requirement on the quality and the position of the probe is high, the error of manual operation is also easy to cause, and after the probe is repeatedly used, abrasion or pollution is also easy to cause testing errors, and the accuracy of the test is affected.

In order to solve the technical problem, an embodiment of the present invention provides a test structure, including: a test body portion including a first face and a second face facing away from the first face, the test body portion including a substrate having first dopant ions and a deep trench isolation structure penetrating through the substrate, the substrate including an interconnect region along a surface direction parallel to the substrate, the deep trench isolation structure including a first deep trench isolation structure for testing, a sidewall of the first deep trench isolation structure being contiguous with a boundary of the interconnect region; a first interconnect structure located on a first side of the test body portion and electrically connected to the substrate of the interconnect region, the first interconnect structure being configured to serve as a first test signal loading terminal; the second interconnection structure is positioned on the second surface of the test main body part, is electrically connected with the first deep groove isolation structure and is used as a second test signal loading end.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 1 to 2 are schematic structural views of a first embodiment of the test structure of the present invention. Wherein fig. 1 is a top view of the test structure of the present invention, and fig. 2 is a cross-sectional view along AA direction of fig. 1.

The test structure comprises: a test body portion 190, the test body portion 190 comprising a first face 160 and a second face 161 facing away from the first face 160, the test body portion 190 comprising a substrate 106 having first dopant ions and a deep trench isolation structure extending through the substrate 106, the substrate 106 comprising an interconnect region 100a in a direction parallel to a surface of the substrate 106, the deep trench isolation structure comprising a first deep trench isolation structure 116 for testing, a sidewall of the first deep trench isolation structure 116 being contiguous with a boundary of the interconnect region 100 a; a first interconnect structure 113 disposed on the first side 160 of the test body 190 and electrically connected to the substrate 106 of the interconnect area 100a, the first interconnect structure 113 being configured to serve as a first test signal loading terminal; and a second interconnection structure 112 located on the second surface 161 of the test body 190, where the second interconnection structure 112 is electrically connected to the first deep trench isolation structure 116, and the second interconnection structure 112 is used as a second test signal loading end.

In the test structure provided in this embodiment, the side wall of the first deep trench isolation structure 116 used for testing is adjacent to the boundary of the interconnection area 100a of the substrate 106, the first interconnection structure 113 used as the first test signal loading end is electrically connected with the substrate 106 of the interconnection area 100a, and the second interconnection structure 112 used as the second test signal loading end is electrically connected with the first deep trench isolation structure 116, so that the first interconnection structure 113, the substrate 106, the first deep trench isolation structure 116 and the second interconnection structure 112 form a test path by loading the test signal through the first test signal loading end and the second test signal loading end, the electrical test is performed on the test path to obtain the electrical signal of the test path, and the electrical thickness and the charge distribution condition of the charge layer adsorbed on the side wall of the first deep trench isolation structure 116 in the test path are characterized, compared with a test structure which is tested by arranging a probe on the cross section of the test structure, the embodiment of the invention avoids the situation that the test structure is damaged due to the fact that the cross section of the test structure is required to be exposed, simultaneously avoids sample preparation errors caused by the fact that the cross section is obtained by cutting the test structure, and also avoids cost waste caused by the fact that the test structure is damaged.

In this embodiment, the test structure is a test structure of an optical device, and the optical device has the same substrate 106 and deep trench isolation structure as the test structure, so that the performance of the optical device can be represented by testing the test structure, and the design and process of the optical device can be adjusted according to the test result of the test structure.

As one example, the optics include a single SPAD sensor. In other embodiments, the optics may also be a charge coupled device (Charge Coupled Device, CCD) image sensor, CMOS image sensor, direct time of flight (Direct Time of Flight, DTOF) sensor, or indirect time of flight (indirect Time of Flight, iTOF) sensor, or the like.

In this embodiment, the substrate 106 provides a process platform for the test structure formation process.

Specifically, the material of the substrate 106 is silicon. In other embodiments, the material of the substrate 106 may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 106 may be a silicon-on-insulator substrate 106 or other types of substrates 106 such as a germanium-on-insulator substrate 106.

In this embodiment, the substrate 106 has a first doped ion, where the doped ion includes an N-type ion or a P-type ion, and the N-type ion includes a P-ion, an As ion, or an Sb ion; the P-type ions include B ions, ga ions, or In ions. As an example, the first dopant ions are P-type ions.

In this embodiment, the interconnection region 100a is a formation region of the first doped region 109 and the second doped region 108.

According to an actual layout design, as an example, in the step of providing the substrate 106, the interconnect region 100a is annular.

In this embodiment, the test structure further includes: a first doped region 109 having a second dopant ion is located in the substrate 106 of the interconnect region 100a and exposed by the first face 160 of the substrate 106, the second dopant ion having a concentration greater than the first dopant ion and a conductivity type of the second dopant ion being the same as the conductivity type of the first dopant ion.

Specifically, the first interconnection structure 113 is electrically connected to the substrate 106 of the interconnection area 100a, and the first doped region 109 located in the substrate 106 of the interconnection area 100a has second doped ions in the first doped region 109, so that current-carrying electrons in the first doped region 109 are increased, and therefore, contact resistance between the first interconnection structure 113 and the substrate 106 of the interconnection area 100a can be reduced, and accordingly, in a process of performing an electrical test on a test structure, a probability that a test result of the test structure is affected is reduced.

In this embodiment, the conductivity type of the second doped ion is the same as that of the first doped ion, so as to achieve a normal function in the optical device, and avoid the occurrence of a PN junction between the substrate 106 and the first doped region 109 due to the different conductivity types of the doped ions, thereby affecting the normal function in the optical device and testing the result in the test structure.

To this end, as an example, the second dopant ions are P-type ions.

In this embodiment, the concentration of the second doping ions is greater than that of the first doping ions, so that the resistance of the first doping region 109 is smaller than that of the substrate 106, and the series resistance of the test path in the test structure is reduced in the subsequent process of electrically testing the test structure, thereby being beneficial to obtaining more accurate test results.

The concentration of the second dopant ion should not be too large or too small. If the concentration of the second doping ions is too small, the conductivity of the first doping region 109 is easily poor, the resistance is high, and in the subsequent process of electrically testing the test structure, the series resistance of the test path in the test structure is increased, so that the test result of the test structure is affected, and a larger test error is caused; if the concentration of the second dopant ions is too high, damage to the substrate 106 is easily caused during the formation process of the first doped region 109, thereby affecting the performance of the test structure. For this purpose, in the present embodiment, the concentration of the second dopant ions is 1E15atoms/cm ² To 1E22atoms/cm ² 。

It should be noted that, along the normal direction of the surface of the substrate 106, the thickness of the first doped region 109 should not be too large or too small. In order to ensure that the first interconnection structure 113 is in good electrical contact with the first doped region 109, the first interconnection structure 113 may extend into a part of the thickness of the first doped region 109, that is, the bottom surface of the first interconnection structure 113 is lower than the top surface of the first doped region 109, so if the thickness of the first doped region 109 is too small, the first interconnection structure 113 is easily brought into contact with the substrate 106, thereby resulting in a larger contact resistance between the first interconnection structure 113 and the first doped region 109, and in the subsequent electrical test of the test structure, the series resistance of the test path in the test structure is increased, thereby affecting the test result of the test structure and causing a larger test error; if the thickness of the first doped region 109 is too large, the first doped region 109 is likely to occupy too many sidewalls of the first deep trench isolation structure 116, which affects the charge adsorption condition of the sidewalls of the first deep trench isolation structure 116, thereby affecting the test result. For this purpose, in the present embodiment, the thickness of the first doped region 109 is 1 nm to 50 nm along the normal direction of the surface of the substrate 106.

In this embodiment, the test structure further includes: a second doped region 108 having a third dopant ion, located in the substrate 106 of the interconnect region 100a and in contact with a surface of the first doped region 109 facing away from the first surface 160, the second doped region 108 being spaced apart from the first deep trench isolation structure 116 in a direction parallel to the surface of the substrate 106, the third dopant ion having a concentration less than the concentration of the first dopant ion and greater than the concentration of the first dopant ion, the third dopant ion having a conductivity type that is the same as the conductivity type of the first dopant ion.

Specifically, since the third doping ions are included in the second doping region 108, the current-carrying electrons in the third doping region 109 are increased, and therefore, in the subsequent electrical testing process of the test structure, the series resistance of the test path can be reduced by the second doping region 108 including the third doping ions, which is beneficial to obtaining a more accurate test result.

In this embodiment, the conductivity type of the third doped ion is the same as that of the first doped ion, so as to achieve a normal function in the optical device, and avoid the occurrence of a PN junction between the substrate 106 and the second doped region 108 due to the different conductivity types of the doped ions, thereby affecting the normal function in the optical device and testing the result in the test structure.

To this end, as an example, the third dopant ion is a P-type ion.

In this embodiment, the concentration of the third doped ion is greater than that of the first doped ion, so that the resistance of the second doped region 108 is smaller than that of the substrate 106, and the series resistance of the test path in the test structure is reduced in the subsequent process of electrically testing the test structure, thereby being beneficial to obtaining a more accurate test result.

In this embodiment, the concentration of the third dopant ion is less than the concentration of the second dopant ion. Specifically, the concentration of the doping ions is affected by the doping depth, the first doping region 109 is located on the first surface 160 of the substrate 106, and the doping depth of the second doping region 108 is greater than the doping depth of the first doping region 109, so that the concentration of the third doping ions is less than the concentration of the second doping ions; meanwhile, the excessive concentration of the third dopant ions easily affects the charge adsorption condition of the sidewall of the first deep trench isolation structure 116, thereby affecting the test result.

The concentration of the third dopant ion should not be too large or too small. If the concentration of the third doped ions is too small, the second doped region 108 is easy to have poor conductive performance and high resistance, and in the subsequent process of electrically testing the test structure, the series resistance of the test path in the test structure is increased, so that the test result of the test structure is affected, and a larger test error is caused; if the concentration of the third dopant ions is too high, the electric charge adsorption property of the sidewall of the first deep trench isolation structure is easily affected, and the size of the second doped region 108 spaced from the first deep trench isolation structure 116 needs to be increased to offset the effect, which correspondingly increases the area of the test structure and reduces the test efficiency. For this purpose, in the present embodiment, the concentration of the third dopant ions is 1E15atoms/cm ² To 1E22atoms/cm ² 。

In particular, the second doped region 108 is preferably not spaced from the first deep trench isolation structure 116 by too large a dimension in a direction parallel to the surface of the substrate 106. If the second doped region 108 is spaced from the first deep trench isolation structure 116 by too large a size, the formation area of the second doped region 108 is easily too small, and the second doped region 108 having the third doped ions cannot have an effect of reducing the series resistance of the test path in the subsequent electrical test of the test structure, thereby affecting the test result. For this purpose, in the present embodiment, the dimension of the second doped region 108 spaced apart from the first deep trench isolation structure 116 along the direction parallel to the surface of the substrate 106 is less than or equal to 1mm.

In this embodiment, the test structure further includes: a first dielectric layer 105 is disposed on a first side 160 of the substrate 106.

The first dielectric layer 105 is used to electrically isolate the first interconnect structure 113.

The material of the first dielectric layer 105 is an insulating material, and the material of the first dielectric layer 105 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the first dielectric layer 105 is silicon oxide.

The first interconnection structure 113 is used as a first test signal loading end, where the first test signal loading end is used to load a corresponding test signal, specifically, the first test signal loading end is used to load a positive voltage or a negative voltage, and the second test signal loading end is used to load a zero potential, so that a voltage difference is formed between the first test signal loading end and the second test signal loading end, and a test path of the test structure is conducted.

In this embodiment, the first interconnect structure 113 is electrically connected to the first doped region 109.

In the process of forming the test structure, in the step of forming the deep trench isolation structure penetrating through the substrate 106 in the substrate 106, the deep trench isolation structure includes a first deep trench isolation structure 116 for testing, where a sidewall of the first deep trench isolation structure 116 is adjacent to a boundary of the interconnect region 100a, that is, a sidewall of the first deep trench isolation structure 116 is in contact with a sidewall of the first doped region 109, and the first interconnect structure 113 is electrically connected to the first doped region 109, so that the first deep trench isolation structure 116, the substrate 106, the second doped region 108, the first doped region 109 and the first interconnect structure 113 form a test path, thereby implementing conduction of the test path of the test structure.

In this embodiment, the first interconnect structure 113 includes: a first conductive plug 103 electrically connected to the substrate 106 of the interconnection region 100 a; one or more first interconnecting lines 100 arranged at intervals in the longitudinal direction are positioned on the surface, facing away from the first surface 160, of the first conductive plugs 103, the first interconnecting lines 100 are electrically connected with the first conductive plugs 103, when the number of layers of the first interconnecting lines 100 is multiple, adjacent layers of the first interconnecting lines 100 are connected through a first interconnecting through hole structure 101, and the first interconnecting line 100, farthest from the first surface 160, of the first interconnecting structures 113 is used as the first test loading end.

In this embodiment, taking the example that the first interconnect structure 113 includes a plurality of layers of first interconnect lines 100 arranged at intervals in the longitudinal direction, for example: when the first interconnect structure 113 includes two layers of the first interconnect lines 100, the first interconnect lines 100 for loading the test signals are corresponding to the second interlayer metal lines (i.e., M2 layers).

In other embodiments, the first interconnect structure 113 may further include a layer of first interconnect lines 100 according to actual process requirements, and the first interconnect lines 100 for loading test signals are first interlayer metal lines (i.e. M1 layer).

In this embodiment, the first conductive plug 103 is used to electrically lead out the substrate 106 of the interconnection area 100a, the first interconnection via structure 101 and the first interconnection line 100 are used to realize electrical connection, and the first interconnection line 100 at the top layer is used to load the first test signal.

In this embodiment, the first interconnect structure 113 is a back-end interconnect structure. The present embodiment utilizes a conventional back-end interconnect structure to load test signals to the second substrate 106 of the first device region and the second device region, which is advantageous for improving process compatibility in forming the test structure.

Specifically, in the semiconductor field, an optical device has a pixel area with a certain area for receiving an optical signal, where the pixel area generally includes a plurality of sub-pixel areas arranged in an array, a device structure such as a photoelectric element is formed in the sub-pixel area, and a deep trench isolation structure is formed between adjacent sub-pixel areas for electrically and optically isolating. For this purpose, in this embodiment, the deep trench isolation structure is used to isolate the optoelectronic element in the substrate 106.

The first deep trench isolation structure 116 includes a conductive layer 114, and an insulating layer 115 between the conductive layer 114 and the substrate 106.

In this embodiment, the material of the conductive layer 114 includes one or more of tungsten, copper, and polysilicon.

Specifically, the second interconnection structure 112 is electrically connected to the conductive layer 114, and the tungsten, copper and polysilicon materials have better conductivity and lower resistivity, so that the series resistance of the test path in the test structure is reduced, thereby being beneficial to obtaining more accurate test results.

In this embodiment, the material of the insulating layer 115 includes silicon oxide or a high-k material, and the silicon oxide or the high-k material are all dielectric materials, so that the deep trench isolation structure can achieve the effect of isolating the optoelectronic element in the substrate 106.

As an example, a high-k material is a material having a k value greater than or equal to 3. For example: tantalum oxide or hafnium oxide.

In this embodiment, the sidewall of the first deep trench isolation structure 116 is adjacent to the boundary of the interconnection area 100a, so that the sidewall of the first deep trench isolation structure 116 contacts with the sidewall of the first doped region 109, and the first deep trench isolation structure 116 and the first doped region 109 can form a test path in the process of performing the electrical test on the test structure.

It should be noted that, according to an actual layout design, as an example, the first deep trench isolation structure 116 is located in an area surrounded by the interconnection area 100a and is surrounded by the interconnection area 100 a.

In this embodiment, the deep trench isolation structure further includes a second deep trench isolation structure 117, where the second deep trench isolation structure 117 surrounds the interconnect region 100a and is adjacent to the boundary of the interconnect region 100a, and the second deep trench isolation structure 117 is used to define the position of the first doped region 109.

Specifically, the second deep trench isolation structure 117 is used to define the formation regions of the first doped region 109 and the second doped region 108, and as an example, the region of the first deep trench isolation structure 116 opposite to the second deep trench isolation structure 117 is the formation region of the first doped region 109 and the second doped region 108.

In this embodiment, the deep trench isolation structure further includes a third deep trench isolation structure 118, where the third deep trench isolation structure 118 surrounds the first deep trench isolation structure 116 and the substrate 106 of the interconnection region 100a, and is spaced apart from the first deep trench isolation structure 116 and the interconnection region 100a along a direction parallel to the surface of the substrate 106, and the third deep trench isolation structure 118 is used for protecting the first deep trench isolation structure 116.

Specifically, the third deep trench isolation structure 118 is configured to protect the first deep trench isolation structure 116, and in a subsequent electrical test process of the test structure, the third deep trench isolation structure 118 can reduce a probability that parasitic capacitance generated by a drift potential in the substrate 106 outside the interconnection area 100a affects a test result of the first deep trench isolation structure 116, thereby improving accuracy of the test result.

In this embodiment, the deep trench isolation structure further includes a fourth deep trench isolation structure 119, which is located in an area surrounded by the first deep trench isolation structure 116 and surrounded by the first deep trench isolation structure 116, and is spaced from the first deep trench isolation structure 116 along a direction parallel to the surface of the substrate 106, where the fourth deep trench isolation structure 119 is used for protecting the first deep trench isolation structure 116.

Specifically, the fourth deep trench isolation structure 119 is configured to protect the first deep trench isolation structure 116, and in a subsequent electrical test process of the test structure, the fourth deep trench isolation structure 119 can reduce a probability that parasitic capacitance generated by a drift potential in an area enclosed by the first deep trench isolation structure 116 affects a test result of the first deep trench isolation structure 116, thereby improving accuracy of the test result.

In this embodiment, the test structure further includes: a second dielectric layer 107 is located on a second side 161 of the substrate 106.

The second dielectric layer 107 is used to electrically isolate the second interconnect structure 112.

The material of the second dielectric layer 107 is an insulating material, and the material of the second dielectric layer 107 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the second dielectric layer 107 is silicon oxide.

In this embodiment, the first interconnection structure 113, the substrate 106, the first deep trench isolation structure 116 and the second interconnection structure 112 form a test path by loading the test signal through the first test signal loading end and the second test signal loading end, the test path is electrically tested to obtain an electrical signal of the test path, and the electrical thickness and the charge distribution condition of the charge layer adsorbed by the side wall of the first deep trench isolation structure 116 in the test path are represented.

The second interconnection structure 112 is used as a second test signal loading end, where the second test signal loading end is used to load a corresponding test signal, specifically, the second test signal loading end is used to load a zero potential, and the first test signal loading end is used to load a positive voltage or a negative voltage, so that a voltage difference is formed between the first test signal loading end and the second test signal loading end, and a test path of the test structure is conducted.

It should be noted that, in this embodiment, the second interconnection structure 112 is electrically connected to the conductive layer 114, and in a subsequent electrical test process of the test structure, the second interconnection structure 112, the first deep trench isolation structure 116, the substrate 106, the second doped region 108, the first doped region 109 and the first interconnection structure 113 form a test path.

In this embodiment, the second interconnect structure 112 includes: a second conductive plug 111 electrically connected to the first deep trench isolation structure 116; and a second interconnection line 110 located on a surface of the second conductive plug 111 facing away from the second surface 161, wherein the second interconnection line 110 is electrically connected to the second conductive plug 111, and the second interconnection line 110 is used as the second test loading end.

In this embodiment, the second conductive plug 111 is used for electrically leading out the first deep trench isolation structure 116, the second conductive plug 111 and the second interconnection line 110 are used for implementing electrical connection, and the second interconnection line 110 is used for loading a second test signal.

In this embodiment, the material of the second conductive plug 111 includes one or more of aluminum, tungsten, and copper.

It should be noted that, the aluminum, tungsten and copper are all conductive materials, the conductivity is higher and the resistivity is lower, so that the series resistance of the test path in the test structure is lower in the subsequent process of electrically testing the test structure, thereby being beneficial to obtaining more accurate test results, and meanwhile, the aluminum, tungsten and copper materials can reduce the probability of optical crosstalk of the photoelectric element in the substrate 106.

In this embodiment, the material of the second interconnect line 110 includes one or more of aluminum, tungsten, and copper.

It should be further noted that the second interconnection line 110 may be electrically connected to other external circuit structures, so as to implement interconnection of the first deep trench isolation structure with an external circuit through the second interconnection line 110.

In this embodiment, the test structure is disposed on the wafer, the wafer includes a dicing street, and the test structure is disposed in the dicing street, so that a process of forming a device product on the wafer can be adopted, and meanwhile, the test structure is formed on the wafer, thereby simplifying a process flow, improving a process efficiency, saving a process cost, and meanwhile, on-line testing can be realized, saving testing time, further saving a process cost, and further being beneficial to guaranteeing consistency of the test structure and the device product.

FIG. 3 is a schematic diagram of a second embodiment of the test structure according to the present invention.

The points of the embodiment of the present invention that are the same as those of the first embodiment are not described herein, and the difference between the embodiment of the present invention and the first embodiment is that:

Referring to fig. 3, the first deep trench isolation structure 516 is annular; the first deep trench isolation structure 516 surrounds the interconnect region 500a.

According to the actual layout design, the side walls of the first deep trench isolation structure 516 include an inner wall 580 and an outer wall 581, and when the electrical thickness and the charge distribution of the charge layer adsorbed by the inner wall 580 of the first deep trench isolation structure 516 in the test path need to be tested, the first deep trench isolation structure 516 surrounds the interconnection area 500a, that is, the inner wall 580 of the first deep trench isolation structure 516 contacts the substrate 519 of the interconnection area 500a.

Fig. 4 is a schematic structural diagram of a third embodiment of the test structure according to the present invention.

referring to fig. 4, the interconnect region 600c includes a first interconnect region 600b, and a second interconnect region 600a surrounding the first interconnect region 600b, and the first deep trench isolation structure 616 is located between the first interconnect region 600b and the second interconnect region 600a and surrounds the first interconnect region 600b.

It should be noted that, according to the actual layout design, the interconnect region 600c includes a first interconnect region 600b and a second interconnect region 600a surrounding the first interconnect region 600b, which provides a process basis for characterizing the electrical thickness and the charge distribution of the charge layer adsorbed on the two sidewalls of the first deep trench isolation structure 616 in the test via.

It should be further noted that, the sidewalls of the first deep trench isolation structure 616 include an inner wall 680 and an outer wall 681, and when it is required to characterize the electrical thickness and the charge distribution of the charge layer absorbed by the inner wall 680 of the first deep trench isolation structure 616 in the test via, the first deep trench isolation structure 616 surrounds the interconnection region 600c, that is, the inner wall 680 of the first deep trench isolation structure 616 contacts the substrate 619 of the interconnection region 600 c; when it is desired to characterize the electrical thickness and charge distribution of the charge layer adsorbed by the outer wall 681 of the first deep trench isolation structure 616 in the test via, the first deep trench isolation structure 616 is located between the first interconnect region 600b and the second interconnect region 600a, and the outer wall 681 of the first deep trench isolation structure 616 is in contact with the substrate 619 of the second interconnect region 600 a. To this end, in order to characterize the electrical thickness and charge distribution of the charge layer adsorbed by the inner wall 680 and the outer wall 681 of the first deep trench isolation structure 616 in the test via, the first deep trench isolation structure 616 is located between the first interconnect region 600b and the second interconnect region 600a and surrounds the first interconnect region 600b.

In this embodiment, the deep trench isolation structure further includes a second deep trench isolation structure 617, where the second deep trench isolation structure 617 surrounds the interconnect region 600c and is adjacent to a boundary of the interconnect region 600c, and the second deep trench isolation structure 617 is used to define a location of the first doped region.

Correspondingly, the embodiment of the invention also provides a method for forming the test structure. Fig. 5 to 11 are schematic structural views corresponding to each step in the first embodiment of the method for forming a test structure according to the present invention.

Referring to fig. 5, a substrate 206 is provided, the substrate 206 having first doping ions, the substrate 206 comprising a first face 260 and a second face 261 facing away from the first face 260, the substrate 206 comprising an interconnect region 200a in a direction parallel to the surface of the substrate 206.

As an example, the test structure is a test structure of an optical device, so that the performance of the optical device can be represented by testing the test structure, and the design and process of the optical device can be adjusted according to the test result of the test structure.

In this embodiment, the substrate 206 provides a process platform for the test structure formation process.

Specifically, the material of the substrate 206 is silicon. In other embodiments, the material of the substrate 206 may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 206 may be a silicon-on-insulator substrate 206 or other types of substrates 206 such as a germanium-on-insulator substrate 206.

In this embodiment, the substrate 206 has a first doped ion, where the doped ion includes an N-type ion or a P-type ion, and the N-type ion includes a P-ion, an As ion, or an Sb ion; the P-type ions include B ions, ga ions, or In ions. As an example, the first dopant ions are P-type ions.

In this embodiment, the interconnection region 200a is used as a formation region for subsequently forming the first doped region and the second doped region.

According to an actual layout design, as an example, in the step of providing the substrate 206, the interconnect region 200a is ring-shaped.

Referring to fig. 6, a first surface 260 of the substrate 206 is first doped, a first doped region 209 having second doping ions is formed in the substrate 206 of the interconnection region 200a, the first doped region 209 is exposed by the first surface 260 of the substrate 206, the second doping ions have a concentration greater than that of the first doping ions, and the second doping ions have a conductivity type identical to that of the first doping ions.

Specifically, in the subsequent step of forming the first interconnect structure, the first interconnect structure may be electrically connected to the substrate 206 of the interconnect region 200a, and the first doped region 209 is formed in the substrate 206 of the interconnect region 200a, so that the contact resistance between the first interconnect structure and the substrate 206 of the interconnect region 200a can be reduced, and accordingly, in the subsequent process of electrically testing the test structure, the probability that the test result of the test structure is affected is reduced.

In this embodiment, the conductivity type of the second doped ion is the same as that of the first doped ion, so as to achieve a normal function in the optical device, and avoid the occurrence of a PN junction between the substrate 206 and the first doped region 209 due to the different conductivity types of the doped ions, thereby affecting the normal function in the optical device and testing the result in the test structure.

To this end, as an example, the second dopant ions are P-type ions.

In this embodiment, the concentration of the second doping ions is greater than that of the first doping ions, so that the resistance of the first doping region 209 is smaller than that of the substrate 206, and the series resistance of the test path in the test structure is reduced in the subsequent electrical test process of the test structure, thereby being beneficial to obtaining more accurate test results.

The concentration of the second dopant ion should not be too large or too small. If the concentration of the second doping ions is too small, the conductivity of the first doping region 209 is easily poor, the resistance is high, and in the subsequent process of electrically testing the test structure, the series resistance of the test path in the test structure is increased, so that the test result of the test structure is affected, and a larger test error is caused; if the concentration of the second dopant ions is too high, damage to the substrate 206 is easily caused during the formation process of the first doped region 209, thereby affecting the performance of the test structure. For this purpose, in the present embodiment, the concentration of the second dopant ions is 1E15atoms/cm ² To 1E22atoms/cm ² 。

It should be noted that, along the normal direction of the surface of the substrate 206, the thickness of the first doped region 209 should not be too large or too small. In order to ensure better electrical contact between the first interconnection structure and the first doped region 209, the first interconnection structure may extend into a part of the thickness of the first doped region 209, that is, the bottom surface of the first interconnection structure is lower than the top surface of the first doped region 209, so if the thickness of the first doped region 209 is too small, the first interconnection structure is easily contacted with the substrate 206, thereby resulting in larger contact resistance between the first interconnection structure and the first doped region 209, and in the subsequent electrical test process of the test structure, the series resistance of the test path in the test structure is increased, thereby affecting the test result of the test structure and causing larger test error; if the thickness of the first doped region 209 is too large, the first doped region 109 is likely to occupy too many sidewalls of the subsequently formed first deep trench isolation structure, which affects the charge adsorption condition of the sidewalls of the first deep trench isolation structure, thereby affecting the test result. For this reason, in the present embodiment, the thickness of the first doped region 209 is 1 nm to 50 nm along the normal direction of the surface of the substrate 206.

In this embodiment, the first doping process performed on the first surface 260 of the substrate 206 includes an ion implantation process.

It should be noted that, during the first doping of the first surface 260 of the substrate 206, the doping amount should not be too large or too small. If the amount of dopant is too large, damage to the substrate 206 is likely to occur, thereby affecting the performance of the test structure; if the doping amount is too small, the thickness of the first doped region 209 is easy to fail to meet the process requirement, and correspondingly, the first interconnection structure is easy to contact with the substrate 206, so that the contact resistance between the first interconnection structure and the first doped region 209 is larger, and in the subsequent process of electrically testing the test structure, the series resistance of a test channel in the test structure is increased, so that the test result of the test structure is influenced, and a larger test error is caused. For this reason, in the present embodiment, the dopant amount is in the range of 1E15atom/cm ³ To 1E22atom/cm ³ 。

It should be further noted that the implantation energy should not be too high or too low during the first doping of the first side 260 of the substrate 206. If the implant energy is too high, damage to the substrate 206 is likely to occur, thereby affecting the performance of the test structure; if the implantation energy is too small, the thickness of the first doped region 209 is easy to be insufficient to meet the process requirement, and correspondingly, the first interconnection structure is easy to be contacted with the substrate 206, so that the contact resistance between the first interconnection structure and the first doped region 209 is larger, and in the subsequent process of electrically testing the test structure, the series resistance of a test channel in the test structure is increased, so that the test result of the test structure is influenced, and a larger test error is caused. For this purpose, in the present embodiment, the implantation energy is 1keV to 50keV.

Referring to fig. 7, after the first doped region 209 is formed, the first face 260 of the substrate 206 is subjected to second doping, a second doped region 208 having third doping ions is formed in the substrate 206 of the interconnection region 200a, the second doped region 208 is in contact with a face of the first doped region 209 facing away from the first face 260, one end of the second doped region 208 is flush with the interconnection region 200a in a direction parallel to a surface of the substrate 206, the other end of the second doped region 208 is recessed inward with respect to the interconnection region 200a, a concentration of the third doping ions is smaller than a concentration of the second doping ions and greater than a concentration of the first doping ions, and a conductivity type of the third doping ions is the same as a conductivity type of the first doping ions.

Specifically, in a subsequent electrical testing process of the test structure, the second doped region 208 with the third doped ions can reduce the series resistance of the test path, thereby being beneficial to obtaining a more accurate test result.

In this embodiment, the conductivity type of the third doped ion is the same as that of the first doped ion, so as to achieve a normal function in the optical device, and avoid the occurrence of a PN junction between the substrate 206 and the second doped region 208 due to the different conductivity types of the doped ions, thereby affecting the normal function in the optical device and testing the result in the test structure.

To this end, as an example, the third dopant ion is a P-type ion.

In this embodiment, the concentration of the third doped ion is greater than that of the first doped ion, so that the resistance of the second doped region 208 is smaller than that of the substrate 206, and the series resistance of the test path in the test structure is reduced in the subsequent electrical test process of the test structure, thereby being beneficial to obtaining a more accurate test result.

In this embodiment, the concentration of the third dopant ion is less than the concentration of the second dopant ion. Specifically, the concentration of the doping ions is affected by the doping depth, the first doping region 209 is located on the first surface 260 of the substrate 206, and the doping depth of the second doping region 208 is greater than the doping depth of the first doping region 209, so that the concentration of the third doping ions is less than the concentration of the second doping ions; meanwhile, the excessive concentration of the third doping ions easily affects the charge adsorption condition of the side wall of the subsequently formed first deep groove isolation structure, so that the test result is affected.

The concentration of the third dopant ion should not be too large or too small. If the concentration of the third doped ions is too small, the second doped region 208 is easy to have poor conductive performance and high resistance, and in the subsequent process of electrically testing the test structure, the series resistance of the test path in the test structure is increased, so that the test result of the test structure is affected, and a larger test error is caused; if the concentration of the third doping ions is too high, the effect is easily caused on the charge adsorption property of the sidewall of the subsequently formed first deep trench isolation structure, and the size of the interval between the second doping region 208 and the first deep trench isolation structure needs to be increased to offset the effect, and accordingly, the area of the test structure is increased, and the test efficiency is reduced. For this purpose, in the present embodiment, the concentration of the third dopant ions is 1E15atoms/cm ² To 1E22atoms/cm ² 。

In this embodiment, a second doped region 208 having third dopant ions is formed in the substrate 206 from a first side 260 of the substrate 206.

In other embodiments, a second doped region may also be formed in the substrate from a second side of the substrate.

In this embodiment, the process of performing the second doping on the first surface 260 of the substrate 206 includes an ion implantation process.

It should be noted that, during the second doping of the first surface 260 of the substrate 206, the doping amount should not be too large or too small. If the dopant amount is too large, the concentration of the third dopant ions is easily caused to be too large, that is, the charge adsorption property of the sidewall of the subsequently formed first deep trench isolation structure is easily affected, and accordingly, the size of the interval between the second doped region 208 and the first deep trench isolation structure needs to be increased to offset the effect, and accordingly, the area of the test structure is increased, and the test efficiency is reduced. If the dopant amount is too small, the thickness of the second doped region 208 may not meet the process requirements, and accordingly, the test structure may be electrically tested laterIn the test process, the series resistance of the test path in the test structure is increased, so that the test result of the test structure is affected, and a larger test error is caused. For this purpose, in this embodiment, the second doping is performed on the first surface 260 of the substrate 206, wherein the doping amount is in the range of 1E15 atoms/cm ³ To 1E22atom/cm ³ 。

It should be noted that the implantation energy should not be too high or too low during the second doping of the first surface 260 of the substrate 206. If the implantation energy is too high, the concentration of the third dopant ions is too high, i.e., the charge adsorption property of the sidewall of the subsequently formed first deep trench isolation structure is easily affected, and accordingly, the size of the second doped region 208 spaced from the first deep trench isolation structure needs to be increased to offset the effect, and accordingly, the area of the test structure is increased, and the test efficiency is reduced; if the implantation energy is too small, the thickness of the second doped region 208 is liable to fail to meet the process requirement, and correspondingly, in the subsequent electrical test process of the test structure, the series resistance of the test path in the test structure is increased, thereby affecting the test result of the test structure and causing a larger test error. For this purpose, in the present embodiment, the implantation energy is 1keV to 50keV.

In this embodiment, the depth of the second doped region 208 in the substrate 206 is greater than the depth of the first doped region 209 in the substrate 206. Specifically, the concentration of the dopant ions is affected by the doping depth, the first doped region 209 is located on the first side 260 of the substrate 206, and the concentration of the third dopant ions is less than the concentration of the second dopant ions, so that the doping depth of the second doped region 208 is greater than the doping depth of the first doped region 209.

In this embodiment, one end of the second doped region 208 is flush with the interconnect region 200a, and the other end of the second doped region 208 is recessed with respect to the interconnect region 200a in a direction parallel to the surface of the substrate 206.

Specifically, the other end of the second doped region 208 is retracted inward relative to the interconnect region 200a, so that the second doped region 208 has reduced influence on the charge layer adsorbed on the sidewall of the subsequently formed first deep trench isolation structure, thereby influencing the test result

Referring to fig. 8, a first dielectric layer 205 and a first interconnect structure 213 in the first dielectric layer 205 are formed on a first side of the substrate 206, the first interconnect structure 213 being electrically connected to the substrate 206 of the interconnect region 200a, the first interconnect structure 213 being for use as a first test signal loading terminal.

The first dielectric layer 205 is used to electrically isolate the first interconnect structure 213.

The material of the first dielectric layer 205 is an insulating material, and the material of the first dielectric layer 205 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the first dielectric layer 205 is silicon oxide.

The first interconnection structure 213 is used as a first test signal loading end, where the first test signal loading end is used to load a corresponding test signal, specifically, the first test signal loading end is used to load a positive voltage or a negative voltage, and a second test signal loading end formed subsequently is used to load a zero potential, so that a voltage difference is formed between the first test signal loading end and the second test signal loading end, and a test path of the test structure is conducted.

In this embodiment, the first interconnect structure 213 is electrically connected to the first doped region 209.

It should be noted that, in the subsequent step of forming a deep trench isolation structure penetrating through the substrate 206 in the substrate 206, the deep trench isolation structure includes a first deep trench isolation structure for testing, where a sidewall of the first deep trench isolation structure is adjacent to a boundary of the interconnection region 200a, that is, the sidewall of the first deep trench isolation structure is in contact with a sidewall of the first doped region 209, and is electrically connected with the first doped region 209 through the first interconnection structure 213, so that the first deep trench isolation structure, the substrate 206, the second doped region 208, the first doped region 209 and the first interconnection structure 213 form a test path, thereby implementing conduction of the test path of the test structure.

In this embodiment, the first interconnect structure 213 includes: a first conductive plug 200 electrically connected to a substrate 206 of the interconnect region 200 a; one or more first interconnecting lines 201 are arranged at intervals in the longitudinal direction and are positioned on the surface, facing away from the first surface, of the first conductive plug 200, the first interconnecting lines 201 are electrically connected with the first conductive plug 200, when the number of layers of the first interconnecting lines 201 is multiple, adjacent layers of the first interconnecting lines 201 are connected through a first interconnecting through hole structure 202, and the first interconnecting line 201, farthest from the first surface, of the first interconnecting structures 213 is used as the first test loading end.

In this embodiment, taking the example that the first interconnect structure 213 includes a plurality of layers of first interconnect lines 201 disposed at intervals in the longitudinal direction, for example: when the first interconnect structure 213 includes two layers of first interconnect lines 201, the first interconnect lines 201 for loading the test signals are corresponding to the second interlayer metal lines (i.e., M2 layers).

In other embodiments, the first interconnect structure 213 may further include a layer of first interconnect lines 201 according to actual process requirements, and the first interconnect lines 201 for loading test signals are first interlayer metal lines (i.e. M1 layer).

In this embodiment, the first conductive plug 200 is used to electrically lead out the substrate 206 of the interconnection area 200a, the first interconnection via structure 202 and the first interconnection line 201 are used to electrically connect, and the first interconnection line 201 at the top layer is used to load the first test signal.

In this embodiment, the first interconnect structure 213 is a back-end interconnect structure. The present embodiment utilizes a conventional back-end interconnect structure to load test signals to substrate 206, which is advantageous for improving process compatibility in forming the test structure.

Referring to fig. 9 to 10, in which fig. 9 is a top view of the test structure, fig. 10 is a cross-sectional view of fig. 9 along BB, a deep trench isolation structure is formed in the substrate 206 from the second side 261 of the substrate 206, penetrating the substrate 206, the deep trench isolation structure including a first deep trench isolation structure 216 for testing, a sidewall of the first deep trench isolation structure 216 being adjacent to a boundary of the interconnect region 200 a.

Specifically, in the semiconductor field, an optical device has a pixel area with a certain area for receiving an optical signal, where the pixel area generally includes a plurality of sub-pixel areas arranged in an array, a device structure such as a photoelectric element is formed in the sub-pixel area, and a deep trench isolation structure is formed between adjacent sub-pixel areas for electrically and optically isolating. For this purpose, in this embodiment, the deep trench isolation structure is used to isolate the optoelectronic element in the substrate 206.

In this embodiment, the step of forming the deep trench isolation structure includes: forming a trench in the substrate 206 from the second side 261 of the substrate 206, the trench penetrating the substrate 206; forming an insulating layer 215 on the side wall of the trench; after the insulating layer 215 is formed, a conductive layer 214 is formed in the remaining space of the trench, and the conductive layer 214 and the insulating layer 215 in the trench form a deep trench isolation structure.

In this embodiment, the material of the conductive layer 214 includes one or more of tungsten, copper, and polysilicon.

Specifically, in the subsequent step of forming the second interconnection structure, the second interconnection structure is electrically connected to the conductive layer 214, and the tungsten, copper and polysilicon materials have better conductive properties and lower resistivity, so that the series resistance of the test path in the test structure is reduced, thereby being beneficial to obtaining more accurate test results.

In this embodiment, the material of the insulating layer 215 includes silicon oxide or a high-k material, and the silicon oxide or the high-k material are all dielectric materials, so that the deep trench isolation structure can achieve the effect of isolating the optoelectronic element in the substrate 206.

In this embodiment, the sidewall of the first deep trench isolation structure 216 is adjacent to the boundary of the interconnection area 200a, so that the sidewall of the first deep trench isolation structure 216 contacts with the sidewall of the first doped region 209, and the first deep trench isolation structure 216 and the first doped region 209 can form a test path in the process of performing the electrical test on the test structure.

It should be noted that, according to an actual layout design, as an example, the first deep trench isolation structure 216 is located in an area surrounded by the interconnection area 200a and is surrounded by the interconnection area 200 a.

In this embodiment, the deep trench isolation structure further includes a second deep trench isolation structure 217 penetrating through the substrate 206, and the second deep trench isolation structure 217 surrounds the interconnect region 200a and is adjacent to the boundary of the interconnect region 200 a.

Specifically, the second deep trench isolation structure 217 is used to define the formation regions of the first doped region 209 and the second doped region 208, and as an example, the region of the first deep trench isolation structure 216 opposite to the second deep trench isolation structure 217 is the formation region of the first doped region 209 and the second doped region 208.

In this embodiment, in the step of forming the deep trench isolation structure, the deep trench isolation structure further includes a third deep trench isolation structure 218 penetrating through the substrate 206, the third deep trench isolation structure 218 surrounds the first deep trench isolation structure 216 and the substrate 206 of the interconnection region 200a, and the third deep trench isolation structure 218 is spaced apart from the first deep trench isolation structure 216 and the interconnection region 200a along a direction parallel to the surface of the substrate 206, and the third deep trench isolation structure 218 is used for protecting the first deep trench isolation structure 216.

Specifically, the third deep trench isolation structure 218 is configured to protect the first deep trench isolation structure 216, and in a subsequent electrical test process of the test structure, the third deep trench isolation structure 218 can reduce a probability that a parasitic capacitance generated by a drift potential in the substrate 206 outside the interconnection area 200a affects a test result of the first deep trench isolation structure 216, thereby improving accuracy of the test result.

It should be noted that, in this embodiment, the deep trench isolation structure further includes a fourth deep trench isolation structure 219 penetrating through the substrate 206, the fourth deep trench isolation structure 219 is located in an area surrounded by the first deep trench isolation structure 216 and is surrounded by the first deep trench isolation structure 216, and along a direction parallel to the surface of the substrate 206, the fourth deep trench isolation structure 219 is spaced from the first deep trench isolation structure 216, and the fourth deep trench isolation structure 219 is used for protecting the first deep trench isolation structure 216.

Specifically, the fourth deep trench isolation structure 219 is configured to protect the first deep trench isolation structure 216, and in a subsequent electrical test process of the test structure, the fourth deep trench isolation structure 219 can reduce a probability that parasitic capacitance generated by a drift potential in a region enclosed by the first deep trench isolation structure 216 affects a test result of the first deep trench isolation structure 216, thereby improving accuracy of the test result.

Referring to fig. 11, after the deep trench isolation structure is formed, a second dielectric layer 207 and a second interconnect structure 212 located in the second dielectric layer 207 are formed on the second side 261 of the substrate, the second interconnect structure 212 is electrically connected with the first deep trench isolation structure 216, and the second interconnect structure 212 is used as a second test signal loading terminal.

The second dielectric layer 207 is used to electrically isolate the second interconnect structure 212.

The material of the second dielectric layer 207 is an insulating material, and the material of the second dielectric layer 207 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the second dielectric layer 207 is silicon oxide.

In this embodiment, the side wall of the first deep trench isolation structure 216 used for testing is adjacent to the boundary of the interconnection area 200a of the substrate, the first interconnection structure 213 used as the first test signal loading end is electrically connected with the substrate of the interconnection area 200a, and the second interconnection structure 212 used as the second test signal loading end is electrically connected with the first deep trench isolation structure 216, so that the first interconnection structure 213, the substrate, the first deep trench isolation structure 216 and the second interconnection structure 212 form a test path through the first test signal loading end and the second test signal loading end, the test path is electrically tested to obtain the electrical signal of the test path, and the electrical thickness and the charge distribution condition of the charge layer adsorbed by the side wall of the first deep trench isolation structure 216 in the test path are characterized.

The second interconnection structure 212 is used as a second test signal loading end, where the second test signal loading end is used to load a corresponding test signal, specifically, the second test signal loading end is used to load a zero potential, and the first test signal loading end is used to load a positive voltage or a negative voltage, so that a voltage difference is formed between the first test signal loading end and the second test signal loading end, and a test path of the test structure is conducted.

It should be noted that, in this embodiment, the second interconnection structure 212 is electrically connected to the conductive layer 214, and in a subsequent electrical test process of the test structure, the second interconnection structure 212, the first deep trench isolation structure 216, the substrate, the second doped region 208, the first doped region 209, and the first interconnection structure 213 form a test path.

In this embodiment, the second interconnect structure 212 includes: a second conductive plug 211 electrically connected to the first deep trench isolation structure 216; and a second interconnection line 210 located on a surface of the second conductive plug 211 opposite to the second surface 261, wherein the second interconnection line 210 is electrically connected to the second conductive plug 211, and the second interconnection line 210 is used as the second test loading end.

In this embodiment, the second conductive plug 211 is used for electrically leading out the first deep trench isolation structure 216, the second conductive plug 211 and the second interconnection line 210 are used for implementing electrical connection, and the second interconnection line 210 is used for loading a second test signal.

In this embodiment, the material of the second conductive plug 211 includes one or more of aluminum, tungsten, and copper.

It should be noted that, aluminum, tungsten and copper are all conductive materials, the conductivity is higher and the resistivity is lower, in the subsequent process of carrying out electrical test on the test structure, the series resistance of the test path in the test structure is lower, so that more accurate test results are advantageously obtained, and meanwhile, the aluminum, tungsten and copper materials can reduce the probability of optical crosstalk of the photoelectric element in the substrate.

In this embodiment, the material of the second interconnect line 210 includes one or more of aluminum, tungsten, and copper.

It should be further noted that the second interconnect line 210 may be electrically connected to other external circuit structures, so as to implement interconnection of the first deep trench isolation structure with an external circuit through the second interconnect line 210.

FIG. 12 is a schematic diagram showing the structure corresponding to each step in the second embodiment of the method for forming a test structure according to the present invention.

referring to fig. 12, in the step of forming the deep trench isolation structure, the first deep trench isolation structure 416 is ring-shaped, and the first deep trench isolation structure 416 surrounds the interconnection region 400a.

According to the actual layout design, the sidewalls of the first deep trench isolation structure 416 are divided into an inner wall 480 and an outer wall 481, and when the electrical thickness and the charge distribution of the charge layer adsorbed by the inner wall 480 of the first deep trench isolation structure 416 in the test via need to be characterized, the first deep trench isolation structure 416 surrounds the interconnection area 400a, that is, the inner wall 480 of the first deep trench isolation structure 416 contacts the substrate 419 of the interconnection area 400a.

FIG. 13 is a schematic diagram showing the structure corresponding to each step in the third embodiment of the method for forming a test structure according to the present invention.

referring to fig. 13, in the step of providing the substrate 319, the interconnect region 300a includes a first interconnect region 300b, and a second interconnect region 300c surrounding the first interconnect region 300b.

Specifically, according to the actual layout design, the interconnect region 300a includes a first interconnect region 300b and a second interconnect region 300c surrounding the first interconnect region 300b, which provides a process basis for subsequent characterization of the electrical thickness and charge distribution of the charge layer adsorbed on the sidewalls of the first deep trench isolation structure 316 in the test via.

With continued reference to fig. 13, in the step of forming the deep trench isolation structure, the first deep trench isolation structure 316 is located between the first interconnect region 300b and the second interconnect region 300c and surrounds the first interconnect region 300b.

It should be noted that, when the electrical thickness and the charge distribution of the charge layer adsorbed on the inner wall of the first deep trench isolation structure 316 in the test path need to be represented, the first deep trench isolation structure 316 surrounds the interconnection area, that is, the inner wall of the first deep trench isolation structure 316 contacts the substrate 319 of the interconnection area; when it is required to characterize the electrical thickness and the charge distribution of the charge layer adsorbed on the outer wall of the first deep trench isolation structure 316 in the test via, the first deep trench isolation structure 316 is located between the first interconnect region 300b and the second interconnect region 300c, and the outer wall of the first deep trench isolation structure 316 is in contact with the substrate 319 of the second interconnect region 300c. To this end, in order to characterize the electrical thickness and charge distribution of the charge layer adsorbed on the inner and outer walls of the first deep trench isolation structure 316 in the test via, the first deep trench isolation structure 316 is located between the first interconnect region 300b and the second interconnect region 300c and surrounds the first interconnect region 300b.

In this embodiment, in the step of forming the deep trench isolation structure, the deep trench isolation structure further includes a second deep trench isolation structure 317 penetrating through the substrate 319, and the second deep trench isolation structure 317 surrounds the interconnect region 300a and is adjacent to a boundary of the interconnect region 300 a.

Specifically, by forming the second deep trench isolation structure 317, a formation region of the first doped region and the second doped region in the second interconnection region 300c is defined.

Correspondingly, the invention further provides a testing method. FIG. 14 is a flow chart of steps of an embodiment of the testing method of the present invention.

In this embodiment, the test method includes the following basic steps:

step S1: providing a test structure of the embodiment of the invention;

step S2: loading corresponding test signals to the first test signal loading end and the second test signal loading end, wherein the test signals are used for enabling the first interconnection structure, the substrate, the first deep groove isolation structure and the second interconnection structure to form a test path;

step S3: acquiring corresponding capacitance values of the test path under different test signals;

step S4: and obtaining the electrical thickness and the charge distribution of the corresponding side wall charge layer of the first deep groove isolation structure according to the capacitance value.

In the test method provided by the embodiment of the invention, the first test signal loading end and the second test signal loading end are used for loading test signals, so that the first interconnection structure, the substrate, the first deep groove isolation structure and the second interconnection structure form a test passage, the test passage is electrically tested, the electrical signals of the test passage are obtained, the electrical thickness and the charge distribution condition of the charge layer adsorbed by the side wall of the first deep groove isolation structure in the test passage are represented, compared with the test structure which is tested by arranging the probe on the cross section of the test structure, the test method provided by the embodiment of the invention avoids the situation that the cross section of the test structure is required to be exposed to damage the test structure, and simultaneously avoids sample preparation errors caused by cutting the test structure, and cost waste caused by damaging the test structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of the embodiments of the present invention is provided with reference to fig. 14.

Referring to fig. 14, step S1 is performed: a test structure of the foregoing inventive embodiment is provided.

The detailed description of the foregoing embodiments of the invention refers to the description of the test structure, and is not repeated herein.

Step S2 is executed: and loading corresponding test signals on the first test signal loading end and the second test signal loading end, wherein the test signals are used for enabling the first interconnection structure, the substrate, the first deep groove isolation structure and the second interconnection structure to form a test path.

Specifically, a first test signal loading end and a second test signal loading end are used for loading test signals, so that a test path is formed by the first interconnection structure, the substrate, the first deep groove isolation structure and the second interconnection structure, the test path is subjected to electrical test, an electrical signal of the test path is obtained, and the electrical thickness and the charge distribution condition of a charge layer adsorbed on the side wall of the first deep groove isolation structure in the test path are represented.

In this embodiment, the step of loading the corresponding test signals on the first test signal loading end and the second test signal loading end includes: and loading zero potential on the second test signal loading end, and enabling the potential of the first test signal loading end to be scanned from negative potential to positive potential or from positive potential to negative potential, so that a voltage difference is formed between the first test signal loading end and the second test signal loading end, and the conduction of a test channel of the test structure is realized.

Step S3 is executed: and acquiring corresponding capacitance values of the test paths under different test signals.

And acquiring a capacitance value of the test path to represent the electrical thickness and the charge distribution condition of the corresponding side wall charge layer of the first deep groove isolation structure.

Step S4 is executed: and obtaining the electrical thickness and the charge distribution of the corresponding side wall charge layer of the first deep groove isolation structure according to the capacitance value.

Under the condition that the charge layer distribution exists on the side wall of the first deep groove isolation structure, the corresponding capacitance value of the test channel under different test signals (the different test signals are different voltage values) is obtained, a first characteristic curve graph of the corresponding capacitance value under different voltage values can be obtained, and according to a second characteristic curve graph of the corresponding capacitance value under different voltage values, where the charge layer does not exist on the side wall of the first deep groove isolation structure, the translation amount of the first characteristic curve graph relative to the second characteristic curve graph can be obtained, the distribution of the charge layers on the side wall of the first deep groove isolation structure is different, and the translation amount is also different, so that the electrical thickness and the charge distribution of the charge layer on the side wall of the first deep groove isolation structure can be calculated in a translation manner.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A test structure, comprising:

a test body portion including a first face and a second face facing away from the first face, the test body portion including a substrate having first dopant ions and a deep trench isolation structure penetrating through the substrate, the substrate including an interconnect region along a surface direction parallel to the substrate, the deep trench isolation structure including a first deep trench isolation structure for testing, a sidewall of the first deep trench isolation structure being contiguous with a boundary of the interconnect region;

a first interconnect structure located on a first side of the test body portion and electrically connected to the substrate of the interconnect region, the first interconnect structure being configured to serve as a first test signal loading terminal;

the second interconnection structure is positioned on the second surface of the test main body part, is electrically connected with the first deep groove isolation structure and is used as a second test signal loading end.

2. The test structure of claim 1, wherein the first deep trench isolation structure is annular;

the first deep trench isolation structure surrounds the interconnect region;

alternatively, the interconnection region comprises a first interconnection region and a second interconnection region surrounding the first interconnection region, and the first deep trench isolation structure is located between the first interconnection region and the second interconnection region and surrounds the first interconnection region;

or the interconnection area is annular, and the first deep groove isolation structure is located in an area surrounded by the interconnection area and surrounded by the interconnection area.

3. The test structure of claim 1, wherein the test structure further comprises: a first doped region having a second dopant ion, located in the substrate of the interconnect region and exposed by the first side of the substrate, the second dopant ion having a concentration greater than the concentration of the first dopant ion, and the second dopant ion having a conductivity type that is the same as the conductivity type of the first dopant ion;

the first interconnect structure is electrically connected with the first doped region.

4. The test structure of claim 3, wherein the first doped region has a thickness of 1 nm to 50 nm along a normal direction of the substrate surface.

5. The test structure of claim 3, wherein a concentration of dopant ions in the first doped region is 1E15atoms/cm ² To 1E22atoms/cm ² 。

6. The test structure of claim 3, wherein the interconnect region comprises a first interconnect region and a second interconnect region surrounding the first interconnect region, the first deep trench isolation structure being located between the first interconnect region and the second interconnect region and surrounding the first interconnect region;

or the interconnection area is annular, and the first deep groove isolation structure is positioned in an area surrounded by the interconnection area and is surrounded by the interconnection area;

the deep trench isolation structure further comprises a second deep trench isolation structure surrounding the interconnection region and adjoining a boundary of the interconnection region, the second deep trench isolation structure being used for defining a position of the first doped region.

7. The test structure of claim 3, wherein the test structure further comprises: the second doped region is positioned in the substrate of the interconnection region and is contacted with the surface of the first doped region, which is opposite to the first surface, the second doped region is spaced from the first deep groove isolation structure along the direction parallel to the surface of the substrate, the concentration of the third doped ions is smaller than that of the first doped ions and larger than that of the first doped ions, and the conductivity type of the third doped ions is the same as that of the first doped ions.

8. The test structure of claim 7, wherein the concentration of the third dopant ions is 1E15atoms/cm ² To 1E22atoms/cm ² 。

9. The test structure of claim 7, wherein the second doped region is spaced from the first deep trench isolation structure by a dimension of less than or equal to 1mm in a direction parallel to the substrate surface.

10. The test structure of any one of claims 1-9, wherein the deep trench isolation structure further comprises a third deep trench isolation structure surrounding the first deep trench isolation structure and the substrate of the interconnect region, the third deep trench isolation structure being spaced apart from the first deep trench isolation structure and the interconnect region in a direction parallel to the substrate surface, the third deep trench isolation structure for protecting the first deep trench isolation structure.

11. The test structure of claim 10, wherein the interconnect region is annular, and the first deep trench isolation structure is located in and surrounded by the interconnect region;

the deep trench isolation structure further comprises a fourth deep trench isolation structure which is located in an area surrounded by the first deep trench isolation structure and surrounded by the first deep trench isolation structure along a direction parallel to the surface of the substrate, the fourth deep trench isolation structure is spaced from the first deep trench isolation structure, and the fourth deep trench isolation structure is used for protecting the first deep trench isolation structure.

12. The test structure of claim 1, wherein the first test signal loading terminal is configured to load a positive voltage or a negative voltage and the second test signal loading terminal is configured to load a zero potential.

13. The test structure of claim 1, wherein the first interconnect structure comprises: a first conductive plug electrically connected to the substrate of the interconnect region; and one or more layers of first interconnection lines are arranged at intervals in the longitudinal direction and are positioned on the surface, opposite to the first surface, of the first conductive plug, the first interconnection lines are electrically connected with the first conductive plug, when the number of layers of the first interconnection lines is multiple, the first interconnection lines of adjacent layers are connected through a first interconnection through hole structure, and the first interconnection line, which is farthest from the first surface, in the first interconnection structure is used as the first test loading end.

14. The test structure of claim 1, wherein the second interconnect structure comprises: the second conductive plug is electrically connected with the first deep groove isolation structure; and the second interconnection line is positioned on the surface of the second conductive plug, which is opposite to the second surface, and is electrically connected with the second conductive plug, and the second interconnection line is used as the second test loading end.

15. The test structure of claim 14, wherein the material of the second conductive plug comprises one or more of aluminum, tungsten, and copper;

the material of the second interconnect line includes one or more of aluminum, tungsten, and copper.

16. The test structure of claim 1, wherein the first deep trench isolation structure comprises a conductive layer, and an insulating layer between the conductive layer and a substrate;

the second interconnect structure is electrically connected to the conductive layer.

17. The test structure of claim 16, wherein the material of the conductive layer comprises one or more of tungsten, copper, and polysilicon;

the material of the insulating layer comprises silicon oxide or a high-k material, wherein the high-k material is a material with a k value of more than or equal to 3.

18. The test structure of claim 1, wherein the test structure is a test structure of an optical device having the same substrate and deep trench isolation structure as the test structure.

19. The test structure of claim 1, wherein the test structure is disposed on a wafer, the wafer including dicing streets, the test structure being located in the dicing streets.

20. A method of forming a test structure, comprising:

providing a substrate, wherein the substrate is provided with first doping ions, the substrate comprises a first surface and a second surface which is away from the first surface, and the substrate comprises an interconnection area along the direction parallel to the surface of the substrate;

forming a first dielectric layer on a first side of the substrate and a first interconnection structure in the first dielectric layer, wherein the first interconnection structure is electrically connected with the substrate of the interconnection area and is used as a first test signal loading end;

forming a deep trench isolation structure penetrating through the substrate in the substrate from the second face of the substrate, wherein the deep trench isolation structure comprises a first deep trench isolation structure used for testing, and the side wall of the first deep trench isolation structure is adjacent to the boundary of the interconnection area;

after the deep trench isolation structure is formed, a second dielectric layer and a second interconnection structure are formed on the second surface of the substrate, wherein the second interconnection structure is electrically connected with the first deep trench isolation structure and is used as a second test signal loading end.

21. The method of forming a test structure of claim 20, wherein in the step of forming the deep trench isolation structure, the first deep trench isolation structure is annular, the first deep trench isolation structure surrounding the interconnect region;

alternatively, in the step of providing a substrate, the interconnect region includes a first interconnect region, and a second interconnect region surrounding the first interconnect region; in the step of forming the deep trench isolation structure, the first deep trench isolation structure is located between the first interconnect region and the second interconnect region and surrounds the first interconnect region;

alternatively, in the step of providing the substrate, the interconnection region is annular; in the step of forming the deep trench isolation structure, the first deep trench isolation structure is located in a region surrounded by the interconnection region and surrounded by the interconnection region.

22. The method of forming a test structure of claim 20, further comprising, after providing a substrate, prior to forming the first dielectric layer: performing first doping on the first surface of the substrate, and forming a first doped region with second doping ions in the substrate positioned in the interconnection region, wherein the first doped region is exposed by the first surface of the substrate, the concentration of the second doping ions is larger than that of the first doping ions, and the conductivity type of the second doping ions is the same as that of the first doping ions;

In the step of forming the first interconnection structure, the first interconnection structure is electrically connected with the first doped region.

23. The method of forming a test structure of claim 21, wherein in the step of providing a substrate, the interconnect region includes a first interconnect region and a second interconnect region surrounding the first interconnect region;

in the step of forming the deep trench isolation structure, the first deep trench isolation structure is located between and surrounding the first interconnect region and the second interconnect region, and the deep trench isolation structure further includes a second deep trench isolation structure penetrating through the substrate, the second deep trench isolation structure surrounding and abutting the interconnect region boundary;

alternatively, in the step of providing a substrate, the interconnection region is annular;

in the step of forming the deep trench isolation structure, the first deep trench isolation structure is located in an area surrounded by the interconnection area and surrounded by the interconnection area, and the deep trench isolation structure further comprises a second deep trench isolation structure penetrating through the substrate, wherein the second deep trench isolation structure surrounds the interconnection area and is adjacent to the boundary of the interconnection area.

24. The method of forming a test structure of claim 22, further comprising, after forming the first doped region, before forming the first dielectric layer: and carrying out second doping on the first surface of the substrate, forming a second doping region with third doping ions in the substrate of the interconnection region, wherein the second doping region is contacted with the surface of the first doping region facing away from the first surface, one end of the second doping region is flush with the interconnection region along the direction parallel to the surface of the substrate, the other end of the second doping region is retracted inwards relative to the interconnection region, the concentration of the third doping ions is smaller than that of the second doping ions and larger than that of the first doping ions, and the conductivity type of the third doping ions is the same as that of the first doping ions.

25. The method of forming a test structure of any of claims 20-24, wherein in the step of forming the deep trench isolation structure, the deep trench isolation structure further comprises a third deep trench isolation structure extending through the substrate, the third deep trench isolation structure surrounding the first deep trench isolation structure and the substrate of the interconnect region, the third deep trench isolation structure being spaced apart from the first deep trench isolation structure and the interconnect region in a direction parallel to the surface of the substrate, the third deep trench isolation structure being configured to protect the first deep trench isolation structure.

26. The method of forming a test structure of any of claims 25, wherein in the step of providing a substrate, the interconnect region is annular;

in the step of forming the deep trench isolation structure, the first deep trench isolation structure is located in an area surrounded by the interconnection area and surrounded by the interconnection area, and the deep trench isolation structure further comprises a fourth deep trench isolation structure penetrating through the substrate, the fourth deep trench isolation structure is located in an area surrounded by the first deep trench isolation structure and surrounded by the first deep trench isolation structure, and is spaced from the first deep trench isolation structure along a direction parallel to the surface of the substrate, and the fourth deep trench isolation structure is used for protecting the first deep trench isolation structure.

27. The test structure of claim 20, wherein the step of forming the deep trench isolation structure comprises: forming a trench in the substrate from a second side of the substrate, the trench penetrating the substrate; forming an insulating layer on the side wall of the groove; after the insulating layer is formed, forming a conductive layer in the residual space of the groove, wherein the conductive layer and the insulating layer in the groove form a deep groove isolation structure;

In the step of forming the second interconnect structure, the second interconnect structure is electrically connected to the conductive layer.

28. A method of testing, comprising:

providing a test structure according to any one of claims 1-19;

loading corresponding test signals to the first test signal loading end and the second test signal loading end, wherein the test signals are used for enabling the first interconnection structure, the substrate, the first deep groove isolation structure and the second interconnection structure to form a test path;

acquiring corresponding capacitance values of the test path under different test signals;

and obtaining the electrical thickness and the charge distribution of the corresponding side wall charge layer of the first deep groove isolation structure according to the capacitance value.

29. The method of testing of claim 28, wherein loading the first test signal loading terminal and the second test signal loading terminal with corresponding test signals comprises: and loading zero potential on the second test signal loading end, and enabling the potential of the first test signal loading end to be scanned from negative potential to positive potential or from positive potential to negative potential.