US20140319610A1 - Lateral Power Semiconductor Device and Method for Manufacturing a Lateral Power Semiconductor Device - Google Patents
Lateral Power Semiconductor Device and Method for Manufacturing a Lateral Power Semiconductor Device Download PDFInfo
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- US20140319610A1 US20140319610A1 US13/873,994 US201313873994A US2014319610A1 US 20140319610 A1 US20140319610 A1 US 20140319610A1 US 201313873994 A US201313873994 A US 201313873994A US 2014319610 A1 US2014319610 A1 US 2014319610A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Definitions
- Embodiments described herein relate to lateral power semiconductor devices with improved avalanche and commutation characteristics, and to methods for manufacturing a lateral power semiconductor device.
- lateral power semiconductor devices are suitable for small and medium currents since they do not need an edge termination region that consumes additional chip area.
- lateral power semiconductor devices are designed to maximize the rated total current for a given chip area. This may cause problems in regions where the electrical field is locally increased due to bending of the electrical field lines.
- a lateral power semiconductor device includes a semiconductor body having a first surface and a second surface opposite the first surface.
- a first main electrode having at least two sections is arranged on the first surface, and a second main electrode is arranged on the first surface between the two sections of the first main electrode.
- a plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode.
- At least one curved semiconductor portion is arranged between the first main electrode and the second main electrode with increasing doping concentration from the first main electrode to the second main electrode.
- a lateral power semiconductor device includes a semiconductor body having a first surface, a semiconductor substrate and a semiconductor layer on the semiconductor substrate, and a loop structure having, from a top view on the first surface, at least one curved semiconductor portion and at least one straight semiconductor portion including a plurality of switchable semiconductor cells.
- Each switchable semiconductor cell includes a drift region formed in the semiconductor layer, a drift control region formed in the semiconductor layer adjacent to the drift region, and an accumulation dielectric electrically insulating the drift region from the drift control region. Insulating layers electrically insulate the drift control region of each switchable semiconductor cell from the semiconductor substrate.
- the curved semiconductor portion is formed in the semiconductor layer, and comprises an outer curved boundary partially surrounding an inner boundary from the top view on the first surface, wherein the doping concentration of the curved semiconductor portion increases from the outer curved boundary to the inner boundary.
- a lateral power semiconductor device includes a semiconductor body having a first surface, a first doping region of a first conductivity type, a second doping region of a second conductivity type forming a pn-junction with the first doping region, a third doping region of the first conductivity type forming a main pn-junction with the second doping region, and a fourth doping region in contact with the third doping region, wherein the main pn-junction surrounds the third doping region from a top view on the first surface.
- the third doping region surrounds the fourth doping region in top view on the first surface.
- the third doping region includes straight semiconductor portions and curved semiconductor portions from the top view on the first surface. The doping concentration of the curved semiconductor portions increases from the main pn-junction to the fourth doping region.
- a method for manufacturing a lateral power semiconductor device includes providing a semiconductor body having a semiconductor substrate and a semiconductor layer on the semiconductor substrate, the semiconductor layer forming a first surface of the semiconductor body; forming a loop structure in the first surface having, from a top view, at least one curved semiconductor portion and at least one straight semiconductor portion having a plurality of switchable semiconductor cells, each switchable semiconductor cell having a drift region formed in the semiconductor layer, a drift control region formed in the semiconductor layer adjacent to the drift region, and an accumulation dielectric electrically insulating the drift region from the drift control region; and forming insulating layers between the drift control region and the semiconductor substrate to electrically insulate the drift control region of each switchable semiconductor cell from the semiconductor substrate; wherein the curved semiconductor portion is formed in the semiconductor layer and comprises an outer curved boundary and an inner boundary from the top view on the first surface, wherein the doping concentration of the curved semiconductor portion increases from the outer curved boundary to the inner boundary.
- FIG. 1 illustrates a top view on a lateral power semiconductor device according to an embodiment
- FIG. 2 illustrates an enlarged view of a portion of a lateral power semiconductor device according to an embodiment
- FIG. 3 illustrates a vertical cross section through a curved semiconductor portion of a lateral power semiconductor device according to an embodiment
- FIGS. 4A and 4B illustrate electrical field distributions across regions of the lateral power semiconductor device
- FIGS. 5A to 5D illustrate switchable semiconductor cells of a lateral power semiconductor device according to an embodiment
- FIGS. 6A to 6D illustrate processes for manufacturing a lateral power semiconductor device according to an embodiment
- FIG. 7 illustrates a process for manufacturing a lateral power semiconductor device according to an embodiment
- FIG. 8 illustrates a process for manufacturing a lateral power semiconductor device according to an embodiment
- FIGS. 9A and 9B illustrate a process for manufacturing a lateral power semiconductor device according to an embodiment.
- lateral intends to describe an orientation parallel to the main surface of a semiconductor substrate.
- vertical as used in this specification intends to describe an orientation, which is arranged perpendicular to the main surface of the semiconductor substrate.
- a second surface of a semiconductor substrate is considered to be formed by the lower or back-side surface while a first surface is considered to be formed by the upper, front or main surface of the semiconductor substrate.
- the terms “above” and “below” as used in this specification therefore describe a relative location of a structural feature to another structural feature with consideration of this orientation.
- electrical connection and “electrically connected” describes an ohmic connection between two elements.
- FIGS. 1-3 depict a lateral power semiconductor device according to an embodiment.
- FIG. 1 illustrates a top view on a first surface 111 (see FIG. 3 ) of a semiconductor body 110 of the lateral power semiconductor device.
- a first main electrode 131 and a second main electrode 132 are arranged on the first surface 111 .
- the first main electrode 131 is disposed from, and surrounds, the second main electrode 132 .
- the first electrode 131 includes at least two straight sections 131 a and 131 b arranged on the first surface 111 .
- the second main electrode 132 is arranged between the two straight sections 131 a and 131 b.
- the first and second main electrodes 131 , 132 are in electrical contact with respective doping regions that are arranged below the first and second main electrodes 131 , 132 that are not shown in FIG. 1 .
- FIG. 2 illustrating an enlarged section of FIG. 1 without the first and second main electrodes 131 , 132 , shows a first semiconductor region 141 which may be, for example a source region.
- the first semiconductor region 141 is of a first conductivity type, which may be, for example, n-type.
- the first semiconductor region 141 may be at least partially omitted at the outer curved boundary.
- FIG. 2 shows the first semiconductor region 141 including first sections 141 a forming straight regions and second sections 141 b , in this case, forming curved regions each of which connects respective two of the first sections 141 a .
- the first sections 141 a can form the source regions of the cells of the lateral power semiconductor device.
- the second sections 141 b are optional and do not need to be formed.
- the optional second sections 141 b are marked by dashed lines. According to an embodiment and shown e.g., in FIG. 5A , in a part of the straight regions, e.g. in a doping region 126 as shown in FIG.
- the first semiconductor region 141 can be alternatively and/or additionally at least partially omitted. These regions where the doping of the semiconductor region 141 is omitted in the straight regions, for example between adjacent regions 241 in FIG. 5A , can be understood as belonging to the second sections 141 b.
- the first semiconductor region 141 when including the first and second sections 141 a , 141 b , completely surrounds a fourth semiconductor region 144 , which may be of the first conductivity type to form a drain region, for example.
- the fourth semiconductor region 144 is disposed between the first sections 141 a of the first semiconductor region 141 , as is the case when the first semiconductor region 141 completely surrounds the fourth semiconductor region 144 .
- the fourth semiconductor region 144 which may form a drain region, is in electrical contact with the second main electrode 132 , which is drain metallization in this embodiment.
- the first semiconductor region 141 is in electrical contact with the first main electrode 131 , which is a source metallization in this embodiment.
- the closed loop structure 120 typically completely surrounds the fourth doping region 144 .
- the closed loop structure 120 is mainly formed by a third doping region 143 which may be of the first conductivity type.
- the third doping region 143 is weakly n-doped having a doping concentration that is less than the doping concentration of the fourth doping region 144 .
- the third doping region 143 typically forms a drift region of the lateral power device.
- Adjacent to the third doping region 143 is a second doping region 142 , of the second conductivity type, i.e. of p-type, that forms a body region.
- a main pn-junction 145 is formed between the second doping region 142 and the third doping region 143 .
- the second doping region 142 is arranged between the first doping region 141 , and the third doping region 143 .
- the first doping 141 region is arranged adjacent to the second doping region 142 .
- the main pn-junction 145 can be considered as forming an outer border or outer curved boundary of the closed loop structure 120 , i.e., of the third doping region 143 .
- the second doping region 142 and first doping region 141 although shown in FIG. 2 to form ring structures following the contour of the main pn-junction 145 , can have shapes deviating from the course of the main pn-junction 145 , for example in the curved semiconductor portions 122 .
- the first doping region 141 and/or the second doping region 142 may be formed by individual doping islands arranged substantially along the line of the main pn-junction 145 as shown in FIG. 2 .
- the course of the main pn-junction 145 can show some deviations compared to FIG. 2 , e.g., can include some wave-kind line.
- one or more of the first doping region 141 and/or second doping region 142 can be connected to the first main electrode 131 .
- the third doping region 143 may be formed as a ring structure having two main straight sections, corresponding to the straight semiconductor portions 121 , running parallel to each other and having the fourth doping region 144 disposed therebetween. Furthermore, the third doping region 143 may include two semi-ring sections that correspond to the curved semiconductor portions 122 and connect the straight sections so that the fourth doping region 144 is completely surrounded by the third doping region 143 .
- the second doping region 142 may include two straight sections 121 between which the straight sections of the third doping region 143 are arranged. Along the outer boundary of the semi-ring sections 122 of the third doping region 143 , islands of the second doping region 142 may be arranged.
- continuous pn-junctions 145 are formed between the straight sections 121 of the second doping region 142 and the third doping region 143 .
- the pn-junction 145 along the outer boundary of the semi-ring sections of the third doping region 143 includes respective sections formed by a respective island of the second doped region 142 and the semi-ring sections 122 of the third doping region 143 .
- the space between adjacent islands of the second doping regions 142 is such that this space is completely depleted in reverse mode of the power device.
- the second sections 141 b of the first doping region 141 When the second sections 141 b of the first doping region 141 are present, these sections 141 b can cause latching during commutation of the power device. To avoid latching, the second sections 141 b may be omitted. Furthermore, when the second sections 141 b of the first doping region 141 are present, a portion of the electron charge emanating from the fourth doping 144 forming a drain region is drained through the second sections 141 b , as the second sections 141 b form together with the second doping region 142 and the third doping region an npn-transistor. In this case, the surplus of charges in the semi-ring sections 122 of the third doping region 143 is beneficially lowered.
- the process that dominates depends on the actual doping and/or geometrical relations.
- latching can be avoided even when the second sections 141 b are formed to reduce the surplus of charges.
- a junction between the third doping region 143 and the fourth doping region 144 may be considered to form an inner boundary 147 of the closed loop structure 120 .
- each of the first and fourth doping region 141 , 144 may have, when viewed onto the first surface 111 , a fin-like shape wherein the fins of each doping region interdigitate with the fins of the other doping region. Irrespective of the actual geometry of the first doping region 141 and the second doping region 144 , both regions remain spaced apart from each other with the closed loop structure 120 arranged between the first and second doping region 141 , 144 .
- the closed loop structure 120 includes a plurality of switchable semiconductor cells 140 arranged in the straight semiconductor portions 121 between the first semiconductor region 141 and the fourth semiconductor region 144 as best shown in FIG. 2 .
- the switchable semiconductor cells 140 are therefore also arranged between the first main electrode 131 and the second main electrode 132 .
- the switchable semiconductor cells 140 provide a controllable conductive path between the first main electrode 131 and the second main electrode 132 as will be described further below.
- a doping region 126 which does not include switchable semiconductor cells, is arranged between the semiconductor cells 140 and the curved semiconductor portion 122 so that the curved semiconductor portion 122 is spaced from the semiconductor cells 140 .
- the doping region 126 is part of the straight portion 121 in this embodiment.
- the curved semiconductor portion 122 has a doping concentration increasing from the first main electrode 131 to the second main electrode 132 . This is illustrated in FIG. 2 by the dashed half-circles with increased density towards the fourth doping region 144 .
- the doping concentration of the curved semiconductor portion 122 can increase by a factor of about 1/R with R being the distance from an imaginary geometrical center arranged in the fourth doping region 144 .
- the doping concentration in the curved semiconductor portion 122 may have a substantially stepwise characteristic with a lower doped part 143 a and a higher doped part 143 a.
- the closed loop structure 120 surrounding the fourth doping region 144 includes at least two curved semiconductor portions 122 and at least two straight semiconductor portions 121 which comprise a plurality of switchable semiconductor cells 140 .
- the number of the curved semiconductor portions 122 and the straight semiconductor portions 121 is, however, not limited to two and depends on the shape of the first and fourth doping region 141 , 144 . In case of fin-shaped first and fourth doping regions 141 , 144 , the number of the curved semiconductor portions 122 and the straight semiconductor portions 121 is larger than two. For example, when the fourth semiconductor region 144 has a substantially square-like shape with rounded edges, the closed loop structure includes four curved semiconductor portions 122 and four straight semiconductor portions 121 .
- the geometrical shape of the closed loop structure 120 of the present embodiment can be described as stadium having two straight semiconductor portions 121 which are arranged parallel to each other and which are connected by the substantially semi-circular curved semiconductor portions 122 .
- the fourth doping region 144 is a rather elongated region with rounded edges, one of which is shown in FIG. 2 .
- the course of the electrical field during blocking state is mainly defined by the course of the main pn-junction 145 , the outer shape of the fourth doping region 144 , and the doping relation of the third doping region 143 .
- the present embodiment does not include active semiconductor cells in the curved semiconductor portions 122 .
- first doping region 141 or the second doping region 142 when the first doping region 141 does not include second sections 141 b , and the fourth doping region 144 , since the semiconductor cells 140 are in blocking state and do not provide a conductive path between the first doping region 141 and the fourth doping region 144 .
- the first and second doping regions 141 , 142 can be on the same electrical potential when both are electrically connected to the first main electrode 131 .
- the maximum of the electric field is located at the main pn junction 145 .
- the field lines of the electrical field between the second doping region 142 , the semiconductor substrate (not shown in FIG.
- the fourth doping region 144 are three-dimensionally bent in the curved semiconductor regions 122 .
- the shape and doping values of the third doping region 143 and the fourth doping region 144 may be further used to increase the electric field at the main pn-junction 145 in the curved semiconductor regions 122 in comparison to the straight semiconductor regions 121 . Therefore, the value of the electric field when avalanche multiplication starts, is first reached in the curved semiconductor regions 122 .
- the fourth doping region 144 is on a higher electrical potential than the first doping region 141 and second doping region 142 during blocking mode.
- the third doping region 143 forms a drift region and is weakly n-doped. Since the absolute value of the electric field decreases proportionally to the charge in the space charge area, the slope of the field curve in the lower doped part 143 a of the third doping region 143 is lesser as compared to the higher doped part 143 b .
- Free electrons are generated in the third doping region 143 by the avalanche effect and move to the fourth doping region 144 on account of the prevailing electrical field between the fourth doping region 144 and the second doping region 142 . Due to the geometrical effect of the curvature, the local exaggeration of the current density and thus the electron density is mainly close to the fourth doping region 144 . This is beneficial particularly when the fourth doping region 144 forms a drain region. In this case, the local exaggeration of the electrical field is remote from the main pn-junction 145 .
- an increased amount of electrons towards the fourth doping region 144 partially compensate the positive net charge of the donators in the n-doped third doping region 143 and fourth doping region 144 .
- the reduction of the positive net charge results in a deviation of the electrical field in comparison to the case in which no current flows and an in which the electrical field distribution is only defined by the background doping distribution.
- the vertical dashed line in FIG. 4A indicates the location of the junction between the third doping region 143 and the fourth doping region 144 .
- the solid line corresponds to the case where no current of generated electrons flows, i.e., where the electrical field is defined by the background doping p only, which is assumed to be constant in each of the respective doping regions 143 a , 143 b and which corresponds to the doping concentration N D + of the donators. Due to a partial compensation by the electrons “accumulating” towards the junction between the third doping region 143 a , 143 b , the background doping is partially compensated so that the “effective” positive background doping ⁇ corresponds to the doping concentration N D + of the donators plus the concentration of the electrons. Note that the charge of electrons is negative which leads to a reduction of ⁇ . The resulting electrical field distribution is indicated by the dashed line in FIG. 4A .
- the “accumulation” of electrons is a dynamic process.
- the density of the electrons is higher close to the fourth doping region 144 because electrons, which are generated in a greater distance from junction between the third and fourth doping region 143 , 144 , flow towards this junction.
- the geometrical effect of the bent electrical field causes the electrons to concentrate towards the curved junction between the third and the fourth doping region 143 , 144 .
- the concentration of electrons is increased and remains increased during avalanche.
- the reduced positive net charge results in a reduction of the slope of the electrical field as illustrated in FIG. 4A which shows that the grad(E) is slightly reduced.
- the blocking voltage increases.
- the counter charge for the charge in the second doping region 142 is delivered in total by the high donator density of the fourth doping region 144 and lead to an almost abrupt reduction of the electric field.
- the increased blocking voltage in the curved semiconductor portion 122 in turn acts against the avalanche so that a self-stabilising effect is observed.
- the background doping concentration of the curved semiconductor portions 122 can be raised. Furthermore, a doping concentration increasing towards the fourth doping region 144 further improves the avalanche robustness as an increasing doping concentration at least partially compensates the geometrical factor of the curved electrical field lines in the curved semiconductor region 122 .
- the doping concentration in the third doping region 143 can increase with 1/R with R being a distance from a geometrical center in the fourth doping region 144 close to the junction between the fourth doping region 144 and the third doping region 143 .
- the curved semiconductor portion 122 can have an outer boundary which is mainly defined by the main pn-junction 145 .
- This outer boundary can be curved in general, for example or can be semi-circular as shown in FIG. 2 . With reducing distance R from the geometrical center of this semi-circle, the doping concentration increases.
- the curved semiconductor portion 122 can have an inner boundary defined by the junction between the third doping region 143 and the fourth doping region 144 .
- the inner boundary may be curved, for example semi-circular, as shown in FIG. 2 .
- the increasing doping concentration within the third doping region 143 may be adapted to follow the bending radius of the inner boundary. In the case of a semi-circular inner boundary as shown in FIG. 2 , the bending radius is constant. In other cases, the bending radius may increase or decrease. The increase of the doping concentration in the third region 143 may then be adapted accordingly.
- the increasing doping concentration results in an electric field distribution as indicated by the dashed line in FIG. 4B , which shows, as comparison, the electrical field distribution for a constant background doping (solid line) at the same blocking voltage applied between the second doping region 142 and the fourth doping region 144 .
- the blocking voltage i.e., the integral over the electric field strength, or in other words the onset of avalanche generation, can be reduced when locally increasing the background doping towards the junction between the third doping region 143 and the fourth doping region 144 .
- the background doping of lateral device having a rated blocking voltage of 600 V is less than about 1.4*10 14 /cm 3 .
- This doping concentration prevails also at the main pn-junction 145 in the curved semiconductor portions 122 .
- the doping concentration increases towards the junction between the third doping region 143 and the fourth doping region 144 to a value of about 10 15 to 10 16 /cm 3 .
- the doping concentration increases from the main pn-junction 145 to the junction between the third doping region 143 and the fourth doping region 144 by a factor of about 5 to 100.
- the maximum permissible avalanche current increases.
- the blocking voltage at which avalanche occurs reduces. This is beneficial since the avalanche breakdown will occur in the curved semiconductor portions 122 and not in the switchable semiconductor cells 140 .
- the lateral semiconductor device exhibits an improved avalanche robustness.
- the curved semiconductor portions 122 can therefore be referred to as “avalanche regions”.
- the region 126 is provided between the curved semiconductor portion 122 and the switchable semiconductor cells 140 in the straight portion 121 as shown in FIG. 2 .
- the lateral width “a” of the region 126 can be between about 5% to 100% of the distance in the straight semiconductor portions 121 between the second semiconductor region 142 and the fourth semiconductor region 144 .
- the distance between the second semiconductor region 142 and the fourth semiconductor region 144 is depending on the desired blocking capability of a lateral semiconductor switch and may be estimated to be approximately 7.5 to 15 ⁇ m per 100V.
- the distance between the second semiconductor region 142 and the fourth semiconductor region 144 should be in the range of about 45 ⁇ m to 90 ⁇ m and thus the value of “a” between about 2.25 ⁇ m and about 90 ⁇ m.
- the semiconductor region 126 has a doping concentration that is less than the doping concentration in the curved semiconductor portion 122 and can correspond to the background doping of the switchable semiconductor cells 140 .
- the peak doping concentration of the background doping within the third doping region 143 of the curved semiconductor portion 122 is spaced from the first surface 111 , as shown in FIG. 3 .
- FIG. 3 is a vertical cross section through the curved semiconductor portion 122 along the radius R shown in FIG. 2 .
- the doping concentration increases, for example according to 1/R.
- the peak doping concentration for a given location X is spaced from the first surface 111 .
- the location of the peak doping concentration is indicated by the dashed line.
- Such a doping profile can be obtained by implantation with an appropriately selected implantation energy which implants the dopants into a given depth which will later corresponds to the location of the peak doping concentration.
- the outer rim of the lateral semiconductor device is at source potential while the center of the lateral semiconductor device is at drain potential.
- Control circuits for controlling the lateral semiconductor device can therefore be integrated into the semiconductor body 110 without additional level shifters.
- the second doping region forming a body region can be in electrical continuity with a p-doped substrate 149 forming a lower part of the semiconductor body 110 . This improves electrical insulation of the lateral semiconductor device, facilitates integration, and ensures that the rim and the lower side formed by a second surface 112 of the semiconductor body 110 is in the same electrical potential.
- the electrical contact between the p-doped substrate 149 and the second doping region 142 may be done without continuous doping as shown in FIG. 3 but with other means like bond wires, soldered clips or other electrical connections outside the semiconductor body 110 .
- the third doping region 143 in the curved semiconductor portion 122 forms a pn-junction with the p-doped substrate 149 . This improves heat dissipation for the heat generated during avalanche.
- the switchable semiconductor cells 140 are so-called TEDFETs in this embodiment and include two functional regions 200 and 300 as illustrated in FIG. 5A .
- Functional region 200 forms a “normal” FET while functional region 300 forms a drift control cell for forming and controlling an accumulation channel in the FET.
- FIG. 5B The structure of the FET (functional region 200 ) is illustrated in FIG. 5B showing a vertical section along line BB in FIG. 5A .
- the FET cell is formed in a semiconductor body 210 including a semiconductor substrate 249 which may be, for example, p-doped and an n-doped semiconductor layer 248 formed on the semiconductor substrate 249 .
- Semiconductor layer 248 can be formed using e.g., epitaxial growth.
- the n-doping of the semiconductor layer 248 forms the background doping of the switchable semiconductor cells 140 .
- the semiconductor body 210 has a first surface 211 and a second surface 212 opposite the first surface 211 .
- the semiconductor layer 248 extends to the first surface 211 and forms the third doping region 143 as described above, i.e., forms a drift region 243 .
- a p-doped region 242 which is part of the second doping region 142 , is formed in the drift region 243 .
- the p-doped region 242 functions as a body region and forms the main pn-junction 245 with the drift region 243 .
- a highly n-doped source region 241 being part of the first doping region 141 , is embedded in the body region 242 .
- a highly n-doped drain region 244 being part of the fourth doping region 144 , is embedded in the drift region 243 and forms an nn+ junction with the drift region 243 .
- a source metallization 231 being part of the first main electrode 131 , is in electrical contact with source region 241 and the body region 241 . Furthermore, a drain metallization 232 , being part of the second main electrode 132 , is in electrical contact with the drain region 244 .
- a gate electrode 233 forming part of a third electrode of the lateral power semiconductor device.
- the gate electrode 233 and the drift region 243 are covered by a comparably thick insulation layer 251 insulating the gate electrode 233 and the drift region 243 against the source metallization 231 and the drain metallization 232 .
- the p-doped body 242 and p-doped semiconductor substrate 249 can be in electrical contact, for example by extending the body region 242 along an outer edge or rim of the semiconductor body 210 as shown in FIG. 3 .
- FIGS. 5A to 5D only show the structure of the switchable semiconductor cells 140 and not the complete device.
- the left side in FIGS. 5A to 5D faces to the outer rim of the semiconductor body 210 while the right side faces the center of the lateral semiconductor device defined by the fourth doping region 144 .
- drift control cell 300 Adjacent to the FET cell 200 , there is formed a drift control cell 300 which is insulated from the FET cell 200 by an accumulation dielectric 350 as best shown in FIGS. 5A and 5C with FIG. 5C being a cross section along line CC in FIG. 5A .
- the drift control cell 300 of the TEDFET is formed in the semiconductor body 310 having the first surface 311 , the second surface 312 , the semiconductor substrate 349 , and the semiconductor layer 348 as described above. However, distal to the FET cell 200 , an insulating layer 353 is formed between the p-doped semiconductor substrate 349 and the n-doped semiconductor layer 348 .
- the semiconductor layer 348 can be formed using e.g., epitaxial growth. Together with the accumulation dielectric 350 , the insulating layer 353 completely electrically insulates the drift control cell 300 from the adjacent FET cell 200 and the semiconductor substrate 349 . This is best shown in FIG. 5D showing a three-dimensional illustration of a switchable semiconductor cell 140 including a FET cell 200 with an adjacent drift control cell 300 .
- the drift control cell 300 includes a p-doped first zone 342 and forming a main pn-junction 345 with a drift control region 343 formed by the n-doped semiconductor layer 348 .
- a highly n-doped second zone 344 is formed in the semiconductor layer 348 and forms an nn+-junction with the drift control region 343 .
- the first zone 342 is contacted by a first terminal 331 while the second zone 344 is contacted by a second terminal 332 .
- the first terminal 331 can be electrically connected to the source metallization 231 through a not shown diode element.
- the second terminal 332 can be electrically to the drain metallization 232 through a not shown diode.
- the insulating layer 353 may also extend below the FET cell insulating the drift region 243 from the substrate 212 . According to a further embodiment, the insulating layer 353 additionally or alternatively may also extend below the curved semiconductor portions 122 insulating the doping region 143 from the substrate 212 . Insulating the drift region 243 and/or the doping region 143 inhibits the injection of carriers into the substrate 212 during operation of the body diode and thus may further improve the dynamic behaviour of the body diode. On the other hand, thermal performance is reduced due to the reduced heat flow through the insulating layer 353 compared to a direct contact of semiconductor material.
- a comparably thick insulating layer 351 which may be continuous with the insulating layer 251 , covers the drift control region 343 and provides insulation against the first and the second terminals 331 , 332 , respectively.
- an accumulation channel is formed in the drift region 243 along the accumulation dielectric 350 to reduce the on-state resistance in the conducting state of the lateral power semiconductor device.
- the switchable semiconductor cells 140 are arranged adjacent to each other so that FET cells 200 and drift control cells 300 are alternatingly arranged in the straight semiconductor portion 121 of the lateral power semiconductor device.
- avalanche breakdown is confined or restricted to the curved semiconductor portions 122 and, hence, does not influence the switchable semiconductor cells 140 and particularly the accumulation dielectric 350 . Therefore, trapping of hot charge carriers, which are generated during avalanche breakdown, in the accumulation dielectric 350 can be significantly reduced. This effect is further improved when the peak doping concentration of the third doping region 143 in the curved semiconductor portion 122 is spaced from the first surface 111 as in this case the likelihood of hot carrier injected into the insulating layer 251 , 351 , which also covers the curved semiconductor portion 122 , is also reduced.
- the above described arrangement of the lateral power semiconductor device further exhibits an improved commutating characteristic so that the lateral power semiconductor device has improved avalanche robustness and an improved commutating characteristic.
- the drift region 243 is flooded with charge carriers.
- the body-diodes when suitably dimensioned to be able to handle large body diode currents, also causes the third doping region 143 , corresponding to the drift region 243 , to be flooded with charge carriers.
- the doping concentration in the curved semiconductor portion 122 increasing towards to the fourth doping region 144 acts as a field-stop region preventing the electrical field from quickly forwarding to the fourth doping region 144 (drain region 244 ).
- the charge carriers remain for a longer time in the third doping region 143 which leads to a more gentle commutation.
- the current density for removing the positive charge carriers (holes) is reduced by the geometrical effect of the curved semiconductor portion 122 as the hole current is towards the outer boundary of the curved semiconductor portion 122 .
- Such behavior is beneficial for bridge circuits and resonant applications, where the body diode can be subjected to hard commutation under specific conditions which may lead to a destruction of the device.
- the above described lateral power semiconductor device allows the semiconductor body 110 , i.e. the second side 112 of the semiconductor body 110 , to be at the source potential. Furthermore, driving circuits can be easily integrated into the semiconductor body 110 laterally outside of the active regions of the power semiconductor device since the outer regions, as well as the backside of the semiconductor body 110 , are on the same electrical potential.
- the fourth semiconductor region 144 can be on source potential while the first and/or the second semiconductor region 141 , 142 can be on drain potential.
- a reverse blocking transistor can be integrated in the regions of the switchable semiconductor cells 140 , for example by forming an optional additional doping region 246 having a doping type opposite to the doping type of the drain regions 244 and which is electrically connected to the drain electrode 232 and isolates the drain region 244 from the drift region 243 .
- the electrical connection in FIG. 5D is indicated by a line 247 , but can be realized e.g., by a grooved contact for the drain electrode 232 or by the additional doping region 246 penetrating a part of the drain regions 244 reaching the first surface 211 .
- a lateral IGBT structure is thus provided that floods the drift region 243 when the gate 233 is charged.
- This modification improves the pulse current robustness of the lateral power semiconductor device.
- the reverse blocking capabilities are improved which drives the reverse current into the curved semiconductor portions 122 of the third doping region 143 having doping relations which are tailored, particularly due to the increasing doping concentration, for optimal diode performance.
- active rectifier operation of the lateral power semiconductor device is also possible by generating a conductive channel along the accumulation dielectric 350 and increasing the voltage applied to the gate electrode 233 .
- a semiconductor body 410 having a semiconductor substrate 449 and a semiconductor layer 448 on the semiconductor substrate 449 is provided.
- the semiconductor layer 448 can be an epitaxially grown layer of a doping type opposite to the doping type of the semiconductor substrate 449 .
- the semiconductor layer 448 forms a pn-junction with the semiconductor substrate 449 .
- the semiconductor layer 448 can also be of the same doping type as the semiconductor substrate 449 .
- the semiconductor layer 448 extends to and forms a first surface 411 of the semiconductor body 410 as illustrated in FIG. 6A .
- a plurality of trenches 460 is formed in the semiconductor layer 448 . This is shown in the left part of FIG. 6A .
- the trenches 460 run along the regions where the drift control regions 343 are formed in subsequent processes. For each drift control region 343 , a respective trench 460 can be formed.
- the mesa regions between adjacent trenches 460 form later the drift regions 243 .
- the trenches 460 can extend, in a top view as for example shown in FIG. 2 , from a region above the main pn-junction 145 to below the main pn-junction 145 when referring to the orientation of FIG. 2 .
- the trenches 460 therefore also extend through the region where later the fourth doping region 144 is formed.
- the trenches 460 may extend along the semiconductor cells 140 from the upper edge of the semiconductor body 110 to the lower edge of the semiconductor body 110 .
- the trenches 460 maybe formed to extend to regions which later form the edges of the lateral power semiconductor devices.
- the trenches 460 may extend to regions just outside of the first semiconductor region 141 .
- the semiconductor body 410 is tempered at an elevated temperature in a deoxidizing atmosphere to cause surface migration of the semiconductor material of the semiconductor layer 448 until the trenches 460 are covered by the semiconductor material to form respective cavities 461 that are laterally spaced apart from each other. Since the “reflow” of the semiconductor material results in a mono-crystalline material, the extension of the trenches into other regions than the regions, where the drift control regions are formed, is uncritical.
- the trenches 460 can have a lateral width of about 300 nm to about 3000 nm and a length of about 30 ⁇ m to about 120 ⁇ m for a device with 600V blocking capability.
- the minimal length of the trenches can correspond with the length I T of the lateral transistor cell which is connected to the desired blocking voltage V B of the lateral transistor.
- the I T in ⁇ m is about 5 . . . 20*V B /100V.
- the trenches can be much longer than these values and can be formed reaching through one or more chips or even through the whole wafer.
- the above width changes in the tempering process and the initial width of the trenches 460 should be adapted to allow for this change.
- the pitch of the trenches 460 can be in the range of several hundred nm which reliably prevents that adjacent trenches 460 merge during the tempering process.
- the depth of the trenches 460 can be in the range of several ⁇ m. These dimensions are only illustrative and not limiting.
- the temperature can be in a range from about 1000° C. to about 1150° C. when the semiconductor layer 448 is a silicon semiconductor.
- the semiconductor material of the semiconductor layer 448 begins to “flow” and the trenches 460 start to get closed by the flowing material.
- the trenches 460 widen in their lower parts due to the flowing material.
- the trenches 460 are spaced apart from each other by a lateral distance which is sufficient that the widening trenches 460 in their lower parts do not merge.
- the tempering can be carried out, according to an embodiment, in a deoxidizing atmosphere, for example in a hydrogen atmosphere at low pressure, for example at about 10 Torr (about 1.3 ⁇ 10 3 Pa).
- the duration of the tempering process can be varied and can be selected in view of the temperature.
- a typical tempering time at the desired tempering temperature is about 10 min.
- a vertical channel 462 is formed extending from the first surface 411 to provide an access to the cavities 461 .
- one respective channel 462 can be formed to extend to one respective cavity 461 .
- one channel 462 can provide access to two or more cavities 461 .
- the cavities 461 which assume the shape of hollow pipes in the left part of FIG. 6C , have internal surfaces.
- the internal surfaces of the cavities 461 are oxidized to form respective insulating layers 470 , which later form the insulating layers 353 .
- the channels 462 provide the access for the oxidising atmosphere to diffuse into the cavities 461 .
- the channels 462 are typically formed in regions outside the active region of the power semiconductor device.
- the channels 462 can be formed in the regions of the kerf or sawing frame along which the semiconductor body 410 is finally cut to separate the power semiconductor devices from each other.
- FIGS. 6A to 6D illustrate the formation of separate insulating layers 470 , which are only formed in the regions below the drift control regions 343 .
- the mesa regions between the trenches 460 remain in contact with the semiconductor substrate 449 .
- the trenches 460 may be formed to extend as far as the semiconductor substrate 449 so that the respective insulating layers 470 are formed in the interface region between the semiconductor substrate 449 and the semiconductor layer or semiconductor layer 448 .
- the mesa regions that later form the drift regions can form respective pn-junctions with the semiconductor substrate 449 . These pn-junctions insulate the drift regions from the semiconductor substrate 449 .
- drift regions in contact with the semiconductor substrate 449 is beneficial for heat transfer from the lateral transistor cells to a heat sink, which is typically connected to the back side of the semiconductor substrate 449 , as the semiconductor material of the drift regions (mesa regions) in continuous with the semiconductor substrate 449 .
- the trenches 460 may only be formed in regions of the later straight semiconductor portions 121 . In other regions such as the curved semiconductor portions 122 and, for example, below the fourth semiconductor region 144 , no trenches 460 are formed so that the semiconductor material also remains continuous in these regions and portions, respectively.
- the cavities 261 which remain hollow even after formation of the insulating layer 471 , reduce the capacitive coupling of the drift control region 343 with the semiconductor substrate 449 .
- a common insulating layer 471 is formed below the drift control regions 343 and the drift regions 243 .
- a plurality of closely spaced trenches 465 is formed in the semiconductor layer 448 . Whether a trench transforms to a single cavity or adjacent trenches merge to a common cavity depends on the lateral spacing, i.e. pitch, of the trenches.
- a cavity 466 is formed that has, in top view, the 2-dimensional extension of the array.
- the cavity 466 may have a plane shape as illustrated in FIG. 6B .
- a rectangular array of closely spaced trenches 465 form a substantially rectangular cavity 466 with rounded corners (seen in top view) while a row of closely spaced trenches 465 forms a substantially elongated cavity. Therefore, by selecting the arrangement of the trenches 108 , virtually any cavity arrangement and shape can be formed.
- a vertical channel 467 is formed to provide access for an oxidising atmosphere to the cavity 466 to form an insulating layer 471 on the internal surfaces of the cavity 466 .
- the channel 467 is typically formed in regions outside the active region of the power semiconductor device and can be sited arbitrarily in the region of the cavity 466 .
- the channel 467 can be formed in the regions of the kerf or sawing frame along which the semiconductor body 410 is finally cut to separate the power semiconductor devices from each other.
- Heat transfer from the lateral transistor to the heat sink is impaired by using a cavity also underneath the drift regions 243 . However, the capacitive coupling between the drift regions 243 and the substrate 449 is reduced.
- a compromise between thermal performance and capacitive coupling of the lateral transistor may be done by combining tubular cavities 461 only under the drift control regions 300 , e.g., in an area closer to the source regions of the lateral device, and a two dimensional cavity 466 under both drift regions 200 and drift control regions 300 , e.g., in an area closer to drain regions.
- the number of channels 462 , 467 may be reduced down to one channel in total.
- the cavity 466 By placing the cavity 466 under the curved semiconductor regions it can be avoided that electrons or holes generated in diode operation of the lateral power semiconductor device or during avalanche can reach the semiconductor substrate and thus can reach other portions of the device.
- Each switchable semiconductor cell 140 includes a drift region 243 formed in the semiconductor layer 448 , particularly in the mesa regions between the regions where the trenches 460 were formed.
- the drift control regions 343 are formed in the semiconductor layer 448 adjacent to the drift region 243 and above the insulating layers 470 .
- the accumulation dielectrics 350 are formed between the drift region 243 and the drift control region 343 , for example by etching thin trenches. The etching stops on the insulating layer 470 .
- the thin trenches are subsequently filled with an insulating material.
- the semiconductor cells 140 form a straight semiconductor portion 121 of the loop structure 120 having, in top view on the first surface, at least one curved semiconductor portion 122 and at least one straight semiconductor portion 121 .
- the curved semiconductor portion 122 is doped so that the doping concentration of the curved semiconductor portion 122 increases from the outer curved boundary 145 to the inner boundary 147 .
- This can be, for example, done using one or several implantation masks.
- the doping of the curved semiconductor portion 122 can be done with ion implantation through windows of a mask and a subsequent annealing step to reach diffusion of the dopant. The maximum doping concentration can be reached without masking the ion implantation which can be done e.g., close to the inner boundary 147 .
- the density of the windows in the mask is reduced thus reducing the mean amount of doping atoms implanted into the semiconductor material per area.
- the minimum doping concentration can be reached by completely blocking the ion implantation, i.e., without opening windows in the mask. This process can be repeated one or more times. From the position of integration it is desirable to use ion implantation steps and masking steps which are anyway needed in the production of the semiconductor chip.
- FIG. 8 shows an implantation mask 880 having a plurality of windows 881 and 882 .
- the dashed lines in FIG. 8 indicate the location of the outer boundary 145 and the inner boundary 147 of the curved portions 122 formed by portions of the third doping region 143 .
- the number, size and shape of the windows 881 may vary, for example in radial direction while keeping the density constant in circumferential direction for a given radius.
- An inner window 882 can be formed as a semi-circular ring.
- the implanted dopants diffuse to smooth the implantation pattern defined by the mask 880 .
- the local variation of the resulting doping can be even better controlled and the duration and/or temperature of the subsequent annealing step can be reduced.
- a first mask 901 is provided covering an outer region of the curved semiconductor portion 122 , for example region 143 a shown in FIG. 2 , and leaving an inner region of the curved semiconductor portion 122 , for example region 143 b , unmasked.
- the first mask 901 includes the first window 981 .
- Dopants are implanted using the first mask 901 as doping mask.
- a second mask 902 having a second window 982 is formed. The second window 982 leaves a portion of the outer region adjoining the inner region unmasked.
- the size of the second window 982 can be larger than the size of the first window 981 and extends further to the outer curved boundary 145 .
- the second mask 902 is used as implantation mask during a further implantation process. Hence, by increasing the size of the second window 982 relative to the first window 981 towards the outer curved boundary 145 , the total amount of dopants that are implanted into the curved semiconductor portion 122 is larger towards the inner boundary 147 than towards the outer boundary 145 .
- the first and second mask 901 , 902 By using the first and second mask 901 , 902 , at least a two-step doping profile from the inner boundary 147 to the outer curved boundary 145 can be obtained. When using more than two masks, the number of steps in the doping profile may be increased.
- the first and second masks 901 , 902 may be portions of implantation masks which are used in other regions to form other doping regions such as the fourth doping region 144 , an optional field-stop layer, or the first doping region 141 .
- the number of lithographic steps can be kept as small as possible.
- the mask windows 881 , 882 , 981 and 982 shown in FIG. 8 , FIGS. 9A and 9B can be permutated in all combinations.
- windows like e.g., 881 may be used also in the first mask 901 and/or the second mask 902 additionally or alternatively to a bigger window 981 , 982 .
- the second mask 902 and the first mask 901 can have overlapping windows like window 981 and window 982 shown in FIGS. 9A and 9B .
- the window of the second mask 902 may be located only over masked areas of the first mask 901 .
- more than two masks can be used.
- the drift regions and the drift control regions are formed in a membrane of the semiconductor body 410 .
- the insulation to the backside can be provided by a hollow recess and/or an insulating layer formed in the recess. This avoids, in diode operation of the lateral power semiconductor device, the electron-hole pairs generated during avalanche from reaching the semiconductor substrate and reaching other portions of the device.
- a recess 480 is formed, for example etched, in the second surface 412 of the semiconductor body 410 .
- the recess 480 extends bottom regions of the drift control regions 343 and the drift regions 243 .
- an insulating layer 471 may be formed on exposed surface of the recess 480 .
- the remaining space of the recess can be left unfilled or can be filled by a material, such as a semiconductor material or an insulator like e.g., ceramics or a polymer which may include other particles, even metal, which improves heat dissipation.
- a material such as a semiconductor material or an insulator like e.g., ceramics or a polymer which may include other particles, even metal, which improves heat dissipation.
- the empty recess provides the insulation even without any extra insulating layer.
- the empty recess 480 can form an insulating layer.
- the insulating layer 471 and/or the recess 480 insulates the drift regions 243 and the drift control regions 343 from any further material which can later be formed on the second side 412 of the semiconductor body 410 .
Abstract
Description
- Embodiments described herein relate to lateral power semiconductor devices with improved avalanche and commutation characteristics, and to methods for manufacturing a lateral power semiconductor device.
- In comparison with vertical devices, lateral power semiconductor devices are suitable for small and medium currents since they do not need an edge termination region that consumes additional chip area. Currently, lateral power semiconductor devices are designed to maximize the rated total current for a given chip area. This may cause problems in regions where the electrical field is locally increased due to bending of the electrical field lines.
- In view of the above, there is a need for improvement.
- According to an embodiment, a lateral power semiconductor device includes a semiconductor body having a first surface and a second surface opposite the first surface. A first main electrode having at least two sections is arranged on the first surface, and a second main electrode is arranged on the first surface between the two sections of the first main electrode. A plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode. At least one curved semiconductor portion is arranged between the first main electrode and the second main electrode with increasing doping concentration from the first main electrode to the second main electrode.
- According to an embodiment, a lateral power semiconductor device includes a semiconductor body having a first surface, a semiconductor substrate and a semiconductor layer on the semiconductor substrate, and a loop structure having, from a top view on the first surface, at least one curved semiconductor portion and at least one straight semiconductor portion including a plurality of switchable semiconductor cells. Each switchable semiconductor cell includes a drift region formed in the semiconductor layer, a drift control region formed in the semiconductor layer adjacent to the drift region, and an accumulation dielectric electrically insulating the drift region from the drift control region. Insulating layers electrically insulate the drift control region of each switchable semiconductor cell from the semiconductor substrate. The curved semiconductor portion is formed in the semiconductor layer, and comprises an outer curved boundary partially surrounding an inner boundary from the top view on the first surface, wherein the doping concentration of the curved semiconductor portion increases from the outer curved boundary to the inner boundary.
- According to an embodiment, a lateral power semiconductor device includes a semiconductor body having a first surface, a first doping region of a first conductivity type, a second doping region of a second conductivity type forming a pn-junction with the first doping region, a third doping region of the first conductivity type forming a main pn-junction with the second doping region, and a fourth doping region in contact with the third doping region, wherein the main pn-junction surrounds the third doping region from a top view on the first surface. The third doping region surrounds the fourth doping region in top view on the first surface. The third doping region includes straight semiconductor portions and curved semiconductor portions from the top view on the first surface. The doping concentration of the curved semiconductor portions increases from the main pn-junction to the fourth doping region.
- According to an embodiment, a method for manufacturing a lateral power semiconductor device includes providing a semiconductor body having a semiconductor substrate and a semiconductor layer on the semiconductor substrate, the semiconductor layer forming a first surface of the semiconductor body; forming a loop structure in the first surface having, from a top view, at least one curved semiconductor portion and at least one straight semiconductor portion having a plurality of switchable semiconductor cells, each switchable semiconductor cell having a drift region formed in the semiconductor layer, a drift control region formed in the semiconductor layer adjacent to the drift region, and an accumulation dielectric electrically insulating the drift region from the drift control region; and forming insulating layers between the drift control region and the semiconductor substrate to electrically insulate the drift control region of each switchable semiconductor cell from the semiconductor substrate; wherein the curved semiconductor portion is formed in the semiconductor layer and comprises an outer curved boundary and an inner boundary from the top view on the first surface, wherein the doping concentration of the curved semiconductor portion increases from the outer curved boundary to the inner boundary.
- Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
- The components in the figures are not necessarily to scale, instead emphasis being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings:
-
FIG. 1 illustrates a top view on a lateral power semiconductor device according to an embodiment; -
FIG. 2 illustrates an enlarged view of a portion of a lateral power semiconductor device according to an embodiment; -
FIG. 3 illustrates a vertical cross section through a curved semiconductor portion of a lateral power semiconductor device according to an embodiment; -
FIGS. 4A and 4B illustrate electrical field distributions across regions of the lateral power semiconductor device; -
FIGS. 5A to 5D illustrate switchable semiconductor cells of a lateral power semiconductor device according to an embodiment; -
FIGS. 6A to 6D illustrate processes for manufacturing a lateral power semiconductor device according to an embodiment; -
FIG. 7 illustrates a process for manufacturing a lateral power semiconductor device according to an embodiment; -
FIG. 8 illustrates a process for manufacturing a lateral power semiconductor device according to an embodiment; and -
FIGS. 9A and 9B illustrate a process for manufacturing a lateral power semiconductor device according to an embodiment. - In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practised. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, leading”, “trailing” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purpose of illustration and is in no way limiting. It is to be understood that other embodiments may be utilised and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. The embodiments being described use specific language, which should not be construed as limiting the scope of the appended claims.
- The term “lateral” as used in this specification intends to describe an orientation parallel to the main surface of a semiconductor substrate.
- The term “vertical” as used in this specification intends to describe an orientation, which is arranged perpendicular to the main surface of the semiconductor substrate.
- In this specification, a second surface of a semiconductor substrate is considered to be formed by the lower or back-side surface while a first surface is considered to be formed by the upper, front or main surface of the semiconductor substrate. The terms “above” and “below” as used in this specification therefore describe a relative location of a structural feature to another structural feature with consideration of this orientation.
- The terms “electrical connection” and “electrically connected” describes an ohmic connection between two elements.
-
FIGS. 1-3 depict a lateral power semiconductor device according to an embodiment.FIG. 1 illustrates a top view on a first surface 111 (seeFIG. 3 ) of asemiconductor body 110 of the lateral power semiconductor device. A firstmain electrode 131 and a secondmain electrode 132 are arranged on thefirst surface 111. The firstmain electrode 131 is disposed from, and surrounds, the secondmain electrode 132. - The
first electrode 131 includes at least twostraight sections first surface 111. The secondmain electrode 132 is arranged between the twostraight sections - The first and second
main electrodes main electrodes FIG. 1 .FIG. 2 , illustrating an enlarged section ofFIG. 1 without the first and secondmain electrodes first semiconductor region 141 which may be, for example a source region. Thefirst semiconductor region 141 is of a first conductivity type, which may be, for example, n-type. - According to an embodiment, the
first semiconductor region 141 may be at least partially omitted at the outer curved boundary.FIG. 2 shows thefirst semiconductor region 141 includingfirst sections 141 a forming straight regions andsecond sections 141 b, in this case, forming curved regions each of which connects respective two of thefirst sections 141 a. Thefirst sections 141 a can form the source regions of the cells of the lateral power semiconductor device. Thesecond sections 141 b are optional and do not need to be formed. The optionalsecond sections 141 b are marked by dashed lines. According to an embodiment and shown e.g., inFIG. 5A , in a part of the straight regions, e.g. in adoping region 126 as shown inFIG. 2 or at the end of drift control regions, thefirst semiconductor region 141 can be alternatively and/or additionally at least partially omitted. These regions where the doping of thesemiconductor region 141 is omitted in the straight regions, for example betweenadjacent regions 241 inFIG. 5A , can be understood as belonging to thesecond sections 141 b. - The
first semiconductor region 141, when including the first andsecond sections fourth semiconductor region 144, which may be of the first conductivity type to form a drain region, for example. When thefirst semiconductor region 141 includes only thefirst sections 141 a, thefourth semiconductor region 144 is disposed between thefirst sections 141 a of thefirst semiconductor region 141, as is the case when thefirst semiconductor region 141 completely surrounds thefourth semiconductor region 144. Thefourth semiconductor region 144, which may form a drain region, is in electrical contact with the secondmain electrode 132, which is drain metallization in this embodiment. Thefirst semiconductor region 141 is in electrical contact with the firstmain electrode 131, which is a source metallization in this embodiment. - Between the first
main electrode 131 and the secondmain electrode 132 there is aclosed loop structure 120 on thefirst surface 111 that includesstraight semiconductor portions 121 andcurved semiconductor portions 122, as best shown inFIG. 1 . Theclosed loop structure 120 typically completely surrounds thefourth doping region 144. - The
closed loop structure 120 is mainly formed by athird doping region 143 which may be of the first conductivity type. In the present embodiment, thethird doping region 143 is weakly n-doped having a doping concentration that is less than the doping concentration of thefourth doping region 144. Thethird doping region 143 typically forms a drift region of the lateral power device. Adjacent to thethird doping region 143 is asecond doping region 142, of the second conductivity type, i.e. of p-type, that forms a body region. A main pn-junction 145 is formed between thesecond doping region 142 and thethird doping region 143. Thesecond doping region 142 is arranged between thefirst doping region 141, and thethird doping region 143. Thefirst doping 141 region is arranged adjacent to thesecond doping region 142. - The main pn-
junction 145 can be considered as forming an outer border or outer curved boundary of theclosed loop structure 120, i.e., of thethird doping region 143. Thesecond doping region 142 andfirst doping region 141, although shown inFIG. 2 to form ring structures following the contour of the main pn-junction 145, can have shapes deviating from the course of the main pn-junction 145, for example in thecurved semiconductor portions 122. - According to an embodiment, the
first doping region 141 and/or thesecond doping region 142 may be formed by individual doping islands arranged substantially along the line of the main pn-junction 145 as shown inFIG. 2 . In this case, the course of the main pn-junction 145 can show some deviations compared toFIG. 2 , e.g., can include some wave-kind line. According to an embodiment, one or more of thefirst doping region 141 and/orsecond doping region 142 can be connected to the firstmain electrode 131. - For example, the
third doping region 143 may be formed as a ring structure having two main straight sections, corresponding to thestraight semiconductor portions 121, running parallel to each other and having thefourth doping region 144 disposed therebetween. Furthermore, thethird doping region 143 may include two semi-ring sections that correspond to thecurved semiconductor portions 122 and connect the straight sections so that thefourth doping region 144 is completely surrounded by thethird doping region 143. Thesecond doping region 142 may include twostraight sections 121 between which the straight sections of thethird doping region 143 are arranged. Along the outer boundary of thesemi-ring sections 122 of thethird doping region 143, islands of thesecond doping region 142 may be arranged. According to this embodiment, continuous pn-junctions 145 are formed between thestraight sections 121 of thesecond doping region 142 and thethird doping region 143. The pn-junction 145 along the outer boundary of the semi-ring sections of thethird doping region 143 includes respective sections formed by a respective island of the seconddoped region 142 and thesemi-ring sections 122 of thethird doping region 143. The space between adjacent islands of thesecond doping regions 142 is such that this space is completely depleted in reverse mode of the power device. - When the
second sections 141 b of thefirst doping region 141 are present, thesesections 141 b can cause latching during commutation of the power device. To avoid latching, thesecond sections 141 b may be omitted. Furthermore, when thesecond sections 141 b of thefirst doping region 141 are present, a portion of the electron charge emanating from thefourth doping 144 forming a drain region is drained through thesecond sections 141 b, as thesecond sections 141 b form together with thesecond doping region 142 and the third doping region an npn-transistor. In this case, the surplus of charges in thesemi-ring sections 122 of thethird doping region 143 is beneficially lowered. Of the above described two processes, the process that dominates depends on the actual doping and/or geometrical relations. Thus, by appropriately selecting the doping relations and/or geometry of the structure, latching can be avoided even when thesecond sections 141 b are formed to reduce the surplus of charges. - A junction between the
third doping region 143 and thefourth doping region 144, for example an nn+-junction, may be considered to form aninner boundary 147 of theclosed loop structure 120. - The geometrical arrangement of the
first doping region 141 and thefourth doping region 144 is not limited to the embodiment shown herein. For example, each of the first andfourth doping region first surface 111, a fin-like shape wherein the fins of each doping region interdigitate with the fins of the other doping region. Irrespective of the actual geometry of thefirst doping region 141 and thesecond doping region 144, both regions remain spaced apart from each other with theclosed loop structure 120 arranged between the first andsecond doping region - The
closed loop structure 120 includes a plurality ofswitchable semiconductor cells 140 arranged in thestraight semiconductor portions 121 between thefirst semiconductor region 141 and thefourth semiconductor region 144 as best shown inFIG. 2 . Theswitchable semiconductor cells 140 are therefore also arranged between the firstmain electrode 131 and the secondmain electrode 132. Theswitchable semiconductor cells 140 provide a controllable conductive path between the firstmain electrode 131 and the secondmain electrode 132 as will be described further below. - As shown in
FIG. 2 , adoping region 126, which does not include switchable semiconductor cells, is arranged between thesemiconductor cells 140 and thecurved semiconductor portion 122 so that thecurved semiconductor portion 122 is spaced from thesemiconductor cells 140. Thedoping region 126 is part of thestraight portion 121 in this embodiment. - The
curved semiconductor portion 122 has a doping concentration increasing from the firstmain electrode 131 to the secondmain electrode 132. This is illustrated inFIG. 2 by the dashed half-circles with increased density towards thefourth doping region 144. The doping concentration of thecurved semiconductor portion 122 can increase by a factor of about 1/R with R being the distance from an imaginary geometrical center arranged in thefourth doping region 144. According to an embodiment, the doping concentration in thecurved semiconductor portion 122 may have a substantially stepwise characteristic with a lowerdoped part 143 a and a higherdoped part 143 a. - In the present embodiment, the
closed loop structure 120 surrounding thefourth doping region 144 includes at least twocurved semiconductor portions 122 and at least twostraight semiconductor portions 121 which comprise a plurality ofswitchable semiconductor cells 140. The number of thecurved semiconductor portions 122 and thestraight semiconductor portions 121 is, however, not limited to two and depends on the shape of the first andfourth doping region fourth doping regions curved semiconductor portions 122 and thestraight semiconductor portions 121 is larger than two. For example, when thefourth semiconductor region 144 has a substantially square-like shape with rounded edges, the closed loop structure includes fourcurved semiconductor portions 122 and fourstraight semiconductor portions 121. - The geometrical shape of the
closed loop structure 120 of the present embodiment can be described as stadium having twostraight semiconductor portions 121 which are arranged parallel to each other and which are connected by the substantially semi-circularcurved semiconductor portions 122. Thefourth doping region 144 is a rather elongated region with rounded edges, one of which is shown inFIG. 2 . - The course of the electrical field during blocking state is mainly defined by the course of the main pn-
junction 145, the outer shape of thefourth doping region 144, and the doping relation of thethird doping region 143. Contrary to other approaches that place active cells into curved regions to maximize the total current of the lateral semiconductor device during the on-state, the present embodiment does not include active semiconductor cells in thecurved semiconductor portions 122. - During blocking operation, there is a large voltage difference between the
first doping region 141, or thesecond doping region 142 when thefirst doping region 141 does not includesecond sections 141 b, and thefourth doping region 144, since thesemiconductor cells 140 are in blocking state and do not provide a conductive path between thefirst doping region 141 and thefourth doping region 144. The first andsecond doping regions main electrode 131. During static blocking operation, the maximum of the electric field is located at themain pn junction 145. The field lines of the electrical field between thesecond doping region 142, the semiconductor substrate (not shown inFIG. 2 ) and thefourth doping region 144 are three-dimensionally bent in thecurved semiconductor regions 122. Thus, there is a local increase of the electrical field in thecurved semiconductor regions 122 in comparison to thestraight semiconductor regions 121. The shape and doping values of thethird doping region 143 and thefourth doping region 144 may be further used to increase the electric field at the main pn-junction 145 in thecurved semiconductor regions 122 in comparison to thestraight semiconductor regions 121. Therefore, the value of the electric field when avalanche multiplication starts, is first reached in thecurved semiconductor regions 122. - When avalanche occurs in the
curved semiconductor region 122, for example close to thesecond semiconductor region 142, charge carriers are generated and separated by the electrical field. Assume that thefourth doping region 144 is on a higher electrical potential than thefirst doping region 141 andsecond doping region 142 during blocking mode. Thethird doping region 143 forms a drift region and is weakly n-doped. Since the absolute value of the electric field decreases proportionally to the charge in the space charge area, the slope of the field curve in the lowerdoped part 143 a of thethird doping region 143 is lesser as compared to the higherdoped part 143 b. Free electrons are generated in thethird doping region 143 by the avalanche effect and move to thefourth doping region 144 on account of the prevailing electrical field between thefourth doping region 144 and thesecond doping region 142. Due to the geometrical effect of the curvature, the local exaggeration of the current density and thus the electron density is mainly close to thefourth doping region 144. This is beneficial particularly when thefourth doping region 144 forms a drain region. In this case, the local exaggeration of the electrical field is remote from the main pn-junction 145. Thus, an increased amount of electrons towards thefourth doping region 144 partially compensate the positive net charge of the donators in the n-dopedthird doping region 143 andfourth doping region 144. The reduction of the positive net charge results in a deviation of the electrical field in comparison to the case in which no current flows and an in which the electrical field distribution is only defined by the background doping distribution. These two cases are schematically illustrated inFIG. 4A , assuming a homogeneous electron current density. Taking into account the increasing electron current density and thus increasing negative charge density, the gradient of the electric field approaching the fourthdoped region 144 decreases in a non-linear way. - The vertical dashed line in
FIG. 4A indicates the location of the junction between thethird doping region 143 and thefourth doping region 144. The solid line corresponds to the case where no current of generated electrons flows, i.e., where the electrical field is defined by the background doping p only, which is assumed to be constant in each of therespective doping regions third doping region FIG. 4A . - It should be noted here that the “accumulation” of electrons is a dynamic process. The density of the electrons is higher close to the
fourth doping region 144 because electrons, which are generated in a greater distance from junction between the third andfourth doping region fourth doping region - The reduced positive net charge results in a reduction of the slope of the electrical field as illustrated in
FIG. 4A which shows that the grad(E) is slightly reduced. As a consequence, the blocking voltage increases. The maximum blocking voltage is provided when the electrical filed is constant (grad(E)=constant). In this case, the counter charge for the charge in thesecond doping region 142 is delivered in total by the high donator density of thefourth doping region 144 and lead to an almost abrupt reduction of the electric field. The increased blocking voltage in thecurved semiconductor portion 122 in turn acts against the avalanche so that a self-stabilising effect is observed. - Assume that the current caused by avalanche increases. As a consequence, to maintain the blocking state, the voltage between the first and the
fourth doping region third doping region 143, would also rise. This can lead to a situation where the maximum of the electrical field is close to or at the junction between the third and thefourth doping region - To prevent this and to allow higher avalanche currents without destruction of the device, the background doping concentration of the
curved semiconductor portions 122 can be raised. Furthermore, a doping concentration increasing towards thefourth doping region 144 further improves the avalanche robustness as an increasing doping concentration at least partially compensates the geometrical factor of the curved electrical field lines in thecurved semiconductor region 122. For example, the doping concentration in thethird doping region 143 can increase with 1/R with R being a distance from a geometrical center in thefourth doping region 144 close to the junction between thefourth doping region 144 and thethird doping region 143. - According to a particular embodiment, the
curved semiconductor portion 122 can have an outer boundary which is mainly defined by the main pn-junction 145. This outer boundary can be curved in general, for example or can be semi-circular as shown inFIG. 2 . With reducing distance R from the geometrical center of this semi-circle, the doping concentration increases. - The
curved semiconductor portion 122 can have an inner boundary defined by the junction between thethird doping region 143 and thefourth doping region 144. The inner boundary may be curved, for example semi-circular, as shown inFIG. 2 . The increasing doping concentration within thethird doping region 143 may be adapted to follow the bending radius of the inner boundary. In the case of a semi-circular inner boundary as shown inFIG. 2 , the bending radius is constant. In other cases, the bending radius may increase or decrease. The increase of the doping concentration in thethird region 143 may then be adapted accordingly. - The increasing doping concentration results in an electric field distribution as indicated by the dashed line in
FIG. 4B , which shows, as comparison, the electrical field distribution for a constant background doping (solid line) at the same blocking voltage applied between thesecond doping region 142 and thefourth doping region 144. The blocking voltage, i.e., the integral over the electric field strength, or in other words the onset of avalanche generation, can be reduced when locally increasing the background doping towards the junction between thethird doping region 143 and thefourth doping region 144. - For illustration purposes only, the background doping of lateral device having a rated blocking voltage of 600 V is less than about 1.4*1014/cm3. This doping concentration prevails also at the main pn-
junction 145 in thecurved semiconductor portions 122. The doping concentration increases towards the junction between thethird doping region 143 and thefourth doping region 144 to a value of about 1015 to 1016/cm3. Typically, the doping concentration increases from the main pn-junction 145 to the junction between thethird doping region 143 and thefourth doping region 144 by a factor of about 5 to 100. - On account of the increased background doping concentration in the
third doping region 143 in thecurved semiconductor portion 122, the maximum permissible avalanche current increases. On the other hand, the blocking voltage at which avalanche occurs reduces. This is beneficial since the avalanche breakdown will occur in thecurved semiconductor portions 122 and not in theswitchable semiconductor cells 140. Furthermore, as described above, since the avalanche in thecurved semiconductor portion 122 is self-stabilising, the lateral semiconductor device exhibits an improved avalanche robustness. Thecurved semiconductor portions 122 can therefore be referred to as “avalanche regions”. - To ensure that the
switchable semiconductor cells 140 forming the active region of the lateral semiconductor device, and the structures of thecells 140, for example oxide layers, are not influenced by the avalanche breakdown, theregion 126 is provided between thecurved semiconductor portion 122 and theswitchable semiconductor cells 140 in thestraight portion 121 as shown inFIG. 2 . The lateral width “a” of theregion 126 can be between about 5% to 100% of the distance in thestraight semiconductor portions 121 between thesecond semiconductor region 142 and thefourth semiconductor region 144. The distance between thesecond semiconductor region 142 and thefourth semiconductor region 144 is depending on the desired blocking capability of a lateral semiconductor switch and may be estimated to be approximately 7.5 to 15 μm per 100V. For a device with a rated blocking voltage of 600V the distance between thesecond semiconductor region 142 and thefourth semiconductor region 144 should be in the range of about 45 μm to 90 μm and thus the value of “a” between about 2.25 μm and about 90 μm. Thesemiconductor region 126 has a doping concentration that is less than the doping concentration in thecurved semiconductor portion 122 and can correspond to the background doping of theswitchable semiconductor cells 140. - According to an embodiment, the peak doping concentration of the background doping within the
third doping region 143 of thecurved semiconductor portion 122 is spaced from thefirst surface 111, as shown inFIG. 3 .FIG. 3 is a vertical cross section through thecurved semiconductor portion 122 along the radius R shown inFIG. 2 . In lateral direction, i.e., from the main pn-junction 145 to the junction between thethird doping region 143 and thefourth doping region 144, the doping concentration increases, for example according to 1/R. The peak doping concentration for a given location X, however, is spaced from thefirst surface 111. The location of the peak doping concentration is indicated by the dashed line. - Such a doping profile can be obtained by implantation with an appropriately selected implantation energy which implants the dopants into a given depth which will later corresponds to the location of the peak doping concentration.
- When the first
main electrode 131 forms a source metallization and the second main electrode 132 a drain metallization, the outer rim of the lateral semiconductor device is at source potential while the center of the lateral semiconductor device is at drain potential. Control circuits for controlling the lateral semiconductor device can therefore be integrated into thesemiconductor body 110 without additional level shifters. Furthermore, as shown inFIG. 3 , the second doping region forming a body region can be in electrical continuity with a p-dopedsubstrate 149 forming a lower part of thesemiconductor body 110. This improves electrical insulation of the lateral semiconductor device, facilitates integration, and ensures that the rim and the lower side formed by asecond surface 112 of thesemiconductor body 110 is in the same electrical potential. According to an embodiment and not shown inFIG. 3 , the electrical contact between the p-dopedsubstrate 149 and thesecond doping region 142 may be done without continuous doping as shown inFIG. 3 but with other means like bond wires, soldered clips or other electrical connections outside thesemiconductor body 110. - In a particular embodiment, the
third doping region 143 in thecurved semiconductor portion 122 forms a pn-junction with the p-dopedsubstrate 149. This improves heat dissipation for the heat generated during avalanche. - With respect to
FIGS. 5A to 5D , the structure of theswitchable semiconductor cells 140 according to an embodiment is described. Theswitchable semiconductor cells 140 are so-called TEDFETs in this embodiment and include twofunctional regions FIG. 5A .Functional region 200 forms a “normal” FET whilefunctional region 300 forms a drift control cell for forming and controlling an accumulation channel in the FET. - The structure of the FET (functional region 200) is illustrated in
FIG. 5B showing a vertical section along line BB inFIG. 5A . - The FET cell is formed in a
semiconductor body 210 including asemiconductor substrate 249 which may be, for example, p-doped and an n-dopedsemiconductor layer 248 formed on thesemiconductor substrate 249.Semiconductor layer 248 can be formed using e.g., epitaxial growth. The n-doping of thesemiconductor layer 248 forms the background doping of theswitchable semiconductor cells 140. Thesemiconductor body 210 has afirst surface 211 and asecond surface 212 opposite thefirst surface 211. Thesemiconductor layer 248 extends to thefirst surface 211 and forms thethird doping region 143 as described above, i.e., forms adrift region 243. A p-dopedregion 242, which is part of thesecond doping region 142, is formed in thedrift region 243. The p-dopedregion 242 functions as a body region and forms the main pn-junction 245 with thedrift region 243. A highly n-dopedsource region 241, being part of thefirst doping region 141, is embedded in thebody region 242. A highly n-dopeddrain region 244, being part of thefourth doping region 144, is embedded in thedrift region 243 and forms an nn+ junction with thedrift region 243. Asource metallization 231, being part of the firstmain electrode 131, is in electrical contact withsource region 241 and thebody region 241. Furthermore, adrain metallization 232, being part of the secondmain electrode 132, is in electrical contact with thedrain region 244. - Above
body region 242, and insulated therefrom by agate dielectric 252, there is arranged agate electrode 233 forming part of a third electrode of the lateral power semiconductor device. Thegate electrode 233 and thedrift region 243 are covered by a comparablythick insulation layer 251 insulating thegate electrode 233 and thedrift region 243 against thesource metallization 231 and thedrain metallization 232. - The p-doped
body 242 and p-dopedsemiconductor substrate 249 can be in electrical contact, for example by extending thebody region 242 along an outer edge or rim of thesemiconductor body 210 as shown inFIG. 3 . - It should be noted that
FIGS. 5A to 5D only show the structure of theswitchable semiconductor cells 140 and not the complete device. The left side inFIGS. 5A to 5D faces to the outer rim of thesemiconductor body 210 while the right side faces the center of the lateral semiconductor device defined by thefourth doping region 144. - Adjacent to the
FET cell 200, there is formed adrift control cell 300 which is insulated from theFET cell 200 by anaccumulation dielectric 350 as best shown inFIGS. 5A and 5C withFIG. 5C being a cross section along line CC inFIG. 5A . - The
drift control cell 300 of the TEDFET is formed in thesemiconductor body 310 having thefirst surface 311, thesecond surface 312, thesemiconductor substrate 349, and thesemiconductor layer 348 as described above. However, distal to theFET cell 200, an insulatinglayer 353 is formed between the p-dopedsemiconductor substrate 349 and the n-dopedsemiconductor layer 348. Thesemiconductor layer 348 can be formed using e.g., epitaxial growth. Together with theaccumulation dielectric 350, the insulatinglayer 353 completely electrically insulates thedrift control cell 300 from theadjacent FET cell 200 and thesemiconductor substrate 349. This is best shown inFIG. 5D showing a three-dimensional illustration of aswitchable semiconductor cell 140 including aFET cell 200 with an adjacentdrift control cell 300. - The
drift control cell 300 includes a p-dopedfirst zone 342 and forming a main pn-junction 345 with adrift control region 343 formed by the n-dopedsemiconductor layer 348. A highly n-dopedsecond zone 344 is formed in thesemiconductor layer 348 and forms an nn+-junction with thedrift control region 343. Thefirst zone 342 is contacted by afirst terminal 331 while thesecond zone 344 is contacted by asecond terminal 332. Thefirst terminal 331 can be electrically connected to thesource metallization 231 through a not shown diode element. Similarly, thesecond terminal 332 can be electrically to thedrain metallization 232 through a not shown diode. - According to an embodiment, the insulating
layer 353 may also extend below the FET cell insulating thedrift region 243 from thesubstrate 212. According to a further embodiment, the insulatinglayer 353 additionally or alternatively may also extend below thecurved semiconductor portions 122 insulating thedoping region 143 from thesubstrate 212. Insulating thedrift region 243 and/or thedoping region 143 inhibits the injection of carriers into thesubstrate 212 during operation of the body diode and thus may further improve the dynamic behaviour of the body diode. On the other hand, thermal performance is reduced due to the reduced heat flow through the insulatinglayer 353 compared to a direct contact of semiconductor material. - A comparably thick
insulating layer 351, which may be continuous with the insulatinglayer 251, covers thedrift control region 343 and provides insulation against the first and thesecond terminals - Due to action of the
drift control region 343, an accumulation channel is formed in thedrift region 243 along theaccumulation dielectric 350 to reduce the on-state resistance in the conducting state of the lateral power semiconductor device. - As shown in
FIG. 5A , theswitchable semiconductor cells 140 are arranged adjacent to each other so thatFET cells 200 and driftcontrol cells 300 are alternatingly arranged in thestraight semiconductor portion 121 of the lateral power semiconductor device. - As described above, avalanche breakdown is confined or restricted to the
curved semiconductor portions 122 and, hence, does not influence theswitchable semiconductor cells 140 and particularly theaccumulation dielectric 350. Therefore, trapping of hot charge carriers, which are generated during avalanche breakdown, in theaccumulation dielectric 350 can be significantly reduced. This effect is further improved when the peak doping concentration of thethird doping region 143 in thecurved semiconductor portion 122 is spaced from thefirst surface 111 as in this case the likelihood of hot carrier injected into the insulatinglayer curved semiconductor portion 122, is also reduced. - The above described arrangement of the lateral power semiconductor device further exhibits an improved commutating characteristic so that the lateral power semiconductor device has improved avalanche robustness and an improved commutating characteristic.
- During commutation, charge carriers stored in the device must be removed to bring the device into the blocking state. When the body-diode of the
FET cells 200 is operating, as is the case for the structure shown inFIG. 5B , thedrift region 243 is flooded with charge carriers. In the region of theswitchable semiconductor cells 140, a large portion of the current is guided as channel current along theaccumulation dielectric 350. Furthermore, the body-diodes, when suitably dimensioned to be able to handle large body diode currents, also causes thethird doping region 143, corresponding to thedrift region 243, to be flooded with charge carriers. When the device is now brought into the blocking state, the doping concentration in thecurved semiconductor portion 122 increasing towards to thefourth doping region 144 acts as a field-stop region preventing the electrical field from quickly forwarding to the fourth doping region 144 (drain region 244). Hence, the charge carriers remain for a longer time in thethird doping region 143 which leads to a more gentle commutation. - Furthermore, the current density for removing the positive charge carriers (holes) is reduced by the geometrical effect of the
curved semiconductor portion 122 as the hole current is towards the outer boundary of thecurved semiconductor portion 122. This leads to a higher switching robustness which is determined mainly by the hole current density. Such behavior is beneficial for bridge circuits and resonant applications, where the body diode can be subjected to hard commutation under specific conditions which may lead to a destruction of the device. - The above described lateral power semiconductor device allows the
semiconductor body 110, i.e. thesecond side 112 of thesemiconductor body 110, to be at the source potential. Furthermore, driving circuits can be easily integrated into thesemiconductor body 110 laterally outside of the active regions of the power semiconductor device since the outer regions, as well as the backside of thesemiconductor body 110, are on the same electrical potential. - Alternatively, the
fourth semiconductor region 144 can be on source potential while the first and/or thesecond semiconductor region - In a further aspect, a reverse blocking transistor can be integrated in the regions of the
switchable semiconductor cells 140, for example by forming an optionaladditional doping region 246 having a doping type opposite to the doping type of thedrain regions 244 and which is electrically connected to thedrain electrode 232 and isolates thedrain region 244 from thedrift region 243. The electrical connection inFIG. 5D is indicated by aline 247, but can be realized e.g., by a grooved contact for thedrain electrode 232 or by theadditional doping region 246 penetrating a part of thedrain regions 244 reaching thefirst surface 211. Without applying a voltage to thedrift control region 343, a lateral IGBT structure is thus provided that floods thedrift region 243 when thegate 233 is charged. This results in a reduction of the drain voltage, and the voltage of thedrift control region 343 is able to generate a continuous channel formed as accumulation channel in thedrift region 243 and as inversion channel in theadditional doping region 246. This modification improves the pulse current robustness of the lateral power semiconductor device. Furthermore, the reverse blocking capabilities are improved which drives the reverse current into thecurved semiconductor portions 122 of thethird doping region 143 having doping relations which are tailored, particularly due to the increasing doping concentration, for optimal diode performance. Furthermore, active rectifier operation of the lateral power semiconductor device is also possible by generating a conductive channel along theaccumulation dielectric 350 and increasing the voltage applied to thegate electrode 233. - With reference to
FIGS. 6A to 6D , a method for manufacturing a lateral power semiconductor device is described. - A
semiconductor body 410 having asemiconductor substrate 449 and asemiconductor layer 448 on thesemiconductor substrate 449 is provided. Thesemiconductor layer 448 can be an epitaxially grown layer of a doping type opposite to the doping type of thesemiconductor substrate 449. In this case, thesemiconductor layer 448 forms a pn-junction with thesemiconductor substrate 449. Thesemiconductor layer 448 can also be of the same doping type as thesemiconductor substrate 449. - The
semiconductor layer 448 extends to and forms afirst surface 411 of thesemiconductor body 410 as illustrated inFIG. 6A . - In a further process, a plurality of
trenches 460 is formed in thesemiconductor layer 448. This is shown in the left part ofFIG. 6A . Thetrenches 460 run along the regions where thedrift control regions 343 are formed in subsequent processes. For eachdrift control region 343, arespective trench 460 can be formed. The mesa regions betweenadjacent trenches 460 form later thedrift regions 243. - The
trenches 460 can extend, in a top view as for example shown inFIG. 2 , from a region above the main pn-junction 145 to below the main pn-junction 145 when referring to the orientation ofFIG. 2 . Thetrenches 460 therefore also extend through the region where later thefourth doping region 144 is formed. As shown in the embodiment ofFIG. 2 , thetrenches 460 may extend along thesemiconductor cells 140 from the upper edge of thesemiconductor body 110 to the lower edge of thesemiconductor body 110. As a plurality of lateral power semiconductor devices is formed on a wafer, thetrenches 460 maybe formed to extend to regions which later form the edges of the lateral power semiconductor devices. Alternatively, thetrenches 460 may extend to regions just outside of thefirst semiconductor region 141. - In a further process, as illustrated in the left part of
FIG. 6B , thesemiconductor body 410 is tempered at an elevated temperature in a deoxidizing atmosphere to cause surface migration of the semiconductor material of thesemiconductor layer 448 until thetrenches 460 are covered by the semiconductor material to formrespective cavities 461 that are laterally spaced apart from each other. Since the “reflow” of the semiconductor material results in a mono-crystalline material, the extension of the trenches into other regions than the regions, where the drift control regions are formed, is uncritical. - As an illustrative example, the
trenches 460 can have a lateral width of about 300 nm to about 3000 nm and a length of about 30 μm to about 120 μm for a device with 600V blocking capability. The minimal length of the trenches can correspond with the length IT of the lateral transistor cell which is connected to the desired blocking voltage VB of the lateral transistor. In an embodiment, the IT in μm is about 5 . . . 20*VB/100V. However the trenches can be much longer than these values and can be formed reaching through one or more chips or even through the whole wafer. The above width changes in the tempering process and the initial width of thetrenches 460 should be adapted to allow for this change. The pitch of thetrenches 460 can be in the range of several hundred nm which reliably prevents thatadjacent trenches 460 merge during the tempering process. The depth of thetrenches 460 can be in the range of several μm. These dimensions are only illustrative and not limiting. - The process conditions during tempering can be adjusted according to specific needs. For illustration purposes, the temperature can be in a range from about 1000° C. to about 1150° C. when the
semiconductor layer 448 is a silicon semiconductor. In this temperature range, the semiconductor material of thesemiconductor layer 448 begins to “flow” and thetrenches 460 start to get closed by the flowing material. On the other hand, thetrenches 460 widen in their lower parts due to the flowing material. Thetrenches 460, however, are spaced apart from each other by a lateral distance which is sufficient that the wideningtrenches 460 in their lower parts do not merge. - The tempering can be carried out, according to an embodiment, in a deoxidizing atmosphere, for example in a hydrogen atmosphere at low pressure, for example at about 10 Torr (about 1.3·103 Pa). The duration of the tempering process can be varied and can be selected in view of the temperature. A typical tempering time at the desired tempering temperature is about 10 min.
- In a further process, as illustrated in the left part of
FIG. 6C , avertical channel 462 is formed extending from thefirst surface 411 to provide an access to thecavities 461. According to an embodiment, onerespective channel 462 can be formed to extend to onerespective cavity 461. According to another embodiment, onechannel 462 can provide access to two ormore cavities 461. - The
cavities 461, which assume the shape of hollow pipes in the left part ofFIG. 6C , have internal surfaces. In a further process, as illustrated in the left part ofFIG. 6D , the internal surfaces of thecavities 461 are oxidized to form respective insulatinglayers 470, which later form the insulating layers 353. Thechannels 462 provide the access for the oxidising atmosphere to diffuse into thecavities 461. - The
channels 462 are typically formed in regions outside the active region of the power semiconductor device. For example, thechannels 462 can be formed in the regions of the kerf or sawing frame along which thesemiconductor body 410 is finally cut to separate the power semiconductor devices from each other. - The left parts of
FIGS. 6A to 6D illustrate the formation of separate insulatinglayers 470, which are only formed in the regions below thedrift control regions 343. In this case, the mesa regions between thetrenches 460 remain in contact with thesemiconductor substrate 449. For example, thetrenches 460 may be formed to extend as far as thesemiconductor substrate 449 so that the respective insulatinglayers 470 are formed in the interface region between thesemiconductor substrate 449 and the semiconductor layer orsemiconductor layer 448. The mesa regions that later form the drift regions can form respective pn-junctions with thesemiconductor substrate 449. These pn-junctions insulate the drift regions from thesemiconductor substrate 449. - Leaving the drift regions in contact with the
semiconductor substrate 449 is beneficial for heat transfer from the lateral transistor cells to a heat sink, which is typically connected to the back side of thesemiconductor substrate 449, as the semiconductor material of the drift regions (mesa regions) in continuous with thesemiconductor substrate 449. To further improve heat transfer, thetrenches 460 may only be formed in regions of the laterstraight semiconductor portions 121. In other regions such as thecurved semiconductor portions 122 and, for example, below thefourth semiconductor region 144, notrenches 460 are formed so that the semiconductor material also remains continuous in these regions and portions, respectively. - In addition to improved heat transfer, the cavities 261, which remain hollow even after formation of the insulating
layer 471, reduce the capacitive coupling of thedrift control region 343 with thesemiconductor substrate 449. - In a further embodiment, as illustrated in the right parts of the
FIGS. 6A to 6D , a common insulatinglayer 471 is formed below thedrift control regions 343 and thedrift regions 243. A plurality of closely spacedtrenches 465 is formed in thesemiconductor layer 448. Whether a trench transforms to a single cavity or adjacent trenches merge to a common cavity depends on the lateral spacing, i.e. pitch, of the trenches. When arranging a plurality of closely spacedtrenches 465 in an array, acavity 466 is formed that has, in top view, the 2-dimensional extension of the array. Thecavity 466 may have a plane shape as illustrated inFIG. 6B . For example, a rectangular array of closely spacedtrenches 465 form a substantiallyrectangular cavity 466 with rounded corners (seen in top view) while a row of closely spacedtrenches 465 forms a substantially elongated cavity. Therefore, by selecting the arrangement of the trenches 108, virtually any cavity arrangement and shape can be formed. - In further processes, as illustrated in the right parts of the
FIGS. 6C and 6D , avertical channel 467 is formed to provide access for an oxidising atmosphere to thecavity 466 to form an insulatinglayer 471 on the internal surfaces of thecavity 466. Thechannel 467 is typically formed in regions outside the active region of the power semiconductor device and can be sited arbitrarily in the region of thecavity 466. For example, thechannel 467 can be formed in the regions of the kerf or sawing frame along which thesemiconductor body 410 is finally cut to separate the power semiconductor devices from each other. Heat transfer from the lateral transistor to the heat sink is impaired by using a cavity also underneath thedrift regions 243. However, the capacitive coupling between thedrift regions 243 and thesubstrate 449 is reduced. - According to an embodiment, a compromise between thermal performance and capacitive coupling of the lateral transistor may be done by combining
tubular cavities 461 only under thedrift control regions 300, e.g., in an area closer to the source regions of the lateral device, and a twodimensional cavity 466 under bothdrift regions 200 and driftcontrol regions 300, e.g., in an area closer to drain regions. In this case, the number ofchannels - By placing the
cavity 466 under the curved semiconductor regions it can be avoided that electrons or holes generated in diode operation of the lateral power semiconductor device or during avalanche can reach the semiconductor substrate and thus can reach other portions of the device. - In further processes, a plurality of
switchable semiconductor cells 140 is formed as illustrated inFIGS. 5A to 5D . Eachswitchable semiconductor cell 140 includes adrift region 243 formed in thesemiconductor layer 448, particularly in the mesa regions between the regions where thetrenches 460 were formed. Thedrift control regions 343 are formed in thesemiconductor layer 448 adjacent to thedrift region 243 and above the insulating layers 470. Theaccumulation dielectrics 350 are formed between thedrift region 243 and thedrift control region 343, for example by etching thin trenches. The etching stops on the insulatinglayer 470. The thin trenches are subsequently filled with an insulating material. - The
semiconductor cells 140 form astraight semiconductor portion 121 of theloop structure 120 having, in top view on the first surface, at least onecurved semiconductor portion 122 and at least onestraight semiconductor portion 121. - In a further process, the
curved semiconductor portion 122 is doped so that the doping concentration of thecurved semiconductor portion 122 increases from the outercurved boundary 145 to theinner boundary 147. This can be, for example, done using one or several implantation masks. To reduce the number of process steps, the doping of thecurved semiconductor portion 122 can be done with ion implantation through windows of a mask and a subsequent annealing step to reach diffusion of the dopant. The maximum doping concentration can be reached without masking the ion implantation which can be done e.g., close to theinner boundary 147. On the way to the outercurved boundary 145, the density of the windows in the mask is reduced thus reducing the mean amount of doping atoms implanted into the semiconductor material per area. The minimum doping concentration can be reached by completely blocking the ion implantation, i.e., without opening windows in the mask. This process can be repeated one or more times. From the position of integration it is desirable to use ion implantation steps and masking steps which are anyway needed in the production of the semiconductor chip. - An example is given in
FIG. 8 , which shows animplantation mask 880 having a plurality ofwindows FIG. 8 indicate the location of theouter boundary 145 and theinner boundary 147 of thecurved portions 122 formed by portions of thethird doping region 143. The number, size and shape of thewindows 881 may vary, for example in radial direction while keeping the density constant in circumferential direction for a given radius. Aninner window 882 can be formed as a semi-circular ring. By varying at least one of the number, size and shape of thewindows 881, the implantation density can be locally adjusted. With a subsequent annealing step, the implanted dopants diffuse to smooth the implantation pattern defined by themask 880. When using small-sized windows, the local variation of the resulting doping can be even better controlled and the duration and/or temperature of the subsequent annealing step can be reduced. - According to another embodiment, as illustrated in
FIGS. 9A and 9B , afirst mask 901 is provided covering an outer region of thecurved semiconductor portion 122, forexample region 143 a shown inFIG. 2 , and leaving an inner region of thecurved semiconductor portion 122, forexample region 143 b, unmasked. Thefirst mask 901 includes thefirst window 981. Dopants are implanted using thefirst mask 901 as doping mask. Then, asecond mask 902 having asecond window 982 is formed. Thesecond window 982 leaves a portion of the outer region adjoining the inner region unmasked. According to an embodiment, the size of thesecond window 982 can be larger than the size of thefirst window 981 and extends further to the outercurved boundary 145. Thesecond mask 902 is used as implantation mask during a further implantation process. Hence, by increasing the size of thesecond window 982 relative to thefirst window 981 towards the outercurved boundary 145, the total amount of dopants that are implanted into thecurved semiconductor portion 122 is larger towards theinner boundary 147 than towards theouter boundary 145. - By using the first and
second mask inner boundary 147 to the outercurved boundary 145 can be obtained. When using more than two masks, the number of steps in the doping profile may be increased. - The first and
second masks fourth doping region 144, an optional field-stop layer, or thefirst doping region 141. Hence, by appropriately combining implantation steps, the number of lithographic steps can be kept as small as possible. - According to several embodiments, the
mask windows FIG. 8 ,FIGS. 9A and 9B can be permutated in all combinations. As an example windows like e.g., 881 may be used also in thefirst mask 901 and/or thesecond mask 902 additionally or alternatively to abigger window second mask 902 and thefirst mask 901 can have overlapping windows likewindow 981 andwindow 982 shown inFIGS. 9A and 9B . However, the window of thesecond mask 902 may be located only over masked areas of thefirst mask 901. Of course, more than two masks can be used. - With reference to
FIG. 7 , a further embodiment for manufacturing a lateral power semiconductor device is described. In this embodiment, the drift regions and the drift control regions are formed in a membrane of thesemiconductor body 410. The insulation to the backside can be provided by a hollow recess and/or an insulating layer formed in the recess. This avoids, in diode operation of the lateral power semiconductor device, the electron-hole pairs generated during avalanche from reaching the semiconductor substrate and reaching other portions of the device. - As illustrated in
FIG. 7 , arecess 480 is formed, for example etched, in thesecond surface 412 of thesemiconductor body 410. Therecess 480 extends bottom regions of thedrift control regions 343 and thedrift regions 243. - In a further process, an insulating
layer 471 may be formed on exposed surface of therecess 480. The remaining space of the recess can be left unfilled or can be filled by a material, such as a semiconductor material or an insulator like e.g., ceramics or a polymer which may include other particles, even metal, which improves heat dissipation. When leaving therecess 480 unfilled, the empty recess provides the insulation even without any extra insulating layer. Hence, theempty recess 480 can form an insulating layer. - As shown in
FIG. 7 , the insulatinglayer 471 and/or therecess 480 insulates thedrift regions 243 and thedrift control regions 343 from any further material which can later be formed on thesecond side 412 of thesemiconductor body 410. - Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
- As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
- With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
Claims (27)
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US13/873,994 US9202910B2 (en) | 2013-04-30 | 2013-04-30 | Lateral power semiconductor device and method for manufacturing a lateral power semiconductor device |
CN201410177306.4A CN104134692B (en) | 2013-04-30 | 2014-04-29 | Lateral direction power semiconductor devices and the method for manufacturing lateral direction power semiconductor devices |
DE102014106107.1A DE102014106107B4 (en) | 2013-04-30 | 2014-04-30 | LATERAL POWER SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING A LATERAL POWER SEMICONDUCTOR ELEMENT |
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US7115946B2 (en) * | 2000-09-28 | 2006-10-03 | Kabushiki Kaisha Toshiba | MOS transistor having an offset region |
DE10211543B4 (en) | 2002-03-15 | 2005-06-30 | Infineon Technologies Ag | Circuit arrangement with a field effect transistor and method for operating the circuit arrangement |
DE10339488B3 (en) | 2003-08-27 | 2005-04-14 | Infineon Technologies Ag | Lateral semiconductor component with at least one field electrode formed in drift zone extending laterally between doped terminal regions |
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US7319256B1 (en) | 2006-06-19 | 2008-01-15 | Fairchild Semiconductor Corporation | Shielded gate trench FET with the shield and gate electrodes being connected together |
DE102006043485B4 (en) | 2006-09-15 | 2008-11-27 | Infineon Technologies Ag | Power semiconductor module and method for operating a power semiconductor module with at least one controllable by field effect semiconductor device |
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