US20140312945A1 - Delay Locked Loop - Google Patents

Delay Locked Loop Download PDF

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Publication number
US20140312945A1
US20140312945A1 US13/909,281 US201313909281A US2014312945A1 US 20140312945 A1 US20140312945 A1 US 20140312945A1 US 201313909281 A US201313909281 A US 201313909281A US 2014312945 A1 US2014312945 A1 US 2014312945A1
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transistor
transistors
ota
charge pump
voltage
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US13/909,281
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Sharat Ippili
Venkata N.S.N. Rao
Prasad Chalasani
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Soctronics Inc
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Assigned to KOOL CHIP, INC. reassignment KOOL CHIP, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHALASANI, PRASAD, IPPILI, SHARAT, RAO, VENKATA N.S.N.
Publication of US20140312945A1 publication Critical patent/US20140312945A1/en
Assigned to SOCTRONICS, INC. reassignment SOCTRONICS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOOL CHIP, INC.
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H04L25/0276—Arrangements for coupling common mode signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This invention generally relates to a delay locked loop, and, in particular, to a low power delay locked loop for semiconductor devices, including memory devices.
  • a high speed synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory (“DDR SDRAM”)
  • data is transferred (input from or output to) to other devices in synchronization with an external clock signal.
  • the high speed synchronous semiconductor memory device such as the DDR SDRAM performs an input or output operation in synchronization with not only a rising edge but also a falling edge of the external clock signal.
  • a clock signal is used as a reference clock signal for adjusting operation timing to guarantee stable data access and data transfer without error.
  • a delay occurring from processing and receiving the data should be compensated for during the data transfer by exactly setting the data transfer at edges of the clock signal or at centers of the clock signal.
  • the clock synchronization circuit may include a phase locked loop (“PLL”) and/or a delay locked loop (“DLL”).
  • PLL phase locked loop
  • DLL delay locked loop
  • the PLL is used because the clock synchronization circuit can adjust the frequency of an internal clock in the semiconductor memory device.
  • the DLL is generally used to adjust the phase of the internal clock.
  • the delay locked loop generates internal clock signals based on the reference clock by compensating for clock skew occurring in the data path.
  • the data path has a predetermined delay amount estimated from the clock skew, where the data or the clock signal passes through the semiconductor memory device.
  • the generated internal clock signals can then be used for synchronizing data input/output.
  • the DLL of the current art consume large amounts of power which are not suitable for low-power devices.
  • a regulator is generally required in the DLL of the current art to supply a stable current to the various elements in the DLL circuit.
  • the regulator consumes a large amount of power, and is not suited for low power applications.
  • external biasing is necessary for the DLL of the current art to operate correctly, which is another source of power consumption. Therefore, it is desirable to provide new methods and circuits for a low power DLL, and, in particular to, a DLL that has self-biased elements and that does not need a regulator for supplying currents to the elements of the DLL circuit.
  • An object of this invention is to provide a low power delay locked loop.
  • Another object of this invention is to provide a self-biased delay locked loop.
  • Yet another object of this invention is to provide a bandwidth programmable delay locked loop.
  • the present invention discloses a delay locked loop, comprising: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.
  • An advantage of this invention is that a low power delay locked loop is provided.
  • Another advantage of this invention is that a self-biased delay locked loop is provided.
  • Yet another advantage of this invention is that a bandwidth programmable delay locked loop is provided.
  • FIG. 1 illustrates a block diagram for a delay locked loop (“DLL”) of the present invention.
  • DLL delay locked loop
  • FIG. 2 illustrates a circuit diagram for a charge pump of a DLL of the present invention.
  • FIG. 3 illustrates a circuit diagram for a bias generation circuit of a DLL of the present invention.
  • FIG. 4 illustrates a circuit diagram for an operational transconductance amplifier of a charge pump of the present invention.
  • FIG. 5 illustrates a circuit diagram for another operational transconductance amplifier of a charge pump of the present invention.
  • FIG. 6 illustrates a slave bias circuit of a DLL of the present invention.
  • a memory system e.g., DDR SDRAM
  • a clock signal with very fine steps to control the delay precisely for N-bit wide data with the clock positioned at the center.
  • a delay locked loop (“DLL”) of the present invention is used to synchronize one or more internal clock signals to a reference clock for the incoming data signal.
  • the internal clock signals must be very precise clock signals relative to the incoming data, which are routed to all the parallel (N-bit) data paths macros.
  • FIG. 1 illustrates a block diagram for a delay locked loop of the present invention.
  • a DLL system of the present invention comprises a bias generation circuit 8 , an initialization circuit 10 , a loop capacitor 12 , a charge pump 14 , a phase detector 16 , and a delay chain 20 .
  • the DLL system works in a negative feedback loop to match the phase of a differential reference clock signal L in .
  • the delay chain 20 outputs a feedback clock signal L out , a differential signal, to the phase detector 16 .
  • the phase detector 16 compares the feedback clock signal L out with the reference clock signal L in .
  • the reference clock signal L in can be received from a phase locked loop (“PLL”) of the associated memory system (or from another part of the semiconductor device).
  • the phase detector 16 outputs signals up, up , dn, and dn which are indicative of the relative phase differences of the differential signals L in and L out .
  • PLL phase locked loop
  • the outputs signals up, up , dn, and dn are inputted to the charge pump 14 to generate a charge pump voltage V CP .
  • the charge pump voltage V CP is connected to the initialization circuit 10 , the loop capacitor 12 , and the bias generation circuit 8 .
  • the initialization circuit 10 provides a pulse generation voltage to the voltage V CP .
  • the negative feedback loop of the DLL takes over, and the initiation circuit 10 is deactivated.
  • the output signals up,up, dn, and dn of the phase detector 16 indicate such changes, which are then used to adjust the feedback clock signal L out to match the phase of the reference clock signal L in .
  • the positive signal of the reference clock signal L in and the positive signal of the feedback clock signal L out are in phase.
  • the reference clock signal L out is leading the feedback clock signal L in in phase, then a continuous output signal do can be generated. This in turn will decrease the control voltages for the delay chain 20 to adjust the phase of the feedback clock signal L out to closer match the reference clock signal L in .
  • a continuous output signal up can be generated, which increases the control voltages for the delay chain 20 to adjust the phase of the feedback clock signal L out to closer match the reference clock signal L in .
  • the output signals up and dn can be generated accordingly to adjust the negative signals of the reference clock signal L in and the feedback clock signal L out .
  • the charge pump voltage V CP is inputted to the bias generation circuit 8 to generate biasing voltages, e.g., V bias master p , V bias master n and any slave biases as needed.
  • the biasing voltages are inputted to the delay chain 20 for controlling the phase delay for internal clocks signals that are generated by the delay chain 20 , e.g., the internal clock signals ⁇ 0 , ⁇ 1 , ⁇ 2 , and ⁇ 3 .
  • the internal clock signals are a preset number of degrees out of phase with the reference clock signal L in .
  • the internal clock signal ⁇ 0 can be 90 degrees out of phase with the reference clock signal L in ;
  • the internal clock signal ⁇ 1 can be 180 degrees out of phase with the reference clock signal L in ;
  • the internal clock signal ⁇ 2 can be 270 degrees out of phase with the reference clock signal L in ;
  • the internal clock signal ⁇ 3 can be 360 degrees out of phase with the reference clock signal L in .
  • Bandwidth control can adjust the internal clock signals to quickly adapt to any changes in phase of the reference clock signal L in by way of the negative feedback loop system of the DLL of the present invention.
  • the DLL loop parameters like bandwidth and damping factors are programmable.
  • the bandwidth and damping factor are a function of the charge pump, loop capacitor C 1 , and delay cell gain.
  • the charge pump current and the delay cell gain can be controlled using digital control bits to program the bandwidth and the damping factor.
  • the delay chain 20 comprises storage delay cells, e.g., delay cells 22 - 30 , where the delay cells are connected in series and generate the internal clock signals having a preset delay in phase.
  • the internal clock signals can be routed to any of the parallel data paths of the memory system.
  • the memory system may have 76 data buses of parallel inputs coming in at different frequencies and/or phases.
  • the delay chain can be further replicated for each of the 76 data buses via a slave bias circuit (not shown).
  • FIG. 2 illustrates a circuit diagram for a charge pump of a DLL of the present invention.
  • the charge pump 14 of the present invention comprises a self-biased operational transconductance amplifier (“OTA 1 ”) 40 , another self-biased operational transconductance amplifier (“OTA 2 ”) 42 , switches 60 and 70 , and transistors 44 - 58 and 64 - 68 (e.g., metal-oxide-semiconductor field-effect transistors).
  • the OTA 1 40 has a positive input that is connected to the charge pump voltage V CP , a negative input that is connected to a voltage V CP — dummy , and differential output signals V BP and V BN .
  • the output signal VBP is connected to the gates of the transistors 44 and 52 , and connected to the gate of the transistor 62 via the switch 60 .
  • the output signal V BN is connected to the gates of the transistors 50 and 58 , and connected to the gate of the transistor 68 via the switch 70 .
  • the OTA 1 40 and the transistors 44 - 50 act as a load, which can be active to prevent spikes in the charge pump voltage V CP .
  • the transistors 44 - 50 are connected in series across voltages V DD and V SS .
  • the voltages V DD and V SS are the respective power and ground supplies to the respective circuit. Typically, the power supply can vary from 1.1V to 0.7V.
  • the source of the transistor 44 is connected to the voltage V DD .
  • the source of the transistor 50 is connected to the voltage V SS .
  • the gate of the transistor 46 is connected to the voltage V SS
  • the gate of the transistor 48 is connected to the voltage V DD .
  • the drains of the transistors 46 and 48 are connected together to generate the voltage V CP — dummy , which is inputted to the negative input of the OTA 1 40 .
  • the drains of the transistors 54 and 56 are connected to each other, providing a voltage V CP .
  • the voltage V CPD is applied to the positive input of the OTA 2 42 .
  • the drains of the transistors 64 and 66 are connected to each other, and further connected to the output and the negative input of the OTA 2 42 in a negative feedback loop.
  • the output of the OTA 2 42 is connected with the charge pump voltage V CP .
  • the sources of the transistors 54 and 64 are connected together, and further connected to the drains of the transistors 52 and 62 .
  • the sources of the transistors 52 and 62 are connected to the voltage V DD .
  • the sources of the transistors 56 and 66 are connected together, and further connected to the drains of the transistors 58 and 68 .
  • the sources of the transistors 58 and 68 are connected to the voltage V SS .
  • the output signal up is connected to the gate of the transistor 54 .
  • the output signal up is connected to the gate of the transistor 64 .
  • the output signal dn is connected to the gate of the transistor 56 .
  • the output signal dn is connected to the gate of the transistor 66 .
  • the switches 60 and 70 provide a bandwidth control for the DLL negative feedback loop.
  • the switches 60 and 70 can be programmed accordingly to adjust the bandwidth control.
  • the switches 60 and 70 are activated, i.e., turned on, when the reference clock signal L in is 1 GHz or above, otherwise the switches 60 and 70 are deactivated, i.e., turned off.
  • FIG. 3 illustrates a circuit diagram for a bias generation circuit of a DLL of the present invention.
  • the bias generation circuit 8 comprises transistors 80 - 106 for generating the biasing voltages V bias master p , V bias master n , and V bias slave n .
  • the sources of the transistors 80 , 84 , 88 , 94 , 98 , and 104 are connected to the voltage V DD .
  • the gates of the transistors 80 and 84 and the drain of the transistor 84 are connected together.
  • the gates of the transistors 88 , 94 , 98 , and 104 and the drain of the transistor 88 are connected together to generate the biasing voltage V bias master p .
  • the biasing voltages can be generated from the charge pump voltage.
  • the drain of the transistor 88 is further connected with the drain of the transistor 86 .
  • the gate of transistor 86 is connected to the charge pump voltage V CP .
  • the source of the transistor 86 is connected to the voltage VSS and the source of the transistor 90 .
  • the drain of the transistor 90 is connected with the drain of the transistor 84 .
  • the gate of transistor 90 is connected to the drains of the transistors 92 and 94 to generate a voltage V DS ⁇ .
  • the voltage V DS ⁇ is applied to any slave bias circuits (see FIG. 6 ) to generate a current locally for any other DLLs.
  • the sources of the transistors 82 , 86 , 90 , 92 , 96 , 100 , 102 , and 106 are connected to the voltage V SS .
  • the gate and drain of the transistor 82 and the drain of transistor 80 are connected together.
  • the gates of the transistors 82 , 92 , 96 and 102 are connected together.
  • the drain of the transistor 96 and the gate of the transistor 100 are connected together and generate the biasing voltage V bias master n .
  • the drain of the transistor 100 is connected with the drain of the transistor 98 .
  • the drain of the transistor 102 , the gate and the drain of the transistor 106 , and the drain of the transistor 104 are connected together, and generate the biasing voltage V bias slave n .
  • FIG. 4 illustrates a circuit diagram for a self-biased operational transconductance amplifier of a charge pump of the present invention.
  • the OTA 1 40 comprises transistors 140 - 158 .
  • the sources of the transistors 140 , 144 , 148 , and 152 are connected to the voltage V DD .
  • the gate of the transistor 140 , the gate and the drain of the transistor 144 , and the drain of the transistor 150 are connected together.
  • the gate and drain of the transistor 148 , the gate of the transistor 152 , and the drain of the transistor 146 are connected together, and generate the OTA 1 40 's output voltage V BP .
  • the charge pump voltage VCP is applied to the gate of the transistor 146 .
  • the voltage V CP — dummy is applied to the gate of the transistor 150 and to the drains of the transistors 154 and 156 .
  • the voltage V SS is applied to the gate of the transistor 154
  • the voltage V DD is applied to the gate of the transistor 156 .
  • the drain and gate of the transistor 142 , the drain of the transistor 140 , and the gate of the transistor 158 are connected to together, and generate the OTA 1 40 's output voltage V BN .
  • the voltage V SS is applied to the sources for the transistors 142 , 146 , 150 , and 158 .
  • the drain of the transistor 152 is connected with the source of the transistor 154 .
  • the source of the transistor 156 is connected to the drain of the transistor 158 .
  • the drains of the transistors 154 and 156 are connected together.
  • the OTA 1 40 is a self-biased operational amplifier that uses a charge pump dummy path to replicate the charge pump loading effect.
  • the voltages V BP and V BN can be used to control the biasing points for the delay cells 22 - 30 . Since OTA 1 40 is self-biased, there is no need for a current source for this operational amplifier, which greatly reduces the power consumption of the DLL of the present invention.
  • FIG. 5 illustrates a circuit diagram for another self-biased operational transconductance amplifier of a charge pump of the present invention.
  • the OTA 2 42 comprises transistors 180 - 194 for generating a voltage V CPD based on the charge pump voltage V CP .
  • the voltage V DD is applied to the sources of the transistors 180 , 184 , 188 , and 192 .
  • the drain of the transistor 180 , the gate and the drain of the transistor 182 , and the gate of the transistor 194 are connected together.
  • the gate of the transistor 180 , the drain and the gate of the transistor 184 , and the drain of the transistor 186 are connected together.
  • the gate of the transistor 192 , the drain and the gate of the transistor 188 , and the drain of the transistor 190 are connected together.
  • the voltage V SS is applied to the sources of the transistors 182 , 186 , 190 and 194 .
  • the charge pump voltage V CP is applied to the gate of the transistor 186
  • the voltage V CPD is applied to the gate of the transistor 190 .
  • the OTA 2 42 can generate enough gain for the DLL with typically less than 5 mV offset.
  • FIG. 6 illustrates a slave bias circuit of a DLL of the present invention.
  • a slave bias input is a buffering circuit to buffer the slave biasing voltage for output to other delay chains for any parallel data.
  • the voltage V bias slave p is mirrored and outputted for receiving the parallel data. For instance, here there are 10 slave bias ports.

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Abstract

A delay locked loop, comprises: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.

Description

    CROSS REFERENCE
  • This application claims priority from a provisional patent application entitled “Apparatuses, Methods, and Systems Using Integrated Circuits” filed on Apr. 19, 2013 and having an Application No. 61/814,153. Said application is incorporated herein by reference.
    • FIELD OF INVENTION
  • This invention generally relates to a delay locked loop, and, in particular, to a low power delay locked loop for semiconductor devices, including memory devices.
    • BACKGROUND
  • In a high speed synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory (“DDR SDRAM”), data is transferred (input from or output to) to other devices in synchronization with an external clock signal. The high speed synchronous semiconductor memory device such as the DDR SDRAM performs an input or output operation in synchronization with not only a rising edge but also a falling edge of the external clock signal. Typically, in a system or a circuit including a semiconductor memory, a clock signal is used as a reference clock signal for adjusting operation timing to guarantee stable data access and data transfer without error. For stable data access and data transfer, a delay occurring from processing and receiving the data should be compensated for during the data transfer by exactly setting the data transfer at edges of the clock signal or at centers of the clock signal.
  • To control the data transfer timing, the clock signal needs to be synchronized with the transition timing of the external clock. Synchronous semiconductor memory devices include a clock synchronization circuit for this purpose. The clock synchronization circuit may include a phase locked loop (“PLL”) and/or a delay locked loop (“DLL”). Typically, in case that a frequency of the external clock differs from that of an internal clock in the semiconductor memory device, the PLL is used because the clock synchronization circuit can adjust the frequency of an internal clock in the semiconductor memory device. In case that a frequency of the external clock is the same as that of an internal clock in the semiconductor memory device, the DLL is generally used to adjust the phase of the internal clock.
  • The delay locked loop generates internal clock signals based on the reference clock by compensating for clock skew occurring in the data path. The data path has a predetermined delay amount estimated from the clock skew, where the data or the clock signal passes through the semiconductor memory device. The generated internal clock signals can then be used for synchronizing data input/output.
  • Although a delay locked loop works well to generate the internal clock signals for the semiconductor memory device, the DLL of the current art consume large amounts of power which are not suitable for low-power devices. For instance, a regulator is generally required in the DLL of the current art to supply a stable current to the various elements in the DLL circuit. The regulator consumes a large amount of power, and is not suited for low power applications. In additional, external biasing is necessary for the DLL of the current art to operate correctly, which is another source of power consumption. Therefore, it is desirable to provide new methods and circuits for a low power DLL, and, in particular to, a DLL that has self-biased elements and that does not need a regulator for supplying currents to the elements of the DLL circuit.
    • SUMMARY OF INVENTION
  • An object of this invention is to provide a low power delay locked loop.
  • Another object of this invention is to provide a self-biased delay locked loop.
  • Yet another object of this invention is to provide a bandwidth programmable delay locked loop.
  • Briefly, the present invention discloses a delay locked loop, comprising: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.
  • An advantage of this invention is that a low power delay locked loop is provided.
  • Another advantage of this invention is that a self-biased delay locked loop is provided.
  • Yet another advantage of this invention is that a bandwidth programmable delay locked loop is provided.
    • DESCRIPTION OF THE DRAWINGS
  • The foregoing and other objects, aspects, and advantages of the invention can be better understood from the following detailed description of the preferred embodiment of the invention when taken in conjunction with the accompanying drawings in which:
  • FIG. 1 illustrates a block diagram for a delay locked loop (“DLL”) of the present invention.
  • FIG. 2 illustrates a circuit diagram for a charge pump of a DLL of the present invention.
  • FIG. 3 illustrates a circuit diagram for a bias generation circuit of a DLL of the present invention.
  • FIG. 4 illustrates a circuit diagram for an operational transconductance amplifier of a charge pump of the present invention.
  • FIG. 5 illustrates a circuit diagram for another operational transconductance amplifier of a charge pump of the present invention.
  • FIG. 6 illustrates a slave bias circuit of a DLL of the present invention.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration of specific embodiments in which the present invention may be practiced.
  • Generally, a memory system, e.g., DDR SDRAM, requires a clock signal with very fine steps to control the delay precisely for N-bit wide data with the clock positioned at the center. To generate the clock signal for the memory system, a delay locked loop (“DLL”) of the present invention is used to synchronize one or more internal clock signals to a reference clock for the incoming data signal. The internal clock signals must be very precise clock signals relative to the incoming data, which are routed to all the parallel (N-bit) data paths macros.
  • FIG. 1 illustrates a block diagram for a delay locked loop of the present invention. A DLL system of the present invention comprises a bias generation circuit 8, an initialization circuit 10, a loop capacitor 12, a charge pump 14, a phase detector 16, and a delay chain 20. The DLL system works in a negative feedback loop to match the phase of a differential reference clock signal Lin. The delay chain 20 outputs a feedback clock signal Lout, a differential signal, to the phase detector 16. The phase detector 16 compares the feedback clock signal Lout with the reference clock signal Lin. The reference clock signal Lin can be received from a phase locked loop (“PLL”) of the associated memory system (or from another part of the semiconductor device). The phase detector 16 outputs signals up, up, dn, and dn which are indicative of the relative phase differences of the differential signals Lin and Lout.
  • The outputs signals up, up, dn, and dn are inputted to the charge pump 14 to generate a charge pump voltage VCP. The charge pump voltage VCP is connected to the initialization circuit 10, the loop capacitor 12, and the bias generation circuit 8. During initiation of the DLL, the initialization circuit 10 provides a pulse generation voltage to the voltage VCP. After initiation, the negative feedback loop of the DLL takes over, and the initiation circuit 10 is deactivated.
  • When there is a phase difference between the reference clock signal Lin and the feedback clock signal Lout, the output signals up,up, dn, and dn of the phase detector 16 indicate such changes, which are then used to adjust the feedback clock signal Lout to match the phase of the reference clock signal Lin. For instance, when the output signals up and dn are equal, then the positive signal of the reference clock signal Lin and the positive signal of the feedback clock signal Lout are in phase. When the reference clock signal Lout is leading the feedback clock signal Lin in phase, then a continuous output signal do can be generated. This in turn will decrease the control voltages for the delay chain 20 to adjust the phase of the feedback clock signal Lout to closer match the reference clock signal Lin. When the feedback clock signal Lout is lagging the reference clock signal Lin, then a continuous output signal up can be generated, which increases the control voltages for the delay chain 20 to adjust the phase of the feedback clock signal Lout to closer match the reference clock signal Lin. Likewise, the output signals up and dn can be generated accordingly to adjust the negative signals of the reference clock signal Lin and the feedback clock signal Lout.
  • The charge pump voltage VCP is inputted to the bias generation circuit 8 to generate biasing voltages, e.g., Vbias master p, Vbias master n and any slave biases as needed. The biasing voltages are inputted to the delay chain 20 for controlling the phase delay for internal clocks signals that are generated by the delay chain 20, e.g., the internal clock signals Φ0, Φ1, Φ2, and Φ3. Typically, the internal clock signals are a preset number of degrees out of phase with the reference clock signal Lin. For instance, the internal clock signal Φ0 can be 90 degrees out of phase with the reference clock signal Lin; the internal clock signal Φ1 can be 180 degrees out of phase with the reference clock signal Lin; the internal clock signal Φ2 can be 270 degrees out of phase with the reference clock signal Lin; and the internal clock signal Φ3 can be 360 degrees out of phase with the reference clock signal Lin.
  • Bandwidth control can adjust the internal clock signals to quickly adapt to any changes in phase of the reference clock signal Lin by way of the negative feedback loop system of the DLL of the present invention. The DLL loop parameters like bandwidth and damping factors are programmable. For instance, the bandwidth and damping factor are a function of the charge pump, loop capacitor C1, and delay cell gain. Thus, the charge pump current and the delay cell gain can be controlled using digital control bits to program the bandwidth and the damping factor.
  • During steady state operation, the feedback clock signal Lout is substantially in phase with the reference clock signal Lin. There might be some delay between the feedback clock signal Lout and the reference clock signal Lin due to the feedback loop routing. The delay chain 20 comprises storage delay cells, e.g., delay cells 22-30, where the delay cells are connected in series and generate the internal clock signals having a preset delay in phase. The internal clock signals can be routed to any of the parallel data paths of the memory system. Typically, the memory system may have 76 data buses of parallel inputs coming in at different frequencies and/or phases. Thus, the delay chain can be further replicated for each of the 76 data buses via a slave bias circuit (not shown).
  • FIG. 2 illustrates a circuit diagram for a charge pump of a DLL of the present invention. The charge pump 14 of the present invention comprises a self-biased operational transconductance amplifier (“OTA1”) 40, another self-biased operational transconductance amplifier (“OTA2”) 42, switches 60 and 70, and transistors 44-58 and 64-68 (e.g., metal-oxide-semiconductor field-effect transistors). The OTA1 40 has a positive input that is connected to the charge pump voltage VCP, a negative input that is connected to a voltage VCP — dummy, and differential output signals VBP and VBN. The output signal VBP is connected to the gates of the transistors 44 and 52, and connected to the gate of the transistor 62 via the switch 60. The output signal VBN is connected to the gates of the transistors 50 and 58, and connected to the gate of the transistor 68 via the switch 70. The OTA1 40 and the transistors 44-50 act as a load, which can be active to prevent spikes in the charge pump voltage VCP.
  • The transistors 44-50 are connected in series across voltages VDD and VSS. The voltages VDD and VSS are the respective power and ground supplies to the respective circuit. Typically, the power supply can vary from 1.1V to 0.7V. The source of the transistor 44 is connected to the voltage VDD. The source of the transistor 50 is connected to the voltage VSS. The gate of the transistor 46 is connected to the voltage VSS, and the gate of the transistor 48 is connected to the voltage VDD. Also, the drains of the transistors 46 and 48 are connected together to generate the voltage VCP — dummy, which is inputted to the negative input of the OTA1 40.
  • The drains of the transistors 54 and 56 are connected to each other, providing a voltage VCP. The voltage VCPD is applied to the positive input of the OTA2 42. The drains of the transistors 64 and 66 are connected to each other, and further connected to the output and the negative input of the OTA2 42 in a negative feedback loop. The output of the OTA2 42 is connected with the charge pump voltage VCP. The sources of the transistors 54 and 64 are connected together, and further connected to the drains of the transistors 52 and 62. The sources of the transistors 52 and 62 are connected to the voltage VDD. The sources of the transistors 56 and 66 are connected together, and further connected to the drains of the transistors 58 and 68. The sources of the transistors 58 and 68 are connected to the voltage VSS.
  • The output signal up is connected to the gate of the transistor 54. The output signal up is connected to the gate of the transistor 64. The output signal dn is connected to the gate of the transistor 56. The output signal dn is connected to the gate of the transistor 66.
  • The switches 60 and 70 provide a bandwidth control for the DLL negative feedback loop. The switches 60 and 70 can be programmed accordingly to adjust the bandwidth control. Generally, the switches 60 and 70 are activated, i.e., turned on, when the reference clock signal Lin is 1 GHz or above, otherwise the switches 60 and 70 are deactivated, i.e., turned off.
  • FIG. 3 illustrates a circuit diagram for a bias generation circuit of a DLL of the present invention. The bias generation circuit 8 comprises transistors 80-106 for generating the biasing voltages Vbias master p, Vbias master n, and Vbias slave n. The sources of the transistors 80, 84, 88, 94, 98, and 104 are connected to the voltage VDD. The gates of the transistors 80 and 84 and the drain of the transistor 84 are connected together. The gates of the transistors 88, 94, 98, and 104 and the drain of the transistor 88 are connected together to generate the biasing voltage Vbias master p. Thus, the biasing voltages can be generated from the charge pump voltage.
  • The drain of the transistor 88 is further connected with the drain of the transistor 86. The gate of transistor 86 is connected to the charge pump voltage VCP. The source of the transistor 86 is connected to the voltage VSS and the source of the transistor 90. The drain of the transistor 90 is connected with the drain of the transistor 84. The gate of transistor 90 is connected to the drains of the transistors 92 and 94 to generate a voltage VDSΦ. The voltage VDSΦ is applied to any slave bias circuits (see FIG. 6) to generate a current locally for any other DLLs.
  • The sources of the transistors 82, 86, 90, 92, 96, 100, 102, and 106 are connected to the voltage VSS. The gate and drain of the transistor 82 and the drain of transistor 80 are connected together. The gates of the transistors 82, 92, 96 and 102 are connected together. The drain of the transistor 96 and the gate of the transistor 100 are connected together and generate the biasing voltage Vbias master n. The drain of the transistor 100 is connected with the drain of the transistor 98. The drain of the transistor 102, the gate and the drain of the transistor 106, and the drain of the transistor 104 are connected together, and generate the biasing voltage Vbias slave n.
  • FIG. 4 illustrates a circuit diagram for a self-biased operational transconductance amplifier of a charge pump of the present invention. The OTA1 40 comprises transistors 140-158. The sources of the transistors 140, 144, 148, and 152 are connected to the voltage VDD. The gate of the transistor 140, the gate and the drain of the transistor 144, and the drain of the transistor 150 are connected together. The gate and drain of the transistor 148, the gate of the transistor 152, and the drain of the transistor 146 are connected together, and generate the OTA1 40's output voltage VBP. The charge pump voltage VCP is applied to the gate of the transistor 146. The voltage VCP — dummy is applied to the gate of the transistor 150 and to the drains of the transistors 154 and 156. The voltage VSS is applied to the gate of the transistor 154, and the voltage VDD is applied to the gate of the transistor 156.
  • The drain and gate of the transistor 142, the drain of the transistor 140, and the gate of the transistor 158 are connected to together, and generate the OTA1 40's output voltage VBN. The voltage VSS is applied to the sources for the transistors 142, 146, 150, and 158. The drain of the transistor 152 is connected with the source of the transistor 154. The source of the transistor 156 is connected to the drain of the transistor 158. The drains of the transistors 154 and 156 are connected together.
  • The OTA1 40 is a self-biased operational amplifier that uses a charge pump dummy path to replicate the charge pump loading effect. The voltages VBP and VBN can be used to control the biasing points for the delay cells 22-30. Since OTA1 40 is self-biased, there is no need for a current source for this operational amplifier, which greatly reduces the power consumption of the DLL of the present invention.
  • FIG. 5 illustrates a circuit diagram for another self-biased operational transconductance amplifier of a charge pump of the present invention. The OTA2 42 comprises transistors 180-194 for generating a voltage VCPD based on the charge pump voltage VCP. The voltage VDD is applied to the sources of the transistors 180, 184, 188, and 192. The drain of the transistor 180, the gate and the drain of the transistor 182, and the gate of the transistor 194 are connected together. The gate of the transistor 180, the drain and the gate of the transistor 184, and the drain of the transistor 186 are connected together. The gate of the transistor 192, the drain and the gate of the transistor 188, and the drain of the transistor 190 are connected together. The voltage VSS is applied to the sources of the transistors 182, 186, 190 and 194. The charge pump voltage VCP is applied to the gate of the transistor 186, and the voltage VCPD is applied to the gate of the transistor 190. The OTA2 42 can generate enough gain for the DLL with typically less than 5 mV offset.
  • FIG. 6 illustrates a slave bias circuit of a DLL of the present invention. A slave bias input is a buffering circuit to buffer the slave biasing voltage for output to other delay chains for any parallel data. Thus, the voltage Vbias slave p is mirrored and outputted for receiving the parallel data. For instance, here there are 10 slave bias ports.
  • While the present invention has been described with reference to certain preferred embodiments or methods, it is to be understood that the present invention is not limited to such specific embodiments or methods. Rather, it is the inventor's contention that the invention be understood and construed in its broadest meaning as reflected by the following claims. Thus, these claims are to be understood as incorporating not only the preferred apparatuses, methods, and systems described herein, but all those other and further alterations and modifications as would be apparent to those of ordinary skilled in the art.

Claims (20)

We claim:
1. A delay locked loop, comprising:
a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal;
a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals;
a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and
a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.
2. The delay locked loop of claim 1 wherein the charge pump comprises a first self-biased amplifier (“OTA1”), a second self-biased amplifier (“OTA2”), and transistors.
3. The delay locked loop of claim 2 wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors, and wherein the OTA1 and the serially connected transistors are connected together to provide a dummy load for the charge pump.
4. The delay locked loop of claim 3
wherein the source of the first transistor is connected to a first voltage,
wherein the drain of the first transistor and the source of the second transistor are connected together,
wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA1 are connected together,
wherein the source of the third transistor is connected to the drain of the fourth transistor,
wherein the source of the fourth transistor is connected to a second voltage,
wherein the positive output of the OTA1 is applied to the gate of the first transistor,
wherein the second voltage is applied to the gate of the second transistor,
wherein the first voltage is applied to the gate of the third transistor,
wherein the negative output of the OTA1 is applied to the gate of the fourth transistor, and
wherein the charge pump voltage is applied to the positive input of the OTA1.
5. The delay locked loop of claim 2 wherein the OTA2 is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector.
6. The delay locked loop of claim 5
wherein a fifth transistor and a sixth transistor of the transistors are connected in series,
wherein a seventh transistor and an eighth transistor of the transistors are connected in series,
wherein the sources of the fifth and seventh transistors are connected together,
wherein the drains of the sixth and eighth transistors are connected together,
wherein the drains of the fifth and sixth transistors and the positive input of the OTA2 are connected together,
wherein the drains of the seventh and eighth transistors, the output of the OTA2, and the negative input of the OTA2 are connected together to generate the charge pump voltage, and
wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.
7. The delay locked loop of claim 6
wherein the charge pump further comprises a first switch and a second switch,
wherein the positive output of the OTA1 is connected to the gate of a ninth transistor of the transistors,
wherein the positive output of the OTA1 is connected to the gate of a tenth transistor of the transistors via the first switch,
wherein the negative output of the OTA1 is connected to the gate of a eleventh transistor of the transistors,
wherein the negative output of the OTA1 is connected to the gate of a twelfth transistor of the transistors via the second switch,
wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage,
wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors,
wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and
wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors.
8. The delay locked loop of claim 1 further comprising an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop.
9. The delay locked loop of claim 1 further comprising a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage.
10. A delay locked loop, comprising:
a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal;
a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals and wherein the charge pump comprises a first self-biased amplifier (“OTA1”), a second self-biased amplifier (“OTA2”), and transistors;
a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and
a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals, and wherein the OTA2 is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector.
11. The delay locked loop of claim 10 wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors, and wherein the OTA1 and the serially connected transistors are connected together to provide a dummy load for the charge pump.
12. The delay locked loop of claim 11
wherein the source of the first transistor is connected to a first voltage,
wherein the drain of the first transistor and the source of the second transistor are connected together,
wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA1 are connected together,
wherein the source of the third transistor is connected to the drain of the fourth transistor,
wherein the source of the fourth transistor is connected to a second voltage,
wherein the positive output of the OTA1 is applied to the gate of the first transistor,
wherein the second voltage is applied to the gate of the second transistor,
wherein the first voltage is applied to the gate of the third transistor,
wherein the negative output of the OTA1 is applied to the gate of the fourth transistor, and
wherein the charge pump voltage is applied to the positive input of the OTA1.
13. The delay locked loop of claim 10
wherein a fifth transistor and a sixth transistor of the transistors are connected in series,
wherein a seventh transistor and an eighth transistor of the transistors are connected in series,
wherein the sources of the fifth and seventh transistors are connected together,
wherein the drains of the sixth and eighth transistors are connected together,
wherein the drains of the fifth and sixth transistors and the positive input of the OTA2 are connected together,
wherein the drains of the seventh and eighth transistors, the output of the OTA2, and the negative input of the OTA2 are connected together to generate the charge pump voltage, and
wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.
14. The delay locked loop of claim 13
wherein the charge pump further comprises a first switch and a second switch,
wherein the positive output of the OTA1 is connected to the gate of a ninth transistor of the transistors,
wherein the positive output of the OTA1 is connected to the gate of a tenth transistor of the transistors via the first switch,
wherein the negative output of the OTA1 is connected to the gate of a eleventh transistor of the transistors,
wherein the negative output of the OTA1 is connected to the gate of a twelfth transistor of the transistors via the second switch,
wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage,
wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors,
wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and
wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors.
15. The delay locked loop of claim 10 further comprising an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop.
16. The delay locked loop of claim 10 further comprising a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage.
17. A delay locked loop, comprising:
a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal;
a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals and wherein the charge pump comprises a first self-biased amplifier (“OTA1”), a second self-biased amplifier (“OTA2”), and transistors;
a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage;
an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop;
a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and
a delay chain,
wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals,
wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors,
wherein the OTA1 and the serially connected transistors are connected together to provide a dummy load for the charge pump, and
wherein the OTA2 is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector.
18. The delay locked loop of claim 17
wherein the source of the first transistor is connected to a first voltage,
wherein the drain of the first transistor and the source of the second transistor are connected together,
wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA1 are connected together,
wherein the source of the third transistor is connected to the drain of the fourth transistor,
wherein the source of the fourth transistor is connected to a second voltage,
wherein the positive output of the OTA1 is applied to the gate of the first transistor,
wherein the second voltage is applied to the gate of the second transistor,
wherein the first voltage is applied to the gate of the third transistor,
wherein the negative output of the OTA1 is applied to the gate of the fourth transistor, and
wherein the charge pump voltage is applied to the positive input of the OTA1.
19. The delay locked loop of claim 17
wherein a fifth transistor and a sixth transistor of the transistors are connected in series,
wherein a seventh transistor and an eighth transistor of the transistors are connected in series,
wherein the sources of the fifth and seventh transistors are connected together,
wherein the drains of the sixth and eighth transistors are connected together,
wherein the drains of the fifth and sixth transistors and the positive input of the OTA2 are connected together,
wherein the drains of the seventh and eighth transistors, the output of the OTA2, and the negative input of the OTA2 are connected together to generate the charge pump voltage, and
wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.
20. The delay locked loop of claim 19
wherein the charge pump further comprises a first switch and a second switch,
wherein the positive output of the OTA1 is connected to the gate of a ninth transistor of the transistors,
wherein the positive output of the OTA1 is connected to the gate of a tenth transistor of the transistors via the first switch,
wherein the negative output of the OTA1 is connected to the gate of a eleventh transistor of the transistors,
wherein the negative output of the OTA1 is connected to the gate of a twelfth transistor of the transistors via the second switch,
wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage,
wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors,
wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and
wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140340129A1 (en) * 2012-04-13 2014-11-20 Atul Maheshwari Frequency control system with dual-input bias generator to separately receive management and operational controls
US20150214965A1 (en) * 2014-01-30 2015-07-30 Sandisk Technologies Inc. Auto-phase synchronization in delay locked loops
US9240912B1 (en) * 2014-11-26 2016-01-19 Altera Corporation Transceiver circuitry with summation node common mode droop reduction
US9705708B1 (en) 2016-06-01 2017-07-11 Altera Corporation Integrated circuit with continuously adaptive equalization circuitry
CN108197047A (en) * 2017-08-18 2018-06-22 Tcl空调器(中山)有限公司 Intelligence interface circuit
US11601130B2 (en) 2021-06-23 2023-03-07 Nxp B.V. Initialization circuit of delay locked loop

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140312928A1 (en) * 2013-04-19 2014-10-23 Kool Chip, Inc. High-Speed Current Steering Logic Output Buffer
US9349421B2 (en) * 2014-02-03 2016-05-24 Soctronics, Inc. Memory interface
US9906383B2 (en) 2015-02-02 2018-02-27 Samsung Electronics Co., Ltd. Semiconductor device, semiconductor system and method of operating semiconductor device
CN106033396A (en) * 2015-03-10 2016-10-19 鸿富锦精密工业（深圳）有限公司 A data storage device and a data transmission system with the same
CN105242766B (en) * 2015-10-22 2017-11-28 深圳拓邦股份有限公司 A kind of voltage jump detection circuit, reset circuit and electronic installation
WO2017081591A1 (en) * 2015-11-13 2017-05-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device
US10218360B2 (en) * 2016-08-02 2019-02-26 Altera Corporation Dynamic clock-data phase alignment in a source synchronous interface circuit
US10461742B2 (en) * 2016-09-01 2019-10-29 Novatek Microelectronics Corp. Chip, selectable mode buffer circuit and mode selecting method thereof
US10771068B2 (en) 2018-02-20 2020-09-08 International Business Machines Corporation Reducing chip latency at a clock boundary by reference clock phase adjustment
KR102530884B1 (en) * 2018-04-06 2023-05-11 에스케이하이닉스 주식회사 Semiconductor memory device and the method for operating the same
TWI675336B (en) * 2018-04-30 2019-10-21 鯨鏈科技股份有限公司 System of smart ticket, method for issuing ticket and computer-readable storage device
TWI670939B (en) * 2018-12-03 2019-09-01 新唐科技股份有限公司 Delay line circuit with calibration function and calibration method thereof
US11099602B2 (en) * 2019-04-30 2021-08-24 International Business Machines Corporation Fault-tolerant clock gating
TWI743538B (en) * 2019-08-21 2021-10-21 群聯電子股份有限公司 Connection interface circuit, memory storage device and signal generation method
US11340786B2 (en) * 2020-08-24 2022-05-24 Advanced Micro Devices, Inc. Apparatus and methods for synchronizing a plurality of double data rate memory ranks
EP4080833A1 (en) * 2021-04-23 2022-10-26 Elmos Semiconductor SE Method and device for transmitting bit flows in a communication bus system
US11768531B2 (en) * 2021-12-30 2023-09-26 Western Digital Technologies, Inc. Power management for storage controllers
TWI813144B (en) * 2022-01-25 2023-08-21 瑞昱半導體股份有限公司 Receiver detection system and receiver detection device

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570045A (en) * 1995-06-07 1996-10-29 Lsi Logic Corporation Hierarchical clock distribution system and method
US6049837A (en) * 1997-12-08 2000-04-11 International Business Machines Corporation Programmable output interface for lower level open system interconnection architecture
US6434704B1 (en) * 1999-08-16 2002-08-13 International Business Machines Corporation Methods for improving the efficiency of clock gating within low power clock trees
US6218884B1 (en) * 2000-03-02 2001-04-17 National Semiconductor Corp. Cancellation of Ron resistance for switching transistor in LVDS driver output
US6718477B1 (en) * 2000-03-06 2004-04-06 William C. Plants Delay locked loop for an FPGA architecture
US6769104B2 (en) * 2002-05-08 2004-07-27 Agilent Technologies, Inc. Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced load
US7336780B2 (en) * 2002-08-01 2008-02-26 Integrated Device Technology, Inc. Differential signaling transmission circuit
US8230114B2 (en) * 2002-08-07 2012-07-24 Broadcom Corporation System and method for implementing a single chip having a multiple sub-layer PHY
US6906426B2 (en) * 2002-08-07 2005-06-14 Broadcom Corporation Transceiver having shadow memory facilitating on-transceiver collection and communication of local parameters
US7640370B1 (en) * 2003-11-25 2009-12-29 Marvell International Ltd. Method and apparatus for controlling data transfer between EEPROM and a physical layer device
JP2005184262A (en) * 2003-12-17 2005-07-07 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and its fabricating process
US7342420B2 (en) * 2004-09-24 2008-03-11 Integrated Device Technology, Inc. Low power output driver
US7584449B2 (en) * 2004-11-22 2009-09-01 Fulcrum Microsystems, Inc. Logic synthesis of multi-level domino asynchronous pipelines
US7231480B2 (en) * 2005-04-06 2007-06-12 Qlogic, Corporation Method and system for receiver detection in PCI-Express devices
US7630851B2 (en) * 2005-06-10 2009-12-08 Azuro (Uk) Limited Estimation of average-case activity for circuit elements in a digital circuit
US7571406B2 (en) * 2005-08-04 2009-08-04 Freescale Semiconductor, Inc. Clock tree adjustable buffer
TWI299616B (en) * 2005-12-16 2008-08-01 Via Tech Inc Transmitter and transmission circuit
JP2007243912A (en) * 2006-02-07 2007-09-20 Renesas Technology Corp Semiconductor integrated circuit
US7339364B2 (en) * 2006-06-19 2008-03-04 International Business Machines Corporation Circuit and method for on-chip jitter measurement
US8122275B2 (en) * 2006-08-24 2012-02-21 Altera Corporation Write-leveling implementation in programmable logic devices
JP4355348B2 (en) * 2007-07-10 2009-10-28 パナソニック株式会社 Clock supply circuit and design method thereof
JP2009152451A (en) * 2007-12-21 2009-07-09 Texas Instr Japan Ltd Integrated circuit device and its layout designing method
US7996804B2 (en) * 2008-01-17 2011-08-09 Lsi Corporation Signal delay skew reduction system
JP2009187104A (en) * 2008-02-04 2009-08-20 Panasonic Corp Semiconductor integrated circuit
US7747809B2 (en) * 2008-02-19 2010-06-29 International Business Machines Corporation Managing PCI express devices during recovery operations
US8661285B2 (en) * 2008-06-06 2014-02-25 Uniquify, Incorporated Dynamically calibrated DDR memory controller
WO2010080176A1 (en) * 2009-01-12 2010-07-15 Rambus Inc. Mesochronous signaling system with multiple power modes
DE102009000697B4 (en) * 2009-02-06 2012-12-06 Infineon Technologies Ag Driver circuit for a two-wire line and method for generating two output currents for a two-wire line
JP2010212377A (en) * 2009-03-09 2010-09-24 Toshiba Corp Semiconductor integrated circuit designing device and semiconductor integrated circuit designing method
US8269525B2 (en) * 2009-11-17 2012-09-18 Ati Technologies Ulc Logic cell having reduced spurious toggling
DE102010046686B3 (en) * 2010-09-28 2012-01-19 Texas Instruments Deutschland Gmbh Electronic device, has current source adjusting output stroke in two operating modes, and another current source adjusting common mode-voltage level of output signal in one of modes and providing maximum series resistance in other mode
US8436669B2 (en) * 2011-04-27 2013-05-07 Nvidia Corporation Single-trigger low-energy flip-flop circuit
US8665663B2 (en) * 2011-04-27 2014-03-04 Nanya Technology Corporation Memory circuit and control method thereof
WO2012164343A1 (en) * 2011-05-27 2012-12-06 Freescale Semiconductor, Inc. Integrated circuit device and method for self-heating an integrated circuit device
JP5568057B2 (en) * 2011-05-30 2014-08-06 株式会社東芝 Memory access circuit and memory system
US8471607B1 (en) * 2011-12-30 2013-06-25 St-Ericsson Sa High-speed frequency divider architecture
US9178730B2 (en) * 2012-02-24 2015-11-03 Freescale Semiconductor, Inc. Clock distribution module, synchronous digital system and method therefor
US8823414B2 (en) * 2012-05-11 2014-09-02 Silicon Laboratories Inc. Multiple signal format output driver with configurable internal load
US8779824B2 (en) * 2012-12-17 2014-07-15 Qualcomm Incorporated Clock distribution using MTJ sensing
US8989313B2 (en) * 2013-03-11 2015-03-24 International Business Machines Corporation Adaptable receiver detection
US20140312928A1 (en) * 2013-04-19 2014-10-23 Kool Chip, Inc. High-Speed Current Steering Logic Output Buffer
JP2015043170A (en) * 2013-08-26 2015-03-05 株式会社東芝 Interface circuit and system
JP6313085B2 (en) * 2014-03-27 2018-04-18 ルネサスエレクトロニクス株式会社 Semiconductor device
US20150323958A1 (en) * 2014-05-08 2015-11-12 Qualcomm Incorporated Clock skew management systems, methods, and related components

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140340129A1 (en) * 2012-04-13 2014-11-20 Atul Maheshwari Frequency control system with dual-input bias generator to separately receive management and operational controls
US9450592B2 (en) * 2012-04-13 2016-09-20 Intel Corporation Frequency control system with dual-input bias generator to separately receive management and operational controls
US20150214965A1 (en) * 2014-01-30 2015-07-30 Sandisk Technologies Inc. Auto-phase synchronization in delay locked loops
US9148157B2 (en) * 2014-01-30 2015-09-29 Sandisk Technologies Inc. Auto-phase synchronization in delay locked loops
US9240912B1 (en) * 2014-11-26 2016-01-19 Altera Corporation Transceiver circuitry with summation node common mode droop reduction
US9705708B1 (en) 2016-06-01 2017-07-11 Altera Corporation Integrated circuit with continuously adaptive equalization circuitry
CN108197047A (en) * 2017-08-18 2018-06-22 Tcl空调器(中山)有限公司 Intelligence interface circuit
US11601130B2 (en) 2021-06-23 2023-03-07 Nxp B.V. Initialization circuit of delay locked loop

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US8952737B2 (en) 2015-02-10
US20160246325A1 (en) 2016-08-25
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US9564905B2 (en) 2017-02-07
US9467149B2 (en) 2016-10-11
US9337846B2 (en) 2016-05-10
US20140314190A1 (en) 2014-10-23
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US20140317432A1 (en) 2014-10-23
US9948310B2 (en) 2018-04-17

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