TWI813144B - Receiver detection system and receiver detection device - Google Patents

Receiver detection system and receiver detection device Download PDF

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Publication number
TWI813144B
TWI813144B TW111103130A TW111103130A TWI813144B TW I813144 B TWI813144 B TW I813144B TW 111103130 A TW111103130 A TW 111103130A TW 111103130 A TW111103130 A TW 111103130A TW I813144 B TWI813144 B TW I813144B
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receiver
detection
mode voltage
detector
common mode
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TW111103130A
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TW202332213A (en
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林昀賢
黃柏凱
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瑞昱半導體股份有限公司
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Priority to US18/097,350 priority patent/US20230236647A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/189—Power distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed is a receiver detection system including a media access control (MAC) circuit, a common-mode voltage detector, and a receiver detector. The common-mode voltage detector is configured to detect whether a common-mode voltage satisfies a voltage condition, and configured to send a ready signal to the receiver detector after the common-mode voltage satisfies the voltage condition. The receiver detector is configured to start a detection process according to the ready signal and a detection start signal of the MAC circuit. In the detection process, the receiver detector sends a detection signal for detecting whether a receiver exists, and then outputs a detection result to the MAC circuit, wherein the detection result indicates whether the receiver exists. The receiver detection system can prevent the receiver detector from starting the detection process before the common-mode voltage satisfies the voltage condition.

Description

接收器偵測系統與接收器偵測裝置Receiver detection system and receiver detection device

本發明是關於偵測系統與裝置，尤其是關於能夠偵測一接收器是否存在的偵測系統與裝置。 The present invention relates to detection systems and devices, and in particular to detection systems and devices capable of detecting the presence of a receiver.

依據快捷週邊組件互連(Peripheral Component Interconnect Express；PCIe)協定或通用序列匯流排(Universal Serial Bus；USB)協定，當一傳送器沒有活動時，該傳送器會進入一擱置狀態(suspend state)以節電，此時該傳送器的共模電壓(亦即：該傳送器之一對差動輸出訊號的和)會降至零伏特(0V)；而當該傳送器被喚醒時，該傳送器會從該擱置狀態進入一恢復狀 態(resume state)，此時該傳送器的共模電壓會從0V逐漸地爬升至

Figure 111103130-A0305-02-0003-3
。在該 共模電壓開始爬升後，該傳送器會發送一偵測訊號以判斷一接收器是否存在。 According to the Peripheral Component Interconnect Express (PCIe) protocol or the Universal Serial Bus (USB) protocol, when a transmitter has no activity, the transmitter will enter a suspend state. To save power, the common-mode voltage of the transmitter (that is, the sum of the differential output signals of one pair of the transmitter) will drop to zero volts (0V); and when the transmitter wakes up, the transmitter will From the idle state to a resume state, the common mode voltage of the transmitter will gradually climb from 0V to
Figure 111103130-A0305-02-0003-3
. After the common-mode voltage begins to climb, the transmitter sends a detection signal to determine whether a receiver is present.

實務上，該共模電壓從0V爬升到

Figure 111103130-A0305-02-0003-4
的爬升時間會受一外部的印 刷電路板上的阻抗(例如：電阻與電容)與一傳輸線之長度的影響。根據不同的阻抗與長度，該爬升時間可能介於數十奈秒至數毫秒，其中該最小爬升時間與該最大爬升時間之間的差異相當大。若在該共模電壓爬升至
Figure 111103130-A0305-02-0003-5
前，該傳送器即發送該偵測訊號，該傳送器可能會得到一錯誤的偵測結果。 In practice, the common-mode voltage climbs from 0V to
Figure 111103130-A0305-02-0003-4
The rise time will be affected by an external printed circuit board impedance (such as resistors and capacitors) and the length of a transmission line. Depending on different impedances and lengths, the climb time may range from tens of nanoseconds to several milliseconds, where the difference between the minimum climb time and the maximum climb time is quite large. If the common mode voltage climbs to
Figure 111103130-A0305-02-0003-5
Before the transmitter sends the detection signal, the transmitter may obtain an erroneous detection result.

為了因應該不確定的爬升時間，目前技術令該傳送器的媒體存取控制(media access control；MAC)電路盡量延遲該傳送器發送該偵測訊號的 時間，以讓該共模電壓有足夠的時間爬升至

Figure 111103130-A0305-02-0004-1
。然而，若該媒體存取控制電路 一律延遲該傳送器發送該偵測訊號的時間，這會造成該傳送器從該擱置狀態進入該恢復狀態的時間一律增加，從而造成該傳送器的效能下降。 In order to cope with the uncertain rise time, the current technology makes the media access control (MAC) circuit of the transmitter delay the time when the transmitter sends the detection signal as much as possible, so that the common mode voltage has enough time climbs to
Figure 111103130-A0305-02-0004-1
. However, if the media access control circuit uniformly delays the time for the transmitter to send the detection signal, this will cause the transmitter to uniformly increase the time it takes to enter the recovery state from the idle state, thereby causing the performance of the transmitter to decrease.

本揭露的目的之一在於提供一種接收器偵測系統與一種接收器偵測裝置，以避免前述先前技術的問題。 One of the objectives of the present disclosure is to provide a receiver detection system and a receiver detection device to avoid the aforementioned problems of the prior art.

本揭露之接收器偵測系統的一實施例包含一媒體存取控制電路、一共模電壓偵測器與一接收器偵測器。該共模電壓偵測器用來偵測一共模電壓是否滿足一電壓條件，並於該共模電壓滿足該電壓條件後，發送一準備完成訊號給該接收器偵測器。該接收器偵測器用來依據該準備完成訊號以及該媒體存取控制電路的一偵測開始訊號開始一偵測程序。於該偵測程序中，該接收器偵測器發出一偵測訊號用於判斷一接收器是否存在，然後輸出一偵測結果給該媒體存取控制電路，其中該偵測結果指出該接收器是否存在。 An embodiment of the disclosed receiver detection system includes a media access control circuit, a common mode voltage detector and a receiver detector. The common mode voltage detector is used to detect whether a common mode voltage meets a voltage condition, and after the common mode voltage meets the voltage condition, sends a ready signal to the receiver detector. The receiver detector is used to start a detection procedure based on the preparation complete signal and a detection start signal of the media access control circuit. In the detection process, the receiver detector sends a detection signal to determine whether a receiver exists, and then outputs a detection result to the media access control circuit, wherein the detection result indicates that the receiver does it exist.

於上述實施例中，該電壓條件包含：該共模電壓不小於一標準共模電壓的70%；以及該共模電壓不大於該標準共模電壓的130%，其中該標準共模電壓為一電源電壓的50%。 In the above embodiment, the voltage conditions include: the common mode voltage is not less than 70% of a standard common mode voltage; and the common mode voltage is not greater than 130% of the standard common mode voltage, where the standard common mode voltage is a 50% of supply voltage.

本揭露之接收器偵測裝置的一實施例包含前述共模電壓偵測器與接收器偵測器。 An embodiment of the receiver detection device of the present disclosure includes the aforementioned common mode voltage detector and receiver detector.

有關本發明的特徵、實作與功效，茲配合圖式作較佳實施例詳細說明如下。 Regarding the characteristics, implementation and effects of the present invention, the preferred embodiments are described in detail below with reference to the drawings.

100:接收器偵測系統 100: Receiver detection system

110:媒體存取控制電路 110:Media access control circuit

120:共模電壓偵測器 120: Common mode voltage detector

130:接收器偵測器 130:Receiver detector

RCV_DETECT:偵測開始訊號 RCV_DETECT: Detection start signal

VCM_READY:準備完成訊號 VCM_READY: Ready to complete signal

DET_SIGNAL:偵測訊號 DET_SIGNAL: detect signal

RXDET:偵測結果 RXDET: detection result

ENDDET:偵測結束訊號 ENDDET: Detection end signal

200:接收器偵測裝置 200: Receiver detection device

210:共模電壓偵測器 210: Common mode voltage detector

220:接收器偵測器 220: Receiver Detector

〔圖1〕顯示本揭露之接收器偵測系統的一實施例；以及〔圖2〕顯示本揭露之接收器偵測裝置的一實施例。 [Fig. 1] shows an embodiment of the receiver detection system of the present disclosure; and [Fig. 2] shows an embodiment of the receiver detection device of the present disclosure.

本說明書揭露一種接收器偵測系統與一種接收器偵測裝置。該系統與裝置能夠避免一接收器偵測器過早地開始偵測一接收器是否存在，從而避免錯誤的偵測結果。 This specification discloses a receiver detection system and a receiver detection device. The system and device can prevent a receiver detector from prematurely starting to detect the presence of a receiver, thereby avoiding erroneous detection results.

圖1顯示本揭露之接收器偵測系統的一實施例。圖1的接收器偵測系統100包含一媒體存取控制(media access control；MAC)電路110、一共模電壓偵測器120以及一接收器偵測器130。 FIG. 1 shows an embodiment of the receiver detection system of the present disclosure. The receiver detection system 100 of FIG. 1 includes a media access control (MAC) circuit 110, a common mode voltage detector 120 and a receiver detector 130.

請參閱圖1。媒體存取控制電路110用來傳送一偵測開始訊號(RCV_DETECT)給接收器偵測器130。於一實作範例中，接收器偵測系統100應用於一傳送器(未顯示於圖)且該傳送器符合快捷週邊組件互連(Peripheral Component Interconnect Express；PCIe)協定或通用序列匯流排(Universal Serial Bus；USB)協定。當該傳送器從一擱置狀態(suspend state)進入一恢復狀態(resume state)時，媒體存取控制電路110據以發出該偵測開始訊號。值得注 意的是，在實施為可行的前提下，接收器偵測系統100可應用於符合其它協定的裝置。 See Figure 1. The media access control circuit 110 is used to send a detection start signal (RCV_DETECT) to the receiver detector 130 . In an implementation example, the receiver detection system 100 is applied to a transmitter (not shown in the figure) and the transmitter complies with the Peripheral Component Interconnect Express (PCIe) protocol or the Universal Serial Bus (Universal Serial Bus). Serial Bus; USB) protocol. When the transmitter enters a resume state from a suspend state, the media access control circuit 110 sends the detection start signal accordingly. Worth noting It is noted that the receiver detection system 100 may be applied to devices complying with other protocols, provided that the implementation is feasible.

請參閱圖1。共模電壓偵測器120用來偵測一共模電壓是否滿足一電壓條件，並於該共模電壓滿足該電壓條件後，發送一準備完成訊號(VCM_READY)給接收器偵測器130。於一實作範例中，共模電壓偵測器120包含一已知的/自行開發的比較器；該比較器用來比較該共模電壓與至少一電壓門檻，以讓共模電壓偵測器120判斷該共模電壓是否滿足該電壓條件。於一實作範例中，共模電壓偵測器120包含一已知的/自行開發的類比至數位轉換器；該類比至數位轉換器用來將該共模電壓轉換為一數位值，以讓共模電壓偵測器120依據該數位值得知該共模電壓的大小，從而判斷該共模電壓是否滿足該電壓條件。 See Figure 1. The common mode voltage detector 120 is used to detect whether a common mode voltage meets a voltage condition, and after the common mode voltage meets the voltage condition, sends a ready signal (VCM_READY) to the receiver detector 130. In an implementation example, the common-mode voltage detector 120 includes a known/self-developed comparator; the comparator is used to compare the common-mode voltage with at least one voltage threshold, so that the common-mode voltage detector 120 Determine whether the common mode voltage meets the voltage condition. In an implementation example, the common-mode voltage detector 120 includes a known/self-developed analog-to-digital converter; the analog-to-digital converter is used to convert the common-mode voltage into a digital value to allow the common The mode voltage detector 120 obtains the magnitude of the common mode voltage according to the digital value, thereby determining whether the common mode voltage meets the voltage condition.

承上所述，於一實作範例中，該電壓條件包含「該共模電壓達到一標準共模電壓」。於一實作範例中，該電壓條件包含「該共模電壓不小於一標準共模電壓的70%」。於一實作範例中，該電壓條件包含「該共模電壓不大於該標準共模電壓的130%」。於一實作範例中，該標準共模電壓為一電源電壓(VDD)的50%。於一實作範例中，該標準共模電壓為前述傳送器之一對差動輸出訊號(例如：符合PCIe/USB協定之高速輸出正端訊號(HSOP)與高速輸出負端訊號(HSON))的和。值得注意的是，前述電壓條件與標準共模電壓可視實施需求而定。另值得注意的是，媒體存取控制電路110於一第一時間點發出該偵測開始訊號，共模電壓偵測器120於一第二時間點偵測到該共模電壓滿足該電壓條件，該第一時間點通常會早於該第二時間點。 Based on the above, in an implementation example, the voltage condition includes "the common mode voltage reaches a standard common mode voltage." In an implementation example, the voltage condition includes "the common mode voltage is not less than 70% of a standard common mode voltage." In an implementation example, the voltage condition includes "the common mode voltage is not greater than 130% of the standard common mode voltage." In an implementation example, the standard common-mode voltage is 50% of a supply voltage (V DD ). In an implementation example, the standard common mode voltage is one pair of differential output signals of the aforementioned transmitter (for example, high-speed output positive signal (HSOP) and high-speed output negative signal (HSON) in compliance with the PCIe/USB protocol) of and. It is worth noting that the aforementioned voltage conditions and standard common-mode voltage depend on implementation requirements. It is also worth noting that the media access control circuit 110 sends the detection start signal at a first time point, and the common mode voltage detector 120 detects that the common mode voltage meets the voltage condition at a second time point. The first time point will usually be earlier than the second time point.

請參閱圖1。接收器偵測器130用來依據前述偵測開始訊號(RCV_DETECT)與準備完成訊號(VCM_READY)開始一偵測程序。於該偵測程序中，接收器偵測器130發出一偵測訊號(DET_SIGNAL)用於判斷一接收器是否存在，然後據以輸出一偵測結果(RXDET)給媒體存取控制電路110，其中該偵測結果指出該接收器是否存在。舉例而言，當該接收器存在時，該偵測結果為一第一準位(例如：高準位)的電壓，而當該接收器不存在時，該偵測結果為一第二準位(例如：低準位)的電壓。值得注意的是，接收器偵測器130本身可用來判斷一接收器是否存在，或者包含接收器偵測器130的裝置(例如：前述傳送器)可用來判斷一接收器是否存在，然後回報一判斷結果給接收器偵測器130。由於本發明著重於何時開始該偵測程序而非如何判斷一接收器是否存在，因此，判斷一接收器是否存在的技術細節在此省略。 See Figure 1. The receiver detector 130 is used to start a detection process based on the aforementioned detection start signal (RCV_DETECT) and preparation completion signal (VCM_READY). In the detection process, the receiver detector 130 sends a detection signal (DET_SIGNAL) to determine whether a receiver exists, and then outputs a detection result (RXDET) to the media access control circuit 110 accordingly, where The detection result indicates whether the receiver is present. For example, when the receiver is present, the detection result is a first level (for example, high level) voltage, and when the receiver is not present, the detection result is a second level. (e.g. low level) voltage. It is worth noting that the receiver detector 130 itself can be used to determine whether a receiver exists, or a device including the receiver detector 130 (such as the aforementioned transmitter) can be used to determine whether a receiver exists and then report a The judgment result is given to the receiver detector 130. Since the present invention focuses on when to start the detection process rather than how to determine whether a receiver exists, the technical details of determining whether a receiver exists are omitted here.

承上所述，於一實作範例中，該偵測程序符合PCIe/USB協定；然此並非本發明的實施限制。於一實作範例中，接收器偵測器130本身用來判斷一接收器是否存在，且該偵測訊號為一脈衝訊號(pulse signal)；該脈衝訊號之訊號範圍的一中間電壓實質等於該共模電壓。於一實作範例中，該偵測訊號為一通知訊號；該通知訊號用來要求包含接收器偵測器130的裝置判斷一接收器是否存在。於一實作範例中，接收器偵測器130進一步用來於該偵測結序結束時，發送一偵測結束訊號(ENDDET)給媒體存取控制電路130；然此並非本發明的實施限制。 As mentioned above, in an implementation example, the detection process complies with the PCIe/USB protocol; however, this is not an implementation limitation of the present invention. In an implementation example, the receiver detector 130 itself is used to determine whether a receiver exists, and the detection signal is a pulse signal; an intermediate voltage of the signal range of the pulse signal is substantially equal to the common mode voltage. In an implementation example, the detection signal is a notification signal; the notification signal is used to request the device including the receiver detector 130 to determine whether a receiver exists. In an implementation example, the receiver detector 130 is further used to send a detection end signal (ENDDET) to the media access control circuit 130 when the detection sequence ends; however, this is not an implementation limitation of the present invention. .

圖2顯示本揭露之接收器偵測裝置的一實施例。圖2的接收器偵測裝置200包含一共模電壓偵測器210與一接收器偵測器220。共模電壓偵測器210的一實施例為圖1的共模電壓偵測器120。接收器偵測器220的一實施例為圖 1的接收器偵測器130。該偵測開始訊號(RCV_DETECT)是由圖1的媒體存取控制電路110或其等效電路發出。由於本技術領域具有通常知識者能夠參酌圖1的實施例來瞭解接收器偵測裝置200的細節與變化，重複及冗餘的說明在此省略。 FIG. 2 shows an embodiment of the receiver detection device of the present disclosure. The receiver detection device 200 of FIG. 2 includes a common mode voltage detector 210 and a receiver detector 220. An embodiment of the common mode voltage detector 210 is the common mode voltage detector 120 of FIG. 1 . An embodiment of the receiver detector 220 is shown in FIG. 1's receiver detector 130. The detection start signal (RCV_DETECT) is sent by the media access control circuit 110 of FIG. 1 or its equivalent circuit. Since those with ordinary skill in the art can refer to the embodiment of FIG. 1 to understand the details and changes of the receiver detection device 200, repeated and redundant descriptions are omitted here.

值得注意的是，在實施為可能的前提下，本技術領域具有通常知識者可選擇性地實施前述任一實施例中部分或全部技術特徵，或選擇性地實施前述複數個實施例中部分或全部技術特徵的組合，以實現本發明的實施彈性。 It is worth noting that, under the premise that implementation is possible, a person with ordinary skill in the art can selectively implement some or all of the technical features in any of the foregoing embodiments, or selectively implement some or all of the foregoing plural embodiments. All technical features are combined to achieve implementation flexibility of the present invention.

綜上所述，本揭露的接收器偵測系統與裝置能夠避免一接收器偵測器過早地開始偵測一接收器是否存在，從而避免錯誤的偵測結果。 In summary, the receiver detection system and device of the present disclosure can prevent a receiver detector from prematurely detecting the presence of a receiver, thereby avoiding erroneous detection results.

雖然本發明之實施例如上所述，然而該些實施例並非用來限定本發明，本技術領域具有通常知識者可依據本發明之明示或隱含之內容對本發明之技術特徵施以變化，凡此種種變化均可能屬於本發明所尋求之專利保護範疇，換言之，本發明之專利保護範圍須視本說明書之申請專利範圍所界定者為準。 Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may make changes to the technical features of the present invention based on the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the patent protection scope of the present invention must be determined by the patent application scope of this specification.

100:接收器偵測系統 110:媒體存取控制電路 120:共模電壓偵測器 130:接收器偵測器 RCV_DETECT:偵測開始訊號 VCM_READY:準備完成訊號 DET_SIGNAL:偵測訊號 RXDET:偵測結果 ENDDET:偵測結束訊號 100: Receiver detection system 110:Media access control circuit 120: Common mode voltage detector 130: Receiver Detector RCV_DETECT: Detection start signal VCM_READY: Ready to complete signal DET_SIGNAL: detect signal RXDET: detection result ENDDET: Detection end signal

Claims (10)

一種接收器偵測系統，包含一媒體存取控制電路、一共模電壓偵測器與一接收器偵測器，其中：該共模電壓偵測器用來偵測一共模電壓是否滿足一電壓條件，並於該共模電壓滿足該電壓條件後，發送一準備完成訊號給該接收器偵測器；該接收器偵測器用來依據該準備完成訊號以及該媒體存取控制電路的一偵測開始訊號開始一偵測程序；以及於該偵測程序中，該接收器偵測器發出一偵測訊號用於判斷一接收器是否存在，然後輸出一偵測結果給該媒體存取控制電路，其中該偵測結果指出該接收器是否存在。 A receiver detection system includes a media access control circuit, a common mode voltage detector and a receiver detector, wherein: the common mode voltage detector is used to detect whether a common mode voltage meets a voltage condition, And after the common mode voltage meets the voltage condition, a ready signal is sent to the receiver detector; the receiver detector is used to rely on the ready signal and a detection start signal of the media access control circuit Start a detection procedure; and in the detection procedure, the receiver detector sends a detection signal to determine whether a receiver exists, and then outputs a detection result to the media access control circuit, wherein the The detection result indicates whether the receiver is present. 如請求項1之接收器偵測系統，其中該接收器偵測器進一步用來於該偵測結序結束時，發送一偵測結束訊號給該媒體存取控制電路。 The receiver detection system of claim 1, wherein the receiver detector is further used to send a detection end signal to the media access control circuit when the detection completion sequence ends. 如請求項1之接收器偵測系統，其中該電壓條件包含：該共模電壓不小於一標準共模電壓的70%。 For example, the receiver detection system of claim 1, wherein the voltage condition includes: the common mode voltage is not less than 70% of a standard common mode voltage. 如請求項1之接收器偵測系統，其中該媒體存取控制電路於一第一時間點發出該偵測開始訊號，該共模電壓偵測器於一第二時間點偵測到該共模電壓滿足該電壓條件，該第一時間點早於該第二時間點。 The receiver detection system of claim 1, wherein the media access control circuit sends the detection start signal at a first time point, and the common mode voltage detector detects the common mode voltage at a second time point. The voltage satisfies the voltage condition and the first time point is earlier than the second time point. 如請求項1之接收器偵測系統，其中該接收器偵測系統應用於一傳送器；當該傳送器從一擱置狀態(suspend state)進入一恢復狀態(resume state)後，該媒體存取控制電路發出該偵測開始訊號。 The receiver detection system of claim 1, wherein the receiver detection system is applied to a transmitter; when the transmitter enters a resume state from a suspend state, the media access The control circuit sends the detection start signal. 一種接收器偵測裝置，包含一共模電壓偵測器與一接收器偵測器，其中： 該共模電壓偵測器用來偵測一共模電壓是否滿足一電壓條件，並於該共模電壓滿足該電壓條件後，發送一準備完成訊號給該接收器偵測器；該接收器偵測器用來依據該準備完成訊號以及一媒體存取控制電路的一偵測開始訊號開始一偵測程序；以及於該偵測程序中，該接收器偵測器發出一偵測訊號用於判斷一接收器是否存在，然後輸出一偵測結果給該媒體存取控制電路，其中該偵測結果指出該接收器是否存在。 A receiver detection device includes a common mode voltage detector and a receiver detector, wherein: The common mode voltage detector is used to detect whether a common mode voltage meets a voltage condition, and after the common mode voltage meets the voltage condition, sends a preparation completion signal to the receiver detector; the receiver detector uses To start a detection procedure based on the preparation completion signal and a detection start signal of a media access control circuit; and in the detection procedure, the receiver detector sends a detection signal for determining a receiver whether the receiver exists, and then outputs a detection result to the media access control circuit, wherein the detection result indicates whether the receiver exists. 如請求項6之接收器偵測裝置，其中該接收器偵測器進一步用來於該偵測結序結束時，發送一偵測結束訊號給該媒體存取控制電路。 The receiver detection device of claim 6, wherein the receiver detector is further used to send a detection end signal to the media access control circuit when the detection completion sequence ends. 如請求項6之接收器偵測裝置，其中該電壓條件包含：該共模電壓不小於一標準共模電壓的70%。 For example, the receiver detection device of claim 6, wherein the voltage condition includes: the common mode voltage is not less than 70% of a standard common mode voltage. 如請求項6之接收器偵測裝置，其中該共模電壓偵測器於一第一時間點收到該偵測開始訊號，該共模電壓偵測器於一第二時間點偵測到該共模電壓滿足該電壓條件，該第一時間點早於該第二時間點。 For example, the receiver detection device of claim 6, wherein the common mode voltage detector receives the detection start signal at a first time point, and the common mode voltage detector detects the detection start signal at a second time point. The common mode voltage satisfies the voltage condition, and the first time point is earlier than the second time point. 如請求項6之接收器偵測裝置，其中該接收器偵測系統應用於一傳送器；當該傳送器從一擱置狀態進入一恢復狀態後，該共模電壓偵測器收到該偵測開始訊號。 The receiver detection device of claim 6, wherein the receiver detection system is applied to a transmitter; when the transmitter enters a recovery state from a idle state, the common mode voltage detector receives the detection Start signal.
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US20150120973A1 (en) * 2012-12-31 2015-04-30 Huawei Technologies Co., Ltd. Method for detecting receive end, detection circuit, optical module, and system
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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150120973A1 (en) * 2012-12-31 2015-04-30 Huawei Technologies Co., Ltd. Method for detecting receive end, detection circuit, optical module, and system
US20210055963A1 (en) * 2019-08-23 2021-02-25 Microchip Technology Incorporated Wake detection at controller for physical layer of single pair ethernet network, and related systems, methods and devices

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