JP5048424B2 - Disconnect detection circuit and transmitter / receiver - Google Patents

Description

  The present invention relates to a disconnection detection circuit that determines device removal in serial data transmission.

  The USB (Universal Serial Bus) standard is widely used as an interface for connecting computers (PCs), printers, scanners, DVD drives, digital video cameras, and the like. Furthermore, in recent years, attention has also been paid to data transfer applications such as cellular phones and portable music players.

  In the USB standard, the host device is required to have a large number of functions such as command transmission to the target device, status check, scheduling, and attachment / detachment check. On the other hand, since the target device has a fairly simple configuration with hardware and software, it can also be used for inexpensive devices. As described above, the USB device intentionally makes the host and the target asymmetrical so that the target side is as simple and inexpensive as possible, and various peripheral devices can be connected to one bus. Although the host-side function is difficult to implement, the host CPU usually has very high performance, and the controller is also built in the chipset, so there are few cost problems.

  Data transmission / reception of USB 2.0, which is a USB high-speed transfer standard, is performed by a small amplitude differential signal. In the high-speed serial interface standard such as USB 2.0, the maximum transfer speed is as high as 480 Mbps, and therefore data is transferred with a pair of small amplitude differential signals. By making the signal a small amplitude, signal transmission / reception is performed at high speed, and by making the signal differential, resistance to noise is increased. Whether or not the counterpart device is removed is also detected by detecting this small amplitude differential signal.

  In the USB 2.0 HS mode (HighSpeed mode), an upstream device (a HOST device called a HOST device or a HUB device) detects a connection state with a downstream device (a target device called a peripheral device). In addition, the USB interface differential signals DP and DM are driven to J state (DP terminal is at H level and DM terminal is at L level) or K state (DP terminal is at L level and DM terminal is at H level). When the differential voltage value between DP and DM at this time is 625 mV or more, it is determined that the downstream device must be recognized as being disconnected. It is also determined that if the voltage is 525 mV or less, the downstream device must be recognized as being connected. As described above, since the threshold value for non-connection / connection is minute, there is a problem that the operation for detecting the connection state tends to be insufficient. In addition, although the USB device is usually implemented as an LSI, it is difficult to guarantee the absolute value in consideration of process variations and variations in ambient temperature in the functions realized by LSI, especially analog circuits. However, in order to realize it, there is a problem that an excessive operating current is required and the circuit scale becomes excessive.

  However, in recent years, the USB-OTG (On-The-Go) standard that can be used as both a host device and a target device has been established as an extension of the USB 2.0 standard, and is being adopted in USB devices for portable devices such as mobile phones. is there. In other words, an OTG device that operates as a target device is being used as a host device when a target device such as a USB memory is connected, and when connected to a PC as usual. In the OTG standard, the function of a conventional upstream device is also required. Accordingly, there is a demand for a smaller and lower current consumption than ever before. As described above, since the monitoring of the attachment / detachment of the target device is a function of the host device, it is also necessary for the OTG device. The attachment / detachment is monitored by a disconnect detection circuit.

  The disconnect detection circuit determines whether the target device is connected based on the amplitude value of the small amplitude differential signal. For example, the USB 2.0 authentication test stipulates that a connection state must be determined when the differential amplitude is 525 mV or less, and a non-connection state must be determined when the differential amplitude is 625 mV or more. Since high-precision detection is required, the operation tends to be insufficient. Moreover, in order to be mounted on a portable device such as a cellular phone, countermeasure techniques are required more than ever, such as reduction of current consumption and reduction of circuit scale.

For example, Japanese Patent Application Laid-Open Nos. 2007-49273 and 2007-73036 have been made in order to solve this problem, and a disconnect circuit suitable for LSI implementation has been proposed. However, since it is a circuit that compares with a fixed reference voltage, it cannot be said to be sufficiently effective.
JP 2007-49273 A JP 2007-73036 A

  In view of such a situation, an object of the present invention is to provide a disconnection detection circuit whose operation is not insufficient even when there is a variation in process and ambient temperature.

  A first disconnect detection circuit according to the present invention receives a serial transmission signal made up of a pair of differential signals transmitted at regular intervals, and amplifies the voltage of the pair of differential signals. A dynamic amplifier, a second differential amplifier that amplifies the inverted voltage of the differential signal, a third differential amplifier that amplifies the output voltage of the DA converter, and a third differential amplifier based on the output voltage of the first differential amplifier. A first subtractor for subtracting the output voltage of the differential amplifier, a first comparator for determining the sign of the subtraction result of the first subtractor, and a third difference from the output voltage of the second differential amplifier. A second subtracter for subtracting the output voltage of the dynamic amplifier; a second comparator for determining whether the subtraction result of the second subtractor is positive; an output voltage of the first comparator; and an output of the second comparator When one of the voltages is positive, output 1 and other If the output of the OR circuit that outputs 0 at the same time and the output of the OR circuit at a predetermined time position of the transmission signal that is determined to be transmitted at regular intervals is 1, the output voltage of the DA converter is decreased. When the output of the OR circuit is 0, the output voltage of the DA converter is increased, and when the output of the OR circuit changes from 1 to 0 or from 0 to 1, the set value of the DA converter is used. It consists of a detection control circuit that uses the amplitude value of the signal. Device removal is determined from the amplitude value.

  A second disconnection detection circuit according to the present invention detects an amplitude value of a differential signal of a transmission signal having a format defined by a pair of differential signals that are determined to be transmitted at regular intervals. A disconnect detection circuit for determining whether the device is removed, a first differential amplifier that amplifies the voltage of the differential signal, a second differential amplifier that amplifies the inverted voltage of the differential signal, and a DA converter A third differential amplifier that amplifies the voltage of the first differential amplifier, a first comparator that compares the output voltage of the first differential amplifier and the output voltage of the third differential amplifier, and the output voltage of the second differential amplifier And the second comparator for comparing the output voltages of the third differential amplifier, 1 is output when either the output voltage of the first comparator or the output voltage of the second comparator is positive, and the others Output 0 if When the output of the OR circuit at the predetermined time position of the R signal and the transmission signal determined to be transmitted every predetermined time is 1, the output voltage of the DA converter is lowered and the output of the OR circuit Is 0, the output voltage of the DA converter is increased, and the setting value of the DA converter when the output of the OR circuit changes from 1 to 0 or from 0 to 1 is detected as the amplitude value of the differential signal It consists of a control circuit. Device removal is determined from the amplitude value.

  The third disconnection detection circuit according to the present invention receives a serial transmission signal composed of a pair of differential signals transmitted at regular intervals and amplifies the voltage of the pair of differential signals. A first differential amplifier capable of amplifying an inverted voltage of the differential signal, a second differential amplifier capable of controlling an offset voltage, amplifying the voltage of the DA converter, and the first and second differences. A third differential amplifier serving as an offset control input of the dynamic amplifier; a first comparator for determining whether the output voltage of the first differential amplifier is positive or negative; and whether the output voltage of the second differential amplifier is positive or negative. A second comparator for determining; an OR circuit that outputs 1 when any of the output voltage of the first comparator and the output voltage of the second comparator is positive; and outputs 0 in other cases; Send at regular intervals When the output of the OR circuit at a predetermined time position of the transmission signal is determined to be 1, the output voltage of the DA converter is decreased, and when the output of the OR circuit is 0, the DA converter voltage And a detection control circuit for setting the DA converter set value when the OR circuit output changes from 1 to 0 or from 0 to 1 as the amplitude value of the differential signal. Device removal is determined from the amplitude value.

  In any one of the disconnection detection circuits, preferably, the first and second differential amplifiers, the first and second subtractors, and the first and second comparators are arranged close to each other.

  Any of the disconnection detection circuits preferably includes holding means for holding the output of the OR circuit, and the DA converter and the other parts can be separately set to an enable state.

  In any one of the disconnect detection circuits, the format of the transmission signal is, for example, the USB 2.0 standard.

  A transmission / reception apparatus according to the present invention is a transmission / reception apparatus of a serial data interface that transmits / receives transmission signals to / from each other, and a transmission circuit that transmits a serial transmission signal composed of a pair of differential signals transmitted every predetermined time; Any one of the disconnect detection circuits described above is included.

  In the disconnect detection method according to the present invention, a serial transmission signal composed of a pair of differential signals transmitted at regular intervals is input, and the voltage of the pair of differential signals and the inverted voltage thereof are differentially amplified. Next, the differential amplification value of the voltage of the differential signal is compared with the output voltage of the DA converter, and the differential amplification value of the inverted voltage of the differential signal is compared with the difference between the output voltages of the DA converter. . When one of the differential amplification values is larger by OR operation of the two comparison results, 1 is output. When the output of the OR operation at a predetermined time position of the transmission signal transmitted every predetermined time is 1, the output voltage of the DA converter is lowered, and when the output of the OR operation is 0, the output voltage of the DA converter And the set value of the DA converter when the output of the OR operation changes from 1 to 0 or from 0 to 1 is used as the amplitude value of the differential signal. Then, the removal of the device is determined from the magnitude of the amplitude value.

The disconnect detection circuit and the transmission / reception apparatus according to the present invention can accurately detect the removal of a device even if an amplification gain or an offset voltage is generated based on a change in process or ambient temperature.
In addition, the circuit scale is small and the device operates with low power consumption.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
With reference to FIG. 1, disconnect detection in the HS mode of the USB 2.0 standard will be described. As shown in FIG. 1, a serial data interface is provided between a transmission side device and a reception side device, and a transmission signal having a format defined by a pair of differential signals DP and DM is transmitted. In the HS mode, the differential signal pair DP, DM is terminated at 45Ω in each of the transmission side device and the reception side device. The transmission driver is determined to drive a current in this state, that is, a differential signal amplitude of approximately 400 mV with a combined resistance of 22.5Ω. Considering the case where the receiving side device is removed now, it can be easily seen that the differential signal amplitude is approximately doubled to 800 mV. In this manner, disconnection detection is performed by detecting the differential amplitude level and determining whether or not the device has been removed. In order to detect this, the disconnection detection circuit detects the differential signal amplitude of the differential signal pair DP and DM on the output side of the transmission driver, and determines whether or not to remove from the magnitude. The transmission side device and the reception side device are, for example, transceivers based on the USB-OTG standard.

  According to the USB standard, data transfer is performed while exchanging a data string of a minimum configuration called a packet between both sides. What is temporal is managed in units of frames starting with SOF (Start Of Flame) packets. In the USB 2.0 HS mode, one frame is 125 μsec, and the packet is scheduled so as not to cross the frame, and the maximum number of data packets that can be inserted in one frame is determined.

  Further, it is determined that a packet starts with a SYNC pattern (sometimes called SOP: Start Of Packet) and ends with an EOP (End Of Packet) pattern. Here, although details are omitted, the differential 1 is represented as J, the differential 0 is represented as K, and the SYNC pattern is a 32-bit pattern of 15 repetitions of KJ and KK. The EOP pattern is a pattern in which the inverted J follows if the previous state is K, and the inverted K if the previous state is J continues for a predetermined bit length (40 bits for the SOF packet described above).

  The transmission of the SOF packet is determined by the host device having a function for managing scheduling, that is, the upper device, and whether or not the downstream device is removed at the differential amplitude level in the EOP period of the SOF packet. It is decided to judge.

  FIG. 2 shows a general waveform when an SOF packet is transmitted in the USB mode HS mode. In the figure, the level of the differentially amplified voltage is shown with respect to time. The packet includes a SYNC pattern at 55 to 115 msec and an EOP pattern at 175 to 255 msec. In this way, the differential amplitude level in the minimum inversion period (240 MHz in terms of frequency) and the non-inversion period (240/40 = 6 Mhz in frequency) like the EOP pattern due to the frequency characteristics of the amplifier. Will be very different. Of course, if an amplifier with a flat amplification factor up to 240 MHz is used, such a waveform will not be obtained, but it is clear that the circuit scale and current consumption become excessive. Therefore, in the USB 2.0 standard, it has been decided to perform disconnect detection in an EOP pattern period (period of 175 to 255 nsec in FIG. 2) in which the amplitude is relatively stable.

FIG. 3 shows an embodiment of the disconnect detection circuit. The voltage difference of the differential signal pair DP-DM is amplified by the first differential amplifier 10, and the voltage difference of DM-DP is amplified by the second differential amplifier 12. At the same time, the reference voltage to be compared generated by the DA converter 16 is also amplified by a third differential amplifier 14 (a circuit made by a so-called replica method) having characteristics similar to those of the differential amplifiers 10 and 12. Is done. The DA converter 16 outputs a reference voltage based on input data (set value DAC data). Each output of the differential amplifier 10 and 12, after being subtracted in the subtracter 18, 20 by the output of the differential amplifier 14 is compared with a zero-cross comparator 22, 24. The outputs of the zero-cross comparators 22 and 24 are ORed by the OR circuit 26, latched by the latch 28 at a predetermined time with the timing signal LT, and output as a latch signal LO. The latch timing is shown in FIG. Here, the analog circuits of the differential amplifiers 10, 12, 14, the subtractors 18, 20, and the zero cross comparators 22, 24 are arranged in the vicinity in the same layout, or in a bilaterally symmetric or vertically symmetric layout. . Thereby, an element with uniform characteristics can be realized relatively easily.

  FIG. 4 shows another embodiment of the disconnect detection circuit. The voltage difference DP-DM of the differential signal pair is amplified by the differential amplifier 10, and the voltage difference of DM-DP is amplified by the differential amplifier 12. At the same time, the reference voltage to be compared (generated by the DA converter 16) is also amplified by the differential amplifier 14 having the same characteristics as the differential amplifiers 10 and 12. The outputs of the differential amplifiers 10 and 12 are compared with the outputs of the differential amplifier 14 by zero cross comparators 22 and 24, respectively. The outputs of the comparators 22 and 24 are latched by the timing signal LT at a predetermined time shown in FIG. 6 in the latch 28 after the OR operation in the OR circuit 26, and output as the latch signal LO.

  In general, it is very difficult to compensate for absolute values such as amplifier characteristics in an LSI in consideration of process variations, ambient temperature, etc., but the relative characteristics can be obtained by arranging them in the same area in the same area in the same LSI. It is relatively easy to align. In the disconnect detection circuit shown in FIGS. 3 and 4, only the characteristics of the differential amplifier, the subtractor, the comparator, etc. are required to be relatively uniform, so that the circuit is small in size and consumes little current. it can. Also, since the DA converter 16 only needs to generate an output change of the OR circuit output for determining the differential amplitude value, the absolute value accuracy is not required so much, and the conversion time is not until the next predetermined transmission signal. Since it only needs to be stable, it can be realized with a circuit having a small size and low current consumption.

  In general, a comparator is faster and more accurate when compared with a reference voltage that does not vary. Therefore, in the circuit of FIG. 3, a subtracter is placed in front of the comparator. However, if the operation speed and accuracy of the comparator are satisfied, it is preferable to use the circuit of FIG. 4 that does not use a subtracter.

  FIG. 5 shows another embodiment of the disconnect detection circuit. The differential signal pair voltage difference DP-DM is amplified by the differential amplifier 10 ', and the DM-DP voltage difference is amplified by the differential amplifier 12'. At the same time, the reference voltage to be compared (generated by the DA converter 16) is also amplified by the differential amplifier 14 having the same characteristics as the differential amplifiers 10 'and 12'. Here, the differential amplifiers 10 ′ and 12 ′ are differential amplifiers having an offset voltage canceling function. After the output of the differential amplifier 14 is canceled as an offset voltage, they are compared by the zero cross comparators 22 and 24. The outputs of the zero cross comparators 22 and 24 are ORed by the OR circuit 26, and then latched by the latch 28 with the timing signal LT at a predetermined time shown in FIG. 6, and output as a latch signal LO. In this disconnect detection circuit, the subtraction of the output of the third differential amplifier is substituted by the offset cancel function, so that the subtracters 18 and 20 can be omitted. Other functions and effects are the same as those of the circuit of FIG. A differential amplifier is often used as an instrumentation amplifier. An instrumentation amplifier usually has a function of canceling an offset in its application. That is, the differential amplifiers 10 ′ and 12 ′ with an offset cancel function used in the present embodiment are highly reliable technologies.

  FIG. 6 shows the timing for determining the latch timing signal LT and the set value for the DA converter in the disconnect detection circuit of FIG. 3, FIG. 4 or FIG. The latch timing signal LT is output at the end of the EOP period of the SOF packet. The Clock, TxValid, TxReady, and TxDATA signals are signals of physical layer blocks including the SIE (Serial Interface Engine) that realizes the logical function of the USB device, the disconnect circuit of the present invention, and the driver and receiver. It is written assuming the industry standard interface UTMI (USB Transceiver Macrocell Interface), but is not limited to UTMI.

  FIG. 7 is a flowchart showing a procedure for detecting a disconnect in the disconnect detection circuit described above. At the latch timing, that is, when the latch timing signal LT is at the H level (YES in S10), the output signal LO of the latch 28 is acquired. BLO (BeforeLO: output signal LO held at the previous timing) is also stored. If both LO and BLO are H (YES in S12), the value (DACdata) set in the DA converter 16 is decremented (S14), and the generated voltage of the DA converter is lowered. If both LO and BLO are L (YES in S16), the value (DACdata) set in the DA converter 16 is incremented (S18), and the generated voltage of the DA converter 16 is increased. If the values of LO and BLO are different (NO in S16), the set value for the DA converter at that time is used as determination data (S20). Here, if the relationship between the setting data to the DA converter 16 and the generated voltage is in a proportional relationship, the setting data should be almost twice the difference between the connected state and the disconnected state of the downstream device. Therefore, it can be easily determined whether or not it has been removed.

  The disconnect detection detects whether or not the connection connector between the devices is physically removed, so that it is not necessary to be able to determine instantaneously. For example, in the USB 2.0 standard, it is described that the determination is made in the EOP portion of the SOF packet. This SOF packet is a packet determined to be transmitted every 125 μs. In other words, during the period when the SOF packet is not transmitted, the disconnect detection circuit is in a disabled state and there is no problem, so disabling for power saving can be easily considered. However, when it is disabled, it is obvious that the next time it is enabled, it is necessary to allow the disconnect circuit to operate stably within a predetermined time. In general, in order to speed up the time until the output voltage of the DA converter 16 is stabilized, it is necessary to increase the operating current inside the DA converter, which in turn increases the circuit size. Therefore, in the power save, the enable time of the DA converter 16 and other parts can be set separately. As a result, it is possible to provide a disconnect detection circuit and a transmission / reception device without using a DA converter with a circuit scale and current consumption larger than necessary.

A specific power save will be described. In the circuits of FIGS. 3 to 5, the enable times of the DA converter 16 and other portions can be set separately. Further, holding means for holding the output of the OR circuit 26 is provided.
(A) holding the output of the OR circuit 26 at a predetermined time of the transmission signal that is determined to be transmitted at regular intervals;
(B) Next, the disconnect detection circuit is set to the disable state, and the power saving mode is set.
(C) The DA converter 16 is enabled (valid) a predetermined time before the transmission time of the next transmission signal,
(D) Thereafter, the parts other than the DA converter 16 are enabled (valid).

The figure for demonstrating the disconnection detection in HS mode of USB2.0 specification The figure which shows a general waveform at the time of transmitting a SOF packet in HS mode The circuit diagram of the disconnection detection circuit of one embodiment of the present invention Circuit diagram of disconnect detection circuit of another embodiment of the present invention Circuit diagram of disconnect detection circuit of another embodiment of the present invention The figure which shows the timing which fixes the setting value to the latch timing signal LT and DA converter Flow chart of procedure for disconnect detection

Explanation of symbols

  10, 12, 14 Differential amplifier, 16 DA converter, 18, 20 Subtractor, 22, 24 Comparator, 26 OR gate, 28 Latch.

Claims (8)

A first differential amplifier for inputting a serial transmission signal consisting of a pair of differential signals transmitted at regular intervals and amplifying the voltage of the pair of differential signals;
A second differential amplifier for amplifying an inverted voltage of the pair of differential signals;
A third differential amplifier for amplifying the output voltage of the DA converter;
A first subtractor that subtracts the output voltage of the third differential amplifier from the output voltage of the first differential amplifier, and a first comparator that determines whether the subtraction result of the first subtractor is positive or negative;
A second subtractor that subtracts the output voltage of the third differential amplifier from the output voltage of the second differential amplifier, and a second comparator that determines whether the subtraction result of the second subtractor is positive or negative.
An OR circuit that outputs 1 when either the subtraction result of the first comparator or the subtraction result of the second comparator is positive, and outputs 0 in other cases;
When the output of the OR circuit at a predetermined time position of the transmission signal transmitted every fixed time is 1, the output voltage of the DA converter is lowered, and when the output of the OR circuit is 0, the DA converter A detection control circuit that raises the output voltage and sets the output voltage of the DA converter when the output of the OR circuit changes from 1 to 0 or from 0 to 1, and sets the amplitude value of the differential signal. Disconnect detection circuit that determines device removal from the value. A first differential amplifier that inputs a serial transmission signal composed of a pair of differential signals transmitted at regular intervals and amplifies the voltage of the pair of differential signals;
A second differential amplifier for amplifying an inverted voltage of the pair of differential signals;
A third differential amplifier for amplifying the voltage of the DA converter;
A first comparator for comparing the output voltage of the first differential amplifier and the output voltage of the third differential amplifier;
A second comparator for comparing the output voltage of the second differential amplifier and the output voltage of the third differential amplifier;
An OR circuit that outputs 1 when either of the output voltage of the first comparator and the output voltage of the second comparator is positive, and outputs 0 in other cases;
When the output of the OR circuit at a predetermined time position of the transmission signal transmitted every fixed time is 1, the output voltage of the DA converter is lowered, and when the output of the OR circuit is 0, the DA converter A detection control circuit that raises the output voltage and uses the output voltage of the DA converter when the output of the OR circuit changes from 1 to 0 or from 0 to 1 as the amplitude value of the differential signal. Disconnect detection circuit that determines device removal. A first differential amplifier capable of offset voltage control, which receives a serial transmission signal composed of a pair of differential signals transmitted at regular intervals and amplifies the voltage of the pair of differential signals;
A second differential amplifier capable of offset voltage control for amplifying an inverted voltage of the differential signal;
A third differential amplifier that amplifies the voltage of the DA converter and serves as an offset control input of the first and second differential amplifiers;
A first comparator for determining whether the output voltage of the first differential amplifier is positive or negative;
A second comparator for determining whether the output voltage of the second differential amplifier is positive or negative;
An OR circuit that outputs 1 when either of the output voltage of the first comparator and the output voltage of the second comparator is positive, and outputs 0 in other cases;
When the output of the OR circuit at the predetermined time position of the transmission signal transmitted at regular time intervals is 1, the output voltage of the DA converter is lowered, and when the output of the OR circuit is 0, the DA converter voltage And a detection control circuit that uses the output voltage of the DA converter when the OR circuit output changes from 1 to 0 or from 0 to 1 as the amplitude value of the differential signal. Disconnect detection circuit to determine.   4. The device according to claim 1, wherein the first and second differential amplifiers, the first and second subtractors, and the first and second comparators are arranged close to each other. 5. The disconnect detection circuit described. Holding means for holding the output of the OR circuit;
The disconnect detection circuit according to any one of claims 1 to 4, wherein the DA converter 16 and other portions can be separately set to an enable state.   The disconnect detection circuit according to claim 1, wherein the transmission signal is a signal conforming to the USB 2.0 standard. A transmission circuit that transmits a serial transmission signal composed of a pair of differential signals that are transmitted at regular intervals, and the disconnection detection circuit according to claim 1,
A serial data interface transmitting / receiving device for transmitting and receiving the transmission signals to and from each other. A serial transmission signal composed of a pair of differential signals transmitted at regular time intervals is input, and the voltage of the pair of differential signals and the voltage of the inverted signal thereof are differentially amplified, respectively.
Comparing the differential amplification value of the voltage of the differential signal with the output voltage of the DA converter;
Comparing the differential amplification value of the inverted voltage of the differential signal with the difference in output voltage of the DA converter;
When one of the differential amplification values is larger than the output voltage of the DA converter by OR operation of the two comparison results, 1 is output,
When the output of the OR operation at a predetermined time position of the transmission signal transmitted every predetermined time is 1, the output voltage of the DA converter is lowered, and when the output of the OR operation is 0, the output of the DA converter The output voltage is raised, and the set value of the DA converter when the output of the OR operation changes from 1 to 0 or from 0 to 1, is used as the amplitude value of the differential signal,
A disconnect detection method for determining device removal from the magnitude of the amplitude value.

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