US20140291830A1 - Semiconductor packages having package-on-package structures - Google Patents
Semiconductor packages having package-on-package structures Download PDFInfo
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- US20140291830A1 US20140291830A1 US14/178,747 US201414178747A US2014291830A1 US 20140291830 A1 US20140291830 A1 US 20140291830A1 US 201414178747 A US201414178747 A US 201414178747A US 2014291830 A1 US2014291830 A1 US 2014291830A1
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Definitions
- An embodiment of the present inventive concept relates to semiconductors and, more particularly, to semiconductor packages having package-on-package structures.
- a problem with using a multi-chip stack package is that there is a strong possibility of a reduction in yield compared to using a single chip package.
- a package-on-package (POP) technology was developed to solve the problem with the reduction in yield and to still realize a high density chip stack. Inusing POP technology, known good packages are stacked to reduce the inferiority of the final product. This POP type package can be used to meet the trend toward both compact size of electronic portable appliances and multiple functions of mobile products.
- SiP System-in-Package
- the present inventive concept provides semiconductor packages having through electrodes and methods of fabricating the same in which a narrower pitch may expand to a wider pitch without interposers.
- a semiconductor package that has a lower package including a lower semiconductor chip on a lower package substrate, and an upper package including an upper semiconductor chip on an upper package substrate.
- the upper semiconductor chip may have a plurality of chip pads and the upper package substrate may have a plurality of substrate pads.
- the upper package may be stacked on the lower package.
- the chip pads may have a first pitch and the substrate pads may have a second pitch greater than the first pitch.
- the upper package substrate may comprise a plurality of connection lines that electrically connect the substrate pads to the chip pads.
- the semiconductor package may further comprise a plurality of connection terminals that electrically connect the upper package to the lower package.
- the connection terminals may be provided between the upper package and the lower package.
- the lower package may further comprise a lower mold layer and a plurality of connection patterns on the lower mold layer.
- the connection patterns may be electrically connected to the connection lines.
- the lower mold layer may comprise an opening exposing a portion of the lower package substrate.
- the connection patterns may extend toward inside the opening to be electrically connected to the lower package substrate.
- the opening may comprise at least one of a line-type trench and a plurality of holes arranged along lateral sides of the lower semiconductor chip.
- a semiconductor package that has a lower package including a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, a lower mold layer encapsulating the lower semiconductor chip, and connection patterns on the lower mold layer that penetrate the lower mold layer to be electrically connected to the lower package substrate, an upper package including an upper package substrate having substrate pads, and an upper semiconductor chip mounted on the upper package substrate, the upper package being stacked on the lower package, and connection terminals interposed between the lower and upper packages, the connection terminals electrically connecting the lower and upper packages.
- the upper semiconductor chip may include chip pads having a pitch narrower than a pitch of the substrate pads.
- the upper package substrate may include connection lines that provide electrical paths between the substrate pads and the chip pads. The connection lines may allow the chip pads to access a wider pitch of the substrate pads to electrically connect the upper semiconductor chip to the lower package substrate.
- the lower package substrate may comprise circuit patterns electrically connected to the connection patterns.
- the lower mold layer may comprise an opening that is spaced apart from a lateral side of the lower semiconductor chip and vertically penetrates the lower mold layer to expose the circuit patterns.
- the connection patterns may extend toward the lower package substrate to pass through the opening to be electrically connected to the circuit patterns.
- the upper semiconductor chip may be disposed on the upper package substrate while a surface of the upper semiconductor chip faces the upper package substrate.
- the surface of the upper semiconductor chip may contact the upper package substrate.
- the lower package further may include internal terminals provided between the lower semiconductor chip and the lower package substrate.
- the lower semiconductor chip may be disposed on the lower package substrate to be electrically connected thereto through the internal terminals while a surface of the lower semiconductor chip faces the lower package substrate.
- the lower semiconductor chip may comprise a logic chip and the upper semiconductor chip may comprise a memory chip.
- the foregoing and/or other features of the present general inventive concept may be achieved by providing a semiconductor package that has a package-on-package type package including lower and upper packages vertically stacked and electrically connected.
- the lower package may comprise a lower semiconductor chip mounted on a lower package substrate and encapsulated by a lower mold layer.
- the upper package may comprise an upper semiconductor chip having chip pads mounted on an upper package substrate without a gap between the upper semiconductor chip and the upper package substrate.
- the upper package substrate may include connection lines electrically connected to the upper semiconductor chip. The connection lines may be configured to provide the chip pads with access to a wider pitch to electrically connect the upper semiconductor chip to the lower package substrate.
- the upper package substrate may comprise substrate pads having a pitch greater than a pitch of the chip pads.
- the package-on-package type package may further comprise connection terminals provided between the lower and upper packages.
- the lower package may further comprise connection patterns disposed on the lower mold layer to be electrically connected to the connection terminals.
- connection patterns may penetrate through the lower mold layer to be electrically connected to the lower package substrate.
- the lower package may further comprise an opening that penetrates through the lower mold layer and provides the connection patterns with paths toward the lower package substrate.
- the opening may comprise at least one of a line-type trench extending along lateral sides of the lower semiconductor chip and a plurality of holes arranged along the lateral sides of the lower semiconductor chip.
- a semiconductor memory having a first package including a first semiconductor chip on a first substrate, and a second package electrically connected to the first package and including a second semiconductor chip, with chip pads having a first pitch, on a second substrate with substrate pads having a second pitch greater than the first pitch, the chip pads electrically connected to the substrate pads by connection lines, and a memory controller electrically connected to the semiconductor memory and configured to write in data to and to read the data from at least one of the first semiconductor chip and the second semiconductor chip.
- the second package may exclude micro-bumps between the second semiconductor chip and the second substrate.
- the first semiconductor chip may be embedded in the first substrate.
- the substrate pads may be located at one of a center of, an edge of, a specific region of, and uniformly across a lower surface of the second substrate, and the chip pads are located at one of a center of, an edge of, and uniformly across an active surface of the second semiconductor chip.
- the electronic system may further include a system bus, a central processing unit electrically connected to the system bus, a random-access memory electrically connected to the system bus, a user interface electrically connected to the system bus, and a modem electrically connected to the system bus, and the memory controller may be electrically connected to the system bus.
- FIGS. 1A is a cross sectional view illustrating a semiconductor package according to an embodiment of the present inventive concept
- FIGS. 1B to 1E are plan views illustrating various examples of an opening of the semiconductor package according to an embodiment of the present inventive concept
- FIG. 1F is a schematic diagram illustrating an electrical connection in an upper package of the semiconductor package according to an embodiment of the present inventive concept
- FIG. 1G is a cross sectional view illustrating a portion of the upper package included in the semiconductor package according to an embodiment of the present inventive concept
- FIGS. 2A to 2F are cross sectional views illustrating semiconductor packages according to embodiments of the present inventive concept
- FIG. 3A is a schematic block diagram illustrating an example of a memory card that includes a semiconductor package according to embodiments of the present inventive concept.
- FIG. 3B is a schematic block diagram illustrating an example of an information process system that includes a semiconductor package according to embodiments of the present inventive concept.
- FIGS. 1A is a cross sectional view illustrating a semiconductor package 1 according to an embodiment of the present inventive concept.
- FIGS. 1B to 1E are plan views illustrating various examples of an opening 137 of the semiconductor package 1 according to an embodiment of the present inventive concept.
- FIG. 1F is a schematic diagram illustrating an electrical connection in an upper package 20 of the semiconductor package 1 according to an embodiment of the present inventive concept.
- FIG. 1G is a cross sectional view illustrating a portion of the upper package 20 included in the semiconductor package 1 according to exemplary embodiments of the present inventive concepts.
- the semiconductor package 1 may be a package-on-package type package that includes the upper package 20 stacked on a lower package 10 .
- the lower package 10 may comprise a lower package substrate 110 , a lower semiconductor chip 120 disposed on the lower package substrate 110 , and a lower mold layer 130 that encapsulates the lower semiconductor chip 120 .
- the upper package 20 may comprise an upper package substrate 210 , an upper semiconductor chip 220 disposed on the upper package substrate 210 , and an upper mold layer 230 that encapsulates the upper semiconductor chip 220 .
- the upper semiconductor chip 220 and the lower semiconductor chip 120 may be a same or a different kind of chip.
- the upper semiconductor chip 220 may be a memory chip and the lower semiconductor chip 120 may be a logic chip.
- the lower semiconductor chip 120 may be bonded onto the lower package substrate 110 , which has circuit patterns 112 , in a flip-chip manner in which an active surface 120 f faces the lower package substrate 110 , and may be electrically connected to the lower package substrate 110 through one or more internal terminals 124 .
- the circuit patterns 112 may provide electrical paths that vertically penetrate the lower package substrate 110 .
- the lower mold layer 130 may comprise the at least one vertical opening 137 that exposes the circuit patterns 112 .
- the opening 137 may have, for example, a trench shape or a hole shape.
- the opening 137 may have a ring-type trench shape that continuously extends along lateral sides of the lower semiconductor chip 120 as illustrated in FIG. 1B , or a line-type trench shape that extends along opposing lateral sides of the lower semiconductor chip 120 as illustrated in FIG. 10 .
- the opening 137 may have, for example, a hole shape that includes a plurality of holes arranged continuously along lateral sides of the lower semiconductor chip 120 as illustrated in FIG. 1D , or arranged along opposing lateral sides of the lower semiconductor chip 120 as illustrated in FIG. 1E .
- connection patterns 135 may be disposed on the lower mold layer 130 to be electrically connected to the circuit patterns 112 .
- the connection patterns 135 may extend toward inside the opening 137 to be directly coupled to the circuit patterns 112 such that the connection patterns 135 may be electrically connected to the lower package substrate 110 .
- An insulation layer 132 may be further provided between the lower mold layer 130 and the connection patterns 135 .
- the insulation layer 132 may prevent an electrical interconnection between the connection patterns 135 and the lower semiconductor chip 120 .
- a sidewall of the opening 137 may be covered by the insulation layer 132 .
- a bottom floor of the opening 137 may not be covered by the insulation layer 132 such that the circuit patterns 112 may be exposed through the opening 137 .
- the lower package substrate 110 may further comprise one or more external terminals 114 coupled to the circuit patterns 112 .
- the lower semiconductor chip 120 may be mounted in a flip-chip manner on the lower package substrate 110 , the lower mold layer 130 may be formed and patterned to form the opening 137 , and the connection patterns 135 may be formed on the lower mold layer 130 , which may fabricate the lower package 10 . Before the connection patterns 135 are formed, the lower mold layer 130 may be grinded to expose the lower semiconductor chip 120 and thereafter the insulation layer 132 may be further formed.
- the upper semiconductor chip 220 may be formed and then the upper package substrate 210 may be formed on an active surface 220 f of the upper semiconductor chip 220 , and the upper mold layer 230 may be formed to encapsulate the upper semiconductor chip 220 , which may fabricate the upper package 20 .
- the upper package 20 may be fabricated by forming the upper semiconductor chip 220 , depositing an insulating material to form the upper package substrate 210 on the upper semiconductor chip 220 , and depositing and patterning a metal layer to form connection lines 215 embedded in the upper package substrate 210 , rather than by mounting the upper semiconductor chip 220 on the upper package substrate 210 .
- the upper semiconductor chip 220 may further comprise chip pads 222 electrically connected to the connection lines 215 , and the upper package substrate 210 may further comprise substrate pads 212 coupled to the connection lines 215 .
- the upper semiconductor chip 220 may be a wide input/output (I/O) memory chip that includes about 128 or more chip pads 222 .
- the substrate pads 212 may be arranged, for example, uniformly and entirely on a lower surface of the upper package substrate 210 . Alternatively, the substrate pads 212 may be arranged, for example, locally on a center, an edge, or a specific region of the lower surface of the upper package substrate 210 .
- the connection lines 215 may provide vertical electrical paths between the chip pads 222 and the substrate pads 212 , as illustrated in FIG. 1F .
- Connection terminals 214 may be further provided to be coupled to the substrate pads 212 .
- the connection terminals 214 may be attached to the upper package substrate 210 .
- the upper package substrate 210 and the upper semiconductor chip 220 may be directly or indirectly contacted to each other, there may no gap between the upper package substrate 210 and the upper semiconductor chip 220 . Because the connection lines 212 and the chip pads 222 may be directly connected to each other, the upper package substrate 210 and the upper semiconductor chip 220 may be electrically connected to each other without an electrical medium such as, for example, micro-bumps.
- the connection lines 215 may be electrically connected to the connection patterns 135 via the connection terminals 214 . Consequently, the connection terminals 214 may electrically connect the upper package 20 to the lower package 10 .
- connection lines 215 may expand a pitch of the chips pad 222 .
- the connection lines 215 may electrically connect the chip pads 222 that has a first pitch P 1 to the substrate pads 212 that has a second pitch P 2 .
- the second pitch P 2 may be greater than the first pitch P 1 , as illustrated in FIG. 1G .
- the first pitch P 1 of the chip pad 222 may be 60 ⁇ m or less
- the second pitch P 2 of the substrate pad 212 may be 120 ⁇ m or more.
- the connection terminals 214 may be arranged to have a pitch that may be identical to or similar to the second pitch P 2 .
- the upper semiconductor chip 220 may be electrically connected to the upper package substrate 210 without an electrical medium such as, for example, micro-bumps or through electrodes.
- the connection lines 215 may expand the narrower pitch P 1 of the chip pad 222 to the wider pitch P 2 of the connection terminal 214 without the help of an interposer, and the connection terminals 214 may electrically connect the upper package 20 to the lower package 10 .
- a total height of the semiconductor package 1 may be reduced. Because there may be no need to form micro-bumps between the upper semiconductor chip 220 and the upper package substrate 210 , there may be no electrical and/or mechanical problems due to, for example, electromigration and/or an intermetallic compound of micro-bumps. In addition, because there may be no interposer, processes to form the interposer and through electrodes therethrough may be skipped.
- FIGS. 2A to 2F are cross sectional views illustrating semiconductor packages according to embodiments of the present inventive concept.
- previously described elements may be identified by similar or identical reference numbers without repeating overlapping descriptions thereof.
- a semiconductor package 2 may further comprise a filling-up insulation layer 134 that fills the opening 137 and covers the connection patterns 135 in the opening 137 .
- the filling-up insulation layer 134 may further extend from the opening 137 toward a center of the lower semiconductor chip 120 to cover the insulation layer 132 .
- a semiconductor package 3 may comprise a lower mold layer 131 that covers lateral sides and top surfaces of the lower semiconductor chip 120 . Therefore, there may be no need to form the insulation layer 132 of the embodiment illustrated in FIG. 1A on the lower mold layer 131 .
- a semiconductor package 4 may comprise the upper semiconductor chip 220 that has an edge pad structure.
- the semiconductor chip 220 may include the chip pads 222 arranged locally on an edge of the active surface 220 f of the upper semiconductor chip 220 .
- a semiconductor package 5 may comprise the upper semiconductor chip 220 that has a full matrix structure.
- the upper semiconductor chip 220 may include the chip pads 222 arranged uniformly on the entire active surface 220 f of the upper semiconductor chip 220 .
- a semiconductor package 6 may comprise the lower semiconductor chip 120 embedded in the lower package substrate 110 that has vias 115 .
- the lower semiconductor chip 120 may be electrically connected to the circuit patterns 112 through the internal terminals 124 , the circuit patterns 112 may be electrically connected to the connection patterns 135 through the vias 115 . Consequently, the lower package 10 may be electrically connected to the upper package 20 through the connection patterns 135 .
- a semiconductor package 7 may comprise the lower semiconductor chip 120 embedded in the lower package substrate 110 that has the connection patterns 135 formed therein.
- the connection patterns 135 may be provided on the lower package substrate 110 , and the opening 137 that exposes the circuit patterns 112 may be arranged along an edge of the lower package substrate 110 .
- the lower semiconductor chip 120 may be exposed through a top surface of the lower package substrate 110 , and the insulation layer 132 may be further provided between the lower semiconductor chip 120 and the connection patterns 135 to electrically insulate the connection patterns 135 from the lower semiconductor chip 120 .
- the semiconductor package 7 may exclude the lower mold layer 130 of the embodiment illustrated in FIG. 1A . Therefore, the semiconductor package 7 may have a reduced total height with respect to the case in which the lower mold layer 130 is included.
- FIG. 3A is a schematic block diagram illustrating an example of a memory card 1200 that includes a semiconductor package according to embodiments of the present inventive concept.
- FIG. 3B is a schematic block diagram illustrating an example of an information process system 1300 that includes a semiconductor package according to embodiments of the present inventive concept.
- a semiconductor memory 1210 that includes at least one of the semiconductor packages 1 to 7 according to embodiments of the present inventive concept may be applicable to the memory card 1200 .
- the memory card 1200 may include a memory controller 1220 that may generally control data exchange between a host 1230 and the semiconductor memory 1210 .
- a Static Random-Access Memory (SRAM) 1221 may be used as a work memory of a central processing unit (CPU) 1222 .
- a host interface (Host I/F) 1223 may have a data exchange protocol of the host 1230 connected to the memory card 1200 .
- An error correction coding (ECC) block 1224 may detect and/or may correct errors of data that are read from the semiconductor memory 1210 .
- a memory interface (Memory I/F) 1225 may interface with the semiconductor memory 1210 according to an embodiment.
- the CPU 1222 may generally control data exchange of the memory controller 1220 .
- the information processing system 1300 may include a memory system 1310 that has at least one of the semiconductor packages 1 to 7 according to embodiments of the present inventive concept.
- the information processing system 1300 may include, for example, a mobile device or a computer.
- the information processing system 1300 may include a modem 1320 , a central processing unit (CPU) 1330 , a Random-Access Memory (RAM) 1340 , and a user interface (User I/F) 1350 electrically connected to the memory system 1310 via a system bus 1360 .
- the memory system 1310 may include a memory 1311 and a memory controller 1312 and may have substantially the same configuration as that of the memory card 1200 in the embodiment illustrated in FIG. 3A .
- the memory system 1310 may store data processed by the CPU 1330 or data input from outside.
- the information process system 1300 may be provided, for example, as a memory card, a solid state disk, a semiconductor device disk, a camera image sensor, and/or other application chipsets.
- the memory system 1310 may be used as a portion of a solid state drive (SSD), and in this case, the information processing system 1300 may stably and reliably store a large amount of data in the memory system 1310 .
- SSD solid state drive
- the upper semiconductor chip 220 may be electrically connected to the upper package substrate 210 without the help of, for example, micro-bumps such that the semiconductor package 1 , 2 , 3 , 4 , 5 , 6 , or 7 may be shrunk and the reliability of the semiconductor package 1 , 2 , 3 , 4 , 5 , 6 , or 7 may be improved. Moreover, there may be no need to form an interposer so that processes to form the interposer and through electrodes therethrough may be skipped, which may reduce fabrication cost.
- known good semiconductor packages may be stacked to fabricate a package-on-package type semiconductor package 1 , 2 , 3 , 4 , 5 , 6 , or 7 that has a good yield as compared with a different type semiconductor packaging technology such as, for example, system-in-package technology.
- a designer may be free to select or choose the kinds of upper and lower semiconductor chips 220 and 120 that may be included in the semiconductor package 1 , 2 , 3 , 4 , 5 , 6 , or 7 .
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Abstract
A semiconductor package includes a lower package with a lower semiconductor chip on a lower package substrate, and an upper package with an upper semiconductor chip on an upper package substrate. The upper semiconductor chip has a plurality of chip pads and the upper package substrate has a plurality of substrate pads. The upper package is stacked on the lower package. The chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch. The upper package substrate has a plurality of connection lines that electrically connect the substrate pads to the chip pads.
Description
- This application claims the benefit of priority under 35 U.S.C. §119 to Korean Patent Application 10-2013-0035310, filed on Apr. 1, 2013, the content of which is incorporated herein in its entirety by reference.
- 1. Field
- An embodiment of the present inventive concept relates to semiconductors and, more particularly, to semiconductor packages having package-on-package structures.
- 2. Description of the Related Art
- In the semiconductor industry, various package technologies have been developed to meet demands for large storage, thin thickness, and small size of semiconductor devices and/or electronic appliances. One approach is a package technology through which semiconductor chips are vertically stacked to realize a high density chip stacking. This package technology can integrate many kinds of semiconductor chips in smaller areas compared to a general package with a single semiconductor chip.
- However, a problem with using a multi-chip stack package is that there is a strong possibility of a reduction in yield compared to using a single chip package. A package-on-package (POP) technology was developed to solve the problem with the reduction in yield and to still realize a high density chip stack. Inusing POP technology, known good packages are stacked to reduce the inferiority of the final product. This POP type package can be used to meet the trend toward both compact size of electronic portable appliances and multiple functions of mobile products.
- System-in-Package (SiP) is another packing technology. The SiP structure also presents a possibility of a reduction in yield but, unlike the POP structure, does not restrict the selection of chips. Thus, there may be a need to improve the POP type semiconductor package to include the merits described above.
- The present inventive concept provides semiconductor packages having through electrodes and methods of fabricating the same in which a narrower pitch may expand to a wider pitch without interposers.
- Additional features and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
- The foregoing and/or other features and utilities of the present general inventive may be achieved by providing semiconductor packages having through electrodes and methods of fabricating the same in which a package substrate and a semiconductor chip are electrically directly connected to each other without micro-bumps and/or through electrodes.
- The foregoing and/or other features and utilities of the present general inventive may be achieved by providing semiconductor packages having through electrodes and methods of fabricating the same in which there is no gap between the package substrate and the semiconductor chip.
- The foregoing and/or other features and utilities of the present general inventive may be achieved by providing a semiconductor package that has a lower package including a lower semiconductor chip on a lower package substrate, and an upper package including an upper semiconductor chip on an upper package substrate. The upper semiconductor chip may have a plurality of chip pads and the upper package substrate may have a plurality of substrate pads. The upper package may be stacked on the lower package. The chip pads may have a first pitch and the substrate pads may have a second pitch greater than the first pitch. The upper package substrate may comprise a plurality of connection lines that electrically connect the substrate pads to the chip pads.
- In an embodiment, the semiconductor package may further comprise a plurality of connection terminals that electrically connect the upper package to the lower package. The connection terminals may be provided between the upper package and the lower package.
- In an embodiment, the lower package may further comprise a lower mold layer and a plurality of connection patterns on the lower mold layer. The connection patterns may be electrically connected to the connection lines.
- In an embodiment, the lower mold layer may comprise an opening exposing a portion of the lower package substrate. The connection patterns may extend toward inside the opening to be electrically connected to the lower package substrate.
- In an embodiment, the opening may comprise at least one of a line-type trench and a plurality of holes arranged along lateral sides of the lower semiconductor chip.
- The foregoing and/or other features and utilities of the present general inventive concept may be achieved by providing a semiconductor package that has a lower package including a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, a lower mold layer encapsulating the lower semiconductor chip, and connection patterns on the lower mold layer that penetrate the lower mold layer to be electrically connected to the lower package substrate, an upper package including an upper package substrate having substrate pads, and an upper semiconductor chip mounted on the upper package substrate, the upper package being stacked on the lower package, and connection terminals interposed between the lower and upper packages, the connection terminals electrically connecting the lower and upper packages. The upper semiconductor chip may include chip pads having a pitch narrower than a pitch of the substrate pads. The upper package substrate may include connection lines that provide electrical paths between the substrate pads and the chip pads. The connection lines may allow the chip pads to access a wider pitch of the substrate pads to electrically connect the upper semiconductor chip to the lower package substrate.
- In an embodiment, the lower package substrate may comprise circuit patterns electrically connected to the connection patterns. The lower mold layer may comprise an opening that is spaced apart from a lateral side of the lower semiconductor chip and vertically penetrates the lower mold layer to expose the circuit patterns. The connection patterns may extend toward the lower package substrate to pass through the opening to be electrically connected to the circuit patterns.
- In an embodiment, the upper semiconductor chip may be disposed on the upper package substrate while a surface of the upper semiconductor chip faces the upper package substrate. The surface of the upper semiconductor chip may contact the upper package substrate.
- In an embodiment, the lower package further may include internal terminals provided between the lower semiconductor chip and the lower package substrate. The lower semiconductor chip may be disposed on the lower package substrate to be electrically connected thereto through the internal terminals while a surface of the lower semiconductor chip faces the lower package substrate.
- In an embodiment, the lower semiconductor chip may comprise a logic chip and the upper semiconductor chip may comprise a memory chip.
- The foregoing and/or other features of the present general inventive concept may be achieved by providing a semiconductor package that has a package-on-package type package including lower and upper packages vertically stacked and electrically connected. The lower package may comprise a lower semiconductor chip mounted on a lower package substrate and encapsulated by a lower mold layer. The upper package may comprise an upper semiconductor chip having chip pads mounted on an upper package substrate without a gap between the upper semiconductor chip and the upper package substrate. The upper package substrate may include connection lines electrically connected to the upper semiconductor chip. The connection lines may be configured to provide the chip pads with access to a wider pitch to electrically connect the upper semiconductor chip to the lower package substrate.
- In an embodiment, the upper package substrate may comprise substrate pads having a pitch greater than a pitch of the chip pads.
- In an embodiment, the package-on-package type package may further comprise connection terminals provided between the lower and upper packages. The lower package may further comprise connection patterns disposed on the lower mold layer to be electrically connected to the connection terminals.
- In an embodiment, the connection patterns may penetrate through the lower mold layer to be electrically connected to the lower package substrate.
- In an embodiment, the lower package may further comprise an opening that penetrates through the lower mold layer and provides the connection patterns with paths toward the lower package substrate. The opening may comprise at least one of a line-type trench extending along lateral sides of the lower semiconductor chip and a plurality of holes arranged along the lateral sides of the lower semiconductor chip.
- The foregoing and/or other features of the present general inventive concept may be achieved by providing as electronic system including a semiconductor memory having a first package including a first semiconductor chip on a first substrate, and a second package electrically connected to the first package and including a second semiconductor chip, with chip pads having a first pitch, on a second substrate with substrate pads having a second pitch greater than the first pitch, the chip pads electrically connected to the substrate pads by connection lines, and a memory controller electrically connected to the semiconductor memory and configured to write in data to and to read the data from at least one of the first semiconductor chip and the second semiconductor chip.
- In an embodiment, the second package may exclude micro-bumps between the second semiconductor chip and the second substrate.
- In an embodiment, the first semiconductor chip may be embedded in the first substrate.
- In an embodiment, the substrate pads may be located at one of a center of, an edge of, a specific region of, and uniformly across a lower surface of the second substrate, and the chip pads are located at one of a center of, an edge of, and uniformly across an active surface of the second semiconductor chip.
- In an embodiment, the electronic system may further include a system bus, a central processing unit electrically connected to the system bus, a random-access memory electrically connected to the system bus, a user interface electrically connected to the system bus, and a modem electrically connected to the system bus, and the memory controller may be electrically connected to the system bus.
- These and/or other features and utilities of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
-
FIGS. 1A is a cross sectional view illustrating a semiconductor package according to an embodiment of the present inventive concept; -
FIGS. 1B to 1E are plan views illustrating various examples of an opening of the semiconductor package according to an embodiment of the present inventive concept; -
FIG. 1F is a schematic diagram illustrating an electrical connection in an upper package of the semiconductor package according to an embodiment of the present inventive concept; -
FIG. 1G is a cross sectional view illustrating a portion of the upper package included in the semiconductor package according to an embodiment of the present inventive concept; -
FIGS. 2A to 2F are cross sectional views illustrating semiconductor packages according to embodiments of the present inventive concept; -
FIG. 3A is a schematic block diagram illustrating an example of a memory card that includes a semiconductor package according to embodiments of the present inventive concept; and -
FIG. 3B is a schematic block diagram illustrating an example of an information process system that includes a semiconductor package according to embodiments of the present inventive concept. - Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept while referring to the figures. Example embodiments, may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments of the present inventive concept to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.
-
FIGS. 1A is a cross sectional view illustrating asemiconductor package 1 according to an embodiment of the present inventive concept.FIGS. 1B to 1E are plan views illustrating various examples of anopening 137 of thesemiconductor package 1 according to an embodiment of the present inventive concept.FIG. 1F is a schematic diagram illustrating an electrical connection in anupper package 20 of thesemiconductor package 1 according to an embodiment of the present inventive concept.FIG. 1G is a cross sectional view illustrating a portion of theupper package 20 included in thesemiconductor package 1 according to exemplary embodiments of the present inventive concepts. - Referring to
FIG. 1A , thesemiconductor package 1 may be a package-on-package type package that includes theupper package 20 stacked on alower package 10. For example, thelower package 10 may comprise alower package substrate 110, alower semiconductor chip 120 disposed on thelower package substrate 110, and alower mold layer 130 that encapsulates thelower semiconductor chip 120. Theupper package 20 may comprise anupper package substrate 210, anupper semiconductor chip 220 disposed on theupper package substrate 210, and anupper mold layer 230 that encapsulates theupper semiconductor chip 220. Theupper semiconductor chip 220 and thelower semiconductor chip 120 may be a same or a different kind of chip. For example, theupper semiconductor chip 220 may be a memory chip and thelower semiconductor chip 120 may be a logic chip. - The
lower semiconductor chip 120 may be bonded onto thelower package substrate 110, which hascircuit patterns 112, in a flip-chip manner in which anactive surface 120 f faces thelower package substrate 110, and may be electrically connected to thelower package substrate 110 through one or moreinternal terminals 124. Thecircuit patterns 112 may provide electrical paths that vertically penetrate thelower package substrate 110. Thelower mold layer 130 may comprise the at least onevertical opening 137 that exposes thecircuit patterns 112. - The
opening 137 may have, for example, a trench shape or a hole shape. For example, theopening 137 may have a ring-type trench shape that continuously extends along lateral sides of thelower semiconductor chip 120 as illustrated inFIG. 1B , or a line-type trench shape that extends along opposing lateral sides of thelower semiconductor chip 120 as illustrated inFIG. 10 . Alternatively, theopening 137 may have, for example, a hole shape that includes a plurality of holes arranged continuously along lateral sides of thelower semiconductor chip 120 as illustrated inFIG. 1D , or arranged along opposing lateral sides of thelower semiconductor chip 120 as illustrated inFIG. 1E . - A plurality of
connection patterns 135 may be disposed on thelower mold layer 130 to be electrically connected to thecircuit patterns 112. Theconnection patterns 135 may extend toward inside theopening 137 to be directly coupled to thecircuit patterns 112 such that theconnection patterns 135 may be electrically connected to thelower package substrate 110. - An
insulation layer 132 may be further provided between thelower mold layer 130 and theconnection patterns 135. For example, when thelower mold layer 130 is formed to expose thelower semiconductor chip 120, theinsulation layer 132 may prevent an electrical interconnection between theconnection patterns 135 and thelower semiconductor chip 120. A sidewall of theopening 137 may be covered by theinsulation layer 132. However, a bottom floor of theopening 137 may not be covered by theinsulation layer 132 such that thecircuit patterns 112 may be exposed through theopening 137. Thelower package substrate 110 may further comprise one or moreexternal terminals 114 coupled to thecircuit patterns 112. - The
lower semiconductor chip 120 may be mounted in a flip-chip manner on thelower package substrate 110, thelower mold layer 130 may be formed and patterned to form theopening 137, and theconnection patterns 135 may be formed on thelower mold layer 130, which may fabricate thelower package 10. Before theconnection patterns 135 are formed, thelower mold layer 130 may be grinded to expose thelower semiconductor chip 120 and thereafter theinsulation layer 132 may be further formed. - The
upper semiconductor chip 220 may be formed and then theupper package substrate 210 may be formed on anactive surface 220 f of theupper semiconductor chip 220, and theupper mold layer 230 may be formed to encapsulate theupper semiconductor chip 220, which may fabricate theupper package 20. In other words, theupper package 20 may be fabricated by forming theupper semiconductor chip 220, depositing an insulating material to form theupper package substrate 210 on theupper semiconductor chip 220, and depositing and patterning a metal layer to formconnection lines 215 embedded in theupper package substrate 210, rather than by mounting theupper semiconductor chip 220 on theupper package substrate 210. - The
upper semiconductor chip 220 may further comprisechip pads 222 electrically connected to theconnection lines 215, and theupper package substrate 210 may further comprisesubstrate pads 212 coupled to the connection lines 215. In an embodiment, theupper semiconductor chip 220 may be a wide input/output (I/O) memory chip that includes about 128 ormore chip pads 222. Thesubstrate pads 212 may be arranged, for example, uniformly and entirely on a lower surface of theupper package substrate 210. Alternatively, thesubstrate pads 212 may be arranged, for example, locally on a center, an edge, or a specific region of the lower surface of theupper package substrate 210. The connection lines 215 may provide vertical electrical paths between thechip pads 222 and thesubstrate pads 212, as illustrated inFIG. 1F .Connection terminals 214 may be further provided to be coupled to thesubstrate pads 212. Theconnection terminals 214 may be attached to theupper package substrate 210. - Because the
upper package substrate 210 and theupper semiconductor chip 220 may be directly or indirectly contacted to each other, there may no gap between theupper package substrate 210 and theupper semiconductor chip 220. Because theconnection lines 212 and thechip pads 222 may be directly connected to each other, theupper package substrate 210 and theupper semiconductor chip 220 may be electrically connected to each other without an electrical medium such as, for example, micro-bumps. The connection lines 215 may be electrically connected to theconnection patterns 135 via theconnection terminals 214. Consequently, theconnection terminals 214 may electrically connect theupper package 20 to thelower package 10. - Referring to
FIG. 1G , theconnection lines 215 may expand a pitch of thechips pad 222. For example, theconnection lines 215 may electrically connect thechip pads 222 that has a first pitch P1 to thesubstrate pads 212 that has a second pitch P2. The second pitch P2 may be greater than the first pitch P1, as illustrated inFIG. 1G . In an embodiment, the first pitch P1 of thechip pad 222 may be 60 μm or less, the second pitch P2 of thesubstrate pad 212 may be 120 μm or more. Theconnection terminals 214 may be arranged to have a pitch that may be identical to or similar to the second pitch P2. According to an embodiment, theupper semiconductor chip 220 may be electrically connected to theupper package substrate 210 without an electrical medium such as, for example, micro-bumps or through electrodes. The connection lines 215 may expand the narrower pitch P1 of thechip pad 222 to the wider pitch P2 of theconnection terminal 214 without the help of an interposer, and theconnection terminals 214 may electrically connect theupper package 20 to thelower package 10. - As described above, because there may no gap between the
upper semiconductor chip 220 and theupper package substrate 210, a total height of thesemiconductor package 1 may be reduced. Because there may be no need to form micro-bumps between theupper semiconductor chip 220 and theupper package substrate 210, there may be no electrical and/or mechanical problems due to, for example, electromigration and/or an intermetallic compound of micro-bumps. In addition, because there may be no interposer, processes to form the interposer and through electrodes therethrough may be skipped. -
FIGS. 2A to 2F are cross sectional views illustrating semiconductor packages according to embodiments of the present inventive concept. In order to keep the description concise, previously described elements may be identified by similar or identical reference numbers without repeating overlapping descriptions thereof. - Referring to
FIG. 2A , asemiconductor package 2 may further comprise a filling-upinsulation layer 134 that fills theopening 137 and covers theconnection patterns 135 in theopening 137. The filling-upinsulation layer 134 may further extend from theopening 137 toward a center of thelower semiconductor chip 120 to cover theinsulation layer 132. - Referring to
FIG. 2B , asemiconductor package 3 may comprise alower mold layer 131 that covers lateral sides and top surfaces of thelower semiconductor chip 120. Therefore, there may be no need to form theinsulation layer 132 of the embodiment illustrated inFIG. 1A on thelower mold layer 131. - Referring to
FIG. 2C , asemiconductor package 4 may comprise theupper semiconductor chip 220 that has an edge pad structure. For example, thesemiconductor chip 220 may include thechip pads 222 arranged locally on an edge of theactive surface 220 f of theupper semiconductor chip 220. - Referring of
FIG. 2D , a semiconductor package 5 may comprise theupper semiconductor chip 220 that has a full matrix structure. For example, theupper semiconductor chip 220 may include thechip pads 222 arranged uniformly on the entireactive surface 220 f of theupper semiconductor chip 220. - Referring of
FIG. 2E , a semiconductor package 6 may comprise thelower semiconductor chip 120 embedded in thelower package substrate 110 that hasvias 115. Thelower semiconductor chip 120 may be electrically connected to thecircuit patterns 112 through theinternal terminals 124, thecircuit patterns 112 may be electrically connected to theconnection patterns 135 through thevias 115. Consequently, thelower package 10 may be electrically connected to theupper package 20 through theconnection patterns 135. - Referring to
FIG. 2F , asemiconductor package 7 may comprise thelower semiconductor chip 120 embedded in thelower package substrate 110 that has theconnection patterns 135 formed therein. For example, theconnection patterns 135 may be provided on thelower package substrate 110, and theopening 137 that exposes thecircuit patterns 112 may be arranged along an edge of thelower package substrate 110. Thelower semiconductor chip 120 may be exposed through a top surface of thelower package substrate 110, and theinsulation layer 132 may be further provided between thelower semiconductor chip 120 and theconnection patterns 135 to electrically insulate theconnection patterns 135 from thelower semiconductor chip 120. In an embodiment, thesemiconductor package 7 may exclude thelower mold layer 130 of the embodiment illustrated inFIG. 1A . Therefore, thesemiconductor package 7 may have a reduced total height with respect to the case in which thelower mold layer 130 is included. -
FIG. 3A is a schematic block diagram illustrating an example of amemory card 1200 that includes a semiconductor package according to embodiments of the present inventive concept.FIG. 3B is a schematic block diagram illustrating an example of aninformation process system 1300 that includes a semiconductor package according to embodiments of the present inventive concept. - Referring to
FIG. 3A , asemiconductor memory 1210 that includes at least one of thesemiconductor packages 1 to 7 according to embodiments of the present inventive concept may be applicable to thememory card 1200. For example, thememory card 1200 may include amemory controller 1220 that may generally control data exchange between ahost 1230 and thesemiconductor memory 1210. A Static Random-Access Memory (SRAM) 1221 may be used as a work memory of a central processing unit (CPU) 1222. A host interface (Host I/F) 1223 may have a data exchange protocol of thehost 1230 connected to thememory card 1200. An error correction coding (ECC)block 1224 may detect and/or may correct errors of data that are read from thesemiconductor memory 1210. A memory interface (Memory I/F) 1225 may interface with thesemiconductor memory 1210 according to an embodiment. TheCPU 1222 may generally control data exchange of thememory controller 1220. - Referring to
FIG. 3B , theinformation processing system 1300 may include amemory system 1310 that has at least one of thesemiconductor packages 1 to 7 according to embodiments of the present inventive concept. Theinformation processing system 1300 may include, for example, a mobile device or a computer. For example, theinformation processing system 1300 may include amodem 1320, a central processing unit (CPU) 1330, a Random-Access Memory (RAM) 1340, and a user interface (User I/F) 1350 electrically connected to thememory system 1310 via asystem bus 1360. Thememory system 1310 may include amemory 1311 and amemory controller 1312 and may have substantially the same configuration as that of thememory card 1200 in the embodiment illustrated inFIG. 3A . Thememory system 1310 may store data processed by theCPU 1330 or data input from outside. Theinformation process system 1300 may be provided, for example, as a memory card, a solid state disk, a semiconductor device disk, a camera image sensor, and/or other application chipsets. In an embodiment, thememory system 1310 may be used as a portion of a solid state drive (SSD), and in this case, theinformation processing system 1300 may stably and reliably store a large amount of data in thememory system 1310. - According to an embodiment of the present inventive concept, the
upper semiconductor chip 220 may be electrically connected to theupper package substrate 210 without the help of, for example, micro-bumps such that thesemiconductor package semiconductor package type semiconductor package lower semiconductor chips semiconductor package - Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.
Claims (18)
1. A semiconductor package, comprising:
a lower package including a lower semiconductor chip on a lower package substrate; and
an upper package, stacked on the lower package, including an upper semiconductor chip on an upper package substrate, the upper semiconductor chip having a plurality of chip pads and the upper package substrate having a plurality of substrate pads,
wherein the chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch, and
wherein the upper package substrate comprises a plurality of connection lines that electrically connect the substrate pads to the chip pads.
2. The semiconductor package of claim 1 , further comprising a plurality of connection terminals that electrically connect the upper package to the lower package,
wherein the connection terminals are provided between the upper package and the lower package.
3. The semiconductor package of claim 2 , wherein the lower package further comprises:
a lower mold layer; and
a plurality of connection patterns on the lower mold layer, wherein the connection patterns are electrically connected to the connection lines.
4. The semiconductor package of claim 3 , wherein the lower mold layer comprises an opening exposing a portion of the lower package substrate, and
wherein the connection patterns extend toward inside the opening to be electrically connected to the lower package substrate.
5. The semiconductor package of claim 4 , wherein the opening comprises at least one of a line-type trench and a plurality of holes arranged along lateral sides of the lower semiconductor chip.
6. A semiconductor package, comprising:
a lower package including a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, a lower mold layer encapsulating the lower semiconductor chip, and connection patterns on the lower mold layer that penetrate the lower mold layer to be electrically connected to the lower package substrate;
an upper package including an upper package substrate having substrate pads, and an upper semiconductor chip mounted on the upper package substrate, the upper package being stacked on the lower package; and
connection terminals interposed between the lower and upper packages, the connection terminals electrically connecting the lower and upper packages,
wherein the upper semiconductor chip includes chip pads having a pitch narrower than a pitch of the substrate pads,
wherein the upper package substrate includes connection lines that provide electrical paths between the substrate pads and the chip pads, and
wherein the connection lines allow the chip pads to access a wider pitch of the substrate pads to electrically connect the upper semiconductor chip to the lower package substrate.
7. The semiconductor package of claim 6 , wherein the lower package substrate comprises circuit patterns electrically connected to the connection patterns,
wherein the lower mold layer comprises an opening that is spaced apart from a lateral side of the lower semiconductor chip and vertically penetrates the lower mold layer to expose the circuit patterns, and
wherein the connection patterns extend toward the lower package substrate to pass through the opening to be electrically connected to the circuit patterns.
8. The semiconductor package of claim 6 , wherein the upper semiconductor chip is disposed on the upper package substrate while a surface of the upper semiconductor chip faces the upper package substrate, and
wherein the surface of the upper semiconductor chip contacts the upper package substrate.
9. The semiconductor package of claim 6 , wherein the lower package further includes internal terminals provided between the lower semiconductor chip and the lower package substrate,
wherein the lower semiconductor chip is disposed on the lower package substrate to be electrically connected thereto through the internal terminals while a surface of the lower semiconductor chip faces the lower package substrate.
10. The semiconductor package of claim 6 , wherein the lower semiconductor chip comprises a logic chip and the upper semiconductor chip comprises a memory chip.
11. A semiconductor package comprising:
a package-on-package type package including lower and upper packages vertically stacked and electrically connected,
wherein the lower package comprises a lower semiconductor chip mounted on a lower package substrate and encapsulated by a lower mold layer,
wherein the upper package comprises an upper semiconductor chip having chip pads mounted on an upper package substrate without a gap between the upper semiconductor chip and the upper package substrate, and
wherein the upper package substrate includes connection lines electrically connected to the upper semiconductor chip, the connection lines configured to provide the chip pads with access to a wider pitch to electrically connect the upper semiconductor chip to the lower package substrate.
12. The semiconductor package of claim 11 , wherein the upper package substrate comprises substrate pads having a pitch greater than a pitch of the chip pads.
13. The semiconductor package of claim 11 , wherein the package-on-package type package further comprises connection terminals provided between the lower and upper packages,
wherein the lower package further comprises connection patterns disposed on the lower mold layer to be electrically connected to the connection terminals.
14. The semiconductor package of claim 13 , wherein the connection patterns penetrate through the lower mold layer to be electrically connected to the lower package substrate.
15. The semiconductor package of claim 14 , wherein the lower package further comprises an opening that penetrates through the lower mold layer and provides the connection patterns with paths toward the lower package substrate,
wherein the opening comprises at least one of a line-type trench extending along lateral sides of the lower semiconductor chip and a plurality of holes arranged along the lateral sides of the lower semiconductor chip.
16. The semiconductor package of claim 11 , wherein the upper package excludes micro-bumps between the upper semiconductor chip and the upper package substrate.
17. The semiconductor package of claim 11 , wherein the lower semiconductor chip is embedded in the lower package substrate.
18. The semiconductor package of claim 12 , wherein the substrate pads are located at one of a center of, an edge of, a specific region of, and uniformly across a lower surface of the upper package substrate, and the chip pads are located at one of a center of, an edge of, and uniformly across an active surface of the upper semiconductor chip.
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KR1020130035310A KR20140119522A (en) | 2013-04-01 | 2013-04-01 | Semiconductor package having package on package structure |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9087759B1 (en) * | 2014-03-28 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming an image sensor device and method of forming the same |
US20180145061A1 (en) * | 2016-11-21 | 2018-05-24 | Samsung Electronics Co., Ltd. | Semiconductor package |
CN108573963A (en) * | 2017-03-07 | 2018-09-25 | 力成科技股份有限公司 | Encapsulation stacking structure and its manufacturing method |
US10121766B2 (en) | 2016-06-30 | 2018-11-06 | Micron Technology, Inc. | Package-on-package semiconductor device assemblies including one or more windows and related methods and packages |
US10319607B2 (en) * | 2014-08-22 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure with organic interposer |
US20210305193A1 (en) * | 2020-03-26 | 2021-09-30 | Lg Electronics Inc. | Power module of double-faced cooling |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210083830A (en) * | 2019-12-27 | 2021-07-07 | 삼성전자주식회사 | Semiconductor package and method of manufacturing thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080048316A1 (en) * | 2006-08-25 | 2008-02-28 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
US20090065920A1 (en) * | 2007-09-06 | 2009-03-12 | Eun-Chul Ahn | Semiconductor package embedded in substrate, system including the same and associated methods |
US20100133704A1 (en) * | 2008-12-01 | 2010-06-03 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias |
US20110037163A1 (en) * | 2009-08-13 | 2011-02-17 | Infineon Technologies Ag | Device including a ring-shaped metal structure and method |
US20120032314A1 (en) * | 2008-05-27 | 2012-02-09 | Nan-Cheng Chen | Package-on-package with fan-out wlcsp |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000032827A (en) | 1998-11-18 | 2000-06-15 | 구자홍 | Method for forming a joint in multi-layer circuit board |
US6489217B1 (en) | 2001-07-03 | 2002-12-03 | Maxim Integrated Products, Inc. | Method of forming an integrated circuit on a low loss substrate |
JP2004335915A (en) | 2003-05-12 | 2004-11-25 | Shinko Electric Ind Co Ltd | Method for manufacturing semiconductor device |
US6875921B1 (en) | 2003-10-31 | 2005-04-05 | Xilinx, Inc. | Capacitive interposer |
KR20050073678A (en) | 2004-01-09 | 2005-07-18 | 주식회사 하이닉스반도체 | Method for manufacturing bga type package |
KR20070022097A (en) | 2004-06-17 | 2007-02-23 | 텍사스 인스트루먼츠 인코포레이티드 | Semiconductor assembly having substrate with electroplated contact pads |
US8075982B2 (en) | 2004-11-15 | 2011-12-13 | Kevin Gerard Donahue | Device for making illuminated markings |
KR100652397B1 (en) | 2005-01-17 | 2006-12-01 | 삼성전자주식회사 | Stack type semiconductor package using an interposer print circuit board |
JP4589170B2 (en) * | 2005-04-28 | 2010-12-01 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JP4715601B2 (en) | 2006-04-07 | 2011-07-06 | 住友電気工業株式会社 | Electrical connection parts |
US8193034B2 (en) * | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US20080284037A1 (en) | 2007-05-15 | 2008-11-20 | Andry Paul S | Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers |
US7944034B2 (en) * | 2007-06-22 | 2011-05-17 | Texas Instruments Incorporated | Array molded package-on-package having redistribution lines |
US7619305B2 (en) | 2007-08-15 | 2009-11-17 | Powertech Technology Inc. | Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking |
US9460951B2 (en) | 2007-12-03 | 2016-10-04 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of wafer level package integration |
US7767496B2 (en) * | 2007-12-14 | 2010-08-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer |
US20090170241A1 (en) * | 2007-12-26 | 2009-07-02 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier |
US7960840B2 (en) | 2008-05-12 | 2011-06-14 | Texas Instruments Incorporated | Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level |
KR20100006898A (en) | 2008-07-10 | 2010-01-22 | 삼성테크윈 주식회사 | Semiconductor package and the fabrication method thereof |
US9559046B2 (en) | 2008-09-12 | 2017-01-31 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias |
JP5370765B2 (en) | 2008-09-29 | 2013-12-18 | 日立化成株式会社 | Package board for mounting semiconductor device and manufacturing method thereof |
US8624360B2 (en) | 2008-11-13 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling channels in 3DIC stacks |
US8592992B2 (en) * | 2011-12-14 | 2013-11-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP |
US7989270B2 (en) * | 2009-03-13 | 2011-08-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors |
TWI394253B (en) | 2009-03-25 | 2013-04-21 | Advanced Semiconductor Eng | Chip having bump and package having the same |
US8018034B2 (en) * | 2009-05-01 | 2011-09-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure |
US20100327419A1 (en) | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
US8263434B2 (en) | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
US8421175B2 (en) | 2009-09-10 | 2013-04-16 | STMicroelectronics ( Research & Development) Limited | Wafer level packaged integrated circuit |
US8446017B2 (en) | 2009-09-18 | 2013-05-21 | Amkor Technology Korea, Inc. | Stackable wafer level package and fabricating method thereof |
US9922955B2 (en) | 2010-03-04 | 2018-03-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP |
KR101667656B1 (en) | 2010-03-24 | 2016-10-20 | 삼성전자주식회사 | Method of forming package on package |
KR101686199B1 (en) | 2010-03-26 | 2016-12-14 | 삼성전자주식회사 | Semiconductor Package Structure |
KR20110126994A (en) | 2010-05-18 | 2011-11-24 | 삼성전자주식회사 | Semiconductor device and methods for fabricating the same |
US8105872B2 (en) * | 2010-06-02 | 2012-01-31 | Stats Chippac, Ltd. | Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die |
US8471577B2 (en) | 2010-06-11 | 2013-06-25 | Texas Instruments Incorporated | Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate |
KR101710178B1 (en) | 2010-06-29 | 2017-02-24 | 삼성전자 주식회사 | An embedded chip on chip package and package on package including the same |
US8648468B2 (en) | 2010-07-29 | 2014-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hermetic wafer level packaging |
US8080445B1 (en) | 2010-09-07 | 2011-12-20 | Stats Chippac, Ltd. | Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers |
KR20120028484A (en) | 2010-09-15 | 2012-03-23 | 삼성전자주식회사 | Complex semiconductor device for use in mobile equipment |
US8786066B2 (en) | 2010-09-24 | 2014-07-22 | Intel Corporation | Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same |
US8304913B2 (en) | 2010-09-24 | 2012-11-06 | Intel Corporation | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby |
JP5587123B2 (en) | 2010-09-30 | 2014-09-10 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US8522096B2 (en) | 2010-11-02 | 2013-08-27 | Syntest Technologies, Inc. | Method and apparatus for testing 3D integrated circuits |
US8466559B2 (en) | 2010-12-17 | 2013-06-18 | Intel Corporation | Forming die backside coating structures with coreless packages |
US9412708B2 (en) | 2011-01-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced ESD protection of integrated circuit in 3DIC package |
US8633100B2 (en) * | 2011-06-17 | 2014-01-21 | Stats Chippac Ltd. | Method of manufacturing integrated circuit packaging system with support structure |
US9030022B2 (en) * | 2011-10-24 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages and methods for forming the same |
KR101867955B1 (en) * | 2012-04-13 | 2018-06-15 | 삼성전자주식회사 | Package on package device and method of fabricating the device |
-
2013
- 2013-04-01 KR KR1020130035310A patent/KR20140119522A/en not_active Application Discontinuation
-
2014
- 2014-02-12 US US14/178,747 patent/US20140291830A1/en not_active Abandoned
-
2016
- 2016-05-20 US US15/160,143 patent/US10141289B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080048316A1 (en) * | 2006-08-25 | 2008-02-28 | Micron Technology, Inc. | Packaged microdevices and methods for manufacturing packaged microdevices |
US20090065920A1 (en) * | 2007-09-06 | 2009-03-12 | Eun-Chul Ahn | Semiconductor package embedded in substrate, system including the same and associated methods |
US20120032314A1 (en) * | 2008-05-27 | 2012-02-09 | Nan-Cheng Chen | Package-on-package with fan-out wlcsp |
US20100133704A1 (en) * | 2008-12-01 | 2010-06-03 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias |
US20110037163A1 (en) * | 2009-08-13 | 2011-02-17 | Infineon Technologies Ag | Device including a ring-shaped metal structure and method |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9087759B1 (en) * | 2014-03-28 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming an image sensor device and method of forming the same |
US9496309B2 (en) | 2014-03-28 | 2016-11-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor device |
US10319607B2 (en) * | 2014-08-22 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure with organic interposer |
US10121766B2 (en) | 2016-06-30 | 2018-11-06 | Micron Technology, Inc. | Package-on-package semiconductor device assemblies including one or more windows and related methods and packages |
US10777530B2 (en) | 2016-06-30 | 2020-09-15 | Micron Technology, Inc. | Package-on-package semiconductor device assemblies including one or more windows and related methods and packages |
US20180145061A1 (en) * | 2016-11-21 | 2018-05-24 | Samsung Electronics Co., Ltd. | Semiconductor package |
US10622340B2 (en) * | 2016-11-21 | 2020-04-14 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11133296B2 (en) | 2016-11-21 | 2021-09-28 | Samsung Electronics Co., Ltd. | Semiconductor package |
CN108573963A (en) * | 2017-03-07 | 2018-09-25 | 力成科技股份有限公司 | Encapsulation stacking structure and its manufacturing method |
US20210305193A1 (en) * | 2020-03-26 | 2021-09-30 | Lg Electronics Inc. | Power module of double-faced cooling |
US11735557B2 (en) * | 2020-03-26 | 2023-08-22 | Lg Magna E-Powertrain Co., Ltd. | Power module of double-faced cooling |
Also Published As
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US20160322338A1 (en) | 2016-11-03 |
KR20140119522A (en) | 2014-10-10 |
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