KR20070022097A - Semiconductor assembly having substrate with electroplated contact pads - Google Patents

Abstract

The apparatus of the present invention includes an insulating substrate 101 having first and second surfaces 101a and 101b and a plurality of metal filled vias 102 extending from the first surface to the second surface. The first and second surfaces have contact pads 103, 104, each comprising a connector stack for at least one of the vias. The stack includes a seed metal layer 110 (copper) in contact with a via metal that can provide a tacky and conductive layer for electroplating on its surface, a first electroplating support layer 111a (copper) adhered to the seed metal layer, and Second electroplating support layer 111b (nickel), and at least one reflow metal bonding layer 112 (palladium, gold) on the second support layer. The electroplating process is substantially pure (at least 99.0%), produces support layers free of unwanted additives such as phosphorus or boron, and exhibits a carefully controlled grain size. Reflow metal connectors 220 and 230 provide contact to chip contact pads and external components.

Metal Fill Vias, Contact Pads, Connector Stacks, Seed Metal Layers, Electroplating Support Layers, Reflow Metals, Electroplating

Description

Semiconductor assembly having a substrate with an electroplated contact pad {SEMICONDUCTOR ASSEMBLY HAVING SUBSTRATE WITH ELECTROPLATED CONTACT PADS}

FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor devices, and more particularly to a method for plating nickel and gold foil layers on contact pads.

Since the introduction of copper as interconnect metallization in integrated circuits, it has been found that copper pads that directly connect with the solder exhibit a weakness that adversely affects the reliability of the solder joint. Likewise, copper contact pads on substrates used in semiconductor assemblies also exhibit the disadvantage of adversely affecting the reliability of solder joints. Electroless plating of nickel layers as a diffusion barrier between copper and solder has been a good solution to limit solder reaction with copper.

However, electroless treatment for depositing nickel, which introduces its own so-called black pad, is a galvanic corrosion of electroless nickel plating during gold plating, often combined with enrichment of the nickel surface by phosphorus. (galvanic corrosion). Often these corrosive effects are amplified by large grains of deposited nickel or by infiltration on grain boundaries. Even if it's a small fraction of a million defects, the black pads are responsible for failures such as solder balls falling off, broken solder joints, and contacts being electrically open. In particular, black pads are difficult to find during quality inspection, and are often exacerbated by the fact that they are only found in the customer's home after the device is soldered.

As an alternative, many copper surface finishes have been proposed that form direct contact between copper and solder. One method is an organic surface protective film that evaporates at high temperatures, which is required for solder reflow. Other methods include a thin layer of gold, a thin layer of tin or a thin layer of solder that will dissolve into the molten solder. These alternatives create direct contact between copper and solder, and must address the diffusion of copper into the solder during the elevated temperatures of solder reflow, which is an inherent technical challenge.

Summary of the Invention

The present invention addresses the need to improve the reliability of solder-copper contacts, specifically the need for substrates used in semiconductor assemblies. Moreover, the solder-copper contact produced by the method of the present invention is free of contamination.

One embodiment of the invention includes an insulating substrate (eg, a polyimide sheet) having a first surface and a second surface, and a plurality of metal filled vias extending from the first surface to the second surface. to be. The first and second substrates have contact pads, each comprising a connector stack for at least one of the vias. The stack includes a seed metal layer (eg, copper) in contact with the via metal that can provide a tacky and conductive layer for electroplating on its surface, and two electroplating support layers adhered to the seed metal layer ( For example, copper followed by nickel), and at least one sacrificial metal layer (eg, palladium or gold) on the nickel support layer.

When reflow metal connectors (eg, tin or tin alloy solder) are attached to the contact pads, the solder joints are free of contamination (eg, phosphorus), making them reliable for life and stress testing and product applications.

Yet another embodiment of the present invention is a semiconductor assembly constituting a semiconductor chip soldered to a substrate. The chip has an active circuit and at least one metallization layer thereon, and further has an electrically conductive coupling surface located directly above the active circuit and the metallization layer. In a structure similar to the substrate structure described above, the chip bonding surface has connector stacks for the metallization layer, and each stack is connected with a metallization layer that can provide a cohesive and conductive layer for electroplating on that surface. And a seed metal layer (eg, Cu). Two electroplated support layers (eg, Cu, followed by Ni) are attached to the seed metal layer, with at least one sacrificial metal layer (eg, Pd or Au) on the Ni support layer such that each stack defines a chip bond pad.

Reflow metal connection elements (eg, Sn or Sn alloy solder) are attached to each chip bond pad. These elements connect to contact pads on the first surface and the first surface of the insulating substrate having a second surface and a plurality of metal filled vias extending from the first surface to the second surface. The substrate contact pads are in a matching position relative to the chip bond pads. Each contact pad includes a connector stack for at least one of the vias. Each stack includes a seed metal layer (eg, Cu) in contact with a via metal that can provide a tacky and conductive layer for electroplating on its surface. Two electroplated support layers (e.g. Cu, followed by Ni) are attached to the seed metal layer, and at least one sacrificial metal layer (e.g. Pb or Au) is formed so that each stack defines a workpiece contact pad. On the support layer.

The second substrate surface may have contact pads in a position operable for connection with external components prepared in a manner similar to the contact pads described above.

Another embodiment of the invention is a method for manufacturing a device. First, a substrate of insulating material (eg, polyimide sheet) is provided having a first surface and a second surface, and a plurality of metal filled vias extending from the first surface to the second surface. A continuous seed metal layer is deposited on the first substrate surface and the second substrate surface, which can provide a layer having a tacky and conductive layer for electroplating on its surface (eg, Cu). Next, a photoresist layer is deposited on the first substrate surface and the second substrate surface, exposed and developed to form windows for selectively exposing the positions of the seed metal. Next, two metal support layers (eg Cu, then Ni) are electroplated over these exposed portions of the seed metal. Subsequently, at least one sacrificial metal layer (eg, Pd or Au) is electroplated over the exposed portions of the Ni support metal. The remaining photoresist layer is removed. Finally, the exposed Cu seed metal is removed to form islands in which the plated support metal and the sacrificial metal function as contact pads.

It is a technical advantage of the present invention that there is no contact pad layout in the design of so-called shortings or buss bars that function to connect pads for plating. As a result, none of this shorting / busbar removal is necessary after the plating step.

Another technical advantage of the present invention is that the electroless nickel and gold plating step, which is expensive and difficult to control, is replaced by an electrolytic plating step that is low cost and easy to adjust.

The technical improvements made by any of the embodiments of the present invention will become apparent from the detailed description of the preferred embodiments of the present invention when considered in connection with the novel features described in the accompanying drawings and the appended claims.

1 is a schematic cross-sectional view of an apparatus including a substrate and contact pads in accordance with an embodiment of the present invention.

2 is a schematic of a semiconductor assembly including a substrate having a semiconductor chip reflow-attached to one substrate surface and reflow elements for attaching to external components on an opposing substrate surface, in accordance with another embodiment of the present invention. Section.

3 is a schematic cross-sectional view of an apparatus at a stage of a manufacturing process flow in accordance with another embodiment of the present invention.

4 is a schematic cross-sectional view of the apparatus at another stage of the manufacturing process flow.

5 is a schematic cross-sectional view of the apparatus at another stage of the manufacturing process flow.

The schematic cross-sectional view of FIG. 1 shows one embodiment of the present invention. In FIG. 1, a portion of the device, designated 100 entirely, is shown, including an insulating substrate designated 101 with a surface 101a and an opposing surface 101b. In the example shown in FIG. 1, the substrate has a sheet-like configuration with each of the first and second approximately flat substrates 101a, 101b. Examples of substrate materials include polymers such as polyimide or epoxy, or composites such as FR-4, FR-5, or glass-fiber reinforced polymers, or other insulating materials. The substrate may have other geometry with two or more opposing surfaces. The substrate of the device has a plurality of metal filled vias extending from surface 101a to surface 101b. Typical metals for vias are copper or a copper alloy and may include gold as another option.

As further shown in FIG. 1, the substrate surface 101a has a plurality of contact pads 103, and the surface 101b has a plurality of contact pads 104. Contact pads 103 and contact pads 104 include a connector stack that contacts at least one of the vias 102. Each stack 103, 104 comprises several electrically conductive layers in series; The materials and the continuous form are the same for the stacks 103 and the stacks 104. This is because the stacks 103 on the first substrate surface 101a and the stacks 104 on the second substrate surface 101b are manufactured in the same processing steps in this embodiment.

There is a seed layer 110 in contact with the via metal. Layer 110 is in direct contact with the via metal. Preferred metal for layer 110 is copper. This metal has the desired properties to promote adhesion to the insulating surfaces of the substrate 101 and the via metal. Copper is also known to have high electrical conductivity and is operable to promote electroplating on its surface. Other materials that provide a suitable surface for electroplating additional copper may alternatively be used for layer 110. Typical layer 110 may have a thickness of 0.2 μm.

The next upper layer on top of layer 110 in stacks 103 and 104 are support layers 111a and 111b, which are electroplated and thus adhere to seed metal layer 110. The preferred metal for the electroplated layer 111a is copper. The thickness is preferably in the range of about 10 to 25 mu m. Metals other than copper may be suitable, having the desired properties in which layers with excellent electrical and thermal conductivity are prepared.

Layer 111b is directly above the top of layer 111a, which is preferably nickel. Layer 111b is suitable for forming a connection with reflow (solder) materials and is a barrier to copper diffusion into solder joints. The preferred thickness range for the nickel layer 111b is between about 6 and 10 μm.

The outermost layers of stacks 103 and 104 are electroplated sacrificial layers 112 to facilitate reflow connections; Specifically, the sacrificial layer 112 is necessary to prevent oxidation of the solderable metal 111b. Thus, sacrificial layer 112 is a reflow metal bonding layer on top of support layer 111b. This may include palladium or gold. Layer 112 is approximately 0.01 to 0.10 μm thick. Often, it is desirable to have two sacrificial layers 112a and 112b, layer 112a is preferably palladium and layer 112b is preferably gold.

Since electrolytic plating treatments (and not electroless plating) have been used to deposit the support layers 111a and 111b and the sacrificial metal layer 112 (or 112a and 112b), these layers are substantially pure and free of other elements. ; Specifically, it is substantially free of phosphorus and boron. The metals for the layers 111a, 111b, 112 have a purity of at least 99.0%, preferably at least 99.9%, more preferably at least 99.99%. Moreover, since the electroplated support layers 111a and 111b and the sacrificial metal layer 112 include crystal grains of controlled size, there is no grain of large size. The absence of unwanted elements and large sized crystals supports the formation of controlled, defect free, mechanically strong impact-durable solder joints.

Electrolytic plating treatments can be applied to any contoured surface as long as they remain interconnected for the electrical bias required during the plating step. As a result, the plating pattern may form any desired pattern on the first and second surfaces of the substrate 101, and often, as shown in FIG. 1, a surface different from the pattern on the surface 101b ( A pattern on 101a) is obtained. In specific embodiments, the workpiece 100 is intended for use in semiconductor assemblies, as shown in FIG. 2. In this case, the contact pads 103 on the first substrate surface 101a are arranged such that their number and position match the bond pads 203 of the semiconductor chip 201. In addition, the contact pads 104 on the second substrate surface 101b are often arranged such that their number and position match the attachment pads of the external component, such as a printed circuit or motherboard.

In the completed semiconductor assembly shown in FIG. 2 and represented generally at 200, reflow metal connection elements 220 are attached to contact pads 103 and interconnected to bond pads 203. Preferably, the reflow metal connection elements comprise tin or tin alloys such as tin / silver, tin / indium, tin / bismuth or tin / lead. Other alternatives include tin / silver / copper, and indium. In the reflow process, the sacrificial layer 112 (or 112a, 112b) of the contact pads 103 is dissolved and absorbed in the reflow alloy materials; These are indicated by broken lines in FIG. 2.

2 illustrates the preferred case, wherein the bond pads 203 of the chip 201 are also prepared by electroplating using a metal layer sequence similar to the contact pad sequence described above for the device 100. The semiconductor chip 201 has an active circuit on its surface 201a and has at least one metallization layer thereon (not shown in FIG. 2). The active circuit also includes a plurality of bonding pad sites 202 disposed on an electrically conductive bonding surface located directly above the active circuit, preferably but not necessarily, directly on the at least one metallization layer.

It is preferred that each bond pad site 202 has a connector stack 203 connected to at least one circuit metallization layer. Each stack 203 includes a seed metal layer 210 in contact with a circuit metallization layer that can provide a tacky and conductive layer for electroplating on its surface. Layer 210 is preferably made of copper, has a high conductivity, and allows electroplating on its surface. Alternatively, seed metal layer 210 may be a layer to ensure that it can be successfully electroplated.

The seed metal layer 210 is formed on the two support layers 211a and 211b, and is electroplated to adhere to the seed metal layer 210. Preferably, the metal of the support layer 211a is copper and the metal of the layer 211b is nickel. Other metals may also be suitable, especially for layer 211b, as long as it facilitates connection with reflow materials. The outermost layer of the stack 203 is preferably an electroplated sacrificial layer 212 that is at least partially palladium or at least partially gold, which prevents oxidation of the solderable metal 211b to facilitate reflow connection. Should be. In some products, it is advantageous to have two sacrificial layers, preferably palladium 212a and preferably gold 212b. In FIG. 2, the layers 212a and 212b are shown in broken lines because they are already dissolved in the reflow element 220 by the reflow process.

2 shows a reflow connection element 220 attached to each chip bond pad stack 203. Thus, the chip 201 and the substrate 101 are assembled. In the embodiment of FIG. 2, the assembly is completed by attaching a reflow connection element 230 to each connection stack 104 of contact pads on the second substrate surface 101b of the substrate 101. These connection stacks 104 include a metal similar to the stack 103, as described in connection with FIG. 1. Again, the electroplated sacrificial metal layer 112 is shown in broken lines because it was dissolved during the reflow treatment with the connection element 230 as the sacrificial layer.

Another embodiment of the invention is a method for manufacturing a device, comprising the following steps:

Providing a substrate 301 (see FIG. 3) of an insulating material, such as polyimide, having first and second surfaces 301a, 301b, respectively. For use in semiconductor technology, the apparatus has a sheet-like substrate suitable for assembling semiconductor chips. The substrate has a plurality of bars 302 filled with a metal such as copper extending from the first surface to the second surface.

Depositing a successive layer 310 of seed metal on the first and second substrate surfaces 301a, 301b, which can provide a layer having a tacky and conductive layer for electroplating thereon. The seed metal preferably comprises copper. Preferred method of deposition is electroless plating; An alternative method is sputtering.

-Depositing, exposing and developing the photoresist layer 340 on the seed metal layer 310 on both substrate surfaces of the first and second substrate surfaces 301a and 301b to selectively select portions of the seed metal 310. Forming windows 341 to expose them. The windows 341 may have various widths on the substrate surfaces 301a, 301b, as shown in FIG. 3. For a device destined for a semiconductor chip assembly, the windows on the first substrate surface may be configured to match the number and location with the bond pads of the semiconductor chip attached to the device. The windows on the second substrate surface may be configured to match the number and location with the contact pads of the external component attached to the device. The schematic cross-sectional view of FIG. 3 is a snapshot of the device state for the above in the manufacturing process flow. Materials other than photoresist may be used to define the plating pattern.

Electroplating the support metal layer 411a over all exposed portions of the seed metal (see FIG. 4). Preferred selection of this support metal is copper; Alternatively it can be a metal or alloy with excellent electrical and thermal conductivity. The electroplating process is substantially pure (at least 99.0%, preferably 99.9%, more preferably 99.99%), creating a support metal layer free of unwanted additives such as phosphorus or boron, and producing a carefully controlled grain size. Indicates.

Electroplating the support metal layer 411b over all exposed portions of the layer 411a (see FIG. 4). Preferred selection of this support metal is nickel; Alternatively, it may be a metal or alloy having affinity with reflow metals (solders). The electroplating process is substantially pure (at least 99.0%, preferably 99.9%, more preferably 99.99%), resulting in a support metal layer free of unwanted additives such as phosphorus or boron, and carefully controlled grain size Indicates.

Electroplating at least one sacrificial metal layer 412 over all exposed portions of the support metal 411b (see FIG. 4). Since layer 412 needs to prevent oxidation of solderable metal 411b, it is preferably at least partially made of palladium or partially gold, or two separate layers 412a and 412b of palladium and gold, respectively, May be Layer 412 is a sacrificial layer that is dissolved in the molten reflow connection element (solder ball) during the reflow process.

-Removing the remaining photoresist layer. 5 is a snapshot of the device state at this point in the manufacturing process flow.

Removing the exposed seed metal layer by etching or the like and electrically isolating the stacks of plated support metal and reflow bonding metal to form an island. Each island stack provides a solderable surface. Portions of the exposed seed metal removed in this treatment step are indicated at 541 in FIG. 5. After removal of the exposed seed metal, the device has the shape shown in FIG. 1. The separate island stacks serve as contact pads of the device.

Additional processing steps not shown in FIG. 5 may also deposit a so-called solder resist (solder mask) between each contact pad to more closely define the contact area for the reflow metal (solder). In another additional processing step not shown in FIG. 5, a reflow metal connecting element (solder ball) may be attached to each of the contact stacks.

Although the present invention has been described by reference to describe embodiments, this detailed description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the embodiments as well as other embodiments of the present invention will become apparent to those skilled in the art with reference to the detailed description. As an example, the material of a semiconductor chip may include silicon, silicon germanium, gallium arsenide or any other semiconductor or compound material used in IC fabrication.

As another example, the connection elements between the substrate and the semiconductor chip can be gold bumps instead of reflow elements.

Claims (9)

As a device, An insulating substrate having a first surface and a second surface and a plurality of metal filled vias extending from the first surface to the second surface; And The first and second substrate surfaces with contact pads Including, Each of the pads comprises a connector stack for at least one of the vias, each stack in contact with the via metal that can provide a tacky and conductive layer for electroplating on its surface And a conductive layer, a first electroplating support metal layer adhered to the seed metal layer, a second electroplating support metal layer on the first support layer, and at least one sacrificial metal layer on the second support layer. The metal and the sacrificial metal having a purity of at least 99.0%. The method of claim 1, The seed metal layer comprises copper, the first electroplating support metal layer comprises copper, the second electroplating support metal layer comprises nickel, and the sacrificial metal layer is palladium, gold, silver or an alloy or combination thereof Device comprising a metal selected from the group consisting of. The method according to claim 1 or 2, At least one of said contact pads has an attached reflow metal connection element. The method of claim 3, The reflow metal connection element comprises tin, tin / silver, tin / indium, tin / bismuth, tin / lead, or other tin alloy or indium. The method according to any one of claims 1 to 4, And the electroplating support layers and sacrificial metal layers comprise crystalline grains of controlled size. As a semiconductor assembly, A semiconductor chip having an active circuit and at least one metallization layer thereon; An electrically conductive bonding surface located directly above the metallization layer, the bonding surface having connector stacks for the metallization layer, each of the stacks providing a cohesive and conductive layer for electroplating on the surface. A seed metal layer in contact with said metallization layer, an electroplating support layer adhered to said seed metal layer, and at least one sacrificial metal layer on said support layer such that each stack defines a chip bond pad; A reflow metal connection element attached to each of said chip bond pads; An insulated substrate having a first surface and a second surface and a plurality of metal filled vias extending from the first surface to the second surface, the first substrate surface having contact pads in a location that matches the chip bond pads Each contact pad includes a connector stack for at least one of the vias, each of the stacks in contact with the via metal capable of providing a tacky and conductive layer for electroplating on its surface. And a seed metal layer, a first electroplating support metal layer adhered to the seed metal layer, a second electroplating support metal layer on the first support layer, and at least one sacrificial metal layer on the second support layer. And the sacrificial metal has a purity of at least 99.0%; And Each contact pad attached to the reflow metal connection element of the respective chip bond pad-the second substrate surface has contact pads in positions operable to connect to external components, the contact pad being in at least one of the vias A seed metal layer in contact with the via metal, the first electroplating adhered to the seed metal layer, the connector stack comprising: a connector stack; A support metal layer, a second electroplating support metal layer on the first support layer, and at least one sacrificial metal layer on the second support layer, wherein the support metal and the sacrificial metal have a purity of at least 99.0%. Semiconductor assembly comprising a. As a device manufacturing method, Providing a substrate of insulating material having a first surface and a second surface, the substrate having a plurality of metal filled vias extending from the first surface to the second surface; Depositing a continuous seed metal layer on the first and second substrate surfaces, which may provide a layer having a tacky and conductive layer for electroplating on the surface; Depositing, exposing and developing a photoresist layer on the seed metal layer on the first and second substrate surfaces to form windows for selectively exposing portions of the seed metal; Electroplating a first support metal layer over exposed portions of the seed metal; Electroplating a second support metal layer over the exposed portions of the first support metal, the first and second support metals having a purity of at least 99.0%; Electroplating at least one sacrificial metal layer over exposed portions of the second support metal, the sacrificial metal having a purity of at least 99.0%; Removing the remaining photoresist layer; And Removing the exposed seed metal layer and isolating the plated support metals and sacrificial metals to form islands Device manufacturing method comprising a. The method of claim 7, wherein The islands are contact pads, and further comprising attaching a reflow metal connection element to at least one of the island contact pads. The method according to claim 7 or 8, The seed metal comprises copper, the first support metal comprises copper, the second support metal comprises nickel, and the sacrificial metal is from the group consisting of palladium, gold, silver and alloys or combinations thereof The device manufacturing method selected.

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