US20140264608A1 - Ditches near semiconductor fins and methods for forming the same - Google Patents
Ditches near semiconductor fins and methods for forming the same Download PDFInfo
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- US20140264608A1 US20140264608A1 US13/838,407 US201313838407A US2014264608A1 US 20140264608 A1 US20140264608 A1 US 20140264608A1 US 201313838407 A US201313838407 A US 201313838407A US 2014264608 A1 US2014264608 A1 US 2014264608A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000000034 method Methods 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000002955 isolation Methods 0.000 claims abstract description 31
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 62
- 229910052732 germanium Inorganic materials 0.000 claims description 61
- 238000000407 epitaxy Methods 0.000 claims description 36
- 238000000137 annealing Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 241000208152 Geranium Species 0.000 description 1
- 229910006990 Si1-xGex Inorganic materials 0.000 description 1
- 229910007020 Si1−xGex Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
Definitions
- MOS transistors are closely related to the drive currents of the MOS transistors, which are further closely related to the mobility of charges in the channels of the MOS transistors.
- MOS transistors have high drive currents when the electron mobility in their channel regions is high
- PMOS transistors have high drive currents when the hole mobility in their channel regions is high.
- III-V compound semiconductors Germanium, silicon germanium, and compound semiconductor materials (referred to as III-V compound semiconductors hereinafter) comprising group III and group V elements are thus good candidates for forming their high electron mobility and/or hole mobility.
- Germanium, silicon germanium, and III-V compound semiconductor regions are also promising materials for forming the channel regions of Fin Field-Effect transistors (FinFETs). Methods and structures for further improving the drive currents on the FinFETs are currently being studied.
- FIGS. 1 through 9 include cross-sectional views and a top view of intermediate stages in the manufacturing of a semiconductor fin and a Fin Field-Effect Transistor (FinFET) in accordance with some exemplary embodiments;
- FinFET Fin Field-Effect Transistor
- FIG. 10 illustrates an I-V curve of a FinFET in accordance with some embodiments.
- FIG. 11 illustrates a cross-sectional view of a FinFET in accordance with alternative embodiments, wherein a germanium-containing region extends to below a bottom of a ditch.
- FinFETs Fin Field-Effect Transistors
- Method of forming the same are provided in accordance with various exemplary embodiments.
- the intermediate stages of forming the FinFETs in accordance with some embodiments are illustrated.
- the variations of the embodiments are discussed.
- like reference numbers are used to designate like elements.
- substrate 10 is provided.
- Substrate 10 may be a semiconductor substrate such as a crystalline silicon substrate.
- substrate 10 is etched to form trenches 12 , which extend from the top surface of substrate 10 into substrate 10 .
- the portion of substrate 10 between neighboring trenches 12 is referred to as semiconductor strip 10 ′ hereinafter.
- Hard mask 11 may be formed to define the patterns of trenches 12 and semiconductor strip 10 ′, wherein substrate 10 is etched using hard mask 11 as an etching mask.
- Hard mask 11 may comprise, for example, silicon nitride, silicon oxide, or multi-layers thereof.
- hard mask 11 includes a silicon oxide layer as a pad oxide layer, and a silicon nitride layer over the silicon oxide layer.
- Trenches 12 include neighboring portions on the opposite sides of semiconductor strip 10 ′.
- Width W 1 of substrate portions 10 ′ may be between about 5 nm and about 200 nm, although different values may be used.
- the neighboring trenches 12 may be physically disconnected from each other, or may be portions of a continuous trench, which may form a trench ring encircling semiconductor strip 10 ′ in some embodiments.
- FIGS. 3 through 5 illustrate the steps for forming germanium-containing Shallow Trench Isolation (STI) portions 16 A ( FIG. 5 ) in accordance with some embodiments.
- germanium-containing layer 14 is formed, for example, using a deposition method such as Chemical Vapor Deposition (CVD).
- CVD Chemical Vapor Deposition
- germanium-containing layer 14 comprises pure germanium or substantially pure germanium, wherein the substantially pure germanium may have a germanium percentage greater than about 90 percent.
- germanium-containing layer 14 comprises silicon germanium, wherein the germanium concentration may be, for example, between about 10 percent and about 20 percent.
- Thickness T 1 of germanium-containing layer 14 may be between about 0.5 nm and about 5 nm.
- germanium-containing layer 14 is formed selectively on the exposed surfaces of substrate 10 , and not on hard mask 11 . In alternative embodiments, germanium-containing layer 14 is formed on the surfaces of both substrate 10 and hard mask 11 .
- FIG. 4 illustrates the formation of STI regions 16 , which is formed by filling trenches 12 ( FIG. 3 ) with dielectric materials such as silicon oxide.
- the formation method may be selected from High-Density Plasma Chemical Vapor Deposition (HDPCVD), Flowable Chemical Vapor Deposition (FCVD), or other applicable methods.
- a Chemical Mechanical Polish (CMP) is then performed to remove excess portions of the dielectric materials, and the remaining portions are STI regions 16 .
- the resulting height H 1 of STI regions 16 may be between about 100 nm and about 400 nm, or greater than 400 nm.
- Hard mask 11 in FIG. 3 may then be removed.
- STI regions 16 hence comprise germanium-containing STI portions 16 A and germanium-free STI portions 16 B, wherein germanium-free STI portions 16 B are formed overlapping the bottom portions of germanium-containing STI portions 16 A. Furthermore, germanium-containing STI portions 16 A may encircle germanium-free STI portions 16 B. Accordingly, germanium-containing STI portions 16 A in each of STI regions 16 may form a basin, with a germanium-free STI portion 16 B in the basin. In some embodiments, the annealing is performed at a temperature between about 400° C.
- the annealing duration may be between about 10 seconds and about 5 minutes.
- Thickness T 2 of the resulting germanium-containing STI portions 16 A may be about 2 nm and about 20 nm in accordance with some exemplary embodiments, although thickness T 2 may be greater or smaller, depending on the annealing time and the thickness of germanium-containing layer 14 ( FIG. 4 ).
- substrate portion 10 ′ is recessed, forming recess 24 between neighboring STI regions 16 .
- the bottom of recess 24 is higher than the bottom surfaces of STI regions 16 .
- the bottom of recess 24 is substantially level with or lower than the bottoms of STI regions 16 .
- depth D 1 of recess 24 is between about 20 nm and about 400 nm.
- the recessing may be performed, for example using a dry etching method, with CF 4 as an etchant gas or gaseous HC 1 .
- epitaxy semiconductor region 26 is grown in recess 24 through epitaxy.
- the top surface of epitaxy semiconductor region 26 may be level with the top surfaces of STI regions 16 .
- Epitaxy semiconductor region 26 may have a lattice constant greater than or smaller than the lattice constant of substrate 10 .
- epitaxy semiconductor region 26 comprises silicon germanium, which is expressed as Si 1-x Ge x , wherein value X is the atomic percentage of germanium in epitaxy semiconductor region 26 , which atomic percentage may be greater than about 0.1 (10 percent) and lower than 1.0 (100 percent) in some exemplary embodiments.
- epitaxy semiconductor region 26 comprises pure germanium or substantially pure germanium (wherein value X is equal to or substantially equal to 1.0). In yet alternative embodiments, epitaxy semiconductor region 26 does not comprise germanium, and may comprise, for example, silicon carbon, silicon phosphorous, a III-V compound semiconductor, or another semiconductor material.
- epitaxy semiconductor region 26 may comprise lower portion 26 A and upper portion 26 B, with upper portion 26 B having a germanium percentage greater than the germanium percentage of lower portion 26 A.
- lower portion 26 A may include Si 1-x1 Ge x1
- upper portion 26 B includes Si 1-x2 Ge x2 , wherein value X2 is greater than value X1.
- lower portion 26 A comprises silicon germanium
- upper portion 26 B comprises substantially pure germanium.
- an entirety of epitaxy semiconductor region 26 is formed of a homogenous germanium-containing material.
- the growth of epitaxy semiconductor region 26 may be performed using selective epitaxy, in which a germanium-containing precursor such as germane (GeH 4 ) is used as the germanium source.
- a germanium-containing precursor such as germane (GeH 4 )
- germane (GeH 4 ) is used as the germanium source.
- precursors such as silane (SiH 4 ) and dichloro-silane (DCS) may be added as the silicon source.
- the temperature of the epitaxy may be between about 400° C. and about 600° C.
- the growth rate of epitaxy semiconductor region 26 is adjusted to a low level.
- the deposition rate of epitaxy semiconductor region 26 may be adjusted to be lower than about 10 ⁇ /second.
- Epitaxy semiconductor region 26 may be grown to a level higher than the top surfaces of STI regions 16 .
- a CMP is then performed to level the top surfaces of STI regions 16 and epitaxy semiconductor region 26 .
- the resulting structure is shown in FIG. 7 .
- the growth of epitaxy semiconductor region 26 is stopped when the top surface of epitaxy semiconductor region 26 is level with or lower than the top surfaces of STI regions 16 .
- the CMP may be performed, or may be skipped.
- an annealing step is performed after the formation of epitaxy semiconductor region 26 .
- the annealing may be performed at a temperature between about 400° C. and about 600° C., or higher than 600° C., for example, between about 600° C. and about 900° C.
- the annealing may be performed for a period of time between about 0.5 minutes and about 30 minutes.
- STI regions 16 are recessed, for example, through an etching step.
- the portions of semiconductor region 26 and substrate portion 10 ′ that are higher than top surfaces 16 C of the resulting STI regions 16 are referred to as semiconductor fin 30 hereinafter.
- the recessing of STI regions 16 may be through an isotropic etching.
- the recessing of STI regions 16 comprises a wet etching using a Hydrogen Fluoride (HF) solution, which may have an HF concentration between about 0.3 percent and about 5 percent. The HF concentration may also be between about 1.5 percent and about 2.5 percent.
- HF Hydrogen Fluoride
- top surfaces 16 C of STI regions 16 includes portions 16 C 1 that are substantially flat. Top surfaces 16 C further include portions 16 C 2 connecting the bottom of fin 30 to portions 16 C 1 . Portions 16 C 2 and 16 C 1 are the top surfaces of germanium-containing STI portions 16 A and germanium-free STI portions 16 B, respectively. Top surface portions 16 C 2 may have a gradually increased height, with the height gradually increases from the regions closer to fin 30 to the regions farther away from fin 30 . In addition, the profile of surface portions 16 C 2 may be rounded, and may have a shape close to a quarter of a circle, with the radius R of the circle being between about 2 nm and about 20 nm, for example.
- Ditches 32 are formed close to fin 30 , wherein surface portions 16 C 2 , which are the portions of top surfaces of STI regions 16 , are inside and exposed to ditches 32 .
- Ditches 32 may have depth D 2 between about 5 nm and about 20 nm.
- ditches 32 may also be smaller than about 5 nm or greater than about 20 nm.
- germanium-containing STI regions 16 A have a higher etching rate than germanium-free STI regions 16 B. Accordingly, the process steps may be adjusted to form germanium-containing STI regions 16 A.
- the step shown in FIG. 3 is performed, and germanium-containing layer 14 is formed, so that germanium-containing STI regions 16 A may be formed through the diffusion of germanium-containing layer 14 .
- the material of epitaxy semiconductor region 26 may be selected to comprise germanium, or may be germanium-free.
- the materials of epitaxy semiconductor region 26 are selected to comprise germanium-containing regions, and an annealing may be performed after the formation of epitaxy semiconductor region 26 in order to form germanium-containing STI regions.
- germanium-containing STI regions 16 A′ are formed adjoining epitaxy semiconductor region 26 .
- no germanium-containing STI regions 16 A′ are formed.
- the resulting germanium-containing STI regions 16 A′ are schematically in FIG. 7 .
- FIG. 8B illustrates a top view of the structure in FIG. 8A , wherein the cross-sectional view in FIG. 8A is obtained from the plane crossing line 8 A- 8 A in FIG. 8B .
- STI regions 16 may form an STI ring encircling the entire substrate portion 10 ′.
- Ditch(es) 32 may form an integrated ditch encircling the entire substrate portion 10 ′.
- ditches 32 have substantially uniform widths W 2 and W 3 .
- width W 3 which is the width of portions 32 B of ditch 32
- width W 2 which is the width of portions 32 A of ditch 32 .
- Portions 32 B are close to and adjoining the short sides of substrate strips 10 ′, while portions 32 A are close to and adjoining the long sides of substrate strips 10 ′.
- Ratio W 3 /W 2 may be between about 0.5 and about 2 in accordance with some embodiments.
- ditch portions 32 B may have a depth greater than the depth of ditch portions 32 A.
- various methods and/or process conditions are adjusted to form and to increase the depth D 2 ( FIG. 8A ) of ditches 32 .
- increasing the temperature in the epitaxy of epitaxy semiconductor region 26 , performing the annealing after the epitaxy, reducing the growth rate of epitaxy semiconductor region 26 , and/or increasing the germanium concentration in epitaxy semiconductor region 26 may result in the formation of ditches 32 and the increase in depth D 2 of ditches 32 .
- the formation of ditches 32 and the increase in depth D 2 may be achieved by increasing the etching selectivity of germanium-containing STI portions 16 A and germanium-free STI portions 16 B.
- the increase in the etching selectivity may be achieved by selecting and tuning the etchant process and the etchant composition for etching STI regions 16 . It is appreciated that the formation of ditches 32 may be affected by several factors, and ditches 32 may not be formed if these factors as a combination do not satisfy the required conditions. Hence, the optimum formation condition of ditches 32 may be found through experiments.
- gate dielectric 40 and gate electrode 42 are formed.
- Gate dielectric 40 may be formed of a dielectric material such as silicon oxide, silicon nitride, an oxynitride, multi-layers thereof, and/or combinations thereof.
- Gate dielectric 40 may also be formed of high-k dielectric materials. The exemplary high-k materials may have k values greater than about 4.0, or greater than about 7.0.
- Gate electrode 42 may be formed of a conductive material selected from doped polysilicon, metals, metal nitrides, metal silicides, and the like. After the formation of gate dielectric 40 and gate electrode 42 , source and drain regions (not shown) are formed.
- ditches 32 results in the increase of fin height H 2 by the height of depth D 2 of ditches 32 compared to if ditches 32 are not formed.
- the on-current of FinFET 38 is hence increased without causing the increase in recessing depth D 3 ( FIG. 8A ).
- fin 30 has a heterogeneous structure, with the lower portion 30 A having a greater bandgap than the upper portion 30 B.
- the channel 44 of FinFET includes lower channel portions 44 A and upper channel portions 44 B.
- the lower channel portions 44 A form a first sub-FinFET with gate dielectric 40 and gate electrode 42 , wherein the first sub-FinFET has a first threshold voltage Vt 1 .
- the upper channel portions 44 B form a second sub-FinFET with gate dielectric 40 and gate electrode 42 , wherein the second sub-FinFET has a second threshold voltage Vt 2 .
- Threshold voltage Vt 2 is lower than threshold voltage Vt 1 in some embodiments.
- the advantageous feature of the corresponding FinFET 38 is illustrated in FIG. 10 .
- FIG. 10 the current I flowing between the source and drain region of FinFET 38 ( FIG. 9 ) is illustrated as a function of the gate voltage (Vg) applied on gate electrode 42 ( FIG. 9 ).
- Lines 50 and 52 are I-V curves of the first sub-FinFET (having channel portions 44 A) and the second sub-FinFET (having channel portions 44 B), respectively, and line 54 is the I-V curve of FinFET 38 .
- the off-state current IOff (corresponding to low gate voltages Vg) of FinFET 38 is the sum of the leakage currents of the first and the second sub-FinFETs, and is mainly determined by the leakage current (line 52 ) of the second sub-FinFET due to its lower threshold voltage Vt 1 . Since the off-state current of the second sub-transistor is very low, the leakage current of FinFET 38 is low.
- the on-current of FinFET 38 is the sum of, and is affected by, both the on-currents of the first and the second sub-FinFETs. The on-current of FinFET 38 is hence high. As shown in FIG. 10 , when gate voltage Vg reaches a certain level, there is a noticeable current jump. Hence, FinFET 38 has a high on-current and a low leakage current.
- FIG. 11 illustrates FinFET 38 in accordance with alternative embodiments.
- semiconductor fin 30 has a homogenous structure comprising, for example, silicon geranium or substantially germanium.
- epitaxy semiconductor region 26 has a bottom lower than the bottoms of ditches 32 , so that the defects in the re-grown epitaxy semiconductor region 26 are limited to the portions lower than the channel region of FinFET 38 .
- the heights of semiconductor fins are increased, resulting in an increase in the on-currents of the FinFETs.
- the recessing distance of STI regions does not need to be increased.
- the increase in the on-current is obtained without the cost of process difficulty.
- the formation of the ditches does not require additional etching process and additional lithography masks. Hence, the manufacturing cost of the embodiments of the present disclosure is low.
- a device in accordance with some embodiments, includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate.
- a semiconductor strip is between and contacting the isolation regions.
- a semiconductor fin overlaps, and is joined to, the semiconductor strip.
- a ditch extends from a top surface of the isolation regions into the isolation regions, wherein the ditch adjoins the semiconductor fin.
- a device in accordance with other embodiments, includes a silicon substrate, STI regions extending into the silicon substrate, and a semiconductor fin between the STI regions.
- the semiconductor fin is higher than neighboring portions of the STI regions.
- the STI regions comprise a top surface, which further includes a first portion being substantially flat, and a second portion connecting a bottom of the fin to the first portion of the top surface. The second portion of the top surface is lower than the first portion of the top surface.
- a method includes recessing a portion of a semiconductor substrate between isolation regions to form a recess in the semiconductor substrate.
- An epitaxy is performed to grow a semiconductor region in the recess.
- the isolation regions are recessed, wherein a top portion of the semiconductor region over the isolation regions forms a semiconductor fin.
- a ditch is formed simultaneously when the step of recessing the isolation regions is performed, with the ditch being in the isolation regions and adjoining the semiconductor fin.
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Abstract
Description
- This application claims the benefit of U.S. Provisional Application No. 61/780,847, filed on Mar. 13, 2013, entitled “Ditches Near Semiconductor Fins and Methods for Forming the Same”, which application is hereby incorporated herein by reference.
- The speed of metal-oxide-semiconductor (MOS) transistors are closely related to the drive currents of the MOS transistors, which are further closely related to the mobility of charges in the channels of the MOS transistors. For example, NMOS transistors have high drive currents when the electron mobility in their channel regions is high, while PMOS transistors have high drive currents when the hole mobility in their channel regions is high. Germanium, silicon germanium, and compound semiconductor materials (referred to as III-V compound semiconductors hereinafter) comprising group III and group V elements are thus good candidates for forming their high electron mobility and/or hole mobility.
- Germanium, silicon germanium, and III-V compound semiconductor regions are also promising materials for forming the channel regions of Fin Field-Effect transistors (FinFETs). Methods and structures for further improving the drive currents on the FinFETs are currently being studied.
- For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1 through 9 include cross-sectional views and a top view of intermediate stages in the manufacturing of a semiconductor fin and a Fin Field-Effect Transistor (FinFET) in accordance with some exemplary embodiments; -
FIG. 10 illustrates an I-V curve of a FinFET in accordance with some embodiments; and -
FIG. 11 illustrates a cross-sectional view of a FinFET in accordance with alternative embodiments, wherein a germanium-containing region extends to below a bottom of a ditch. - The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
- Semiconductor fins, Fin Field-Effect Transistors (FinFETs), and the methods of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the FinFETs in accordance with some embodiments are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
- Referring to
FIG. 1 ,substrate 10 is provided.Substrate 10 may be a semiconductor substrate such as a crystalline silicon substrate. Next, as shown inFIG. 2 ,substrate 10 is etched to formtrenches 12, which extend from the top surface ofsubstrate 10 intosubstrate 10. The portion ofsubstrate 10 between neighboringtrenches 12 is referred to assemiconductor strip 10′ hereinafter.Hard mask 11 may be formed to define the patterns oftrenches 12 andsemiconductor strip 10′, whereinsubstrate 10 is etched usinghard mask 11 as an etching mask.Hard mask 11 may comprise, for example, silicon nitride, silicon oxide, or multi-layers thereof. In some exemplary embodiments,hard mask 11 includes a silicon oxide layer as a pad oxide layer, and a silicon nitride layer over the silicon oxide layer. -
Trenches 12 include neighboring portions on the opposite sides ofsemiconductor strip 10′. Width W1 ofsubstrate portions 10′ may be between about 5 nm and about 200 nm, although different values may be used. The neighboringtrenches 12 may be physically disconnected from each other, or may be portions of a continuous trench, which may form a trench ring encirclingsemiconductor strip 10′ in some embodiments. -
FIGS. 3 through 5 illustrate the steps for forming germanium-containing Shallow Trench Isolation (STI)portions 16A (FIG. 5 ) in accordance with some embodiments. Referring toFIG. 3 , germanium-containinglayer 14 is formed, for example, using a deposition method such as Chemical Vapor Deposition (CVD). In some embodiments, germanium-containinglayer 14 comprises pure germanium or substantially pure germanium, wherein the substantially pure germanium may have a germanium percentage greater than about 90 percent. In alternative embodiments, germanium-containinglayer 14 comprises silicon germanium, wherein the germanium concentration may be, for example, between about 10 percent and about 20 percent. Thickness T1 of germanium-containinglayer 14 may be between about 0.5 nm and about 5 nm. It is appreciated that the values recited in the description are merely examples, and may be changed to different values. The thicknesses of the vertical portions and the horizontal portions of germanium-containinglayer 14 may be close to each other, and hence germanium-containinglayer 14 may be a conformal layer. In some embodiments, germanium-containinglayer 14 is formed selectively on the exposed surfaces ofsubstrate 10, and not onhard mask 11. In alternative embodiments, germanium-containinglayer 14 is formed on the surfaces of bothsubstrate 10 andhard mask 11. -
FIG. 4 illustrates the formation ofSTI regions 16, which is formed by filling trenches 12 (FIG. 3 ) with dielectric materials such as silicon oxide. The formation method may be selected from High-Density Plasma Chemical Vapor Deposition (HDPCVD), Flowable Chemical Vapor Deposition (FCVD), or other applicable methods. A Chemical Mechanical Polish (CMP) is then performed to remove excess portions of the dielectric materials, and the remaining portions areSTI regions 16. The resulting height H1 ofSTI regions 16 may be between about 100 nm and about 400 nm, or greater than 400 nm.Hard mask 11 inFIG. 3 may then be removed. - Next, an annealing is performed, so that the germanium atoms in germanium-containing
layer 14 diffuse intoSTI regions 16. The resulting structure is shown inFIG. 5 .STI regions 16 hence comprise germanium-containingSTI portions 16A and germanium-free STI portions 16B, wherein germanium-free STI portions 16B are formed overlapping the bottom portions of germanium-containingSTI portions 16A. Furthermore, germanium-containingSTI portions 16A may encircle germanium-free STI portions 16B. Accordingly, germanium-containingSTI portions 16A in each ofSTI regions 16 may form a basin, with a germanium-free STI portion 16B in the basin. In some embodiments, the annealing is performed at a temperature between about 400° C. and about 900° C. The annealing duration may be between about 10 seconds and about 5 minutes. Thickness T2 of the resulting germanium-containingSTI portions 16A may be about 2 nm and about 20 nm in accordance with some exemplary embodiments, although thickness T2 may be greater or smaller, depending on the annealing time and the thickness of germanium-containing layer 14 (FIG. 4 ). - Referring to
FIG. 6 ,substrate portion 10′ is recessed, formingrecess 24 between neighboringSTI regions 16. In some embodiments, the bottom ofrecess 24 is higher than the bottom surfaces ofSTI regions 16. In alternative embodiments, the bottom ofrecess 24 is substantially level with or lower than the bottoms ofSTI regions 16. In some exemplary embodiments, depth D1 ofrecess 24 is between about 20 nm and about 400 nm. The recessing may be performed, for example using a dry etching method, with CF4 as an etchant gas or gaseous HC1. - Referring to
FIG. 7 ,epitaxy semiconductor region 26 is grown inrecess 24 through epitaxy. The top surface ofepitaxy semiconductor region 26 may be level with the top surfaces ofSTI regions 16.Epitaxy semiconductor region 26 may have a lattice constant greater than or smaller than the lattice constant ofsubstrate 10. In some embodiments,epitaxy semiconductor region 26 comprises silicon germanium, which is expressed as Si1-xGex, wherein value X is the atomic percentage of germanium inepitaxy semiconductor region 26, which atomic percentage may be greater than about 0.1 (10 percent) and lower than 1.0 (100 percent) in some exemplary embodiments. In alternative embodiments,epitaxy semiconductor region 26 comprises pure germanium or substantially pure germanium (wherein value X is equal to or substantially equal to 1.0). In yet alternative embodiments,epitaxy semiconductor region 26 does not comprise germanium, and may comprise, for example, silicon carbon, silicon phosphorous, a III-V compound semiconductor, or another semiconductor material. - In some embodiments in which
epitaxy semiconductor region 26 comprises germanium,epitaxy semiconductor region 26 may compriselower portion 26A andupper portion 26B, withupper portion 26B having a germanium percentage greater than the germanium percentage oflower portion 26A. For example,lower portion 26A may include Si1-x1Gex1, andupper portion 26B includes Si1-x2Gex2, wherein value X2 is greater than value X1. In alternative embodiments,lower portion 26A comprises silicon germanium, whileupper portion 26B comprises substantially pure germanium. In other embodiments, an entirety ofepitaxy semiconductor region 26 is formed of a homogenous germanium-containing material. - The growth of
epitaxy semiconductor region 26 may be performed using selective epitaxy, in which a germanium-containing precursor such as germane (GeH4) is used as the germanium source. In addition, in the embodiments in whichepitaxy semiconductor region 26 comprises silicon, precursors such as silane (SiH4) and dichloro-silane (DCS) may be added as the silicon source. The temperature of the epitaxy may be between about 400° C. and about 600° C. In some embodiments, the growth rate ofepitaxy semiconductor region 26 is adjusted to a low level. For example, the deposition rate ofepitaxy semiconductor region 26 may be adjusted to be lower than about 10 Å/second. -
Epitaxy semiconductor region 26 may be grown to a level higher than the top surfaces ofSTI regions 16. A CMP is then performed to level the top surfaces ofSTI regions 16 andepitaxy semiconductor region 26. The resulting structure is shown inFIG. 7 . In alternative embodiments, the growth ofepitaxy semiconductor region 26 is stopped when the top surface ofepitaxy semiconductor region 26 is level with or lower than the top surfaces ofSTI regions 16. In these embodiments, the CMP may be performed, or may be skipped. In some embodiments, after the formation ofepitaxy semiconductor region 26, an annealing step is performed. The annealing may be performed at a temperature between about 400° C. and about 600° C., or higher than 600° C., for example, between about 600° C. and about 900° C. The annealing may be performed for a period of time between about 0.5 minutes and about 30 minutes. - Referring to
FIG. 8A ,STI regions 16 are recessed, for example, through an etching step. The portions ofsemiconductor region 26 andsubstrate portion 10′ that are higher thantop surfaces 16C of the resultingSTI regions 16 are referred to assemiconductor fin 30 hereinafter. The recessing ofSTI regions 16 may be through an isotropic etching. In some embodiments, the recessing ofSTI regions 16 comprises a wet etching using a Hydrogen Fluoride (HF) solution, which may have an HF concentration between about 0.3 percent and about 5 percent. The HF concentration may also be between about 1.5 percent and about 2.5 percent. - As a result of the etching,
top surfaces 16C ofSTI regions 16 includes portions 16C1 that are substantially flat.Top surfaces 16C further include portions 16C2 connecting the bottom offin 30 to portions 16C1. Portions 16C2 and 16C1 are the top surfaces of germanium-containingSTI portions 16A and germanium-free STI portions 16B, respectively. Top surface portions 16C2 may have a gradually increased height, with the height gradually increases from the regions closer tofin 30 to the regions farther away fromfin 30. In addition, the profile of surface portions 16C2 may be rounded, and may have a shape close to a quarter of a circle, with the radius R of the circle being between about 2 nm and about 20 nm, for example. -
Ditches 32 are formed close tofin 30, wherein surface portions 16C2, which are the portions of top surfaces ofSTI regions 16, are inside and exposed to ditches 32.Ditches 32 may have depth D2 between about 5 nm and about 20 nm. Alternatively, ditches 32 may also be smaller than about 5 nm or greater than about 20 nm. - The mechanism for the formation of
ditches 32 is not fully understood. A possible explanation is that germanium-containingSTI regions 16A have a higher etching rate than germanium-free STI regions 16B. Accordingly, the process steps may be adjusted to form germanium-containingSTI regions 16A. For example, the step shown inFIG. 3 is performed, and germanium-containinglayer 14 is formed, so that germanium-containingSTI regions 16A may be formed through the diffusion of germanium-containinglayer 14. In these embodiments, since germanium-containingSTI regions 16A are formed through the formation of germanium-containinglayer 14, the material ofepitaxy semiconductor region 26 may be selected to comprise germanium, or may be germanium-free. In alternative embodiments, the step shown inFIG. 3 and the subsequent annealing for diffusing germanium-containinglayer 14 are skipped. In these embodiments, the materials of epitaxy semiconductor region 26 (FIG. 7 ) are selected to comprise germanium-containing regions, and an annealing may be performed after the formation ofepitaxy semiconductor region 26 in order to form germanium-containing STI regions. In these embodiments, however, as shown inFIG. 7 , germanium-containingSTI regions 16A′ are formed adjoiningepitaxy semiconductor region 26. In portions ofSTI regions 16 adjoining non-germanium containing regions (such as on the sidewalls ofsubstrate portion 10′ and at the bottoms of STI regions 16), no germanium-containingSTI regions 16A′ are formed. The resulting germanium-containingSTI regions 16A′ are schematically inFIG. 7 . -
FIG. 8B illustrates a top view of the structure inFIG. 8A , wherein the cross-sectional view inFIG. 8A is obtained from theplane crossing line 8A-8A inFIG. 8B . As shown inFIG. 8B ,STI regions 16 may form an STI ring encircling theentire substrate portion 10′. Ditch(es) 32 may form an integrated ditch encircling theentire substrate portion 10′. In some embodiments, ditches 32 have substantially uniform widths W2 and W3. In alternative embodiments, width W3, which is the width ofportions 32B ofditch 32, is greater than width W2, which is the width ofportions 32A ofditch 32.Portions 32B are close to and adjoining the short sides of substrate strips 10′, whileportions 32A are close to and adjoining the long sides of substrate strips 10′. Ratio W3/W2 may be between about 0.5 and about 2 in accordance with some embodiments. In addition,ditch portions 32B may have a depth greater than the depth ofditch portions 32A. - In accordance with some embodiments, various methods and/or process conditions are adjusted to form and to increase the depth D2 (
FIG. 8A ) ofditches 32. For example, increasing the temperature in the epitaxy ofepitaxy semiconductor region 26, performing the annealing after the epitaxy, reducing the growth rate ofepitaxy semiconductor region 26, and/or increasing the germanium concentration inepitaxy semiconductor region 26 may result in the formation ofditches 32 and the increase in depth D2 of ditches 32. Furthermore, the formation ofditches 32 and the increase in depth D2 may be achieved by increasing the etching selectivity of germanium-containingSTI portions 16A and germanium-free STI portions 16B. The increase in the etching selectivity may be achieved by selecting and tuning the etchant process and the etchant composition for etchingSTI regions 16. It is appreciated that the formation ofditches 32 may be affected by several factors, and ditches 32 may not be formed if these factors as a combination do not satisfy the required conditions. Hence, the optimum formation condition ofditches 32 may be found through experiments. - The structure shown in
FIGS. 8A and 8B may be used to formFinFET 38, as shown inFIG. 9 . Referring toFIG. 9 ,gate dielectric 40 andgate electrode 42 are formed.Gate dielectric 40 may be formed of a dielectric material such as silicon oxide, silicon nitride, an oxynitride, multi-layers thereof, and/or combinations thereof.Gate dielectric 40 may also be formed of high-k dielectric materials. The exemplary high-k materials may have k values greater than about 4.0, or greater than about 7.0.Gate electrode 42 may be formed of a conductive material selected from doped polysilicon, metals, metal nitrides, metal silicides, and the like. After the formation ofgate dielectric 40 andgate electrode 42, source and drain regions (not shown) are formed. - As shown in
FIG. 9 , the formation of ditches 32 (FIG. 8A ) results in the increase of fin height H2 by the height of depth D2 ofditches 32 compared to ifditches 32 are not formed. The on-current ofFinFET 38 is hence increased without causing the increase in recessing depth D3 (FIG. 8A ). - Furthermore, in accordance with some embodiments, as shown in
FIG. 9 ,fin 30 has a heterogeneous structure, with thelower portion 30A having a greater bandgap than theupper portion 30B. Thechannel 44 of FinFET includeslower channel portions 44A andupper channel portions 44B. Thelower channel portions 44A form a first sub-FinFET withgate dielectric 40 andgate electrode 42, wherein the first sub-FinFET has a first threshold voltage Vt1. Theupper channel portions 44B form a second sub-FinFET withgate dielectric 40 andgate electrode 42, wherein the second sub-FinFET has a second threshold voltage Vt2. Threshold voltage Vt2 is lower than threshold voltage Vt1 in some embodiments. The advantageous feature of the correspondingFinFET 38 is illustrated inFIG. 10 . - In
FIG. 10 , the current I flowing between the source and drain region of FinFET 38 (FIG. 9 ) is illustrated as a function of the gate voltage (Vg) applied on gate electrode 42 (FIG. 9 ). Lines 50 and 52 are I-V curves of the first sub-FinFET (havingchannel portions 44A) and the second sub-FinFET (havingchannel portions 44B), respectively, and line 54 is the I-V curve ofFinFET 38. It is observed that the off-state current IOff (corresponding to low gate voltages Vg) ofFinFET 38 is the sum of the leakage currents of the first and the second sub-FinFETs, and is mainly determined by the leakage current (line 52) of the second sub-FinFET due to its lower threshold voltage Vt1. Since the off-state current of the second sub-transistor is very low, the leakage current ofFinFET 38 is low. On the other hand, the on-current ofFinFET 38 is the sum of, and is affected by, both the on-currents of the first and the second sub-FinFETs. The on-current ofFinFET 38 is hence high. As shown inFIG. 10 , when gate voltage Vg reaches a certain level, there is a noticeable current jump. Hence,FinFET 38 has a high on-current and a low leakage current. -
FIG. 11 illustratesFinFET 38 in accordance with alternative embodiments. In these embodiments,semiconductor fin 30 has a homogenous structure comprising, for example, silicon geranium or substantially germanium. In the embodiments wherein pure or substantially pure germanium is used to formsemiconductor fin 30,epitaxy semiconductor region 26 has a bottom lower than the bottoms ofditches 32, so that the defects in the re-grownepitaxy semiconductor region 26 are limited to the portions lower than the channel region ofFinFET 38. - In the embodiments of the present disclosure, by forming ditches in STI regions, the heights of semiconductor fins are increased, resulting in an increase in the on-currents of the FinFETs. The recessing distance of STI regions, however, does not need to be increased. Hence, the increase in the on-current is obtained without the cost of process difficulty. In addition, the formation of the ditches does not require additional etching process and additional lithography masks. Hence, the manufacturing cost of the embodiments of the present disclosure is low.
- In accordance with some embodiments, a device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor strip is between and contacting the isolation regions. A semiconductor fin overlaps, and is joined to, the semiconductor strip. A ditch extends from a top surface of the isolation regions into the isolation regions, wherein the ditch adjoins the semiconductor fin.
- In accordance with other embodiments, a device includes a silicon substrate, STI regions extending into the silicon substrate, and a semiconductor fin between the STI regions. The semiconductor fin is higher than neighboring portions of the STI regions. The STI regions comprise a top surface, which further includes a first portion being substantially flat, and a second portion connecting a bottom of the fin to the first portion of the top surface. The second portion of the top surface is lower than the first portion of the top surface.
- In accordance with yet other embodiments, a method includes recessing a portion of a semiconductor substrate between isolation regions to form a recess in the semiconductor substrate. An epitaxy is performed to grow a semiconductor region in the recess. The isolation regions are recessed, wherein a top portion of the semiconductor region over the isolation regions forms a semiconductor fin. A ditch is formed simultaneously when the step of recessing the isolation regions is performed, with the ditch being in the isolation regions and adjoining the semiconductor fin.
- Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
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