US20140145765A1 - Voltage ramp-up protection - Google Patents
Voltage ramp-up protection Download PDFInfo
- Publication number
- US20140145765A1 US20140145765A1 US13/686,889 US201213686889A US2014145765A1 US 20140145765 A1 US20140145765 A1 US 20140145765A1 US 201213686889 A US201213686889 A US 201213686889A US 2014145765 A1 US2014145765 A1 US 2014145765A1
- Authority
- US
- United States
- Prior art keywords
- voltage
- node
- circuit
- amplifier
- receive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims abstract description 27
- 230000004044 response Effects 0.000 claims abstract description 11
- 230000001052 transient effect Effects 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 abstract description 5
- 230000003044 adaptive effect Effects 0.000 description 28
- 238000010586 diagram Methods 0.000 description 6
- 230000015654 memory Effects 0.000 description 4
- LAHWLEDBADHJGA-UHFFFAOYSA-N 1,2,4-trichloro-5-(2,5-dichlorophenyl)benzene Chemical compound ClC1=CC=C(Cl)C(C=2C(=CC(Cl)=C(Cl)C=2)Cl)=C1 LAHWLEDBADHJGA-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 229920005994 diacetyl cellulose Polymers 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 230000001225 therapeutic effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/613—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in parallel with the load as final control devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L5/00—Automatic control of voltage, current, or power
- H03L5/02—Automatic control of voltage, current, or power of power
Definitions
- This disclosure relates generally to electronic devices, and more specifically, to systems and methods for voltage ramp-up protection.
- CMOS Complementary Metal-Oxide Semiconductor
- ICs integrated circuits
- CMOS Complementary Metal-Oxide Semiconductor
- Examples of modern ICs include microprocessors, microcontrollers, memories, etc.
- CMOS Complementary Metal-Oxide Semiconductor
- one or more components within an IC may operate based upon a “voltage reference.”
- a “voltage reference circuit” may be designed within the IC.
- a bandgap circuit is configured to output a temperature independent voltage reference with a value of approximately 1.25 V, or another value suitably close to the theoretical 1.22 eV bandgap of silicon at 0 K—that is, the energy required to promote an electron from its valence band to its conduction band to become a mobile charge.
- a typical bandgap circuit may include a set of Self-Cascode MOS Field-Effect Transistor (SCM) structures and one or more bipolar transistor(s) operating in an open loop configuration.
- SCM Self-Cascode MOS Field-Effect Transistor
- FIG. 1 is a diagram of an example of an electronic device including one or more integrated circuits according to some embodiments.
- FIG. 2 is a block diagram of an example of an integrated circuit according to some embodiments.
- FIG. 3 is a circuit diagram of an example of circuitry configured to provide voltage ramp-up protection according to some embodiments.
- FIG. 4 is a graph illustrating an example of a ramp-up protection operation according to some embodiments.
- FIG. 5 is a flowchart of an example of a method for voltage ramp-up protection according to some embodiments.
- Embodiments disclosed herein are directed to systems and methods for voltage ramp-up protection.
- these systems and methods may be incorporated into a wide range of electronic devices including, for example, computer systems or Information Technology (IT) products (e.g., servers, desktops, laptops, switches, routers, etc.), telecommunications hardware, consumer devices or appliances (e.g., mobile phones, tablets, televisions, cameras, sound systems, etc.), scientific instrumentation, industrial robotics, medical or laboratory electronics (e.g., imaging, diagnostic, or therapeutic equipment, etc.), transportation vehicles (e.g., automobiles, buses, trains, watercraft, aircraft, etc.), military equipment, etc. More generally, the systems and methods discussed herein may be incorporated into any device or system having one or more electronic parts or components.
- IT Information Technology
- electronic device 100 may be any of the aforementioned electronic devices, or any other electronic device.
- electronic device 100 includes one or more Printed Circuit Boards (PCBs) 101 , and at least one of PCBs 101 includes one or more electronic chip(s) or integrated circuit(s) 102 .
- PCBs 101 includes one or more electronic chip(s) or integrated circuit(s) 102 .
- integrated circuit(s) 102 may implement one or more of the systems and methods described in more detail below.
- Examples of integrated circuit(s) 102 may include, for instance, a System-On-Chip (SoC), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), a processor, a microprocessor, a controller, a microcontroller (MCU), or the like.
- SoC System-On-Chip
- ASIC Application Specific Integrated Circuit
- DSP Digital Signal Processor
- FPGA Field-Programmable Gate Array
- processor a microprocessor
- controller a microcontroller
- integrated circuit(s) 102 may include a memory circuit or device such as, for example, a Random Access Memory (RAM), a Static RAM (SRAM), a Magnetoresistive RAM (MRAM), a Nonvolatile RAM (NVRAM, such as “FLASH” memory, etc.), and/or a Dynamic RAM (DRAM) such as Synchronous DRAM (SDRAM), a Double Data Rate (e.g., DDR, DDR2, DDR3, etc.) RAM, an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), etc.
- RAM Random Access Memory
- SRAM Static RAM
- MRAM Magnetoresistive RAM
- NVRAM Nonvolatile RAM
- DRAM Dynamic RAM
- SDRAM Synchronous DRAM
- EPROM Erasable Programmable ROM
- EEPROM Electrically Erasable Programmable ROM
- integrated circuit(s) 102 may include one or more mixed- signal or analog circuits, such as, for example, Analog-to-Digital Converter (ADCs), Digital-to-Analog Converter (DACs), Phased Locked Loop (PLLs), oscillators, filters, amplifiers, transformers, etc. Additionally or alternatively, integrated circuit(s) 102 may include one or more Micro-ElectroMechanical Systems (MEMS), Nano-ElectroMechanical Systems (NEMS), or the like.
- ADCs Analog-to-Digital Converter
- DACs Digital-to-Analog Converter
- PLLs Phased Locked Loop
- integrated circuit(s) 102 may include one or more Micro-ElectroMechanical Systems (MEMS), Nano-ElectroMechanical Systems (NEMS), or the like.
- MEMS Micro-ElectroMechanical Systems
- NEMS Nano-ElectroMechanical Systems
- integrated circuit(s) 102 may include a number of different portions, areas, or regions. These various portions may include one or more processing cores, cache memories, internal bus(es), timing units, controllers, analog sections, mechanical elements, etc.
- integrated circuit(s) 102 may include a circuit configured to receive two or more supply voltages (e.g., two, three, four, etc.).
- a dual-supply circuit may receive an analog supply voltage configured to power an analog component as well as a digital supply voltage configured to power a logic or digital component.
- the analog supply voltage may be of the order of 5 V ⁇ 10%, for example, whereas the digital supply voltage may be of the order of 1.2 V ⁇ 10%.
- Other types of circuits may receive any suitable number of supply voltages.
- integrated circuit(s) 102 may be disposed within an electronic component package configured to be mounted onto PCB 101 using any suitable packaging technology such as, for example, Ball Grid Array (BGA) packaging or the like.
- PCB 101 may be mechanically mounted within or fastened onto electronic device 100 .
- PCB 101 may take a variety of forms and/or may include a plurality of other elements or components in addition to integrated circuit(s) 102 .
- FIG. 2 is a block diagram of integrated circuit 200 that illustrates an example of integrated circuit(s) 102 discussed in FIG. 1 according to some embodiments.
- integrated circuit 200 includes high-voltage (HV) circuitry 202 configured to receive high-voltage supply voltage (V hv ) 201 .
- HV circuitry 202 is operably coupled to first low-voltage (LV1) circuitry 204 , and it is configured to provide output voltage (V out ) 203 thereto.
- HV circuitry 202 is also operably coupled to adaptive clamping circuitry 207 , and it is configured to provide Operational Transconductance Amplifier (OTA) voltage output (V ola ) thereto.
- HV circuitry 202 may include second low-voltage (LV2) circuitry 205 .
- Adaptive clamping circuitry 207 is configured to receive V hv 201 , and it is operably coupled to V out 203 's node (shown in more detail in FIG. 3 below). In addition, adaptive clamping circuitry 207 is also configured to receive enabling signal (en) 208 and reference voltage (V ref ) 209 .
- HV circuitry 202 may be a bandgap reference circuit and LV1 circuitry 204 may be any other analog or digital circuit that operates based upon a lower voltage (e.g., a bandgap voltage) provided by HV circuitry 202 (i.e., V out 203 ).
- V hv 201 may be an analog supply voltage provided to IC 200 by an external source (not shown) and it may be of the order of 5 V ⁇ 10%, for example, whereas V ref 209 may be a digital supply voltage provided to IC 200 by another external source (not shown), and it may be of the order of 1.2 V ⁇ 10%.
- LV1 circuitry 204 may receive HV circuitry 202 's internally generated supply voltage V out 203 , which may be of the order of 0.9 V ⁇ 10%.
- V hv 201 , V out 203 , and V ref 209 may vary depending upon the type of technology, application, etc.
- adaptive clamping circuitry 207 may be configured to operate in response to the application of en signal 208 .
- en signal 208 may be provided in connection with a “Power-on-Reset” (PoR) event.
- PoR event may include one or more actions performed by or upon IC 200 in response to the turning on of power to the electronic device or part(s) thereof, or other command that creates a reset signal configured to place IC 200 in a known state.
- en signal 208 may cease to be provided to adaptive clamping circuitry 207 a predetermined amount of time after the PoR event (e.g., ⁇ 10 or ⁇ 20 ⁇ s).
- adaptive clamping circuitry 207 may be configured to receive V ota 206 , compare V out 203 with V ref 209 , and modify V out 203 in a manner proportional to the difference between V out 203 and V ref 209 .
- adaptive clamping circuitry 207 may protect LV1 circuitry 204 and/or LV2 circuitry 205 from inadvertent exposure to a high voltage supply. Such exposure may be caused, for example, due to a fast slew rate of V hv 201 during power-up of IC 200 .
- the rate of change of V hv 201 may be faster than the propagation delay of LV2 circuitry 205 , thus creating a “sneak path” or “sneak condition” between V hv 201 's node and V out 203 's node which, in the absence of adaptive clamping circuitry 207 , would allow an excess or undesired current to flow from V hv 201 's node and V out 203 's node.
- adaptive clamping circuitry 207 may monitor V hv 201 's node and/or V out 203 's node. Then, in response to V hv 201 's slew rate creating a sneak condition between V hv 201 's node and/or V out 203 's node, adaptive clamping circuitry 207 may operate to counteract the sneak condition.
- the modules or blocks shown in FIG. 2 may represent processing circuitry, logic functions, other circuitry and/or data structures configured to perform perform specified operations. Although these modules are shown as distinct blocks, in other embodiments at least some of the operations performed by these modules may be combined in to fewer blocks. For example, in some cases, adaptive clamping circuitry 207 may be integrated into HV circuitry 202 . Conversely, any given one of modules 202 , 204 , 205 , and/or 207 may be implemented such that its operations are divided among two or more logical blocks. Although shown with a particular configuration, in other embodiments these various modules or blocks may be rearranged in other suitable ways.
- FIG. 3 is a circuit diagram of an example of circuitry 300 configured to provide voltage ramp-up protection according to some embodiments.
- HV circuitry 202 is a bandgap reference circuit that includes LV2 circuitry 205 having OTA 301 .
- the output of OTA 301 produces V ota 206 , which is operably coupled to the gates of P-type Metal-Oxide Semiconductor (PMOS) transistors 303 - 306 .
- PMOS transistors 303 - 306 have their sources operably coupled to V hv 201 .
- PMOS P-type Metal-Oxide Semiconductor
- the drain of PMOS transistor 303 is operably coupled to resistor 307 , which is operably coupled to the emitter of PNP Bipolar Junction Transistor (BJT) 308 , the base and collector of which are operably coupled to ground (Gnd).
- the drain of PMOS transistor 303 is also operably coupled to a first input of OTA 301 .
- the drain of PMOS transistor 304 is operably coupled to the emitter of of BJT 309 , the base and collector of which are coupled to Gnd.
- the drain of PMOS transistor 304 is also operably coupled to a second input of OTA 205 .
- the drain of PMOS transistor 305 is operably coupled to resistor 311 at V out 203 's node, and V out 203 's node is operably coupled to the emitter of BJT 312 , the base and collector of which are operably coupled to Gnd.
- the drain of PMOS transistor 306 is operably coupled to resistor 310 , which in turn is operably coupled to Gnd.
- Another resistor 313 is operably coupled between the node of V out 203 and Gnd.
- HV circuitry 202 receives V hv 201 and produces bandgap voltage V out 203 .
- OTA 301 may include one or more low-power elements, and in some cases its signal propagation delay may be incommensurate with the slew rate of V hv 201 . In other words, after a certain threshold, the feedback path provided by OTA 301 may not be able to keep up with the rate of change of V hv 201 . Accordingly, an undesired or excess electrical current may transiently flow through a “sneak path” within HV circuitry 202 in the direction from V hv 201 to V out 203 (e.g., through PMOS transistor 305 ). Such “sneak condition” may increase the value of V out 203 and negatively affect the operation of LV1 circuitry 204 and/or LV2 circuitry 205 .
- Adaptive clamping circuitry 207 may operate to counteract the sneak condition.
- adaptive clamping circuitry 207 includes PMOS transistor 314 having its source operably coupled to V hv 201 , its gate operably coupled to the gate of PMOS transistors 303 - 306 , and its drain biasing amplifier 315 .
- Amplifier 315 may receive V ref 209 at its inverting input and V out 203 at its non-inverting input.
- the output of amplifier 315 is operably coupled to the gates of N-type MOS (NMOS) transistors 316 and 317 .
- the source of NMOS transistor 316 is operably coupled to the drain of PMOS transistor 306 , and the drain of NMOS transistor 316 is operably coupled to Gnd.
- the source of NMOS transistor 317 is operably coupled to V out 203 's node, and the drain of NMOS transistor 317 is operably coupled to Gnd.
- the channel length of NMOS transistor 316 may be the same as that of PMOS transistors 306 , 305 , 304 , and/or 303 . Therefore, the electrical current received at the source of NMOS transistor 316 may be a tail current proportional to the transient current circulating within HV circuitry 202 .
- amplifier 315 is configured to receive a biasing current proportional to the excess, transient current flowing through HV circuitry 202 due to the slew rate of V hv 201 .
- adaptive clamping circuitry 207 effectively detects the supply slewing of V hv 201 .
- the output of amplifier 315 is configured to reduce a value of V out 203 in a manner proportional to a difference between V out 203 and V ref 209 , thus counteracting the sneak condition within HV circuitry 202 .
- an enabling NMOS transistor or switch (not shown) may be operably coupled between the drain of PMOS transistor 314 and amplifier 315 .
- the gate of the enabling transistor may be configured to receive en signal 208 shown in FIG. 2 , which may be a PoR signal or the like.
- adaptive clamping circuitry 207 may ameliorate LV1 circuitry 204 's vulnerability to voltage ramping in V hv 201 during power-up or the like, but may be turned off otherwise thus preserving energy.
- FIG. 4 shows graph 400 illustrating an example of a ramp-up protection operation according to some embodiments.
- V hv 201 goes from 0 V to 3.75 V in a given period of time (e.g., at a rate of 1000 V/ms).
- V old 401 The absence of adaptive clamping circuitry 207 is illustrated by V old 401 , which peaks well beyond 1.5 V and then settles at the desired V out .
- the desired V out value is 0.9 V (e.g., a bandgap reference voltage) to be provided to LV1 circuitry 204 .
- adaptive clamping circuitry 207 In contrast, when using adaptive clamping circuitry 207 , V out 203 is clamped at 1.5 V before settling at a V out of 0.9 V. Therefore, adaptive clamping circuitry 207 effectively protects LV1 circuitry 204 from receiving voltages greater than 1.5 V.
- FIG. 5 is a flowchart of an example of method 500 for voltage ramp-up protection.
- method 500 may be performed, at least in part, by adaptive clamping circuitry 207 shown in FIGS. 2 and 3 .
- method 500 may include monitoring one or more nodes within a high voltage circuit.
- adaptive clamping circuitry 207 may monitor V hv 201 and/or V out 203 of HV circuitry 202 .
- method 500 may include detecting a sneak condition.
- adaptive clamping circuitry 207 may detect, via PMOS transistor 314 , that an excess electrical current is flowing through a sneak path within HV circuitry 202 . Then, at block 503 , method 500 may include counteracting the sneak condition. For example, adaptive clamping circuitry 207 may compare V ref 209 against V out 203 and it may subtract from V out 203 a voltage proportional to the difference between the two, thus maintaining V out 203 under a selected threshold value.
- V ref 209 may be a low voltage supply voltage (e.g., of the order of 1.2 V ⁇ 10%) to IC 200 .
- adaptive clamping circuitry 207 may ameliorate LV1 circuitry 204 's vulnerability to voltage ramp-ups in V hv 201 .
- adaptive clamping circuitry 207 may provide the ability to ramp up HV supplies (e.g., V hs 201 ) at high slew rates without exposing LV devices (e.g., LV1 circuitry 204 ) to voltages beyond their reliability range.
- adaptive clamping circuitry 207 may be able to counteract sneak paths resulting from V hv 201 's slew rates of up to 100 V/ms. Additionally or alternatively, adaptive clamping circuitry 207 may be able to counteract sneak paths resulting from V hs 201 's slew rates of up to 1000 V/ms.
- the embodiment shown in FIG. 3 may leverage a mirror current to accelerate the act of clamping V out 203 . In other words, the same mechanism that creates the sneak condition—that is, the excess electrical current—may be used to facilitate detection and clamping.
- IC 200 When IC 200 is a dual-supply circuit, for example (or when it is configured to receive more than two supply voltages), it may receive a digital or logical supply voltage from an external circuit that may be used as V ref 209 ; and which may be used to clamp V out 203 without IC 200 having to generate an additional reference voltage for that purpose.
- V ref 209 an external circuit that may be used as V ref 209 ; and which may be used to clamp V out 203 without IC 200 having to generate an additional reference voltage for that purpose.
- power supply sequencing it should be noted that the systems and methods described above are designed to operate regardless of which power supply (between an analog and digital power supply to IC 200 ) is turned on first.
- V hv 201 is at 5 V while V ref is at 0 V
- V out 203 is clamped to ground, thus protecting LV1 circuitry 204 .
- the digital or logic supply to IC 200 is turned on before the analog supply, there is no sneak path from V hv 201 to V out 203 .
- adaptive clamping circuitry 207 has a compact footprint and does not compromise the output level of V out 203 .
- conventional capacitively coupled solutions e.g., slew rate rail detectors, etc.
- an integrated may include, a voltage clamping circuit operably coupled to a first node and to a second node, the first node configured to receive a first voltage and the second node configured to output a second voltage smaller than the first voltage, the voltage clamping circuit configured to modify the second voltage in response to a slew rate of the first voltage triggering a sneak condition between the first and second nodes.
- the sneak condition may include an electrical path tending to allow an unintended current to flow from the first node to the second node.
- the first node and the second nodes may be part of a voltage reference circuit.
- the voltage reference circuit may be a bandgap circuit.
- the voltage reference circuit may include at least one element having a propagation delay incommensurate with the slew rate of the first voltage.
- the at least one element may include a first amplifier.
- the voltage clamping circuit may include a second amplifier configured to receive a biasing current proportional to an excess current to flow from the first node to the second node.
- the second amplifier may be configured to reduce a value of the second voltage at the second node in a manner proportional to a difference between the second voltage and a digital power supply voltage provided to the integrated circuit.
- the voltage clamping circuit may be configured to be turned on in response to a Power-on-Reset (PoR) event. Additionally or alternatively, the voltage clamping circuit may be configured to be turned off a predetermined period of time after the PoR event.
- PoR Power-on-Reset
- a method may include monitoring at least one of a first node or a second node of a circuit, the first node configured to receive a first voltage greater than a second voltage present at a second node, the circuit configured to receive at least one analog supply voltage and at least one digital supply voltage.
- the method may also include, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition using the at least one digital supply voltage as a reference voltage.
- sneak condition may favor an excess current's flow from the first node to the second node and, in some situations, the first voltage may be the at least one analog supply voltage.
- a circuit element operably coupled between the first node and the second node may have a propagation delay longer than a ramp-up time of the first voltage.
- counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value defined based upon the reference voltage. Additionally or alternatively, maintaining the second voltage below at or below a predetermined value may include modifying the second voltage in a manner proportional to a difference between the second voltage and the reference voltage.
- the method may include providing a second amplifier configured to receive a biasing current proportional to a transient current to flow from the first node to the second node.
- the first circuit is a bandgap voltage circuit.
- the method may also include protecting a circuit from an overvoltage condition, the circuit operably coupled to the second node and configured to receive the second voltage.
- the monitoring and the counteracting may occur in response to a Power-on-Reset (PoR) event. Additionally or alternatively, the monitoring and the counteracting may cease to occur a predetermined period of time after the PoR event.
- PoR Power-on-Reset
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Control Of Electrical Variables (AREA)
- Amplifiers (AREA)
Abstract
Description
- This disclosure relates generally to electronic devices, and more specifically, to systems and methods for voltage ramp-up protection.
- Complementary Metal-Oxide Semiconductor (CMOS) technology is commonly used to manufacture integrated circuits (ICs). Examples of modern ICs include microprocessors, microcontrollers, memories, etc. Generally speaking, one or more components within an IC may operate based upon a “voltage reference.” To provide such a voltage reference, a “voltage reference circuit” may be designed within the IC.
- An example of a voltage reference circuit is the “bandgap circuit.” A bandgap circuit is configured to output a temperature independent voltage reference with a value of approximately 1.25 V, or another value suitably close to the theoretical 1.22 eV bandgap of silicon at 0 K—that is, the energy required to promote an electron from its valence band to its conduction band to become a mobile charge. For example, a typical bandgap circuit may include a set of Self-Cascode MOS Field-Effect Transistor (SCM) structures and one or more bipolar transistor(s) operating in an open loop configuration.
- The present invention(s) is/are illustrated by way of example and is/are not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
-
FIG. 1 is a diagram of an example of an electronic device including one or more integrated circuits according to some embodiments. -
FIG. 2 is a block diagram of an example of an integrated circuit according to some embodiments. -
FIG. 3 is a circuit diagram of an example of circuitry configured to provide voltage ramp-up protection according to some embodiments. -
FIG. 4 is a graph illustrating an example of a ramp-up protection operation according to some embodiments. -
FIG. 5 is a flowchart of an example of a method for voltage ramp-up protection according to some embodiments. - Embodiments disclosed herein are directed to systems and methods for voltage ramp-up protection. In many implementations, these systems and methods may be incorporated into a wide range of electronic devices including, for example, computer systems or Information Technology (IT) products (e.g., servers, desktops, laptops, switches, routers, etc.), telecommunications hardware, consumer devices or appliances (e.g., mobile phones, tablets, televisions, cameras, sound systems, etc.), scientific instrumentation, industrial robotics, medical or laboratory electronics (e.g., imaging, diagnostic, or therapeutic equipment, etc.), transportation vehicles (e.g., automobiles, buses, trains, watercraft, aircraft, etc.), military equipment, etc. More generally, the systems and methods discussed herein may be incorporated into any device or system having one or more electronic parts or components.
- Turning to
FIG. 1 , a block diagram ofelectronic device 100 is depicted. In some embodiments,electronic device 100 may be any of the aforementioned electronic devices, or any other electronic device. As illustrated,electronic device 100 includes one or more Printed Circuit Boards (PCBs) 101, and at least one ofPCBs 101 includes one or more electronic chip(s) or integrated circuit(s) 102. In some implementations, integrated circuit(s) 102 may implement one or more of the systems and methods described in more detail below. - Examples of integrated circuit(s) 102 may include, for instance, a System-On-Chip (SoC), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), a processor, a microprocessor, a controller, a microcontroller (MCU), or the like. Additionally or alternatively, integrated circuit(s) 102 may include a memory circuit or device such as, for example, a Random Access Memory (RAM), a Static RAM (SRAM), a Magnetoresistive RAM (MRAM), a Nonvolatile RAM (NVRAM, such as “FLASH” memory, etc.), and/or a Dynamic RAM (DRAM) such as Synchronous DRAM (SDRAM), a Double Data Rate (e.g., DDR, DDR2, DDR3, etc.) RAM, an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), etc.
- Additionally or alternatively, integrated circuit(s) 102 may include one or more mixed- signal or analog circuits, such as, for example, Analog-to-Digital Converter (ADCs), Digital-to-Analog Converter (DACs), Phased Locked Loop (PLLs), oscillators, filters, amplifiers, transformers, etc. Additionally or alternatively, integrated circuit(s) 102 may include one or more Micro-ElectroMechanical Systems (MEMS), Nano-ElectroMechanical Systems (NEMS), or the like.
- As such, integrated circuit(s) 102 may include a number of different portions, areas, or regions. These various portions may include one or more processing cores, cache memories, internal bus(es), timing units, controllers, analog sections, mechanical elements, etc. Thus, in various embodiments, integrated circuit(s) 102 may include a circuit configured to receive two or more supply voltages (e.g., two, three, four, etc.). For example, a dual-supply circuit may receive an analog supply voltage configured to power an analog component as well as a digital supply voltage configured to power a logic or digital component. In some implementations, the analog supply voltage may be of the order of 5 V±10%, for example, whereas the digital supply voltage may be of the order of 1.2 V±10%. Other types of circuits may receive any suitable number of supply voltages.
- Generally speaking, integrated circuit(s) 102 may be disposed within an electronic component package configured to be mounted onto PCB 101 using any suitable packaging technology such as, for example, Ball Grid Array (BGA) packaging or the like. In some applications, PCB 101 may be mechanically mounted within or fastened onto
electronic device 100. It should be noted that, in certain implementations, PCB 101 may take a variety of forms and/or may include a plurality of other elements or components in addition to integrated circuit(s) 102. -
FIG. 2 is a block diagram ofintegrated circuit 200 that illustrates an example of integrated circuit(s) 102 discussed inFIG. 1 according to some embodiments. As shown,integrated circuit 200 includes high-voltage (HV)circuitry 202 configured to receive high-voltage supply voltage (Vhv) 201.HV circuitry 202 is operably coupled to first low-voltage (LV1)circuitry 204, and it is configured to provide output voltage (Vout) 203 thereto.HV circuitry 202 is also operably coupled toadaptive clamping circuitry 207, and it is configured to provide Operational Transconductance Amplifier (OTA) voltage output (Vola) thereto. In this example,HV circuitry 202 may include second low-voltage (LV2)circuitry 205. -
Adaptive clamping circuitry 207 is configured to receiveV hv 201, and it is operably coupled toV out 203's node (shown in more detail inFIG. 3 below). In addition,adaptive clamping circuitry 207 is also configured to receive enabling signal (en) 208 and reference voltage (Vref) 209. - The terms “high-voltage” and “low-voltage” are generally used to indicate that a particular circuit operates with a supply voltage higher than that of another circuit. In general, an HV circuit may have thicker oxide devices than an LV circuit and/or it may use more power than the low-voltage circuit. For example,
HV circuitry 202 may be a bandgap reference circuit andLV1 circuitry 204 may be any other analog or digital circuit that operates based upon a lower voltage (e.g., a bandgap voltage) provided by HV circuitry 202 (i.e., Vout 203). - In some implementations,
V hv 201 may be an analog supply voltage provided toIC 200 by an external source (not shown) and it may be of the order of 5 V±10%, for example, whereasV ref 209 may be a digital supply voltage provided toIC 200 by another external source (not shown), and it may be of the order of 1.2 V±10%. Meanwhile,LV1 circuitry 204 may receiveHV circuitry 202's internally generatedsupply voltage V out 203, which may be of the order of 0.9 V±10%. It should be understood in light of the present disclosure, however, that the exact voltages supplied toHV circuitry 202,adaptive clamping circuitry 207, and LV1 circuitry 204 (i.e.,V hv 201,V out 203, and Vref 209) may vary depending upon the type of technology, application, etc. - In some implementations,
adaptive clamping circuitry 207 may be configured to operate in response to the application ofen signal 208. For example, in some situations, ensignal 208 may be provided in connection with a “Power-on-Reset” (PoR) event. A PoR event may include one or more actions performed by or upon IC 200 in response to the turning on of power to the electronic device or part(s) thereof, or other command that creates a reset signal configured to place IC 200 in a known state. Additionally or alternatively, ensignal 208 may cease to be provided to adaptive clamping circuitry 207 a predetermined amount of time after the PoR event (e.g., ˜10 or ˜20 μs). - In operation,
adaptive clamping circuitry 207 may be configured to receiveV ota 206, compareV out 203 withV ref 209, and modifyV out 203 in a manner proportional to the difference betweenV out 203 andV ref 209. As such,adaptive clamping circuitry 207 may protectLV1 circuitry 204 and/orLV2 circuitry 205 from inadvertent exposure to a high voltage supply. Such exposure may be caused, for example, due to a fast slew rate ofV hv 201 during power-up ofIC 200. Specifically, in some cases, the rate of change ofV hv 201 may be faster than the propagation delay ofLV2 circuitry 205, thus creating a “sneak path” or “sneak condition” betweenV hv 201's node andV out 203's node which, in the absence ofadaptive clamping circuitry 207, would allow an excess or undesired current to flow fromV hv 201's node andV out 203's node. - Accordingly, in some embodiments,
adaptive clamping circuitry 207 may monitorV hv 201's node and/orV out 203's node. Then, in response toV hv 201's slew rate creating a sneak condition betweenV hv 201's node and/orV out 203's node,adaptive clamping circuitry 207 may operate to counteract the sneak condition. - In some embodiments, the modules or blocks shown in
FIG. 2 may represent processing circuitry, logic functions, other circuitry and/or data structures configured to perform perform specified operations. Although these modules are shown as distinct blocks, in other embodiments at least some of the operations performed by these modules may be combined in to fewer blocks. For example, in some cases,adaptive clamping circuitry 207 may be integrated intoHV circuitry 202. Conversely, any given one ofmodules -
FIG. 3 is a circuit diagram of an example ofcircuitry 300 configured to provide voltage ramp-up protection according to some embodiments. In this particular example,HV circuitry 202 is a bandgap reference circuit that includesLV2 circuitry 205 havingOTA 301. The output ofOTA 301 producesV ota 206, which is operably coupled to the gates of P-type Metal-Oxide Semiconductor (PMOS) transistors 303-306. PMOS transistors 303-306 have their sources operably coupled toV hv 201. The drain ofPMOS transistor 303 is operably coupled toresistor 307, which is operably coupled to the emitter of PNP Bipolar Junction Transistor (BJT) 308, the base and collector of which are operably coupled to ground (Gnd). The drain ofPMOS transistor 303 is also operably coupled to a first input ofOTA 301. - The drain of
PMOS transistor 304 is operably coupled to the emitter of ofBJT 309, the base and collector of which are coupled to Gnd. The drain ofPMOS transistor 304 is also operably coupled to a second input ofOTA 205. The drain ofPMOS transistor 305 is operably coupled toresistor 311 atV out 203's node, andV out 203's node is operably coupled to the emitter ofBJT 312, the base and collector of which are operably coupled to Gnd. The drain ofPMOS transistor 306 is operably coupled toresistor 310, which in turn is operably coupled to Gnd. Anotherresistor 313 is operably coupled between the node ofV out 203 and Gnd. - In operation,
HV circuitry 202 receivesV hv 201 and producesbandgap voltage V out 203.OTA 301 may include one or more low-power elements, and in some cases its signal propagation delay may be incommensurate with the slew rate ofV hv 201. In other words, after a certain threshold, the feedback path provided byOTA 301 may not be able to keep up with the rate of change ofV hv 201. Accordingly, an undesired or excess electrical current may transiently flow through a “sneak path” withinHV circuitry 202 in the direction fromV hv 201 to Vout 203 (e.g., through PMOS transistor 305). Such “sneak condition” may increase the value ofV out 203 and negatively affect the operation ofLV1 circuitry 204 and/orLV2 circuitry 205. -
Adaptive clamping circuitry 207 may operate to counteract the sneak condition. Particularly, in this example,adaptive clamping circuitry 207 includesPMOS transistor 314 having its source operably coupled toV hv 201, its gate operably coupled to the gate of PMOS transistors 303-306, and itsdrain biasing amplifier 315.Amplifier 315 may receiveV ref 209 at its inverting input andV out 203 at its non-inverting input. The output ofamplifier 315 is operably coupled to the gates of N-type MOS (NMOS)transistors NMOS transistor 316 is operably coupled to the drain ofPMOS transistor 306, and the drain ofNMOS transistor 316 is operably coupled to Gnd. The source ofNMOS transistor 317 is operably coupled toV out 203's node, and the drain ofNMOS transistor 317 is operably coupled to Gnd. - In some implementations, the channel length of
NMOS transistor 316 may be the same as that ofPMOS transistors NMOS transistor 316 may be a tail current proportional to the transient current circulating withinHV circuitry 202. In other words,amplifier 315 is configured to receive a biasing current proportional to the excess, transient current flowing throughHV circuitry 202 due to the slew rate ofV hv 201. As such,adaptive clamping circuitry 207 effectively detects the supply slewing ofV hv 201. - The output of
amplifier 315 is configured to reduce a value ofV out 203 in a manner proportional to a difference betweenV out 203 andV ref 209, thus counteracting the sneak condition withinHV circuitry 202. In some cases, an enabling NMOS transistor or switch (not shown) may be operably coupled between the drain ofPMOS transistor 314 andamplifier 315. The gate of the enabling transistor may be configured to receive ensignal 208 shown inFIG. 2 , which may be a PoR signal or the like. Accordingly,adaptive clamping circuitry 207 may ameliorateLV1 circuitry 204's vulnerability to voltage ramping inV hv 201 during power-up or the like, but may be turned off otherwise thus preserving energy. -
FIG. 4 showsgraph 400 illustrating an example of a ramp-up protection operation according to some embodiments. Particularly, a ramp-up scenario forV hv 201 is depicted whereV hv 201 goes from 0 V to 3.75 V in a given period of time (e.g., at a rate of 1000 V/ms). The absence ofadaptive clamping circuitry 207 is illustrated byV old 401, which peaks well beyond 1.5 V and then settles at the desired Vout. In this case, the desired Vout value is 0.9 V (e.g., a bandgap reference voltage) to be provided toLV1 circuitry 204. In contrast, when usingadaptive clamping circuitry 207,V out 203 is clamped at 1.5 V before settling at a Vout of 0.9 V. Therefore,adaptive clamping circuitry 207 effectively protectsLV1 circuitry 204 from receiving voltages greater than 1.5 V. - It should be noted that the voltage values shown in
FIG. 4 are provided for ease of explanation only. In any given application, those voltage values and/or slew rate(s) may change depending upon the particular application or design requirements. -
FIG. 5 is a flowchart of an example ofmethod 500 for voltage ramp-up protection. In some embodiments,method 500 may be performed, at least in part, byadaptive clamping circuitry 207 shown inFIGS. 2 and 3 . As illustrated, atblock 501,method 500 may include monitoring one or more nodes within a high voltage circuit. For example,adaptive clamping circuitry 207 may monitorV hv 201 and/orV out 203 ofHV circuitry 202. - At
block 502,method 500 may include detecting a sneak condition. For instance,adaptive clamping circuitry 207 may detect, viaPMOS transistor 314, that an excess electrical current is flowing through a sneak path withinHV circuitry 202. Then, atblock 503,method 500 may include counteracting the sneak condition. For example,adaptive clamping circuitry 207 may compareV ref 209 againstV out 203 and it may subtract from Vout 203 a voltage proportional to the difference between the two, thus maintainingV out 203 under a selected threshold value. - In some embodiments,
V ref 209 may be a low voltage supply voltage (e.g., of the order of 1.2 V ±10%) toIC 200. - It should be understood that the various operations described herein, particularly in connection with
FIGS. 2-5 , may be implemented in by processing circuitry, electronic hardware, or a combination thereof. The order in which each operation of a given method is performed may be changed, and various elements of the systems illustrated herein may be added, reordered, combined, omitted, modified, etc. It is intended that the invention(s) described herein embrace all such modifications and changes and, accordingly, the above description should be regarded in an illustrative rather than a restrictive sense. - As described above, in some embodiments,
adaptive clamping circuitry 207 may ameliorateLV1 circuitry 204's vulnerability to voltage ramp-ups inV hv 201. For example,adaptive clamping circuitry 207 may provide the ability to ramp up HV supplies (e.g., Vhs 201) at high slew rates without exposing LV devices (e.g., LV1 circuitry 204) to voltages beyond their reliability range. - In some situations,
adaptive clamping circuitry 207 may be able to counteract sneak paths resulting fromV hv 201's slew rates of up to 100 V/ms. Additionally or alternatively,adaptive clamping circuitry 207 may be able to counteract sneak paths resulting fromV hs 201's slew rates of up to 1000 V/ms. For example, the embodiment shown inFIG. 3 may leverage a mirror current to accelerate the act of clampingV out 203. In other words, the same mechanism that creates the sneak condition—that is, the excess electrical current—may be used to facilitate detection and clamping. - When
IC 200 is a dual-supply circuit, for example (or when it is configured to receive more than two supply voltages), it may receive a digital or logical supply voltage from an external circuit that may be used asV ref 209; and which may be used to clampV out 203 withoutIC 200 having to generate an additional reference voltage for that purpose. Moreover, with respect to power supply sequencing, it should be noted that the systems and methods described above are designed to operate regardless of which power supply (between an analog and digital power supply to IC 200) is turned on first. For example, if the analog supply toIC 200 is turned on before the digital or logic supply (e.g.,V hv 201 is at 5 V while Vref is at 0 V), thenV out 203 is clamped to ground, thus protectingLV1 circuitry 204. Conversely, if the digital or logic supply toIC 200 is turned on before the analog supply, there is no sneak path fromV hv 201 toV out 203. - Furthermore,
adaptive clamping circuitry 207 has a compact footprint and does not compromise the output level ofV out 203. In contrast, conventional capacitively coupled solutions (e.g., slew rate rail detectors, etc.) have a large footprint and/or have long latch time out values, which may compromiseIC 200's start up timing. - In an illustrative, non-limiting embodiment, an integrated may include, a voltage clamping circuit operably coupled to a first node and to a second node, the first node configured to receive a first voltage and the second node configured to output a second voltage smaller than the first voltage, the voltage clamping circuit configured to modify the second voltage in response to a slew rate of the first voltage triggering a sneak condition between the first and second nodes. For example, the sneak condition may include an electrical path tending to allow an unintended current to flow from the first node to the second node.
- Also, the first node and the second nodes may be part of a voltage reference circuit. For instance, the voltage reference circuit may be a bandgap circuit. The voltage reference circuit may include at least one element having a propagation delay incommensurate with the slew rate of the first voltage. For example, the at least one element may include a first amplifier. In that case, the voltage clamping circuit may include a second amplifier configured to receive a biasing current proportional to an excess current to flow from the first node to the second node. The second amplifier may be configured to reduce a value of the second voltage at the second node in a manner proportional to a difference between the second voltage and a digital power supply voltage provided to the integrated circuit.
- In some implementations, the voltage clamping circuit may be configured to be turned on in response to a Power-on-Reset (PoR) event. Additionally or alternatively, the voltage clamping circuit may be configured to be turned off a predetermined period of time after the PoR event.
- In another illustrative, non-limiting embodiment, a method may include monitoring at least one of a first node or a second node of a circuit, the first node configured to receive a first voltage greater than a second voltage present at a second node, the circuit configured to receive at least one analog supply voltage and at least one digital supply voltage. The method may also include, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition using the at least one digital supply voltage as a reference voltage. For example, sneak condition may favor an excess current's flow from the first node to the second node and, in some situations, the first voltage may be the at least one analog supply voltage.
- In some cases, a circuit element operably coupled between the first node and the second node may have a propagation delay longer than a ramp-up time of the first voltage. Also, counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value defined based upon the reference voltage. Additionally or alternatively, maintaining the second voltage below at or below a predetermined value may include modifying the second voltage in a manner proportional to a difference between the second voltage and the reference voltage.
- For example, in cases where the first and second nodes may be part of a first circuit and the first circuit may include a first amplifier, the method may include providing a second amplifier configured to receive a biasing current proportional to a transient current to flow from the first node to the second node. the first circuit is a bandgap voltage circuit. The method may also include protecting a circuit from an overvoltage condition, the circuit operably coupled to the second node and configured to receive the second voltage.
- Again, the monitoring and the counteracting may occur in response to a Power-on-Reset (PoR) event. Additionally or alternatively, the monitoring and the counteracting may cease to occur a predetermined period of time after the PoR event.
- Although the invention(s) is/are described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention(s), as set forth in the claims below. For example, although presented in the context of bandgap circuits, various systems and methods described herein may be implemented in other types of voltage reference circuits, or other types of circuits. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention(s). Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
- Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The terms “coupled” or “operably coupled” are defined as connected, although not necessarily directly, and not necessarily mechanically. The terms “a” and “an” are defined as one or more unless stated otherwise. The terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”) and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a system, device, or apparatus that “comprises,” “has,” “includes” or “contains” one or more elements possesses those one or more elements but is not limited to possessing only those one or more elements. Similarly, a method or process that “comprises,” “has,” “includes” or “contains” one or more operations possesses those one or more operations but is not limited to possessing only those one or more operations.
Claims (14)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/686,889 US8729951B1 (en) | 2012-11-27 | 2012-11-27 | Voltage ramp-up protection |
JP2013226682A JP6219676B2 (en) | 2012-11-27 | 2013-10-31 | Protection from ramp-up voltage |
TW102139854A TWI605660B (en) | 2012-11-27 | 2013-11-01 | Integrated circuit and method for voltage ramp-up protection |
EP13193712.0A EP2735934A1 (en) | 2012-11-27 | 2013-11-20 | Voltage ramp-up protection |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/686,889 US8729951B1 (en) | 2012-11-27 | 2012-11-27 | Voltage ramp-up protection |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP13193712.0A Previously-Filed-Application EP2735934A1 (en) | 2012-11-27 | 2013-11-20 | Voltage ramp-up protection |
Publications (2)
Publication Number | Publication Date |
---|---|
US8729951B1 US8729951B1 (en) | 2014-05-20 |
US20140145765A1 true US20140145765A1 (en) | 2014-05-29 |
Family
ID=49666984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/686,889 Active US8729951B1 (en) | 2012-11-27 | 2012-11-27 | Voltage ramp-up protection |
Country Status (4)
Country | Link |
---|---|
US (1) | US8729951B1 (en) |
EP (1) | EP2735934A1 (en) |
JP (1) | JP6219676B2 (en) |
TW (1) | TWI605660B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9383764B1 (en) * | 2015-01-29 | 2016-07-05 | Dialog Semiconductor (Uk) Limited | Apparatus and method for a high precision voltage reference |
TWI672576B (en) | 2017-05-02 | 2019-09-21 | 立積電子股份有限公司 | Bandgap reference circuit, voltage generator and voltage control method thereof |
CN107706899A (en) * | 2017-11-12 | 2018-02-16 | 苏州普罗森美电子科技有限公司 | New-energy automobile sound protection circuit |
US11068011B2 (en) * | 2019-10-30 | 2021-07-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Signal generating device and method of generating temperature-dependent signal |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4027177A (en) * | 1975-03-05 | 1977-05-31 | Motorola, Inc. | Clamping circuit |
US5081410A (en) * | 1990-05-29 | 1992-01-14 | Harris Corporation | Band-gap reference |
US6664821B2 (en) * | 2001-03-12 | 2003-12-16 | Koninklijke Philips Electronics N.V. | Line driver with current source output and low sensitivity to load variations |
US7245468B2 (en) * | 2005-02-04 | 2007-07-17 | Agere Systems Inc. | Electro-static discharge (ESD) power clamp with power up detection |
US7453244B1 (en) * | 2005-05-16 | 2008-11-18 | National Semiconductor Corporation | Low dropout regulator with control loop for avoiding hard saturation |
Family Cites Families (70)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2871380A (en) | 1958-03-25 | 1959-01-27 | Levinthal Electronic Products | High voltage pulse generator |
US2998499A (en) | 1958-06-04 | 1961-08-29 | Gen Electric | Electric circuit breaker |
US3379897A (en) | 1965-04-22 | 1968-04-23 | Bell Telephone Labor Inc | Frequency division by sequential countdown of paralleled chain counters |
US3538347A (en) | 1967-04-20 | 1970-11-03 | Gen Electric | Expandable clamp circuit |
US3924456A (en) | 1973-08-17 | 1975-12-09 | Western Electric Co | Methods and apparatus for detecting the presence of cracks in a workpiece by the use of stress waves emitted therefrom |
JPS5296032A (en) | 1976-02-09 | 1977-08-12 | Fuji Xerox Co Ltd | Power source apparatus for developing electrode |
US5003197A (en) | 1989-01-19 | 1991-03-26 | Xicor, Inc. | Substrate bias voltage generating and regulating apparatus |
US5136455A (en) | 1990-03-16 | 1992-08-04 | Esp Electronic Systems Protection, Inc. | Electromagnetic interference suppression device |
JPH0812754B2 (en) | 1990-08-20 | 1996-02-07 | 富士通株式会社 | Boost circuit |
US5093634A (en) | 1990-10-31 | 1992-03-03 | At&T Bell Laboratories | Merged current clamp in triple-input transconductor, for use in oscillator |
US5432322A (en) | 1992-11-13 | 1995-07-11 | Bruder Healthcare Company | Electric heating pad |
US5412526A (en) | 1993-02-10 | 1995-05-02 | Square D Company | Surge arrester circuit and housing therefor |
US5546016A (en) | 1995-07-03 | 1996-08-13 | Intel Corporation | MOS termination for low power signaling |
US5724652A (en) | 1996-10-24 | 1998-03-03 | Motorola, Inc. | Method for acquiring a rapid automatic gain control (AGC) response in a narrow band receiver |
US5742899A (en) | 1996-10-24 | 1998-04-21 | Motorola, Inc. | Fast attack automatic gain control (AGC) loop for narrow band receivers |
US5838524A (en) | 1997-03-21 | 1998-11-17 | Cherry Semiconductor Corporation | Current limit circuit for inhibiting voltage overshoot |
JP4330183B2 (en) | 1997-09-30 | 2009-09-16 | 株式会社ルネサステクノロジ | Semiconductor memory device |
US6084388A (en) * | 1998-09-30 | 2000-07-04 | Infineon Technologies Corporation | System and method for low power start-up circuit for bandgap voltage reference |
US6104170A (en) | 1998-12-23 | 2000-08-15 | Fairchild Semiconductor Corporation | Method and circuit for preventing oscillations in a battery charger |
US7276847B2 (en) | 2000-05-17 | 2007-10-02 | Varian Semiconductor Equipment Associates, Inc. | Cathode assembly for indirectly heated cathode ion source |
US6252493B1 (en) | 2000-10-27 | 2001-06-26 | The Wiremold Company Brooks Electronics Division | High current varistor |
DE10061563B4 (en) | 2000-12-06 | 2005-12-08 | RUBITEC Gesellschaft für Innovation und Technologie der Ruhr-Universität Bochum mbH | Method and apparatus for switching on and off of power semiconductors, in particular for a variable-speed operation of an asynchronous machine, operating an ignition circuit for gasoline engines, and switching power supply |
US6433613B1 (en) | 2000-12-15 | 2002-08-13 | Fairchild Semiconductor Corporation | Translating switch circuit with disabling option |
US6785828B2 (en) | 2000-12-20 | 2004-08-31 | Intel Corporation | Apparatus and method for a low power, multi-level GTL I/O buffer with fast restoration of static bias |
US6617880B2 (en) | 2000-12-20 | 2003-09-09 | Intel Corporation | Method and apparatus for a low power, multi-mode GTL I/O buffer utilizing midrail I/O buffer pad clamping |
DE10110140C1 (en) | 2001-03-02 | 2003-02-06 | Infineon Technologies Ag | Overload protection circuit for line drivers |
US6472856B2 (en) | 2001-03-09 | 2002-10-29 | Semtech Corporation | Bounded power supply voltage positioning |
US6351138B1 (en) | 2001-03-22 | 2002-02-26 | Pericom Semiconductor Corp. | Zero-DC-power active termination with CMOS overshoot and undershoot clamps |
TW516267B (en) | 2002-01-16 | 2003-01-01 | Winbond Electronics Corp | Dynamic pre-charging current sensing amplifier |
US6853153B2 (en) | 2002-02-26 | 2005-02-08 | Analog Microelectronics, Inc. | System and method for powering cold cathode fluorescent lighting |
TW574782B (en) * | 2002-04-30 | 2004-02-01 | Realtek Semiconductor Corp | Fast start-up low-voltage bandgap voltage reference circuit |
ITMI20021321A1 (en) | 2002-06-14 | 2003-12-15 | St Microelectronics Srl | PROTECTION CIRCUIT OF A POWER DEVICE IN FAULT CONDITIONS |
US20040052387A1 (en) | 2002-07-02 | 2004-03-18 | American Technology Corporation. | Piezoelectric film emitter configuration |
US6731150B2 (en) | 2002-08-28 | 2004-05-04 | Micron Technology, Inc. | Amplifiers with variable swing control |
US6894473B1 (en) * | 2003-03-05 | 2005-05-17 | Advanced Micro Devices, Inc. | Fast bandgap reference circuit for use in a low power supply A/D booster |
JP4315724B2 (en) * | 2003-04-17 | 2009-08-19 | 三洋電機株式会社 | Start-up circuit of band gap type reference voltage circuit |
KR100562501B1 (en) * | 2003-05-02 | 2006-03-21 | 삼성전자주식회사 | Power-on reset circuit and semiconductor integrated circuit device including the same |
WO2005101156A1 (en) * | 2004-04-16 | 2005-10-27 | Matsushita Electric Industrial Co., Ltd. | Reference voltage generating circuit |
JP4658587B2 (en) | 2004-12-22 | 2011-03-23 | ローム株式会社 | Motor drive device |
US20060145673A1 (en) | 2005-01-03 | 2006-07-06 | Fogg John K | Method and apparatus for reducing inrush current to a voltage regulating circuit |
US7518348B1 (en) | 2005-04-20 | 2009-04-14 | National Semiconductor Corporation | Adaptive error amplifier clamp circuit to improve transient response of DC/DC converter with current mode control |
US7423888B2 (en) | 2005-06-08 | 2008-09-09 | Tamura Corporation | Voltage conversion circuit and switching power supply device |
US7253600B2 (en) | 2005-07-19 | 2007-08-07 | Cambridge Analog Technology, Llc | Constant slope ramp circuits for sample-data circuits |
US7396524B2 (en) | 2005-08-02 | 2008-07-08 | Main Line Health Heart Center | Methods for screening compounds for proarrhythmic risk and antiarrhythmic efficacy |
US7289003B2 (en) | 2005-08-03 | 2007-10-30 | Seiko Epson Corporation | Method and apparatus for amplitude control using dynamic biasing in a voltage controlled oscillator |
US7649722B2 (en) | 2005-09-14 | 2010-01-19 | Interuniversitair Microelektronica Centrum (Imec) | Electrostatic discharge protected circuits |
FR2893256B1 (en) | 2005-11-14 | 2008-08-15 | Yves Scherman | GENERATOR OF ELECTRIC PULSES UNIPOLAR. |
JP4833652B2 (en) | 2005-12-08 | 2011-12-07 | ローム株式会社 | Regulator circuit and automobile equipped with the same |
US20070206306A1 (en) | 2006-03-01 | 2007-09-06 | Shingo Hokuto | Magnetic head drive circuit |
DE102006017487A1 (en) | 2006-04-13 | 2007-10-18 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Semiconductor-based integrated circuit component for switching discharge, voltage limitation or vibration damping |
US7466185B2 (en) | 2006-10-23 | 2008-12-16 | Infineon Technologies Ag | IGBT-Driver circuit for desaturated turn-off with high desaturation level |
JP2008228362A (en) | 2007-03-08 | 2008-09-25 | Matsushita Electric Ind Co Ltd | Power supply unit |
US8041552B2 (en) | 2007-04-10 | 2011-10-18 | Intergrated Device Technology, Inc. | Behavioral modeling of high speed differential signals based on physical characteristics |
US20090015978A1 (en) | 2007-07-12 | 2009-01-15 | Clark O Melville | Non-inductive silicon transient voltage suppressor |
US7671675B2 (en) | 2007-08-20 | 2010-03-02 | Rohm Co., Ltd. | Output limiting circuit, class D power amplifier and audio equipment |
US8303463B2 (en) | 2007-10-26 | 2012-11-06 | GM Global Technology Operations LLC | Method and apparatus to control clutch fill pressure in an electro-mechanical transmission |
US8062174B2 (en) | 2007-10-27 | 2011-11-22 | GM Global Technology Operations LLC | Method and apparatus to control clutch stroke volume in an electro-mechanical transmission |
DE102008021383B3 (en) | 2008-04-29 | 2009-09-17 | Continental Automotive Gmbh | Method and device for computer-aided recognition of the jamming of an object |
US8269474B2 (en) | 2008-07-23 | 2012-09-18 | Intersil Americas Inc | System and method for reducing voltage overshoot during load release within a buck regulator |
JP5097664B2 (en) | 2008-09-26 | 2012-12-12 | ラピスセミコンダクタ株式会社 | Constant voltage power circuit |
US8026736B2 (en) | 2008-12-30 | 2011-09-27 | Intel Corporation | Water-level charged device model for electrostatic discharge test methods, and apparatus using same |
US8455947B2 (en) | 2009-02-18 | 2013-06-04 | Infineon Technologies Ag | Device and method for coupling first and second device portions |
JP5747445B2 (en) | 2009-05-13 | 2015-07-15 | 富士電機株式会社 | Gate drive device |
US8455794B2 (en) | 2009-06-03 | 2013-06-04 | Illinois Tool Works Inc. | Welding power supply with digital control of duty cycle |
US8546726B2 (en) | 2009-06-03 | 2013-10-01 | Illinois Tool Works Inc. | Systems and devices for determining weld cable inductance |
US8270242B2 (en) | 2009-06-25 | 2012-09-18 | Atmel Corporation | Sense amplifier apparatus and methods |
US8169845B2 (en) | 2009-06-25 | 2012-05-01 | Atmel Corporation | Apparatus and methods for sense amplifiers |
TWI407694B (en) | 2010-01-27 | 2013-09-01 | Novatek Microelectronics Corp | Output buffer circuit and method for avoiding voltage overshoot |
US8531811B2 (en) | 2010-06-08 | 2013-09-10 | Schneider Electric USA, Inc. | Clamping control circuit for hybrid surge protection devices |
US8731753B2 (en) | 2010-09-30 | 2014-05-20 | GM Global Technology Operations LLC | Control of engine start for a hybrid system |
-
2012
- 2012-11-27 US US13/686,889 patent/US8729951B1/en active Active
-
2013
- 2013-10-31 JP JP2013226682A patent/JP6219676B2/en active Active
- 2013-11-01 TW TW102139854A patent/TWI605660B/en active
- 2013-11-20 EP EP13193712.0A patent/EP2735934A1/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4027177A (en) * | 1975-03-05 | 1977-05-31 | Motorola, Inc. | Clamping circuit |
US5081410A (en) * | 1990-05-29 | 1992-01-14 | Harris Corporation | Band-gap reference |
US6664821B2 (en) * | 2001-03-12 | 2003-12-16 | Koninklijke Philips Electronics N.V. | Line driver with current source output and low sensitivity to load variations |
US7245468B2 (en) * | 2005-02-04 | 2007-07-17 | Agere Systems Inc. | Electro-static discharge (ESD) power clamp with power up detection |
US7453244B1 (en) * | 2005-05-16 | 2008-11-18 | National Semiconductor Corporation | Low dropout regulator with control loop for avoiding hard saturation |
Also Published As
Publication number | Publication date |
---|---|
TWI605660B (en) | 2017-11-11 |
TW201436406A (en) | 2014-09-16 |
EP2735934A1 (en) | 2014-05-28 |
JP2014106967A (en) | 2014-06-09 |
JP6219676B2 (en) | 2017-10-25 |
US8729951B1 (en) | 2014-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9076656B2 (en) | Electrostatic discharge (ESD) clamp circuit with high effective holding voltage | |
US9774258B2 (en) | Zero-current crossing detection circuits | |
US8729951B1 (en) | Voltage ramp-up protection | |
US9588531B2 (en) | Voltage regulator with extended minimum to maximum load current ratio | |
US8901991B2 (en) | Power monitoring circuitry | |
CN107004638B (en) | Semiconductor integrated circuit having a plurality of transistors | |
JP2013192444A (en) | Power module including leakage current protection circuit | |
US9092043B2 (en) | Power switch with current limitation and zero direct current (DC) power consumption | |
US9092045B2 (en) | Startup circuits with native transistors | |
US8736333B1 (en) | Schmitt trigger circuit with near rail-to-rail hysteresis | |
US9141119B2 (en) | Reducing output voltage ripple of power supplies | |
EP2940862B1 (en) | Reference buffer with wide trim range | |
US9356590B1 (en) | Production test trimming acceleration | |
US9467107B2 (en) | Rail-to-rail follower circuits | |
US20140139201A1 (en) | Low-power voltage tamper detection | |
US10007282B2 (en) | Voltage regulator | |
US9509305B2 (en) | Power gating techniques with smooth transition | |
US9110484B2 (en) | Temperature dependent biasing for leakage power reduction | |
US9356569B2 (en) | Ready-flag circuitry for differential amplifiers | |
US10101761B2 (en) | Semiconductor device | |
US9194890B2 (en) | Metal-oxide-semiconductor (MOS) voltage divider with dynamic impedance control | |
US20160105170A1 (en) | Reset signal generator and integrated circuit having the same | |
JP2016092195A (en) | Power supply circuit, electronic circuit, and integrated circuit | |
KR20110137242A (en) | Semiconductor integrated circuit including internal circuits and electrostatic discharge protection circuits | |
US20100315156A1 (en) | Volatage bandgap reference circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOY, JON S.;SAEZ, RICHARD TITOV LARA;GUERRERO, LUIS EDUARDO RUEDA;SIGNING DATES FROM 20121119 TO 20121127;REEL/FRAME:029360/0119 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030258/0540 Effective date: 20130214 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030258/0523 Effective date: 20130214 Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SUPPLEMENT TO IP SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030258/0558 Effective date: 20130214 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424 Effective date: 20130521 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266 Effective date: 20131101 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037357/0671 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037357/0685 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037486/0517 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037518/0292 Effective date: 20151207 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037494/0312 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:039361/0212 Effective date: 20160218 |
|
AS | Assignment |
Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: MERGER;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:041144/0363 Effective date: 20161107 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:041703/0536 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042985/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042762/0145 Effective date: 20160218 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
AS | Assignment |
Owner name: SHENZHEN XINGUODU TECHNOLOGY CO., LTD., CHINA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS.;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:048734/0001 Effective date: 20190217 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050745/0001 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051030/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:053547/0421 Effective date: 20151207 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |