US20140019658A1 - Hub devices and methods for initializing hub device - Google Patents

Hub devices and methods for initializing hub device Download PDF

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Publication number
US20140019658A1
US20140019658A1 US13/939,691 US201313939691A US2014019658A1 US 20140019658 A1 US20140019658 A1 US 20140019658A1 US 201313939691 A US201313939691 A US 201313939691A US 2014019658 A1 US2014019658 A1 US 2014019658A1
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Prior art keywords
chip
signal
external memory
memory device
firmware data
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Abandoned
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US13/939,691
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English (en)
Inventor
Chih-Long Ho
Yi-Te Chen
Wen-hao Cheng
Kuo-Yu Wu
Chun-Heng Lin
Po-Ming HUANG
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Via Technologies Inc
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Via Technologies Inc
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Publication date
Priority claimed from TW102120062A external-priority patent/TWI489286B/zh
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Priority to US13/939,691 priority Critical patent/US20140019658A1/en
Assigned to VIA TECHNOLOGIES, INC. reassignment VIA TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, YI-TE, CHENG, WEN-HAO, HO, CHIH-LONG, HUANG, PO-MING, LIN, Chun-heng, WU, KUO-YU
Publication of US20140019658A1 publication Critical patent/US20140019658A1/en
Priority to US15/167,668 priority patent/US9817788B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/40—Bus coupling
    • G06F2213/4004—Universal serial bus hub with a plurality of upstream ports

Definitions

  • the invention relates to a hub device, and more particularly to a hub device with extended port number and reduced manufacturing costs.
  • portable electronic devices such as cellular phones, tablet computers, MP3 players, portable hard disks, global positioning systems (GPS), digital cameras, portable gaming devices, or others.
  • GPS global positioning systems
  • the portable electronic devices are easy to be carried, once data transmission or system data update is required, the portable electronic devices still have to connect to a host device.
  • the number of ports of a host device is usually limited.
  • a hub device is required to extend the number of ports of the host device.
  • An exemplary embodiment of a hub device comprises a first chip, a second chip and an external memory device.
  • the first chip comprises at least a first upstream port and a plurality of first downstream ports.
  • the second chip comprises at least a second upstream port and a plurality of second downstream ports.
  • An external memory device stores firmware data corresponding to the first chip and the second chip.
  • One of the first downstream ports of the first chip is coupled to the second upstream port of the second chip to form a tiered hub, wherein the first chip and the second chip are sequentially enabled and the first chip and the second chip sequentially load the corresponding firmware data.
  • An exemplary embodiment of a method for initializing a hub device wherein the hub device comprises at least a first chip and a second chip, and an external memory device.
  • the external memory device is shared by the first chip and the second chip and stores firmware data of the first chip and the second chip.
  • the method comprises: generating a first start-up signal to enable the first chip; reading the firmware data corresponding to the first chip from the external memory device by the first chip; generating a second start-up signal to enable the second chip; and reading the firmware data corresponding to the second chip from the external memory device by the second chip.
  • the hub device comprises at least a first chip and a second chip, and an external memory device.
  • the external memory device is shared by the first chip and the second chip and stores firmware data of the first chip and the second chip, comprises: generating a first start-up signal to enable the first chip; reading the firmware data corresponding to the first chip and the second chip from the external memory device by the first chip; generating a second start-up signal to enable the second chip; and receiving the firmware data corresponding to the second chip from the first chip by the second chip.
  • FIG. 1 shows a schematic block diagram of a hub device according to an embodiment of the invention
  • FIG. 2 shows a schematic block diagram of a hub device according to another embodiment of the invention.
  • FIG. 3 shows a schematic block diagram of a hub device according to yet another embodiment of the invention.
  • FIG. 4 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 5 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 6 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 7 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 8 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 9 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 10 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 11 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 12 shows a block diagram of a chip according to an embodiment of the invention.
  • FIG. 13 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 14 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 15 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • FIG. 16 shows a flow chart of a method for initializing a hub device according to an embodiment of the invention
  • FIG. 17 shows another flow chart of a method for initializing a hub device according to another embodiment of the invention.
  • FIG. 18 shows a flow chart of a method for starting-up a chip based on a start-up program according to an embodiment of the invention.
  • a novel hub device structure which can simply achieve port extension based on the existing hub devices, is provided.
  • the cost of manufacturing the hub device can be greatly reduced by the ability to share an external memory device therewith.
  • the cost of manufacturing the hub device can be further reduced by the ability to share a crystal oscillator.
  • the hub device comprises a plurality of chips and an external memory device shared by the chips.
  • Each chip may be a hub device chip and may comprise at least one upstream port and a plurality of downstream ports for providing hub function.
  • each chip can be solely implemented as the hub chip of a hub device.
  • a downstream port of at least one chip is coupled to an upstream port of one or more chips to form a tiered hub. In this manner, port extension can be achieved based on the existing hub chips.
  • there is no need to configure a dedicated external memory device for each chip In other words, only one external memory device has to be configured in the hub device and shared by the chips. Therefore, the cost of manufacturing the hub device can be further reduced.
  • the proposed hub devices are further introduced in the following paragraphs.
  • FIG. 1 shows a schematic block diagram of a hub device according to an embodiment of the invention.
  • the hub device 100 may comprise at least chips 110 and 120 and an external memory device 150 disposed outside of the chips 110 and 120 .
  • the chips 110 and 120 may respectively comprise at least one upstream port UP and a plurality of downstream ports DN.
  • the upstream port UP of the chip 110 may be coupled to a host 50 and one of the downstream ports DN of the chip 110 may be coupled to the upstream port UP of the chip 120 to form a tiered hub.
  • the chip 110 may be regarded as a first tier chip or the top tier chip of the hub device 100
  • the chip 120 may be regarded as a second tier chip or a bottom tier chip of the hub device 100 .
  • FIG. 2 shows a schematic block diagram of a hub device according to another embodiment of the invention.
  • the hub device 200 may comprise at least chips 210 , 220 and 230 and an external memory device 250 disposed outside of the chips 210 , 220 and 230 .
  • the chips 210 , 220 and 230 may respectively comprise at least one upstream port UP and a plurality of downstream ports DN.
  • the upstream port UP of the chip 210 may be coupled to a host 50 and two of the downstream ports DN of the chip 210 may be respectively coupled to the upstream port UP of the chip 220 and the upstream port UP of the chip 230 to form a tiered hub.
  • the chip 210 may be regarded as a first tier chip or the top tier chip of the hub device 200
  • the chips 220 and 230 may be regarded as a second tier chips or bottom tier chips of the hub device 200 .
  • FIG. 3 shows a schematic block diagram of a hub device according to yet another embodiment of the invention.
  • the hub device 300 may comprise at least chips 310 , 320 and 330 and an external memory device 350 disposed outside of the chips 310 , 320 and 330 .
  • the chips 310 , 320 and 330 may respectively comprise at least one upstream port UP and a plurality of downstream ports DN.
  • the upstream port UP of the chip 310 may be coupled to a host 50
  • one of the downstream ports DN of the chip 310 may be coupled to the upstream port UP of the chip 320
  • one of the downstream ports DN of the chip 320 may be coupled to the upstream port UP of the chip 330 to form a tiered hub.
  • the chip 310 may be regarded as a first tier chip or the top tier chip of the hub device 300
  • the chip 320 may be regarded as a second tier chip of the hub device 300
  • the chip 330 may be regarded as a third tier chip or a bottom tier chip of the hub device 300 .
  • FIG. 1 to FIG. 3 merely show three of several possible designs of a tiered hub, and the invention should not be limited to the structure as shown in FIG. 1 to FIG. 3 .
  • Those who are skilled in this technology can make various alterations and modifications based on the concept as illustrated above to derive other non-discussed structures. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.
  • FIG. 1-3 presents a simplified block diagram, in which only the elements relevant to the invention are shown. However, those who are skilled in this technology can easily derive other elements and thus the invention should not be limited what is shown in FIG. 1-3 .
  • the shared external memory device may store firmware data corresponding to each chip.
  • the firmware data may comprise firmware or software programs and the data required by each chip for operating, such as relative parameters or look up tables.
  • the corresponding firmware data is loaded to finish initialization procedure of each chip. After initialization, each chip may begin operation by executing the corresponding firmware or software programs.
  • FIG. 4 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 400 may comprise chips 410 , 420 and 430 , a start-up circuit 440 , oscillators 461 , 462 and 463 , and an external memory device 450 disposed outside of the chips 410 , 420 and 430 .
  • the chips 410 , 420 and 430 may be sequentially enabled and may sequentially load the corresponding firmware data to finish the initialization procedure.
  • the start-up circuit 440 may generate a start-up signal S Start and transmit the start-up signal S Start to a reset signal input terminal RST to enable/reset the chip 410 .
  • the start-up circuit 440 may generate the start-up signal S Start based on the received electric power.
  • the oscillators 461 , 462 and 463 may respectively generate a clock signal and provide the corresponding clock signal to a clock signal input terminal CLK of the chips 410 , 420 and 430 .
  • the chips 410 , 420 and 430 may execute super high speed data transmission (for example, USB 3.0) or non-super high speed data transmission (for example, USB 2.0 or USB 1.0) based on the corresponding clock signal.
  • the chip 410 is a first tier chip or the top tier chip of the hub device 400 .
  • the chip 410 receives the start-up signal S Start , the chip 410 is enabled or reset.
  • the chip 410 may obtain control right of accessing the external memory device 450 so as to read the corresponding firmware data from the external memory device 450 .
  • the chip 410 may store the corresponding firmware data in an internal memory device (not shown) of the chip 410 to finish the initialization procedure.
  • the chip 410 may further generate a start-up signal and transmit the start-up signal to a reset signal input terminal RST of the chip 420 to enable/reset the chip 420 .
  • the chip 410 may release the control right of accessing the external memory device 450 .
  • the other chips for example, the chip 420 or 430
  • the chip 420 may obtain the control right of accessing the external memory device 450 after being enabled or reset, so as to read the required firmware data and achieve the goal of sharing the external memory device 450 among the chips 410 , 420 and 430 .
  • the chip 420 is a tier of the chips, other than the first tier chip, of the hub device 400 .
  • the chip 420 when the chip 420 receives a start-up signal, the chip 420 is enabled or reset. Next, the chip 420 acquires the control right of accessing the external memory device 450 so as to read the corresponding firmware data from the external memory device 450 .
  • the chip 420 may store the corresponding firmware data in the internal memory device (not shown) of the chip 420 to finish the initial procedure. As discussed above, after obtaining the required firmware data from the external memory device 450 , the chip 420 may release the control right of accessing the external memory device 450 .
  • the chip 420 may further generate a start-up signal and transmit the start-up signal to a reset signal input terminal RST of the chip 430 to enable/reset the chip 430 .
  • the chip 430 is a tier of the chip, other than the first tier chip, of the hub device 400 .
  • the chip 430 may be enabled or reset.
  • the chip 430 reads the corresponding firmware data from the external memory device 450 .
  • the chip 430 may store the received firmware data in the internal memory device (not shown) of the chip 430 to finish the initialization procedure.
  • the external memory device 450 may be coupled to the chips 410 , 420 and 430 via a Serial Peripheral Interface (SPI) bus or an Inter-Integrated Circuit (I2C) bus.
  • SPI Serial Peripheral Interface
  • I2C Inter-Integrated Circuit
  • the chip 410 , 420 or 430 may apply different voltage levels at the pin SPI_CS# of the SPI bus to obtain or release the control right of accessing the external memory device 450 .
  • the chip 410 may be a main control chip of the hub device 400 and the firmware data corresponding to the chips 410 , 420 and 430 may be the same or different.
  • the chips 410 , 420 and 430 may sequentially access the same or different memory block of the external memory device 450 .
  • the external memory device 450 for example, EEPROM with SPI interface
  • the access of the external memory device 450 may be well controlled, such that one chip may access the shared external memory device 450 only when another chip has finished accessing the external memory device 450 . Therefore, collision (that is, two or more chips accessing the shared external memory device 450 at the same time) can be prevented.
  • FIG. 5 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 500 may at least comprise chips 510 , 520 and 530 , a start-up circuit 540 , oscillators 561 , 562 and 563 , delay circuits 591 , 592 and 593 and an external memory device 550 disposed outside of the chips 510 , 520 and 530 .
  • the chips 510 , 520 and 530 may be sequentially enabled and may sequentially load corresponding firmware data to finish the initialization procedure.
  • the start-up circuit 540 may generate the start-up signal S Start and transmit the start-up signal S Start to the chip 510 to enable/reset the chip 510 . Meanwhile, the start-up signal S Start generated by the start-up circuit 540 may further be transmitted to the delay circuit 591 .
  • the delay circuit 591 may delay the start-up signal S Start and may generate another start-up signal to the chip 520 and the delay circuit 592 after a predetermined time interval. According to an embodiment of the invention, the delay circuit 591 may wait or delay the start-up signal S Start for the predetermined time interval as discussed above, and then transmit the start-up signal to the chip 520 and the delay circuit 592 . Similarly, the delay circuit 592 may wait or delay the start-up signal S Start for the predetermined time interval as discussed above, and then transmit the start-up signal to the chip 530 and the delay circuit 593 . In the embodiment of the invention, the predetermined time interval may be longer than the time interval required by each chip to read the corresponding firmware data.
  • the predetermined time interval may be longer than the time interval required by each chip to read the corresponding firmware data and finish initialization procedure. Thereby, simultaneous access of the external memory device 550 by different chips at the same time may be prevented.
  • the start-up signal received by each chip of the hub device may also be generated through different start-up circuits, as long as the timing of the start-up signal received by each chip can be well-controlled, such that simultaneous access of the external memory device 550 by different chips can be prevented.
  • FIG. 6 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 600 may at least comprise chips 610 , 620 and 630 , a start-up circuit 640 , an oscillator 660 and an external memory device 650 disposed outside of the chips 610 , 620 and 630 .
  • the chips 610 , 620 and 630 may be sequentially enabled and may sequentially load the corresponding firmware data to finish the initialization procedure.
  • FIG. 6 Most of the elements in FIG. 6 are the same as FIG. 4 .
  • the main difference therebetween is that the chips 610 , 620 and 630 share the clock signal generated by the same oscillator 660 in FIG. 6 . Therefore, for descriptions of like elements, reference may be made to FIG. 4 , and are omitted here for brevity.
  • FIG. 7 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 700 may at least comprise chips 710 , 720 and 730 , a start-up circuit 740 , an oscillator 760 , delay circuits 791 , 792 and 793 and an external memory device 750 disposed outside of the chips 710 , 720 and 730 .
  • the chips 710 , 720 and 730 may be sequentially enabled and may sequentially load the corresponding firmware data to finish the initialization procedure.
  • FIG. 7 Most of the elements in FIG. 7 are the same as FIG. 5 . The main difference therebetween is that the chips 710 , 720 and 730 share the clock signal generated by the same oscillator 760 in FIG. 7 . Therefore, for descriptions of like elements, reference may be made to FIG. 4 and FIG. 5 , and are omitted here for brevity.
  • FIG. 8 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 800 may at least comprise chips 810 , 820 and 830 , a start-up circuit 840 , oscillators 861 , 862 and 863 , and an external memory device 850 disposed outside of the chips 810 , 820 and 830 .
  • the chips 810 , 820 and 830 may be sequentially enabled and may sequentially load the corresponding firmware data to finish the initialization procedure.
  • the first tier chip 810 is coupled to the external memory device 850 for reading the corresponding firmware data of the chips 810 , 820 and 830 from the external memory device 850 and storing the firmware data in the internal memory device (not shown) of the chip 810 in FIG. 8 .
  • the chips 820 and 830 When the chips 820 and 830 are sequentially enabled, the chips 820 and 830 further receive the corresponding firmware data from the chip 810 .
  • the chips 820 and 830 receive the firmware data from chip 810 instead of direct accessing the firmware data stored in the external memory device 850 .
  • the top tier chip for example, chip 810
  • the other tiers of chips for example, the chips 820 and 830
  • the chips in the lower tiers may receive the firmware data from the chip in the upper tier to finish the initialization procedure.
  • the chips 810 , 820 and 830 are mutually connected through a transmission bus disposed therebetween, such as Serial Peripheral Interface (SPI) bus, a System Management (SM) bus, an Inter-Integrated Circuit (I2C) bus, or others.
  • SPI Serial Peripheral Interface
  • SM System Management
  • I2C Inter-Integrated Circuit
  • the chip 810 may also not store the firmware data corresponding to the chips 820 and 830 in the internal memory device, but directly read the firmware data corresponding to the chips 820 and 830 from the external memory device 850 and transmit the corresponding firmware data to the chips 820 and 830 , respectively, during the initialization procedure of the chips 820 and 830 .
  • the firmware data corresponding to the chips 810 , 820 and 830 may be the same or different data.
  • the chip 830 may also receive the corresponding firmware data from the chip 820 instead of from the chip 810 .
  • the chip 820 may receive the firmware data corresponding to the chip 830 at the same time.
  • the chip 810 (or in some embodiments, the chip 820 ) may actively or passively (for example, in response to a request signal) transmit the firmware data of the chips 820 and 830 (or in some embodiments, the chip 830 ).
  • FIG. 8 The descriptions of the remaining elements in FIG. 8 may refer to the illustrations of FIG. 4 , and are omitted here for brevity.
  • FIG. 9 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 900 may comprise chips 910 , 920 and 930 , a start-up circuit 940 , oscillators 961 , 962 and 963 , delay circuits 991 , 992 and 993 and an external memory device 950 disposed outside of the chips 910 , 920 and 930 .
  • the chips 910 , 920 and 930 may be sequentially enabled and may sequentially load the corresponding firmware data to finish the initialization procedure.
  • FIG. 9 Note that most of the elements in FIG. 9 are the same as FIG. 5 .
  • the chip 920 obtains the corresponding firmware data from the upper tier chip 910 instead of the external memory device 950 in FIG. 9 .
  • the chip 930 also obtains the corresponding firmware data from the upper tier chip (such as 910 or 920 ) instead of the external memory device 950 . Therefore, for descriptions of like elements, reference may be made to FIG. 4 , FIG. 5 and FIG. 8 , and are omitted here for brevity.
  • FIG. 10 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 1000 may comprise chips 1010 , 1020 and 1030 , a start-up circuit 1040 , an oscillator 1060 and an external memory device 1050 disposed outside of the chips 1010 , 1020 and 1030 .
  • the chips 1010 , 1020 and 1030 may be sequentially enabled and may sequentially load the corresponding firmware data to finish the initialization procedure.
  • FIG. 10 Note that most of the elements in FIG. 10 are the same as FIG. 8 .
  • the main difference therebetween is that the chips 1010 , 1020 and 1030 share the clock signal generated by the same oscillator 1060 in FIG. 10 . Therefore, for descriptions of like elements, reference may be made to FIG. 4 and FIG. 8 , and are omitted here for brevity.
  • FIG. 11 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 1100 may comprise at least chips 1110 , 1120 and 1130 , a start-up circuit 1140 , an oscillator 1160 , delay circuits 1191 , 1192 and 1193 and an external memory device 1150 disposed outside of the chips 1110 , 1120 and 1130 .
  • the chips 1110 , 1120 and 1130 may be sequentially enabled and may sequentially load the corresponding firmware data to finish the initialization procedure.
  • FIG. 11 Note that most of the elements in FIG. 11 are the same as FIG. 9 .
  • the main difference therebetween is that the chips 1110 , 1120 and 1130 share the clock signal generated by the same oscillator 1160 in FIG. 11 . Therefore, for descriptions of like elements, reference may be made to FIG. 4 , FIG. 5 , FIG. 8 and FIG. 9 , and are omitted here for brevity.
  • control signals received by the chips in the hub device can be sequentially generated for sequentially enabling each chip and collision (that is, when two or more chips access the shared external memory device at the same time) can be prevented.
  • sequentially enabling the chips are further illustrated in the following paragraphs.
  • FIG. 12 shows a block diagram of a chip according to an embodiment of the invention.
  • the chip 1210 may be any tier of chip in the hub device, and may comprise at least an upstream port UP, a plurality of downstream ports DN, a processor 1211 , an internal statistic random access memory (SRAM) 1212 , an internal read only memory (ROM) 1213 , an input/output (I/O) interface module 1214 and a register 1215 .
  • the processor 1211 may be arranged to execute the software and firmware programs stored in the internal SRAM 1212 or internal ROM 1213 for maintaining the operations of the chip. Accompanied with the block as shown in FIG. 12 , several embodiments of the chips being sequentially enabled are illustrated in the following paragraphs.
  • FIG. 13 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 1300 may comprise at least chips 1310 and 1320 , a start-up circuit 1340 , switch circuits 1380 and 1385 and an external memory device 1350 disposed outside of the chips 1310 and 1320 .
  • the chips 1310 and 1320 may be sequentially enabled and may sequentially load the corresponding firmware data from the external memory device 1350 to finish the initialization procedure.
  • the external memory device 1350 may be coupled to the chips 1310 and 1320 via the SPI bus, and coupled to the I/O interface module of the chips 1310 and 1320 via the SPI bus.
  • the pin SPI_CS# of the SPI bus as discussed above is coupled to a General Purpose Input/Output (GPIO) pin of the I/O interface module of the chips 1310 and 1320 .
  • the chip 1310 may control the switch circuit 1380 so as to selectively conduct the transmission path between the GPIO pin of the chip 1310 and the pin SPI_CS# of the SPI bus, or conduct the transmission path between the GPIO pin of the chip 1320 and the pin SPI_CS# of the SPI bus. Thereby, the chip 1310 or 1320 may obtain the control right of accessing the external memory device 1350 .
  • the start-up circuit 1340 may be coupled to a voltage input terminal VDD and the chip 1310 , and may comprise a resistor R and a capacitor C coupled in serial.
  • the start-up circuit 1340 may generate the start-up signal S Start based on the voltage at the voltage input terminal VDD, and may transmit the start-up signal S Start to a reset signal input terminal RST of the chip 1310 , to enable/reset the chip 1310 .
  • the processor may set the voltage levels at the GPIO pin GPIO 1 _ 1 and GPIO 2 _ 1 to a first predetermined level (for example, a low voltage level).
  • Switching of the switch circuit 1380 is controlled by setting the voltage level at the GPIO pin GPIO 1 _ 1 to the first predetermined level, so as to conduct the transmission path between the GPIO pin GPIO 2 _ 1 and the pin SPI_CS#.
  • the chip 1310 may obtain the control right of accessing the external memory device 1350 after coupling the voltage level (the first predetermined level) at the GPIO pin GPIO 2 _ 1 to the pin SPI_CS#, and then the chip 1310 may access the firmware data required during the initialization procedure.
  • the switch circuit 1380 may comprise two complementary switches 1380 _ 1 and 1380 _ 2 .
  • two Transistor-Transistor Logic (TTL) devices are respectively coupled to the pins GPIO 1 _ 1 , GPIO 2 _ 1 and the pin SPI_CS#.
  • the control terminal, input terminal and output terminal of the switch 1380 _ 2 are respectively coupled to the pins GPIO 1 _ 1 , GPIO 2 _ 2 and the pin SPI_CS#.
  • the switches 1380 _ 1 and 1380 _ 2 are two complementary switches and the control terminals of the switches 1380 _ 1 and 1380 _ 2 are both coupled to the pin GPIO 1 _ 1 , the pin SPI_CS# will not be coupled to both the voltage levels at the pin GPIO 2 _ 1 and the pin GPIO 2 _ 2 at the same time. Thus, simultaneous access of the external memory device 1350 by the chips 1310 and 1320 can be prevented.
  • the chip 1310 may receive the corresponding firmware data from the external memory device 1350 via the SPI bus 1390 and then write or store the firmware data in the internal SRAM of the chip 1310 .
  • the processor of the chip 1310 may set the voltage level at the pin GPIO 1 _ 1 from the first predetermined level to a second predetermined level (for example, high voltage level).
  • Switching of the switch circuit 1380 can be controlled by setting the voltage level at the pin GPIO 1 _ 1 to the second predetermined level, so as to turn off the transmission path between the pin GPIO 2 _ 1 of the chip 1310 and the pin SPI_CS#, and conduct the transmission path between the pin GPIO 2 _ 2 of the chip 1320 and the pin SPI_CS#.
  • the chip 1310 may release the control right of accessing the external memory device 1350 .
  • the pin GPIO 1 _ 1 is further coupled to the switch circuit 1385 .
  • the switch circuit 1385 is conducted.
  • a second start-up signal is generated and transmitted to the reset signal input terminal RST of the chip 1320 to enable/reset the chip 1320 .
  • the processor of the chip 1320 may set the voltage level at the GPIO pin GPIO 2 _ 2 to the first predetermined voltage level (for example, the low voltage level).
  • the chip 1310 already released the control right of accessing the external memory device 1350 when the chip 1320 was enabled/reset and the switch circuit 1380 already conducted the transmission path between the pin GPIO 2 _ 2 and the pin SPI_CS#. Therefore, the chip 1320 may obtain the control right of accessing the external memory device 1350 via the voltage level at the pin GPIO 2 _ 2 (that is, the first predetermined voltage). Next, the chip 1320 may receive the corresponding firmware data from the external memory device 1350 via the SPI bus 1395 and then write or store the firmware data in the internal SRAM of the chip 1320 to finish the initialization procedure.
  • the SPI bus 1390 or the SPI bus 1395 in FIG. 13 does not comprise the SPI pin SPI_CS#. However, when implementing, the SPI bus 1390 or the SPI bus 1395 in FIG. 13 actually comprises the SPI pin SPI_CS#.
  • the invention is not limited to the methods of setting the voltage at the GPIO pin and the control logic of the switch circuit as discussed above. Any setting method and control logics that can achieve the same or similar results can all be applied in the embodiments of the invention.
  • FIG. 14 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 1400 may comprise at least chips 1410 and 1420 , a start-up circuit 1440 , switch circuit 1485 and an external memory device 1450 disposed outside of the chips 1410 and 1420 .
  • the chips 1410 and 1420 may be sequentially enabled and may sequentially load the corresponding firmware data to finish the initialization procedure.
  • the external memory device 1450 may be coupled to the chips 1410 and 1420 via the SPI bus, and the I/O interface module of the chips 1410 and 1420 may comprise a plurality of GPIO pins. For example, as shown in FIG.
  • the switch circuit 1485 is coupled between the pin GPIO 1 _ 1 of a plurality of GPIO pins of chip 1410 and the reset signal input terminal RST of the chip 1420 .
  • the pin SPI_CS# of the external memory device 1450 is coupled to the pin GPIO 1 _ 1 of a plurality of GPIO pins of chip 1410 and the pin GPIO 2 _ 2 of a plurality of GPIO pins of chip 1420 .
  • the timing of enabling/resetting the chip 1420 is controlled by the chip 1410 .
  • the processor of the chip 1410 may set the voltage level at the pin GPIO 1 _ 1 to the first predetermined level (for example, a low voltage level) as discussed above to obtain the control right of accessing the external memory device 1450 , and may read the required firmware data from the external memory device 1450 via the SPI bus 1490 and write or store the firmware data into the internal SRAM of the chip 1410 . Meanwhile, since the voltage level at the pin GPIO 1 _ 1 is at the first predetermined level (for example, a low voltage level), the switch circuit 1485 will not be conducted to enable/reset the chip 1420 .
  • the first predetermined level for example, a low voltage level
  • the processor of the chip 1410 may set the voltage level of the pin GPIO 1 _ 1 to the second predetermined level (for example, a high voltage level) as discussed above to release the control right of accessing the SPI bus. Meanwhile, since the voltage level at the pin GPIO 1 _ 1 changes (for example, from the low voltage level to the high voltage level), the switch circuit 1485 may switch to enable or reset the chip 1420 .
  • the second predetermined level for example, a high voltage level
  • the processor of the chip 1420 may further set the voltage level of the pin GPIO 2 _ 2 to the first predetermined level (for example, a low voltage level) as discussed above to obtain the control right of accessing the external memory device 1450 and access the required firmware data from the external memory device 1450 via the SPI bus 1495 and then write or store the firmware data into the internal SRAM of the chip 1420 to finish the initialization procedure.
  • the first predetermined level for example, a low voltage level
  • FIG. 15 shows a schematic block diagram of a hub device according to still another embodiment of the invention.
  • the hub device 1500 may comprise at least chips 1510 and 1520 , a start-up circuit 1540 , switch circuits 1585 and an external memory device 1550 disposed outside of the chips 1510 and 1520 .
  • the chips 1510 and 1520 may be sequentially enabled and sequentially load the corresponding firmware data to finish the initialization procedure.
  • the external memory device 1550 may be coupled to the chip 1510 via the SPI bus 1590 .
  • the chip 1510 may be coupled to the chip 1520 via the SPI bus 1595 .
  • the I/O interface module of the chips 1510 and 1520 may comprise a plurality of GPIO pins. As shown in FIG.
  • the switch circuit 1585 is disposed between the pin GPIO 1 _ 1 of the plurality of GPIO pins of the chip 1510 and reset the signal input terminal RST of the chip 1520 .
  • the pin SPI_CS# of the external memory device 1550 may also be coupled to the pin GPIO 1 _ 1 of the chip 1510 .
  • the enable/reset timing of the chip 1520 may be controlled by the chip 1510 .
  • the processor of the chip 1510 may set the voltage level of the pin GPIO 1 _ 1 to the first predetermined level (for example, a low voltage level) as discussed above to obtain the control right of accessing the external memory device 1550 , and may read the required firmware data from the external memory device 1550 via the SPI bus 1590 .
  • the chip 1510 may further read the firmware data of the chip 1520 during the initialization procedure.
  • the switch circuit 1585 is not conducted to enable/reset the chip 1520 .
  • the processor of the chip 1510 may set the voltage level at the pin GPIO 1 _ 1 to the second predetermined level (for example, the high voltage level) to release the control right of accessing the SPI interface as discussed above. Meanwhile, since the voltage level at the pin GPIO 1 _ 1 changes (for example, from low voltage level to high voltage level), the switch circuit 1585 may switch to enable or reset the chip 1520 .
  • the second predetermined level for example, the high voltage level
  • the processor of the chip 1510 may transmit the corresponding firmware data required by the chip 1520 in the initialization procedure to the chip 1520 via the bus 1595 between the chips 1510 and 1520 .
  • the chip 1520 may store the received firmware data in the internal SRAM to finish the initialization procedure.
  • the chip 1510 may further set the internal register of the chip 1520 via the bus 1595 so as to enable the chip 1520 to directly execute the programs stored in the internal SRAM thereof. Note that in the embodiment of the invention, after the chip 1520 is enabled, the chip 1520 can directly execute the programs stored in the internal SRAM instead of obtaining the programs stored in the external memory device 1550 via the pin SPI_CS# of the external memory device 1550 .
  • the GPIO pin (for example, the pin GPIO 2 _ 2 of the plurality of GPIO pins in the above embodiments) in the I/O interface module of the chip 1520 is not coupled to the pin SPI_CS# of the external memory device 1550 .
  • the bus 1595 between the chips 1510 and 1520 may be the SM bus, I2C bus or SPI bus.
  • the SM bus, I2C bus or SPI bus may be implemented by the plurality of GPIO pins in the I/O interface module in the chips 1510 and 1520 .
  • the chip 1510 may actively transmit the firmware data of the chip 1520 to the chip 1520 , or the chip 1510 may issue a request signal to the chip 1510 and then the chip 1510 may transmit the firmware data of the chip 1520 to the chip 1520 in response to the request signal. Therefore, the invention should not be limited to either way of implementation.
  • FIG. 16 shows a flow chart of a method for initializing a hub device according to an embodiment of the invention.
  • the hub device comprises two chips and an external memory device shared by the two chips.
  • a first start-up signal is generated to enable the first chip (step S 1602 ).
  • the first start-up signal may be generated by the start-up circuit.
  • the first chip reads the firmware data corresponding to the first chip from the external memory device (step S 1604 ).
  • the first chip may write the firmware data corresponding to the first chip into the internal SRAM of the first chip.
  • a second start-up signal is generated to enable the second chip (step S 1606 ).
  • the second start-up signal may be generated by other circuits (for example, other start-up circuit or delay circuit) or by the first chip. Note that steps S 1604 and S 1606 may be simultaneously executed. Finally, after the first chip has finished reading the external memory device or releases the control right of accessing the external memory device, the second chip reads the firmware data corresponding to the second chip from the external memory device (Step S 1608 ). In an embodiment, the second may write the firmware data corresponding to the second chip into the internal SRAM of the second chip.
  • FIG. 17 shows another flow chart of a method for initializing a hub device according to another embodiment of the invention.
  • the hub device comprises two chips and an external memory device shared by the two chips.
  • a first start-up signal is generated to enable the first chip (step S 1702 ).
  • the first start-up signal may be generated by the start-up circuit.
  • the first chip reads the firmware data corresponding to the first chip and the second chip from the external memory device.
  • the firmware data corresponding to the first chip and the second chip is written to the internal SRAM of the first chip (step S 1704 ).
  • a second start-up signal is generated to enable the second chip (step S 1706 ).
  • the second start-up signal may be generated by other circuits (for example, other start-up circuit or delay circuit) or by the first chip.
  • steps S 1704 and S 1706 may be simultaneously executed.
  • the second chip receives the firmware data corresponding to the second chip from the first chip, and writes the firmware data corresponding to the second chip to the internal SRAM of the second chip (Step S 1708 ).
  • the first chip may transmit the firmware data corresponding to the second chip to the second chip actively or in response to a request signal.
  • each chip has to determine whether the external memory device exists, so as to determine whether to load the firmware data from the external memory device.
  • the chip since each tier of chip may have different operations, in some embodiments of the invention, the chip has to determine which tier of chip in the tired hub device it belongs to. For example, the way to handle the over current condition for different tiers of chips may be different.
  • each chip may also have to determine whether it is the first tier chip or not.
  • the first tier chip has to generate the corresponding signals to enable/reset other tiers of chips, access the corresponding firmware data for the other tiers of chips, and/or set the registers of the other tiers of chips, and so on. If not, the other tiers of chips may wait for the firmware data transmitted by the first tier chip, or actively transmit a request signal to the first tier chip.
  • each chip may determine which tier in the tiered hub device it belongs to based on voltage level of GPIO pins. The voltage levels at the GPIO pins may be set when manufacturing the hub device. According to some other embodiments of the invention, each chip may also determine which tier in the tiered hub device it belongs to based on the data stored in the internal ROM. Generally, the internal ROM may store some programs to maintain the basic function of the chips. For example, the boot sequence or other programs, and some important information, such as the information regarding the address for accessing the external memory device.
  • FIG. 18 shows a flow chart of a method for starting-up a chip based on a start-up program according to an embodiment of the invention.
  • the chip When the chip is enabled or reset, the chip may further determine to firstly execute the program stored in the memory device based on the setting values of the register. Generally, the register may be set in advance such that the chip may execute the power on procedure stored in the internal ROM. Therefore, the processor may execute the boot sequence first. Based on the boot sequence, the processor may first determine whether the external memory device exists and whether the stored firmware data of the external memory device is valid (step S 1802 ). For example, if the external memory device exists, the processor may read the content in the header of the external memory device so as to obtain the information regarding the address and data size of the firmware data, and determine whether the firmware data are valid based on the information.
  • the processor When the firmware data stored in the external memory device is valid, the processor starts to access the external memory device to obtain the corresponding firmware data.
  • the processor stores the obtained firmware data in the internal SRAM (Step S 1804 ), and then the processor may execute the programs stored in the internal SRAM (Step S 1806 ) and operate according to the programs.
  • the processor may next trigger a software reboot procedure so as to reboot the chip from the internal SRAM and execute the programs stored in the internal SRAM.
  • the processor may further change to execute the programs stored in the internal SRAM by changing the setting values of the register.
  • the processor may directly execute the basic program stored in the internal ROM (Step S 1808 ) and operate according to the programs.
  • any component or collection of components that perform the functions described above can be generically considered as one or more processors that control the above discussed function.
  • the one or more processors can be implemented in numerous ways, such as with dedicated hardware, or with general purpose hardware that is programmed using microcode or software to perform the functions recited above.

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