US20130288422A1 - Solid-state image sensor, method of manufacturing the same, and image pickup apparatus - Google Patents
Solid-state image sensor, method of manufacturing the same, and image pickup apparatus Download PDFInfo
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- US20130288422A1 US20130288422A1 US13/832,438 US201313832438A US2013288422A1 US 20130288422 A1 US20130288422 A1 US 20130288422A1 US 201313832438 A US201313832438 A US 201313832438A US 2013288422 A1 US2013288422 A1 US 2013288422A1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
- H01L27/14627—Microlenses
Definitions
- the present invention relates to a solid-state image sensor, a method of manufacturing the same, and an image pickup apparatus.
- CMOS complementary metal oxide semiconductor
- FIG. 9 An example of a structure of the CMOS solid-state image sensor is shown in FIG. 9 .
- a photodiode 102 and a floating diffusion 103 is formed in a semiconductor substrate 101 .
- the photodiode 102 has a P-N junction structure including an N-type impurity region 104 and a P-type impurity region 105 .
- the floating diffusion 103 is formed of an N-type impurity region 106 .
- a transfer transistor 107 is formed on the semiconductor substrate 101 .
- the transfer transistor 107 is structured so that the photodiode 102 and the floating diffusion 103 are set as a source/drain region, respectively.
- the transfer transistor 107 includes a gate insulating film 108 , a gate electrode 109 , and spacers 110 and 111 .
- the gate insulating film 108 is formed between the photodiode 102 and the floating diffusion 103 .
- the gate electrode 109 is formed on the gate insulating film 108 .
- the spacer 110 is formed on a sidewall of the gate electrode 109 on a side of the photodiode 102
- the spacer 111 is formed on the other sidewall of the gate electrode 109 on a side of the floating diffusion 103 .
- the spacers 110 and 111 that cover the sidewalls of the gate electrode 109 are symmetrically formed. Therefore, a length L 3 of the spacer 110 and a length L 4 of the spacer 111 are set to be the same length (size).
- the P-type impurity region 105 is formed in the self-aligned manner with respect to the spacer 110
- the N-type impurity region 106 is formed in the self-aligned manner with respect to the spacer 111 .
- the length L 3 of the spacer 110 and the length L 4 of the spacer 111 affect characteristics of a solid-state image sensor. For example, if the length L 4 of the spacer 111 on the floating diffusion 103 side is short, a dark current is increased due to a so-called GIDL (gate induced drain leakage). To prevent this, it is desirable to set the length L 4 of the spacer 111 to be long to some extent.
- GIDL gate induced drain leakage
- the length L 3 of the spacer 110 on the photodiode 102 side is long, pinning of the N-type impurity region 104 of the photodiode 102 is weaken, resulting in the increase in the dark current. Further, if the length L 3 of the spacer 110 is short, the dark current is suppressed, but an afterimage is deteriorated. Accordingly, an optimal size of the length L 3 of the spacer 110 needs to be set to strike a balance between the characteristics of the dark current and the afterimage.
- Japanese Patent Application Laid-open No. 2002-110957 discloses a CMOS image sensor in which a spacer formed on a side of a photodiode is longer than a spacer formed on a side of a floating diffusion.
- the lengths L 3 and L 4 of the spacers 110 and 111 are the same due to the structural symmetry as described above. Therefore, for example, in the case where the length L 4 of the spacer 111 is increased in order to suppress the dark current on the floating diffusion 103 side, the length L 3 of the spacer 110 , which is formed to have the same size as the spacer 111 , may be deviated from an optimal value.
- the length L 3 of the spacer 110 is optimized in order to strike the balance between the characteristics of the dark current and the afterimage on the photodiode 102 side
- the length L 4 of the spacer 111 which is formed to have the same size as the spacer 110 , becomes too short, resulting in the increase in the dark current.
- an appropriate control on both the suppression of the dark current on the floating diffusion 103 side and the optimization of the dark current and the afterimage on the photodiode 102 side is difficult to be performed.
- a solid-state image sensor In view of the above-mentioned circumstances, it is desirable to provide a solid-state image sensor, a method of manufacturing the same, and an image pickup apparatus that are capable of simultaneously realizing a suppression of a dark current on a charge detector side and an optimization of characteristics of a dark current and an afterimage on a photoelectric converter side.
- a solid-state image sensor comprising a photoelectric converter, a charge detector, and a transfer transistor.
- the photoelectric converter stores a signal charge that is subjected to photoelectric conversion.
- the charge detector detects the signal charge.
- the transfer transistor transfers the signal charge from the photoelectric converter to the charge detector.
- the transfer transistor includes a gate insulating film, a gate electrode formed on the gate insulating film, a first spacer formed on a sidewall of the gate electrode on a side of the photoelectric converter, and a second spacer formed on another sidewall of the gate electrode on a side of the charge detector.
- the first spacer is shorter than the second spacer.
- the length of the first spacer on the photoelectric converter side, can be set in accordance with an optimal value for striking characteristics of a dark current and an after image regardless of the length of the second spacer.
- the length of the second spacer on the charge detector side, can be set in accordance with a size suitable for suppressing the dark current regardless of the length of the first spacer.
- a first method of manufacturing a solid-state image sensor includes forming a gate electrode on a semiconductor substrate through a first insulating film, etching the gate electrode so that a part of the gate electrode on a side of a photoelectric converter formation region is lower than a part of the gate electrode on a side of a charge detector formation region, forming a second insulating film on the semiconductor substrate in a state of covering the first insulating film and the gate electrode, and etching the first insulating film and the second insulating film so that a first spacer formed on a sidewall of the gate electrode on the side of the photoelectric converter formation region is shorter than a second spacer formed on a sidewall of the gate electrode on the side of the charge detector formation region.
- the first method of manufacturing the solid-state image sensor according to the embodiment of the present invention obtained is the solid-state image sensor in which the first spacer formed on the sidewall of the gate electrode on the photoelectric converter formation region side is set to be shorter than the second spacer formed on the sidewall of the gate electrode on the charge detector formation region side. Further, the length of the first spacer can be controlled with the amount of etching by which the gate electrode is etched being set as a process parameter, and the length of the second spacer can be controlled with a thickness of the second insulating film being set as a process parameter.
- a second method of manufacturing a solid-state image sensor includes forming a gate electrode on a semiconductor substrate through a first insulating film, forming a second insulating film on the semiconductor substrate in a state of covering the first insulating film and the gate electrode, etching the first insulating film and the second insulating film so that a first spacer formed on a sidewall of the gate electrode on a side of a photoelectric converter formation region has the same length as a second spacer formed on a sidewall of the gate electrode on a side of a charge detector formation region, and etching the first spacer so that the first spacer is shorter than the second spacer.
- the solid-state image sensor in which the first spacer formed on the sidewall of the gate electrode on the photoelectric converter formation region side is set to be shorter than the second spacer formed on the sidewall of the gate electrode on the charge detector formation region side. Further, the length of the first spacer can be controlled with the amount of etching by which the first spacer is etched being set as a process parameter, and the length of the second spacer can be controlled with a thickness of the second insulating film being set as a process parameter.
- the solid-state image sensor including the photoelectric converter, the charge detector, and the transfer transistor, suppression of the dark current on the charge detector side and striking of the balance between the characteristics of the dark current and the after image can be realized at the same time.
- FIG. 1 is a schematic view showing a structural example of a CMOS solid-state image sensor as an example of a solid-state image sensor to which the present invention is applied;
- FIG. 2 is an enlarged cross-sectional view showing a part of a solid-state image sensor according to a first embodiment of the present invention
- FIGS. 3A and 3B are diagrams (part 1) for explaining a method of manufacturing the solid-state image sensor according to the first embodiment of the present invention
- FIGS. 4A and 4B are diagrams (part 2) for explaining the method of manufacturing the solid-state image sensor according to the first embodiment of the present invention.
- FIG. 5 is an enlarged cross-sectional view showing a part of a solid-state image sensor according to a second embodiment of the present invention.
- FIGS. 6A and 6B are diagrams (part 1) for explaining a method of manufacturing the solid-state image sensor according to the second embodiment of the present invention.
- FIGS. 7A and 7B are diagrams (part 2) for explaining the method of manufacturing the solid-state image sensor according to the second embodiment of the present invention.
- FIG. 8 is a block diagram showing a structural example of an image pickup apparatus to which the present invention is applied.
- FIG. 9 is a cross-sectional view showing an example of a solid-state image sensor in related art.
- FIG. 1 is a schematic diagram showing a structural example of a CMOS solid-state image sensor as an example of a solid-state image sensor to which the present invention is applied.
- a solid-state image sensor 10 shown in FIG. 1 includes a unit pixel 11 , a vertical scanning circuit 12 , a vertical scanning pulse driver 13 , a horizontal selection transistor 14 , and a horizontal scanning circuit 15 .
- the unit pixels 11 are two-dimensionally disposed in a matrix pattern to form an imaging area.
- the vertical scanning circuit 12 is provided outside the imaging area.
- the unit cell 11 is constituted of a photodiode PD and four transistors of a transfer transistor 22 , an amplification transistor 23 , a reset transistor 24 , and an XY address transistor 25 .
- a MOS transistor is used for each of the pixel transistors 22 to 25 . It should be noted that in this case, only the unit pixel in an m-th row and an n-th column is shown for simplification of the figure.
- the transfer transistor 22 has a source connected to a cathode of the photodiode PD and a drain connected to a gate of the amplification transistor 23 .
- a connection portion of the drain of the transfer transistor 22 and the gate of the amplification transistor 23 corresponds to a floating diffusion FD.
- the drain of the amplification transistor 23 is connected to a power source VDD, and the source thereof is connected to a vertical signal line 26 .
- the reset transistor 24 has a drain connected to a vertical reset line 27 , a source connected to the connection potion (FD) between the drain of the transfer transistor 22 and the gate of the amplification transistor 23 , and a gate connected to a horizontal reset line 28 .
- the XY address transistor 25 has a gate connected to a vertical read line 29 , a drain connected to a horizontal read line 30 , and a source connected to the gate of the transfer transistor 22 .
- the vertical scanning circuit 12 sequentially outputs vertical read scanning pulses ⁇ VRm ( ⁇ VR1, ⁇ VR2, . . . , ⁇ VRm, . . . , ⁇ VRM) and vertical reset scanning pulses ⁇ VSm ( ⁇ VS1, ⁇ VS2, . . . , ⁇ VSm, . . . , ⁇ VSM).
- the vertical read scanning pulses VRm are applied to the vertical read line 29 in the corresponding row.
- the vertical reset scanning pulses ⁇ VSm are applied to the vertical reset line 27 in the corresponding row through the vertical scanning pulse driver 13 .
- the vertical scanning pulse driver 13 has a circuit terminal on the power source side that is connected to a power source line 31 of the power source voltage VDD and a circuit terminal on a GND side that is connected to a GND line 32 .
- the vertical scanning pulse driver 13 drives the vertical reset line 27 based on the vertical reset scanning pulses ⁇ VSm supplied from the vertical scanning circuit 12 .
- the vertical scanning pulse driver 13 shifts a GND level of the GND line 32 to about 0.5 to 0.8 V, with the vertical reset scanning pulses ⁇ VSm being at an “L” level, to be given to the vertical reset line 27 .
- the horizontal scanning circuit 15 sequentially outputs horizontal read scanning pulses ⁇ HRn ( ⁇ HR1, ⁇ HR2, . . . , ⁇ HRn, . . . , ⁇ HRN), horizontal selection scanning pulses ⁇ Hn ( ⁇ H1, ⁇ H2, . . . , ⁇ Hn, . . . , ⁇ HN), and horizontal reset scanning pulse ⁇ HSn ( ⁇ HS1, ⁇ HS2, . . . , ⁇ HSn, . . . , ⁇ HSN).
- the horizontal read scanning pulses ⁇ HRn are applied to the horizontal read line 30 of a corresponding column.
- the horizontal reset scanning pulses ⁇ HSn are applied to the horizontal reset line 28 of a corresponding column.
- the horizontal selection scanning pulses ⁇ Hn are applied to the gate of the horizontal selection transistor 14 of a corresponding column.
- the horizontal selection transistor 14 is connected between an end of the vertical signal line 26 and a horizontal signal line 33 for each column.
- FIG. 2 is an enlarged cross-sectional view of the solid-state image sensor according to the first embodiment of the present invention.
- the photodiode PD serves as the photoelectric converter for storing a signal charge that has been subjected to a photoelectric conversion. More specifically, the photodiode PD converts incident light to an electric signal depending on a light amount thereof and generates a signal charge, and stores the generated signal charge therein.
- the photodiode PD has a P-N junction structure including an N-type impurity region 52 and a P-type impurity region 53 .
- the floating diffusion FD serves as the charge detector that detects the signal charge transferred by the transfer transistor 22 from the photodiode PD.
- the floating diffusion FD is formed of an N-type impurity region 54 .
- the transfer transistor 22 transfers the signal charge stored through the photoelectric conversion by the photodiode PD to the floating diffusion FD.
- the transfer transistor 22 includes the photodiode PD and the floating diffusion FD as source and drain regions, respectively.
- the transfer transistor 22 is provided with a gate insulating film 55 , a gate electrode 56 , a first spacer 57 , and a second spacer 58 .
- the gate insulating film 55 is formed between the photodiode PD and the floating diffusion FD.
- the gate electrode 56 is formed on the gate insulating film 55 .
- the first spacer 57 is disposed on a sidewall of the gate electrode 56 on a side of the photodiode PD.
- the second spacer 58 is disposed on the other sidewall of the gate electrode 56 on a side of the floating diffusion FD.
- the P-type impurity region 53 is formed in a self-aligned manner with respect to the first spacer 57
- the N-type impurity region 54 is formed in the self-aligned manner with respect to the second spacer 58 .
- the first spacer 57 and the second spacer 58 are asymmetrically formed. More specifically, when a length L 1 of the first spacer 57 and a length L 2 of the second spacer 58 are compared with each other, the length L 1 of the first spacer 57 is set to be shorter than the length L 2 of the second spacer 58 .
- the length of the spacer refers to a spacer size in a length direction (hereinafter, also referred to as “gate length direction”) of the gate electrode 56 .
- the length direction of the gate electrode 56 corresponds to a horizontal direction in FIG. 2
- a width direction of the gate electrode 56 corresponds to a depth direction in FIG. 2 .
- the length of the spacer is defined by a size from the sidewall of the gate electrode 56 to an end portion of the spacer in the length direction of the gate electrode 56 . Therefore, the length L 1 of the first spacer 57 is defined by the size from the one sidewall of the gate electrode 56 to the end portion of the first spacer 57 , and the length L 2 of the second spacer 58 is defined from the other sidewall of the gate electrode 56 to the end portion of the second spacer 58 .
- the length L 1 of the first spacer 57 is set to an optimal size for striking a balance between characteristics of a dark current and an afterimage on the photodiode PD side.
- the length L 2 of the second spacer 58 is set to a size suitable for suppressing a dark current on the floating diffusion FD side.
- the size optimal for striking the balance between the characteristics of the dark current and the afterimage on the photodiode PD side is smaller than the size suitable for suppressing the dark current on the floating diffusion FD side. Therefore, the length L 1 of the first spacer 57 is set to be shorter than the length L 2 of the second spacer 58 as described above.
- a step is formed on an upper surface of the gate electrode 56 .
- a height of the gate electrode 56 on the photodiode PD side is lower than a height of the gate electrode 56 on the floating diffusion FD side.
- the height of the gate electrode 56 refers to a size of the gate electrode in a thickness direction of the semiconductor substrate 51 .
- FIGS. 3A , 3 B, 4 A, and 4 B are diagrams for explaining a method of manufacturing the solid-state image sensor according to the first embodiment of the present invention.
- a first insulating film 61 and the gate electrode 56 are formed in this order, along with an element isolation region (not shown).
- the first insulating film 61 corresponds to the gate insulating film 55 as described above, and is formed so as to broadly cover an upper surface of the semiconductor substrate 51 in this stage.
- the gate electrode 56 is formed into a predetermined shape by a patterning process.
- N-type impurities is performed to the semiconductor substrate 51 , thereby forming the N-type impurity region 52 .
- a photodiode formation region 59 in which the photodiode PD is formed and a floating diffusion formation region 60 in which the floating diffusion FD is formed are provided to the semiconductor substrate 51 .
- the photodiode formation region 59 is provided on the side opposite to the floating diffusion formation region 60 with respect to the gate electrode 56 .
- the N-type impurity region 52 is formed by performing the ion implantation of the N-type impurities to the photodiode formation region 59 .
- the gate electrode 56 is selectively etched so that the height H 1 of the gate electrode 56 on the photodiode formation region 59 side is lower than the height H 2 of the gate electrode 56 on the floating diffusion formation region 60 side.
- the height H 1 of the gate electrode 56 on the photodiode formation region 59 side is determined in consideration of the length L 1 (see, FIG. 2 ) of the first spacer 57 formed in the following process.
- a second insulating film 62 is formed in a state of covering the first insulating film 61 and the gate electrode 56 .
- the second insulating film 62 is deposited so as to cover the entire surface of the semiconductor substrate 51 .
- a thickness of the second insulating film 62 is determined in consideration of the length L 2 (see, FIG. 2 ) of the second spacer 58 formed in the following process.
- the first insulating film 61 and the second insulating film 62 are etched (etching back process), thereby exposing the surface (upper surface) of the semiconductor substrate 51 .
- the first spacer 57 is formed on the sidewall of the gate electrode 56 on the photodiode formation region 59 side
- the second spacer 58 is formed on the other sidewall of the gate electrode 56 on the floating diffusion formation region 60 side.
- the first spacer 57 is formed of an insulating material protruded from the sidewall of the gate electrode 56 toward the photodiode formation region 59 side.
- the second spacer 58 is formed of an insulating material protruded from the other sidewall of the gate electrode 56 toward the floating diffusion formation region 60 side.
- the first and second insulating films 61 and 62 are etched at the same time other than a part lower than the gate electrode 56 .
- the gate insulating film 55 is formed of the insulating material of the first insulating film 61 .
- the first spacer 57 is formed of the insulating material of the first insulating film 61 and the second insulating film 62
- the second spacer 58 is formed of the insulating material of the first insulating film 61 and the second insulating film 62 .
- the lengths L 1 and L 2 of the spacers 57 and 58 formed by etching the first insulating film 61 and the second insulating film 62 become longer as the heights H 1 and H 2 of the gate electrode 56 are increased. Further, the length L 1 of the first spacer 57 depends on the height H 1 of the gate electrode 56 on the photodiode formation region 59 side, and the length L 2 of the second spacer 58 depends on the height H 2 of the gate electrode 56 on the floating diffusion formation region 60 side. In this case, the heights H 1 and H 2 of the gate electrode 56 has a relationship of “H 1 ⁇ H 2 ”. Therefore, in accordance with this relationship, the length L 1 of the first spacer 57 is formed to be shorter than the length L 2 of the second spacer 58 .
- the P-type impurity region 53 is formed. Further, by performing the ion implantation of the N-type impurities to the semiconductor substrate 51 with the floating diffusion formation region 60 being a target, the N-type impurity region 54 is formed.
- the P-type impurity region 53 is formed by performing the ion implantation of the P-type impurities to the semiconductor substrate 51 with the first spacer 57 being a mask. Therefore, the P-type impurity region 53 is formed in the self-aligned manner with respect to the first spacer 57 .
- the N-type impurity region 54 is formed by performing the ion implantation of the N-type impurities to the semiconductor substrate 51 with the second spacer 58 being a mask. Therefore, the N-type impurity region 54 is formed in the self-aligned manner with respect to the second spacer 58 . In this stage, the photodiode PD constituted of the N-type impurity region 52 and the P-type impurity region 53 and the floating diffusion FD formed of the N-type impurity region 54 are formed. As a result, the solid-state image sensor having the structure shown in FIG. 2 can be obtained.
- the length L 1 of the first spacer 57 is set to be shorter than the length L 2 of the second spacer 58 . Therefore, on the photodiode PD side, regardless of the length L 2 of the second spacer 58 , the length L 1 of the first spacer 57 can be set in accordance with the optimal value for striking the balance between the characteristics of the dark current and the afterimage. In addition, on the floating diffusion FD side, regardless of the length L 1 of the first spacer 57 , the length L 2 of the second spacer 58 can be set in accordance with the size suitable for suppressing the dark current. As a result, the suppression of the dark current on the floating diffusion FD side and the striking of the balance between the characteristics of the dark current and the afterimage on the photodiode PD side can be realized at the same time.
- the height of the gate electrode 56 on the photodiode PD side is set to be lower than that of the gate electrode 56 on the floating diffusion FD side. Therefore, the second insulating film 62 having the uniform thickness is formed on the semiconductor substrate 51 , and then the first insulating film 61 and the second insulating film 62 are just etched, with the result that the structure of the solid-state image sensor in which the length L 1 of the first spacer 57 is shorter than the length L 2 of the second spacer 58 can be realized.
- the height H 1 of the gate electrode 56 on the photodiode formation region 59 side is determined depending on the amount of etching at the time when the gate electrode 56 is selectively etched.
- the length L 1 of the first spacer 57 depends on the height H 1 of the gate electrode 56 on the photodiode formation region 59 side. Therefore, the length L 1 of the first spacer 57 can be controlled with the amount of etching at the time when the gate electrode 56 is selectively etched being set as a process parameter.
- the height H 2 of the gate electrode 56 on the floating diffusion formation region 60 side is determined depending on the deposition thickness by which the second insulating film 62 is deposited. Further, the length L 2 of the second spacer 58 depends on the height H 2 of the gate electrode 56 on the floating diffusion formation region 60 side. Therefore, the length L 2 of the second spacer 58 can be controlled with the deposition thickness of the second insulating film 62 being set as a process parameter. As a result, the length L 1 of the first spacer 57 and the length L 2 of the second spacer 58 can be controlled independently of each other. Thus, the suppression of the dark current on the floating diffusion FD side and the striking of the balance between the characteristics of the dark current and the afterimage on the photodiode PD side can be realized at the same time.
- FIG. 5 is an enlarged cross-sectional view showing a part of a solid-state image sensor according to a second embodiment of the present invention. It should be noted that in the second embodiment of the present invention, the same components as those of the first embodiment are denoted by the same reference numerals or symbols.
- the semiconductor substrate 51 is provided with the photodiode PD serving as the photoelectric converter and the floating diffusion FD serving as the charge detector.
- the photodiode PD has a P-N junction structure including the N-type impurity region 52 and the P-type impurity region 53 .
- the floating diffusion FD is formed of the N-type impurity region 54 .
- the transfer transistor 22 includes the gate insulating film 55 , the gate electrode 56 , the first spacer 57 , and the second spacer 58 . Further, on the semiconductor substrate 51 , the first spacer 57 and the second spacer 58 are asymmetrically formed. That is, when the length L 1 of the first spacer 57 and the length L 2 of the second spacer 58 are compared, the length L 1 of the first spacer 57 is set to be shorter than the length L 2 of the second spacer 58 .
- the structure mentioned above is the same as that of the first embodiment.
- the height of the gate electrode 56 on the photodiode PD side and that on the floating diffusion FD side are set to be different.
- a step is not formed on the gate electrode 56 , and the gate electrode 56 on the photodiode PD side and that on the floating diffusion FD side are the same.
- FIGS. 6A , 6 B, 7 A, and 7 B are diagrams for explaining a method of manufacturing the solid-state image sensor according to the second embodiment of the present invention.
- the first insulating film 61 and the gate electrode 56 are formed in addition to an element isolation region (not shown).
- the first insulating film 61 corresponds to the gate insulating film 55 and is formed so as to broadly cover the upper surface of the semiconductor substrate 51 in this stage.
- the gate electrode 56 is formed into a predetermined shape by a patterning process.
- an ion implantation of N-type impurities is performed to the semiconductor substrate 51 , thereby forming the N-type impurity region 52 .
- the photodiode formation region 59 and the floating diffusion formation region 60 are provided to the semiconductor substrate 51 .
- the N-type impurity region 52 is formed by performing the ion implantation of the N-type impurities to the photodiode formation region 59 .
- the second insulating film 62 is formed in a state of covering the gate insulating film 55 and the gate electrode 56 .
- the second insulating film 62 is deposited so as to cover the entire surface of the semiconductor substrate 51 .
- the thickness of the second insulating film 62 is determined in consideration of the length L 2 (see, FIG. 2 ) of the second spacer 58 formed in the following process.
- the first insulating film 61 and the second insulating film 62 are etched (etching back process), thereby exposing the surface (upper surface) of the semiconductor substrate 51 .
- the first spacer 57 is formed on a sidewall of the gate electrode 56 on the photodiode formation region 59 side
- the second spacer 58 is formed on the other sidewall of the gate electrode 56 on the floating diffusion formation region 60 side.
- the first spacer 57 is formed of an insulating material protruded from the sidewall of the gate electrode 56 toward the photodiode formation region 59 side.
- the second spacer 58 is formed of an insulating material protruded from the other sidewall of the gate electrode 56 toward the floating diffusion formation region 60 side.
- the first and second insulating films 61 and 62 are etched at the same time other than the part lower than the gate electrode 56 .
- the gate insulating film 55 is formed of the insulating material of the first insulating film 61 .
- the first spacer 57 is formed of the insulating material of the first insulating film 61 and the second insulating film 62
- the second spacer 58 is formed of the insulating material of the first insulating film 61 and the second insulating film 62 .
- the first spacer 57 and the second spacer 58 are symmetrically formed. Therefore, the length L 1 of the first spacer 57 and the length L 2 of the second spacer 58 are the same.
- the first spacer 57 on the photodiode formation region 59 side is selectively etched, thereby reducing the length L 1 of the first spacer 57 .
- the first spacer 57 and the second spacer 58 are asymmetrically formed, and the length L 1 of the first spacer 57 is set to be shorter than the length L 2 of the second spacer 58 .
- the P-type impurity region 53 is formed. Further, by performing the ion implantation of the N-type impurities to the semiconductor substrate 51 with the floating diffusion formation region 60 being a target, the N-type impurity region 54 is formed.
- the P-type impurity region 53 is formed by performing the ion implantation of the P-type impurities to the semiconductor substrate 51 with the first spacer 57 being a mask. Therefore, the P-type impurity region 53 is formed in the self-aligned manner with respect to the first spacer 57 .
- the N-type impurity region 54 is formed by performing the ion implantation of the N-type impurities to the semiconductor substrate 51 with the second spacer 58 being a mask. Therefore, the N-type impurity region 54 is formed in the self-aligned manner with respect to the second spacer 58 . In this stage, the photodiode PD constituted of the N-type impurity region 52 and the P-type impurity region 53 and the floating diffusion FD formed of the N-type impurity region 54 are formed. As a result, the solid-state image sensor having the structure shown in FIG. 5 can be obtained.
- the length L 1 of the first spacer 57 is set to be shorter than the length L 2 of the second spacer 58 . Therefore, on the photodiode PD side, regardless of the length L 2 of the second spacer 58 , the length L 1 of the first spacer 57 can be set in accordance with the optimal value for striking the balance between the characteristics of the dark current and the afterimage. In addition, on the floating diffusion FD side, regardless of the length L 1 of the first spacer 57 , the length L 2 of the second spacer 58 can be set in accordance with the size suitable for suppressing the dark current. As a result, the suppression of the dark current on the floating diffusion FD side and the striking of the balance between the characteristics of the dark current and the afterimage on the photodiode PD side can be realized at the same time.
- the length L 1 of the first spacer 57 is determined depending on the amount of etching at the time when the first spacer 57 is selectively etched. Therefore, the length L 1 of the first spacer 57 can be controlled with the amount of etching at the time when the first spacer 57 is selectively etched being set as a process parameter. Further, in the process of manufacturing the solid-state image sensor, the height of the gate electrode 56 is determined depending on the deposition thickness by which the second insulating film 62 is deposited. Further, the length L 2 of the second spacer 58 depends on the height of the gate electrode 56 .
- the length L 2 of the second spacer 58 can be controlled with the deposition thickness of the second insulating film 62 being set as a process parameter.
- the length L 1 of the first spacer 57 and the length L 2 of the second spacer 58 can be controlled independently of each other.
- the first spacer 57 and the second spacer 58 are symmetrically formed by etching the insulating films 61 and 62 , and then the first spacer 57 is selectively etched to shorten the length L 1 thereof, but the present invention is not limited to this.
- a third spacer (not shown) may be formed so as to cover the sidewall of the second spacer 58 , thereby increasing the length of the spacer on the floating diffusion FD side.
- FIG. 8 is a block diagram showing a structural example of an image pickup apparatus to which the present invention is applied.
- An image pickup apparatus 90 shown in FIG. 8 includes an optical system having a lens group 91 , a solid-state image pickup apparatus 92 , a DSP circuit 93 , a frame memory 94 , a display apparatus 95 , a recording apparatus 96 , an operation system 97 , and a power source system 98 .
- the DSP circuit 93 , the frame memory 94 , the display apparatus 95 , the recording apparatus 96 , the operation system 97 , and the power source system 98 are mutually connected through a bus line 99 .
- the lens group 91 collects incident light (image light) from a subject and forms an image on an imaging surface of the solid-state image pickup apparatus 92 .
- the solid-state image pickup apparatus 92 converts a light amount of the incident light that is imaged on the imaging surface by the lens group 91 into an electrical signal for each pixel, and outputs it as a pixel signal.
- As an element structure of the solid-state image pickup apparatus 92 the structure of the solid-state image sensor described above is applied.
- the display apparatus 95 is formed of a panel-type display apparatus such as a liquid crystal display apparatus and an organic EL (electro-luminescence) display apparatus, and displays a moving image or a still image taken by the solid-state image pickup apparatus 92 .
- the recording apparatus 96 records the moving image or the still image taken by the solid-state image pickup apparatus 92 on a recording medium such as a non-volatile memory, a videotape, and a DVD (digital versatile disk).
- the operation system 97 gives operation commands for various functions of the image pickup apparatus 90 under the control of a user who uses the image pickup apparatus 90 .
- the power source system 98 appropriately supplies various power sources as operation sources to the DSP circuit 93 , the frame memory 94 , the display apparatus 95 , the recording apparatus 96 , and the operation system 97 .
- the image pickup apparatus 90 as described above is applied to a camera module for a mobile apparatus, such as a video camera, a digital still camera, and a camera cellular phone.
- the present invention can also be applied to, for example, vehicles such as an automobile and an airplane in which a camera equipped with the solid-state image sensor is incorporated.
- the element structure according to the above embodiments can be employed as the solid-state image sensor for cameras incorporated in the front, the back, the sides of the automobile.
- vehicles such as an automobile and an airplane equipped with the solid-state image sensor that uses the element structure of the above embodiments can be a form of the image pickup apparatus according to the present invention, in addition to the camera module for the mobile apparatus described above.
Abstract
Disclosed is a solid-state image sensor including a photoelectric converter, a charge detector, and a transfer transistor. The photoelectric converter stores a signal charge that is subjected to photoelectric conversion. The charge detector detects the signal charge. The transfer transistor transfers the signal charge from the photoelectric converter to the charge detector. In the solid-state image sensor, the transfer transistor includes a gate insulating film, a gate electrode formed on the gate insulating film, a first spacer formed on a sidewall of the gate electrode on a side of the photoelectric converter, and a second spacer formed on another sidewall of the gate electrode on a side of the charge detector. The first spacer is longer than the second spacer.
Description
- The present application is a divisional of U.S. application Ser. No. 12/657,047, filed on Jan. 13, 2010, which claims priority from Japanese Patent Application No. JP 2009-007346 filed in the Japanese Patent Office on Jan. 16, 2009, all of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a solid-state image sensor, a method of manufacturing the same, and an image pickup apparatus.
- 2. Description of the Related Art
- As a solid-state image sensor, a CMOS (complementary metal oxide semiconductor) solid-state image sensor is widely known. An example of a structure of the CMOS solid-state image sensor is shown in
FIG. 9 . InFIG. 9 , aphotodiode 102 and afloating diffusion 103 is formed in asemiconductor substrate 101. Thephotodiode 102 has a P-N junction structure including an N-type impurity region 104 and a P-type impurity region 105. Thefloating diffusion 103 is formed of an N-type impurity region 106. - Further, on the
semiconductor substrate 101, atransfer transistor 107 is formed. Thetransfer transistor 107 is structured so that thephotodiode 102 and thefloating diffusion 103 are set as a source/drain region, respectively. Thetransfer transistor 107 includes agate insulating film 108, agate electrode 109, andspacers gate insulating film 108 is formed between thephotodiode 102 and thefloating diffusion 103. Thegate electrode 109 is formed on thegate insulating film 108. Thespacer 110 is formed on a sidewall of thegate electrode 109 on a side of thephotodiode 102, and thespacer 111 is formed on the other sidewall of thegate electrode 109 on a side of thefloating diffusion 103. - The
spacers gate electrode 109 are symmetrically formed. Therefore, a length L3 of thespacer 110 and a length L4 of thespacer 111 are set to be the same length (size). In addition, the P-type impurity region 105 is formed in the self-aligned manner with respect to thespacer 110, and the N-type impurity region 106 is formed in the self-aligned manner with respect to thespacer 111. - The length L3 of the
spacer 110 and the length L4 of thespacer 111 affect characteristics of a solid-state image sensor. For example, if the length L4 of thespacer 111 on thefloating diffusion 103 side is short, a dark current is increased due to a so-called GIDL (gate induced drain leakage). To prevent this, it is desirable to set the length L4 of thespacer 111 to be long to some extent. - On the other hand, if the length L3 of the
spacer 110 on thephotodiode 102 side is long, pinning of the N-type impurity region 104 of thephotodiode 102 is weaken, resulting in the increase in the dark current. Further, if the length L3 of thespacer 110 is short, the dark current is suppressed, but an afterimage is deteriorated. Accordingly, an optimal size of the length L3 of thespacer 110 needs to be set to strike a balance between the characteristics of the dark current and the afterimage. - Japanese Patent Application Laid-open No. 2002-110957 discloses a CMOS image sensor in which a spacer formed on a side of a photodiode is longer than a spacer formed on a side of a floating diffusion.
- In the solid-state image sensor shown in
FIG. 9 , the lengths L3 and L4 of thespacers spacer 111 is increased in order to suppress the dark current on thefloating diffusion 103 side, the length L3 of thespacer 110, which is formed to have the same size as thespacer 111, may be deviated from an optimal value. Conversely, in the case where the length L3 of thespacer 110 is optimized in order to strike the balance between the characteristics of the dark current and the afterimage on thephotodiode 102 side, the length L4 of thespacer 111, which is formed to have the same size as thespacer 110, becomes too short, resulting in the increase in the dark current. For this reason, in related art, an appropriate control on both the suppression of the dark current on thefloating diffusion 103 side and the optimization of the dark current and the afterimage on thephotodiode 102 side is difficult to be performed. - In view of the above-mentioned circumstances, it is desirable to provide a solid-state image sensor, a method of manufacturing the same, and an image pickup apparatus that are capable of simultaneously realizing a suppression of a dark current on a charge detector side and an optimization of characteristics of a dark current and an afterimage on a photoelectric converter side.
- According to an embodiment of the present invention, there is provided a solid-state image sensor, comprising a photoelectric converter, a charge detector, and a transfer transistor. The photoelectric converter stores a signal charge that is subjected to photoelectric conversion. The charge detector detects the signal charge. The transfer transistor transfers the signal charge from the photoelectric converter to the charge detector. The transfer transistor includes a gate insulating film, a gate electrode formed on the gate insulating film, a first spacer formed on a sidewall of the gate electrode on a side of the photoelectric converter, and a second spacer formed on another sidewall of the gate electrode on a side of the charge detector. The first spacer is shorter than the second spacer.
- In the solid-state image sensor according to the embodiment of the present invention, on the photoelectric converter side, the length of the first spacer can be set in accordance with an optimal value for striking characteristics of a dark current and an after image regardless of the length of the second spacer. In addition, on the charge detector side, the length of the second spacer can be set in accordance with a size suitable for suppressing the dark current regardless of the length of the first spacer.
- According to another embodiment of the present invention, there is provided a first method of manufacturing a solid-state image sensor. The method includes forming a gate electrode on a semiconductor substrate through a first insulating film, etching the gate electrode so that a part of the gate electrode on a side of a photoelectric converter formation region is lower than a part of the gate electrode on a side of a charge detector formation region, forming a second insulating film on the semiconductor substrate in a state of covering the first insulating film and the gate electrode, and etching the first insulating film and the second insulating film so that a first spacer formed on a sidewall of the gate electrode on the side of the photoelectric converter formation region is shorter than a second spacer formed on a sidewall of the gate electrode on the side of the charge detector formation region.
- In the first method of manufacturing the solid-state image sensor according to the embodiment of the present invention, obtained is the solid-state image sensor in which the first spacer formed on the sidewall of the gate electrode on the photoelectric converter formation region side is set to be shorter than the second spacer formed on the sidewall of the gate electrode on the charge detector formation region side. Further, the length of the first spacer can be controlled with the amount of etching by which the gate electrode is etched being set as a process parameter, and the length of the second spacer can be controlled with a thickness of the second insulating film being set as a process parameter.
- According to another embodiment of the present invention, there is provided a second method of manufacturing a solid-state image sensor. The second method includes forming a gate electrode on a semiconductor substrate through a first insulating film, forming a second insulating film on the semiconductor substrate in a state of covering the first insulating film and the gate electrode, etching the first insulating film and the second insulating film so that a first spacer formed on a sidewall of the gate electrode on a side of a photoelectric converter formation region has the same length as a second spacer formed on a sidewall of the gate electrode on a side of a charge detector formation region, and etching the first spacer so that the first spacer is shorter than the second spacer.
- In the second method of manufacturing the solid-state image sensor according to the embodiment of the present invention, obtained is the solid-state image sensor in which the first spacer formed on the sidewall of the gate electrode on the photoelectric converter formation region side is set to be shorter than the second spacer formed on the sidewall of the gate electrode on the charge detector formation region side. Further, the length of the first spacer can be controlled with the amount of etching by which the first spacer is etched being set as a process parameter, and the length of the second spacer can be controlled with a thickness of the second insulating film being set as a process parameter.
- According to the embodiments of the present invention, in the solid-state image sensor including the photoelectric converter, the charge detector, and the transfer transistor, suppression of the dark current on the charge detector side and striking of the balance between the characteristics of the dark current and the after image can be realized at the same time.
- These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of best mode embodiments thereof, as illustrated in the accompanying drawings.
-
FIG. 1 is a schematic view showing a structural example of a CMOS solid-state image sensor as an example of a solid-state image sensor to which the present invention is applied; -
FIG. 2 is an enlarged cross-sectional view showing a part of a solid-state image sensor according to a first embodiment of the present invention; -
FIGS. 3A and 3B are diagrams (part 1) for explaining a method of manufacturing the solid-state image sensor according to the first embodiment of the present invention; -
FIGS. 4A and 4B are diagrams (part 2) for explaining the method of manufacturing the solid-state image sensor according to the first embodiment of the present invention; -
FIG. 5 is an enlarged cross-sectional view showing a part of a solid-state image sensor according to a second embodiment of the present invention; -
FIGS. 6A and 6B are diagrams (part 1) for explaining a method of manufacturing the solid-state image sensor according to the second embodiment of the present invention; -
FIGS. 7A and 7B are diagrams (part 2) for explaining the method of manufacturing the solid-state image sensor according to the second embodiment of the present invention; -
FIG. 8 is a block diagram showing a structural example of an image pickup apparatus to which the present invention is applied; and -
FIG. 9 is a cross-sectional view showing an example of a solid-state image sensor in related art. - Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the technical scope of the present invention is not limited to the following embodiments and includes various modifications and alternations insofar as they are within the scope in which specific effects can be obtained from constituents of the present invention and combinations thereof.
- The embodiments of the present invention will be described in an order of the following items.
-
- 1. Overall structure of solid-state image sensor
- 2. Structure of solid-state image sensor according to first embodiment
- 3. Method of manufacturing solid-state image sensor according to first embodiment
- 4. Structure of solid-state image sensor according to second embodiment
- 5. Method of manufacturing solid-state image sensor according to second embodiment
- 6. Application example
-
FIG. 1 is a schematic diagram showing a structural example of a CMOS solid-state image sensor as an example of a solid-state image sensor to which the present invention is applied. A solid-state image sensor 10 shown inFIG. 1 includes aunit pixel 11, avertical scanning circuit 12, a verticalscanning pulse driver 13, ahorizontal selection transistor 14, and ahorizontal scanning circuit 15. Theunit pixels 11 are two-dimensionally disposed in a matrix pattern to form an imaging area. Thevertical scanning circuit 12 is provided outside the imaging area. - The
unit cell 11 is constituted of a photodiode PD and four transistors of atransfer transistor 22, anamplification transistor 23, areset transistor 24, and anXY address transistor 25. For each of thepixel transistors 22 to 25, a MOS transistor is used. It should be noted that in this case, only the unit pixel in an m-th row and an n-th column is shown for simplification of the figure. - In the
unit pixel 11, thetransfer transistor 22 has a source connected to a cathode of the photodiode PD and a drain connected to a gate of theamplification transistor 23. A connection portion of the drain of thetransfer transistor 22 and the gate of theamplification transistor 23 corresponds to a floating diffusion FD. The drain of theamplification transistor 23 is connected to a power source VDD, and the source thereof is connected to a vertical signal line 26. - The
reset transistor 24 has a drain connected to a vertical reset line 27, a source connected to the connection potion (FD) between the drain of thetransfer transistor 22 and the gate of theamplification transistor 23, and a gate connected to a horizontal reset line 28. TheXY address transistor 25 has a gate connected to avertical read line 29, a drain connected to ahorizontal read line 30, and a source connected to the gate of thetransfer transistor 22. - Outside the image pickup area, the
vertical scanning circuit 12 sequentially outputs vertical read scanning pulses φVRm (φVR1, φVR2, . . . , φVRm, . . . , φVRM) and vertical reset scanning pulses φVSm (φVS1, φVS2, . . . , φVSm, . . . , φVSM). The vertical read scanning pulses VRm are applied to thevertical read line 29 in the corresponding row. The vertical reset scanning pulses φVSm are applied to the vertical reset line 27 in the corresponding row through the verticalscanning pulse driver 13. - The vertical
scanning pulse driver 13 has a circuit terminal on the power source side that is connected to apower source line 31 of the power source voltage VDD and a circuit terminal on a GND side that is connected to aGND line 32. The verticalscanning pulse driver 13 drives the vertical reset line 27 based on the vertical reset scanning pulses φVSm supplied from thevertical scanning circuit 12. At this time, the verticalscanning pulse driver 13 shifts a GND level of theGND line 32 to about 0.5 to 0.8 V, with the vertical reset scanning pulses φVSm being at an “L” level, to be given to the vertical reset line 27. - The
horizontal scanning circuit 15 sequentially outputs horizontal read scanning pulses φHRn (φHR1, φHR2, . . . , φHRn, . . . , φHRN), horizontal selection scanning pulses φHn (φH1, φH2, . . . , φHn, . . . , φHN), and horizontal reset scanning pulse φHSn (φHS1, φHS2, . . . , φHSn, . . . , φHSN). The horizontal read scanning pulses φHRn are applied to thehorizontal read line 30 of a corresponding column. The horizontal reset scanning pulses φHSn are applied to the horizontal reset line 28 of a corresponding column. The horizontal selection scanning pulses φHn are applied to the gate of thehorizontal selection transistor 14 of a corresponding column. Thehorizontal selection transistor 14 is connected between an end of the vertical signal line 26 and ahorizontal signal line 33 for each column. -
FIG. 2 is an enlarged cross-sectional view of the solid-state image sensor according to the first embodiment of the present invention. InFIG. 2 , on asemiconductor substrate 51, the photodiode PD, the floating diffusion FD, and thetransfer transistor 22 described above are formed. The photodiode PD serves as the photoelectric converter for storing a signal charge that has been subjected to a photoelectric conversion. More specifically, the photodiode PD converts incident light to an electric signal depending on a light amount thereof and generates a signal charge, and stores the generated signal charge therein. The photodiode PD has a P-N junction structure including an N-type impurity region 52 and a P-type impurity region 53. The floating diffusion FD serves as the charge detector that detects the signal charge transferred by thetransfer transistor 22 from the photodiode PD. The floating diffusion FD is formed of an N-type impurity region 54. - The
transfer transistor 22 transfers the signal charge stored through the photoelectric conversion by the photodiode PD to the floating diffusion FD. Thetransfer transistor 22 includes the photodiode PD and the floating diffusion FD as source and drain regions, respectively. Thetransfer transistor 22 is provided with agate insulating film 55, agate electrode 56, afirst spacer 57, and asecond spacer 58. Thegate insulating film 55 is formed between the photodiode PD and the floating diffusion FD. Thegate electrode 56 is formed on thegate insulating film 55. Thefirst spacer 57 is disposed on a sidewall of thegate electrode 56 on a side of the photodiode PD. Thesecond spacer 58 is disposed on the other sidewall of thegate electrode 56 on a side of the floating diffusion FD. In addition, the P-type impurity region 53 is formed in a self-aligned manner with respect to thefirst spacer 57, and the N-type impurity region 54 is formed in the self-aligned manner with respect to thesecond spacer 58. - On the
semiconductor substrate 51, thefirst spacer 57 and thesecond spacer 58 are asymmetrically formed. More specifically, when a length L1 of thefirst spacer 57 and a length L2 of thesecond spacer 58 are compared with each other, the length L1 of thefirst spacer 57 is set to be shorter than the length L2 of thesecond spacer 58. The length of the spacer refers to a spacer size in a length direction (hereinafter, also referred to as “gate length direction”) of thegate electrode 56. The length direction of thegate electrode 56 corresponds to a horizontal direction inFIG. 2 , and a width direction of thegate electrode 56 corresponds to a depth direction inFIG. 2 . The length of the spacer is defined by a size from the sidewall of thegate electrode 56 to an end portion of the spacer in the length direction of thegate electrode 56. Therefore, the length L1 of thefirst spacer 57 is defined by the size from the one sidewall of thegate electrode 56 to the end portion of thefirst spacer 57, and the length L2 of thesecond spacer 58 is defined from the other sidewall of thegate electrode 56 to the end portion of thesecond spacer 58. - The length L1 of the
first spacer 57 is set to an optimal size for striking a balance between characteristics of a dark current and an afterimage on the photodiode PD side. The length L2 of thesecond spacer 58 is set to a size suitable for suppressing a dark current on the floating diffusion FD side. The size optimal for striking the balance between the characteristics of the dark current and the afterimage on the photodiode PD side is smaller than the size suitable for suppressing the dark current on the floating diffusion FD side. Therefore, the length L1 of thefirst spacer 57 is set to be shorter than the length L2 of thesecond spacer 58 as described above. - Further, on an upper surface of the
gate electrode 56, a step is formed. By providing the step, a height of thegate electrode 56 on the photodiode PD side is lower than a height of thegate electrode 56 on the floating diffusion FD side. The height of thegate electrode 56 refers to a size of the gate electrode in a thickness direction of thesemiconductor substrate 51. When the height of thegate electrode 56 is defined from a boundary surface between thegate insulating film 55 and thegate electrode 56, a height H1 of thegate electrode 56 on the photodiode PD side is lower than a height H2 of thegate electrode 56 on the floating diffusion FD side. -
FIGS. 3A , 3B, 4A, and 4B are diagrams for explaining a method of manufacturing the solid-state image sensor according to the first embodiment of the present invention. First, as shown inFIG. 3A , on thesemiconductor substrate 51, a first insulatingfilm 61 and thegate electrode 56 are formed in this order, along with an element isolation region (not shown). The first insulatingfilm 61 corresponds to thegate insulating film 55 as described above, and is formed so as to broadly cover an upper surface of thesemiconductor substrate 51 in this stage. Thegate electrode 56 is formed into a predetermined shape by a patterning process. Subsequently, an ion implantation of N-type impurities is performed to thesemiconductor substrate 51, thereby forming the N-type impurity region 52. Here, to thesemiconductor substrate 51, aphotodiode formation region 59 in which the photodiode PD is formed and a floatingdiffusion formation region 60 in which the floating diffusion FD is formed are provided. Thephotodiode formation region 59 is provided on the side opposite to the floatingdiffusion formation region 60 with respect to thegate electrode 56. The N-type impurity region 52 is formed by performing the ion implantation of the N-type impurities to thephotodiode formation region 59. - Next, as shown in
FIG. 3B , thegate electrode 56 is selectively etched so that the height H1 of thegate electrode 56 on thephotodiode formation region 59 side is lower than the height H2 of thegate electrode 56 on the floatingdiffusion formation region 60 side. In this case, the height H1 of thegate electrode 56 on thephotodiode formation region 59 side is determined in consideration of the length L1 (see,FIG. 2 ) of thefirst spacer 57 formed in the following process. - Next, as shown in
FIG. 4A , on thesemiconductor substrate 51, a second insulatingfilm 62 is formed in a state of covering the first insulatingfilm 61 and thegate electrode 56. In this case, the second insulatingfilm 62 is deposited so as to cover the entire surface of thesemiconductor substrate 51. At this time, a thickness of the second insulatingfilm 62 is determined in consideration of the length L2 (see,FIG. 2 ) of thesecond spacer 58 formed in the following process. - Next, as shown in
FIG. 4B , the first insulatingfilm 61 and the second insulatingfilm 62 are etched (etching back process), thereby exposing the surface (upper surface) of thesemiconductor substrate 51. As a result, thefirst spacer 57 is formed on the sidewall of thegate electrode 56 on thephotodiode formation region 59 side, and thesecond spacer 58 is formed on the other sidewall of thegate electrode 56 on the floatingdiffusion formation region 60 side. In this case, thefirst spacer 57 is formed of an insulating material protruded from the sidewall of thegate electrode 56 toward thephotodiode formation region 59 side. Thesecond spacer 58 is formed of an insulating material protruded from the other sidewall of thegate electrode 56 toward the floatingdiffusion formation region 60 side. In addition, in the etching process of the first insulatingfilm 61 and the second insulatingfilm 62, the first and second insulatingfilms gate electrode 56. In this way, on the lower side of thegate electrode 56, thegate insulating film 55 is formed of the insulating material of the first insulatingfilm 61. In addition, on the one sidewall of thegate electrode 56, thefirst spacer 57 is formed of the insulating material of the first insulatingfilm 61 and the second insulatingfilm 62, and on the other sidewall of thegate electrode 56, thesecond spacer 58 is formed of the insulating material of the first insulatingfilm 61 and the second insulatingfilm 62. - The lengths L1 and L2 of the
spacers film 61 and the second insulatingfilm 62 become longer as the heights H1 and H2 of thegate electrode 56 are increased. Further, the length L1 of thefirst spacer 57 depends on the height H1 of thegate electrode 56 on thephotodiode formation region 59 side, and the length L2 of thesecond spacer 58 depends on the height H2 of thegate electrode 56 on the floatingdiffusion formation region 60 side. In this case, the heights H1 and H2 of thegate electrode 56 has a relationship of “H1<H2”. Therefore, in accordance with this relationship, the length L1 of thefirst spacer 57 is formed to be shorter than the length L2 of thesecond spacer 58. - Next, by performing the ion implantation of the P-type impurities to the
semiconductor substrate 51 with thephotodiode formation region 59 being a target, the P-type impurity region 53 is formed. Further, by performing the ion implantation of the N-type impurities to thesemiconductor substrate 51 with the floatingdiffusion formation region 60 being a target, the N-type impurity region 54 is formed. The P-type impurity region 53 is formed by performing the ion implantation of the P-type impurities to thesemiconductor substrate 51 with thefirst spacer 57 being a mask. Therefore, the P-type impurity region 53 is formed in the self-aligned manner with respect to thefirst spacer 57. The N-type impurity region 54 is formed by performing the ion implantation of the N-type impurities to thesemiconductor substrate 51 with thesecond spacer 58 being a mask. Therefore, the N-type impurity region 54 is formed in the self-aligned manner with respect to thesecond spacer 58. In this stage, the photodiode PD constituted of the N-type impurity region 52 and the P-type impurity region 53 and the floating diffusion FD formed of the N-type impurity region 54 are formed. As a result, the solid-state image sensor having the structure shown inFIG. 2 can be obtained. - In the first embodiment of the present invention, in the structure of the solid-state image sensor, the length L1 of the
first spacer 57 is set to be shorter than the length L2 of thesecond spacer 58. Therefore, on the photodiode PD side, regardless of the length L2 of thesecond spacer 58, the length L1 of thefirst spacer 57 can be set in accordance with the optimal value for striking the balance between the characteristics of the dark current and the afterimage. In addition, on the floating diffusion FD side, regardless of the length L1 of thefirst spacer 57, the length L2 of thesecond spacer 58 can be set in accordance with the size suitable for suppressing the dark current. As a result, the suppression of the dark current on the floating diffusion FD side and the striking of the balance between the characteristics of the dark current and the afterimage on the photodiode PD side can be realized at the same time. - In addition, in the first embodiment of the present invention, in the structure of the solid-state image sensor, the height of the
gate electrode 56 on the photodiode PD side is set to be lower than that of thegate electrode 56 on the floating diffusion FD side. Therefore, the second insulatingfilm 62 having the uniform thickness is formed on thesemiconductor substrate 51, and then the first insulatingfilm 61 and the second insulatingfilm 62 are just etched, with the result that the structure of the solid-state image sensor in which the length L1 of thefirst spacer 57 is shorter than the length L2 of thesecond spacer 58 can be realized. - Further, in the process of manufacturing the solid-state image sensor, the height H1 of the
gate electrode 56 on thephotodiode formation region 59 side is determined depending on the amount of etching at the time when thegate electrode 56 is selectively etched. In addition, the length L1 of thefirst spacer 57 depends on the height H1 of thegate electrode 56 on thephotodiode formation region 59 side. Therefore, the length L1 of thefirst spacer 57 can be controlled with the amount of etching at the time when thegate electrode 56 is selectively etched being set as a process parameter. Further, in the process of manufacturing the solid-state image sensor, the height H2 of thegate electrode 56 on the floatingdiffusion formation region 60 side is determined depending on the deposition thickness by which the second insulatingfilm 62 is deposited. Further, the length L2 of thesecond spacer 58 depends on the height H2 of thegate electrode 56 on the floatingdiffusion formation region 60 side. Therefore, the length L2 of thesecond spacer 58 can be controlled with the deposition thickness of the second insulatingfilm 62 being set as a process parameter. As a result, the length L1 of thefirst spacer 57 and the length L2 of thesecond spacer 58 can be controlled independently of each other. Thus, the suppression of the dark current on the floating diffusion FD side and the striking of the balance between the characteristics of the dark current and the afterimage on the photodiode PD side can be realized at the same time. -
FIG. 5 is an enlarged cross-sectional view showing a part of a solid-state image sensor according to a second embodiment of the present invention. It should be noted that in the second embodiment of the present invention, the same components as those of the first embodiment are denoted by the same reference numerals or symbols. InFIG. 5 , thesemiconductor substrate 51 is provided with the photodiode PD serving as the photoelectric converter and the floating diffusion FD serving as the charge detector. The photodiode PD has a P-N junction structure including the N-type impurity region 52 and the P-type impurity region 53. The floating diffusion FD is formed of the N-type impurity region 54. Thetransfer transistor 22 includes thegate insulating film 55, thegate electrode 56, thefirst spacer 57, and thesecond spacer 58. Further, on thesemiconductor substrate 51, thefirst spacer 57 and thesecond spacer 58 are asymmetrically formed. That is, when the length L1 of thefirst spacer 57 and the length L2 of thesecond spacer 58 are compared, the length L1 of thefirst spacer 57 is set to be shorter than the length L2 of thesecond spacer 58. The structure mentioned above is the same as that of the first embodiment. - Here, in the first embodiment, by providing the step to the
gate electrode 56, the height of thegate electrode 56 on the photodiode PD side and that on the floating diffusion FD side are set to be different. In contrast, in this embodiment, a step is not formed on thegate electrode 56, and thegate electrode 56 on the photodiode PD side and that on the floating diffusion FD side are the same. -
FIGS. 6A , 6B, 7A, and 7B are diagrams for explaining a method of manufacturing the solid-state image sensor according to the second embodiment of the present invention. First, as shown inFIG. 6A , on thesemiconductor substrate 51, the first insulatingfilm 61 and thegate electrode 56 are formed in addition to an element isolation region (not shown). The first insulatingfilm 61 corresponds to thegate insulating film 55 and is formed so as to broadly cover the upper surface of thesemiconductor substrate 51 in this stage. Thegate electrode 56 is formed into a predetermined shape by a patterning process. Subsequently, an ion implantation of N-type impurities is performed to thesemiconductor substrate 51, thereby forming the N-type impurity region 52. As in the case of the first embodiment, to thesemiconductor substrate 51, thephotodiode formation region 59 and the floatingdiffusion formation region 60 are provided. The N-type impurity region 52 is formed by performing the ion implantation of the N-type impurities to thephotodiode formation region 59. - Next, as shown in
FIG. 6B , on thesemiconductor substrate 51, the second insulatingfilm 62 is formed in a state of covering thegate insulating film 55 and thegate electrode 56. In this case, the second insulatingfilm 62 is deposited so as to cover the entire surface of thesemiconductor substrate 51. At this time, the thickness of the second insulatingfilm 62 is determined in consideration of the length L2 (see,FIG. 2 ) of thesecond spacer 58 formed in the following process. - Next, as shown in
FIG. 7A , the first insulatingfilm 61 and the second insulatingfilm 62 are etched (etching back process), thereby exposing the surface (upper surface) of thesemiconductor substrate 51. As a result, thefirst spacer 57 is formed on a sidewall of thegate electrode 56 on thephotodiode formation region 59 side, and thesecond spacer 58 is formed on the other sidewall of thegate electrode 56 on the floatingdiffusion formation region 60 side. In this case, thefirst spacer 57 is formed of an insulating material protruded from the sidewall of thegate electrode 56 toward thephotodiode formation region 59 side. Thesecond spacer 58 is formed of an insulating material protruded from the other sidewall of thegate electrode 56 toward the floatingdiffusion formation region 60 side. In addition, in the etching process of the first insulatingfilm 61 and the second insulatingfilm 62, the first and second insulatingfilms gate electrode 56. In this way, on the lower side of thegate electrode 56, thegate insulating film 55 is formed of the insulating material of the first insulatingfilm 61. In addition, on the sidewall of thegate electrode 56, thefirst spacer 57 is formed of the insulating material of the first insulatingfilm 61 and the second insulatingfilm 62, and on the other sidewall of thegate electrode 56, thesecond spacer 58 is formed of the insulating material of the first insulatingfilm 61 and the second insulatingfilm 62. In this stage, thefirst spacer 57 and thesecond spacer 58 are symmetrically formed. Therefore, the length L1 of thefirst spacer 57 and the length L2 of thesecond spacer 58 are the same. - Next, as shown in
FIG. 7B , thefirst spacer 57 on thephotodiode formation region 59 side is selectively etched, thereby reducing the length L1 of thefirst spacer 57. In this stage, thefirst spacer 57 and thesecond spacer 58 are asymmetrically formed, and the length L1 of thefirst spacer 57 is set to be shorter than the length L2 of thesecond spacer 58. - Next, by performing the ion implantation of the P-type impurities to the
semiconductor substrate 51 with thephotodiode formation region 59 being a target, the P-type impurity region 53 is formed. Further, by performing the ion implantation of the N-type impurities to thesemiconductor substrate 51 with the floatingdiffusion formation region 60 being a target, the N-type impurity region 54 is formed. The P-type impurity region 53 is formed by performing the ion implantation of the P-type impurities to thesemiconductor substrate 51 with thefirst spacer 57 being a mask. Therefore, the P-type impurity region 53 is formed in the self-aligned manner with respect to thefirst spacer 57. The N-type impurity region 54 is formed by performing the ion implantation of the N-type impurities to thesemiconductor substrate 51 with thesecond spacer 58 being a mask. Therefore, the N-type impurity region 54 is formed in the self-aligned manner with respect to thesecond spacer 58. In this stage, the photodiode PD constituted of the N-type impurity region 52 and the P-type impurity region 53 and the floating diffusion FD formed of the N-type impurity region 54 are formed. As a result, the solid-state image sensor having the structure shown inFIG. 5 can be obtained. - In the second embodiment of the present invention, in the structure of the solid-state image sensor, the length L1 of the
first spacer 57 is set to be shorter than the length L2 of thesecond spacer 58. Therefore, on the photodiode PD side, regardless of the length L2 of thesecond spacer 58, the length L1 of thefirst spacer 57 can be set in accordance with the optimal value for striking the balance between the characteristics of the dark current and the afterimage. In addition, on the floating diffusion FD side, regardless of the length L1 of thefirst spacer 57, the length L2 of thesecond spacer 58 can be set in accordance with the size suitable for suppressing the dark current. As a result, the suppression of the dark current on the floating diffusion FD side and the striking of the balance between the characteristics of the dark current and the afterimage on the photodiode PD side can be realized at the same time. - Further, in the process of manufacturing the solid-state image sensor, the length L1 of the
first spacer 57 is determined depending on the amount of etching at the time when thefirst spacer 57 is selectively etched. Therefore, the length L1 of thefirst spacer 57 can be controlled with the amount of etching at the time when thefirst spacer 57 is selectively etched being set as a process parameter. Further, in the process of manufacturing the solid-state image sensor, the height of thegate electrode 56 is determined depending on the deposition thickness by which the second insulatingfilm 62 is deposited. Further, the length L2 of thesecond spacer 58 depends on the height of thegate electrode 56. Therefore, the length L2 of thesecond spacer 58 can be controlled with the deposition thickness of the second insulatingfilm 62 being set as a process parameter. As a result, the length L1 of thefirst spacer 57 and the length L2 of thesecond spacer 58 can be controlled independently of each other. Thus, the suppression of the dark current on the floating diffusion FD side and the striking of the balance between the characteristics of the dark current and the afterimage on the photodiode PD side can be realized at the same time. - It should be noted that in the second embodiment, the
first spacer 57 and thesecond spacer 58 are symmetrically formed by etching the insulatingfilms first spacer 57 is selectively etched to shorten the length L1 thereof, but the present invention is not limited to this. For example, after thefirst spacer 57 and thesecond spacer 58 are symmetrically formed by etching the insulatingfilms second spacer 58, thereby increasing the length of the spacer on the floating diffusion FD side. -
FIG. 8 is a block diagram showing a structural example of an image pickup apparatus to which the present invention is applied. An image pickup apparatus 90 shown inFIG. 8 includes an optical system having alens group 91, a solid-stateimage pickup apparatus 92, aDSP circuit 93, aframe memory 94, adisplay apparatus 95, arecording apparatus 96, anoperation system 97, and apower source system 98. Among those components, theDSP circuit 93, theframe memory 94, thedisplay apparatus 95, therecording apparatus 96, theoperation system 97, and thepower source system 98 are mutually connected through a bus line 99. - The
lens group 91 collects incident light (image light) from a subject and forms an image on an imaging surface of the solid-stateimage pickup apparatus 92. The solid-stateimage pickup apparatus 92 converts a light amount of the incident light that is imaged on the imaging surface by thelens group 91 into an electrical signal for each pixel, and outputs it as a pixel signal. As an element structure of the solid-stateimage pickup apparatus 92, the structure of the solid-state image sensor described above is applied. - The
display apparatus 95 is formed of a panel-type display apparatus such as a liquid crystal display apparatus and an organic EL (electro-luminescence) display apparatus, and displays a moving image or a still image taken by the solid-stateimage pickup apparatus 92. Therecording apparatus 96 records the moving image or the still image taken by the solid-stateimage pickup apparatus 92 on a recording medium such as a non-volatile memory, a videotape, and a DVD (digital versatile disk). - The
operation system 97 gives operation commands for various functions of the image pickup apparatus 90 under the control of a user who uses the image pickup apparatus 90. Thepower source system 98 appropriately supplies various power sources as operation sources to theDSP circuit 93, theframe memory 94, thedisplay apparatus 95, therecording apparatus 96, and theoperation system 97. - The image pickup apparatus 90 as described above is applied to a camera module for a mobile apparatus, such as a video camera, a digital still camera, and a camera cellular phone. But, in addition to those modules, the present invention can also be applied to, for example, vehicles such as an automobile and an airplane in which a camera equipped with the solid-state image sensor is incorporated. In this case, in an example of an automobile, in a system that displays, on an in-car display apparatus, a blind spot for a driver by taking an image thereof, the element structure according to the above embodiments can be employed as the solid-state image sensor for cameras incorporated in the front, the back, the sides of the automobile. In addition, vehicles such as an automobile and an airplane equipped with the solid-state image sensor that uses the element structure of the above embodiments can be a form of the image pickup apparatus according to the present invention, in addition to the camera module for the mobile apparatus described above.
- It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
Claims (2)
1. A method of manufacturing a solid-state image sensor, comprising:
forming a gate electrode on a semiconductor substrate through a first insulating film;
etching the gate electrode so that a part of the gate electrode on a side of a photoelectric converter formation region is lower than a part of the gate electrode on a side of a charge detector formation region;
forming a second insulating film on the semiconductor substrate in a state of covering the first insulating film and the gate electrode; and
forming, by etching the first insulating film and the second insulating film, a first spacer on a sidewall of the gate electrode on the side of the photoelectric converter formation region and a second spacer on a sidewall of the gate electrode on the side of the charge detector formation region.
2. A method of manufacturing a solid-state image sensor, comprising:
forming a gate electrode on a semiconductor substrate through a first insulating film;
forming a second insulating film on the semiconductor substrate in a state of covering the first insulating film and the gate electrode;
forming, by etching the first insulating film and the second insulating film, a first spacer on a sidewall of the gate electrode on a side of a photoelectric converter formation region and a second spacer on a sidewall of the gate electrode on a side of a charge detector formation region; and
etching the first spacer.
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US13/832,438 US20130288422A1 (en) | 2009-01-16 | 2013-03-15 | Solid-state image sensor, method of manufacturing the same, and image pickup apparatus |
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JP2009007346A JP5446280B2 (en) | 2009-01-16 | 2009-01-16 | Solid-state imaging device, manufacturing method thereof, and imaging apparatus |
JPP2009-007346 | 2009-01-16 | ||
US12/657,047 US8450780B2 (en) | 2009-01-16 | 2010-01-13 | Solid-state imaging sensor, method of manufacturing the same, and image pickup apparatus |
US13/832,438 US20130288422A1 (en) | 2009-01-16 | 2013-03-15 | Solid-state image sensor, method of manufacturing the same, and image pickup apparatus |
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JP2014150230A (en) * | 2013-02-04 | 2014-08-21 | Toshiba Corp | Solid state image pickup device manufacturing method and solid state image pickup device |
TWI676280B (en) * | 2014-04-18 | 2019-11-01 | 日商新力股份有限公司 | Solid-state imaging device and electronic device therewith |
JP2017130577A (en) | 2016-01-21 | 2017-07-27 | ソニー株式会社 | Semiconductor device and manufacturing method of the same, solid-state image pickup element and electronic apparatus |
US10536652B2 (en) * | 2018-01-08 | 2020-01-14 | Semiconductor Components Industries, Llc | Image sensors with split photodiodes |
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US20050277239A1 (en) * | 2004-06-09 | 2005-12-15 | Dongbuanam Semiconductor Inc. | Method for manufacturing CMOS image sensor |
US20070145509A1 (en) * | 2005-12-28 | 2007-06-28 | Lim Keun H | CMOS Image Sensor and Method for Manufacturing the Same |
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JP2827882B2 (en) * | 1994-02-24 | 1998-11-25 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JP2707977B2 (en) * | 1994-09-01 | 1998-02-04 | 日本電気株式会社 | MOS type semiconductor device and method of manufacturing the same |
JPH1032327A (en) * | 1996-07-12 | 1998-02-03 | Nittetsu Semiconductor Kk | Semiconductor device, its manufacture formation of resist pattern, and reticle used for the formation |
JPH10116986A (en) * | 1996-08-22 | 1998-05-06 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
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JP2000138369A (en) * | 1998-10-30 | 2000-05-16 | Sharp Corp | Manufacture of semiconductor device |
KR100345669B1 (en) | 2000-08-18 | 2002-07-24 | 주식회사 하이닉스반도체 | Image sensor having nonsymmetric spacer on each side wall of transfer transistor gate electrode and method for forming the same |
JP2004335588A (en) * | 2003-05-01 | 2004-11-25 | Renesas Technology Corp | Solid state imaging apparatus and its manufacturing method |
JP2005311496A (en) * | 2004-04-19 | 2005-11-04 | Sony Corp | Solid-state imaging apparatus |
JP2006134951A (en) * | 2004-11-02 | 2006-05-25 | Matsushita Electric Ind Co Ltd | Solid state imaging device |
KR100672701B1 (en) * | 2004-12-29 | 2007-01-22 | 동부일렉트로닉스 주식회사 | CMOS Image sensor and method for fabricating the same |
US7205591B2 (en) * | 2005-04-06 | 2007-04-17 | International Business Machines Corporation | Pixel sensor cell having reduced pinning layer barrier potential and method thereof |
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US20050277239A1 (en) * | 2004-06-09 | 2005-12-15 | Dongbuanam Semiconductor Inc. | Method for manufacturing CMOS image sensor |
US20070145509A1 (en) * | 2005-12-28 | 2007-06-28 | Lim Keun H | CMOS Image Sensor and Method for Manufacturing the Same |
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US20100181602A1 (en) | 2010-07-22 |
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