US20130285216A1 - Semiconductor structure having low thermal stress - Google Patents

Semiconductor structure having low thermal stress Download PDF

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US20130285216A1
US20130285216A1 US13/926,419 US201313926419A US2013285216A1 US 20130285216 A1 US20130285216 A1 US 20130285216A1 US 201313926419 A US201313926419 A US 201313926419A US 2013285216 A1 US2013285216 A1 US 2013285216A1
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layer
semiconductor structure
substrate
epitaxy
epitaxy layer
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US8629534B2 (en
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Shih-Cheng Huang
Po-Min Tu
Shun-Kuei Yang
Chia-Hung Huang
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Advanced Optoelectronic Technology Inc
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Advanced Optoelectronic Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02614—Transformation of metal, e.g. oxidation, nitridation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present disclosure relates to a semiconductor structure and a method for manufacturing thereof, and more particularly, to a semiconductor structure having low thermal stress and a method for manufacturing thereof.
  • An LED often includes an LED chip to emit light.
  • a conventional LED chip includes a substrate, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially grown on the substrate.
  • the substrate is generally made of sapphire (Al 2 O 3 ) for providing growing environment to the layers.
  • sapphire substrate has a low heat conductive capability, causing that heat generated by the layers cannot be timely dissipated. Therefore, a new type substrate made of Si is developed. Such Si substrate has a heat conductive index larger than the sapphire substrate so that the heat generated by the layers can be effectively removed.
  • the coefficient of thermal expansion (CTE) of the Si substrate does not well match with that of the layers.
  • the Si substrate has a deformation different from that of the layers, resulting in a thermal stress concentrated at an interface between the substrate and the layers. Such concentrated thermal stress may cause fracture of the layers or even damage of the LED chip.
  • FIG. 1 shows a first process of manufacturing a semiconductor structure of a first embodiment of the present disclosure.
  • FIG. 2 shows a second process of manufacturing the semiconductor structure of the first embodiment of the present disclosure.
  • FIG. 3 shows a third process of manufacturing the semiconductor structure of the first embodiment of the present disclosure.
  • FIG. 4 shows a forth process of manufacturing the semiconductor structure of the first embodiment of the present disclosure.
  • FIG. 5 shows a fifth process of manufacturing the semiconductor structure of the first embodiment of the present disclosure.
  • FIG. 6 shows the semiconductor structure of the first embodiment which has been manufactured after the processes of FIGS. 1-5 .
  • FIG. 7 shows a semiconductor structure of a second embodiment which has been manufactured after the processes of FIGS. 1-5 .
  • the present disclosure discloses a semiconductor structure which has a low thermal stress.
  • the semiconductor structure includes a substrate 100 , a supporting layer 101 a and a blocking layer 103 alternately formed on a top face of the substrate 100 and an epitaxy layer 104 formed on the supporting layer 101 a.
  • the substrate 100 may be made of sapphire, Si, SiC or GaN, wherein Si is preferable in the present disclosure.
  • the material of Si has a heat conductive index larger than that of sapphire so that the substrate 100 can have a better heat conduction capability.
  • the supporting layer 101 a may be an AlN or Al 2 O 3 layer.
  • the supporting layer 101 a is divided by multiple grooves 105 to form a plurality of spaced islands.
  • the blocking layer 103 is discontinuously distributed in the grooves 105 to be alternate with the islands of the supporting layer 101 a.
  • the blocking layer 103 may be a SiO 2 or Si 3 N 4 layer which has a thickness far less than that of the blocking layer 101 a.
  • the thickness of the blocking layer 103 is about one-fifth (1 ⁇ 5) of that of the blocking layer 101 a.
  • the epitaxy layer 104 includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer (not shown) sequentially grown from a top face of the supporting layer 101 a.
  • the N-type semiconductor layer may be an N-doped GaN, AlGaN, InGaN or AlInGaN layer
  • the P-type semiconductor layer may be a P-doped GaN, AlGaN, InGaN or AlInGaN layer
  • the light-emitting layer may be a multi-quantum well structure.
  • the blocking layer 103 prevents the epitaxy layer 104 from growing on a top surface thereof, the epitaxy layer 104 can only be grown on the top face of the supporting layer 101 a vertically and upwardly. During vertical growth, the eiptaxy layer 104 also has a lateral growing trend so that discrete parts of the epitaxy layer 104 grown from the top face of the supporting layer 101 a would join with each other at places over the blocking layer 103 . The epitaxy layer 104 is thus grown to a continuous layer.
  • the epitaxy layer 104 forms a plurality of triangle slots 106 over the blocking layer 103 and communicating with the grooves 105 , respectively. Each of the slots 106 has a width gradually decreasing along a direction from the substrate 100 towards the epitaxy layer 104 .
  • the temperature of the environment in step 5) can be controlled according to the thickness of the aluminum film 101 and reaction time of the aluminum film 101 and the substrate 100 ; however, a temperature higher than 1000° C. is preferable in the present disclosure.
  • the lateral growing of the epitaxy layer 104 can be limited to leave the slots 106 a extending through the whole epitaxy layer 104 .
  • the epitaxy layer 104 is thus divided by the slots 106 a to plural of individual islands.
  • the width D of each groove 105 and the thickness d of the epitaxy layer 104 should conform to the relation of D>2 d, to realize the separation between the islands of the epitaxy layer 104 .
  • Such discrete islands of the epitaxy layer 104 can be directly used as LED chips without further dicing, thereby reducing manufacturing process of the semiconductor structure.
  • a buffer layer (not shown) can be formed on the top face of the supporting layer 101 a before growing the epitaxy layer 104 .
  • the buffer layer can provide better growing environment for the epitaxy layer 104 so that less dislocations would be generated within the epitaxy layer 104 .
  • the buffer layer can be made of GaN, AN or other suitable materials.
  • the grooves 105 between bottom areas of the epitaxy layer 104 can effectively relieve concentrated thermal stress between the epitaxy layer 104 and the substrate 100 , thereby protecting the epitaxy layer 104 from facture.
  • lateral faces of the epitaxy layer 104 defining the slots 106 can totally reflect more light emitted downwardly from the epitaxy layer 104 towards a top face of the epitaxy layer 104 , thereby increasing light-extracting efficiency of the semiconductor structure.

Abstract

A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This patent application is a divisional application of patent application Ser. No. 12/975,235, filed on Dec. 21, 2010, entitled “SEMICONDUCTOR STRUCTURE HAVING LOW THERMAL STRESS AND METHOD FOR MANUFACTURING THEREOF”, which is assigned to the same assignee as the present application, and which is based on and claims priority from Chinese Patent Application No. 201010217575.0 filed in China on Jul. 05, 2010. The disclosures of patent application Ser. No. 12/975,235 and the Chinese Patent Application No. 201010217575.0 are incorporated herein by reference in their entirety.
    • Background
  • 1. Technical Field
  • The present disclosure relates to a semiconductor structure and a method for manufacturing thereof, and more particularly, to a semiconductor structure having low thermal stress and a method for manufacturing thereof.
  • 2. Description of Related Art
  • As new type light source, LEDs are widely used in various applications. An LED often includes an LED chip to emit light. A conventional LED chip includes a substrate, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer sequentially grown on the substrate. The substrate is generally made of sapphire (Al2O3) for providing growing environment to the layers. However, such sapphire substrate has a low heat conductive capability, causing that heat generated by the layers cannot be timely dissipated. Therefore, a new type substrate made of Si is developed. Such Si substrate has a heat conductive index larger than the sapphire substrate so that the heat generated by the layers can be effectively removed.
  • Nevertheless, the coefficient of thermal expansion (CTE) of the Si substrate does not well match with that of the layers. Thus, during operation of the LED chip, the Si substrate has a deformation different from that of the layers, resulting in a thermal stress concentrated at an interface between the substrate and the layers. Such concentrated thermal stress may cause fracture of the layers or even damage of the LED chip.
  • What is needed, therefore, is a semiconductor structure which can overcome the limitations described above.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
  • FIG. 1 shows a first process of manufacturing a semiconductor structure of a first embodiment of the present disclosure.
  • FIG. 2 shows a second process of manufacturing the semiconductor structure of the first embodiment of the present disclosure.
  • FIG. 3 shows a third process of manufacturing the semiconductor structure of the first embodiment of the present disclosure.
  • FIG. 4 shows a forth process of manufacturing the semiconductor structure of the first embodiment of the present disclosure.
  • FIG. 5 shows a fifth process of manufacturing the semiconductor structure of the first embodiment of the present disclosure.
  • FIG. 6 shows the semiconductor structure of the first embodiment which has been manufactured after the processes of FIGS. 1-5.
  • FIG. 7 shows a semiconductor structure of a second embodiment which has been manufactured after the processes of FIGS. 1-5.
    •  DETAILED DESCRIPTION OF THE EMBODIMENTS
  • Referring to FIG. 6, the present disclosure discloses a semiconductor structure which has a low thermal stress. The semiconductor structure includes a substrate 100, a supporting layer 101 a and a blocking layer 103 alternately formed on a top face of the substrate 100 and an epitaxy layer 104 formed on the supporting layer 101 a.
  • The substrate 100 may be made of sapphire, Si, SiC or GaN, wherein Si is preferable in the present disclosure. The material of Si has a heat conductive index larger than that of sapphire so that the substrate 100 can have a better heat conduction capability. The supporting layer 101 a may be an AlN or Al2O3 layer. The supporting layer 101 a is divided by multiple grooves 105 to form a plurality of spaced islands. The blocking layer 103 is discontinuously distributed in the grooves 105 to be alternate with the islands of the supporting layer 101 a. The blocking layer 103 may be a SiO2 or Si3N4 layer which has a thickness far less than that of the blocking layer 101 a. Preferably, the thickness of the blocking layer 103 is about one-fifth (⅕) of that of the blocking layer 101 a. The epitaxy layer 104 includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer (not shown) sequentially grown from a top face of the supporting layer 101 a. The N-type semiconductor layer may be an N-doped GaN, AlGaN, InGaN or AlInGaN layer, the P-type semiconductor layer may be a P-doped GaN, AlGaN, InGaN or AlInGaN layer, and the light-emitting layer may be a multi-quantum well structure. Since the blocking layer 103 prevents the epitaxy layer 104 from growing on a top surface thereof, the epitaxy layer 104 can only be grown on the top face of the supporting layer 101 a vertically and upwardly. During vertical growth, the eiptaxy layer 104 also has a lateral growing trend so that discrete parts of the epitaxy layer 104 grown from the top face of the supporting layer 101 a would join with each other at places over the blocking layer 103. The epitaxy layer 104 is thus grown to a continuous layer. The epitaxy layer 104 forms a plurality of triangle slots 106 over the blocking layer 103 and communicating with the grooves 105, respectively. Each of the slots 106 has a width gradually decreasing along a direction from the substrate 100 towards the epitaxy layer 104.
  • Also referring to FIGS. 1-5, a method for manufacturing the above semiconductor structure is given below, including steps:
      • 1) providing a Si substrate 100;
      • 2) forming an aluminum film 101 on the substrate 100, the aluminum film 101 can be formed on the substrate 101 by thermal evaporation, E-beam evaporation, ion-beam sputtering, chemical vapor deposition, physical vapor deposition or electroplating;
      • 3) forming a patterned photoresist layer 102 on the aluminum film 101, the photoresist layer 102 being patterned by lithography to form multiple gapped areas, in which the shapes of the areas can be selected from circle, rectangle, triangle or other suitable shapes, depending on actual requirements;
      • 4) etching the aluminum film 101, wherein since parts of the aluminum film 101 just below the gapped areas of the photoresist layer 102 are protected by the photoresist layer 102, they would not be etched and continue remaining on the top face of the substrate 100; while the other parts of the aluminum film 101 exposed under gaps between the areas of the photoresist layer 102 would be fully etched to expose the top face of the substrate 100;
      • 5) removing the photoresist layer 102 by etching or other methods to expose the remaining aluminum film 101;
      • 6) putting the substrate 100 into a high-temperature environment containing plenty of O2 or N2, in which the aluminum film 101 on the substrate 100 is oxidized or nitrided to Al2O3 or AlN to thereby form a supporting layer 101 a, and the exposed top face of the Si substrate 100 is oxidized or nitrided to SiO2 or Si3N4 to thereby form a blocking layer 103; and
      • 7) growing an epitaxy layer 104 on the supporting layer 101 a.
  • The temperature of the environment in step 5) can be controlled according to the thickness of the aluminum film 101 and reaction time of the aluminum film 101 and the substrate 100; however, a temperature higher than 1000° C. is preferable in the present disclosure.
  • Also referring to FIG. 7, by controlling relation between a width D of each groove 105 and a thickness d of the epitaxy layer 104, the lateral growing of the epitaxy layer 104 can be limited to leave the slots 106 a extending through the whole epitaxy layer 104. The epitaxy layer 104 is thus divided by the slots 106 a to plural of individual islands. Preferably, the width D of each groove 105 and the thickness d of the epitaxy layer 104 should conform to the relation of D>2 d, to realize the separation between the islands of the epitaxy layer 104. Such discrete islands of the epitaxy layer 104 can be directly used as LED chips without further dicing, thereby reducing manufacturing process of the semiconductor structure.
  • Furthermore, a buffer layer (not shown) can be formed on the top face of the supporting layer 101 a before growing the epitaxy layer 104. The buffer layer can provide better growing environment for the epitaxy layer 104 so that less dislocations would be generated within the epitaxy layer 104. The buffer layer can be made of GaN, AN or other suitable materials.
  • The grooves 105 between bottom areas of the epitaxy layer 104 can effectively relieve concentrated thermal stress between the epitaxy layer 104 and the substrate 100, thereby protecting the epitaxy layer 104 from facture. In addition, since difference of the refractive index between the epitaxy layer 104 and air contained within the slots 106, lateral faces of the epitaxy layer 104 defining the slots 106 can totally reflect more light emitted downwardly from the epitaxy layer 104 towards a top face of the epitaxy layer 104, thereby increasing light-extracting efficiency of the semiconductor structure.
  • It is believed that the present disclosure and its advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the present disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments.

Claims (9)

What is claimed is:
1. A semiconductor structure comprising:
a substrate;
a supporting layer formed on a face of the substrate and consisting of a plurality of discrete islands and a plurality of grooves each between two adjacent islands of the supporting layer;
a blocking layer formed on the face of the substrate and consisting of a plurality of discrete portions alternate with the islands of the supporting layer; and
an epitaxy layer formed on the islands of the supporting layer;
wherein the plurality of grooves are below the epitaxy layer, and the portions of the blocking layer are in the grooves, respectively.
2. The semiconductor structure as claimed in claim 1, wherein the blocking layer has a thickness less than that of the supporting layer.
3. The semiconductor structure as claimed in claim 1, wherein the epitaxy layer has a plurality of slots defined in a bottom face thereof, each of the slots communicating with a corresponding groove.
4. The semiconductor structure as claimed in claim 3, wherein each of the slots has a width gradually decreasing along a direction from the substrate towards the epitaxy layer.
5. The semiconductor structure as claimed in claim 3, wherein each of the slots is terminated within the epitaxy layer.
6. The semiconductor structure as claimed in claim 3, wherein each of the slots is extended through the epitaxy layer to divide the epitaxy layer into a plurality of individual parts.
7. The semiconductor structure as claimed in claim 1, wherein the blocking layer is made of SiO2 or Si3N4.
8. The semiconductor structure as claimed in claim 1, wherein the supporting layer is made of Al2O3 or AlN.
9. The semiconductor structure as claimed in claim 1, wherein the substrate is made of Si.
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CN201010217575.0A CN102315347B (en) 2010-07-05 2010-07-05 Light emitting diode epitaxial structure and manufacture method thereof
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US12/975,235 US8501582B2 (en) 2010-07-05 2010-12-21 Semiconductor structure having low thermal stress and method for manufacturing thereof
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