US20130205114A1 - Object-based memory storage - Google Patents

Object-based memory storage Download PDF

Info

Publication number
US20130205114A1
US20130205114A1 US13/835,109 US201313835109A US2013205114A1 US 20130205114 A1 US20130205114 A1 US 20130205114A1 US 201313835109 A US201313835109 A US 201313835109A US 2013205114 A1 US2013205114 A1 US 2013205114A1
Authority
US
United States
Prior art keywords
data
storage device
storage
volatile
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/835,109
Inventor
Anirudh Badam
David Nellans
Robert Wipfel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Technologies LLC
Original Assignee
Fusion IO LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/952,098 external-priority patent/US20080140724A1/en
Application filed by Fusion IO LLC filed Critical Fusion IO LLC
Priority to US13/835,109 priority Critical patent/US20130205114A1/en
Publication of US20130205114A1 publication Critical patent/US20130205114A1/en
Assigned to FUSION-IO, INC. reassignment FUSION-IO, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WIPFEL, ROBERT, BADAM, ANIRUDH, NELLANS, DAVID
Assigned to FUSION-IO, LLC reassignment FUSION-IO, LLC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: Fusion-io, Inc
Assigned to SanDisk Technologies, Inc. reassignment SanDisk Technologies, Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUSION-IO, LLC
Assigned to SanDisk Technologies, Inc. reassignment SanDisk Technologies, Inc. CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO'S 13/925,410 AND 61/663,464 PREVIOUSLY RECORDED AT REEL: 035168 FRAME: 0366. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: FUSION-IO, LLC
Assigned to FUSION-IO, LLC reassignment FUSION-IO, LLC CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO'S 13/925,410 AND 61/663,464 PREVIOUSLY RECORDED AT REEL: 034838 FRAME: 0091. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Assignors: Fusion-io, Inc
Assigned to SanDisk Technologies, Inc. reassignment SanDisk Technologies, Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LONGITUDE ENTERPRISE FLASH SARL
Assigned to SANDISK TECHNOLOGIES LLC reassignment SANDISK TECHNOLOGIES LLC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SANDISK TECHNOLOGIES INC
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661Format or protocol conversion arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0674Disk device
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/14Mounting supporting structure in casing or on frame or rack
    • H05K7/1438Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
    • H05K7/1439Back panel mother boards
    • H05K7/1444Complex or three-dimensional-arrangements; Stepped or dual mother boards
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/10Indexing scheme relating to G06F11/10
    • G06F2211/1002Indexing scheme relating to G06F11/1076
    • G06F2211/1014Compression, i.e. RAID systems with parity using compression techniques
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7201Logical to physical mapping or translation of blocks or pages
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7202Allocation control and policies
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/01Protocols
    • H04L67/10Protocols in which an application is distributed across nodes in the network
    • H04L67/1097Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Definitions

  • a block-based approach can improve performance time for certain types of storage devices, such as magnetic disk drives or other drives that include mechanical movement for reading/writing/erasing data stored on the storage devices. Due to the mechanical movement, random access to the storage devices is more time expensive than sequential access. Block-based approaches typically write data to physically sequential addresses on the storage devices to reduce access time.
  • Block-based approaches also typically access blocks of a predetermined size, regardless of whether the data being written to or read from the storage devices fills an entire block. Additionally, applications often use objects (which may vary greatly in size) as a basis of programming. Object based programming frequently uses an object store on top of the block storage layer or other block abstraction to be able to store and track the location of each object on the storage device.
  • block-based approaches may not be necessary to optimize the access speed of the flash memory.
  • many flash memory devices still use a block-based approach, which introduces unnecessary programming and operating system resource overheads because of the need to maintain tables and to perform read-modify-writes necessary for garbage collection and for compacting live objects to minimize fragmentation of data on the storage device.
  • FIG. 1 depicts a schematic diagram of one embodiment of a computing device in a network system.
  • FIG. 2 depicts a schematic diagram of one embodiment of a non-volatile storage device.
  • FIG. 3 depicts a schematic diagram of one embodiment of a storage controller.
  • FIG. 4A depicts a schematic diagram of one embodiment of a log structure in a memory device.
  • FIG. 4B depicts a schematic diagram of one embodiment of a table.
  • FIG. 5 depicts a schematic diagram of garbage collection in a log structure on a memory device.
  • FIG. 6 depicts a flow chart diagram of one embodiment of a method for object based storage on a memory device.
  • Reference to a computer readable medium may take any physical form capable of storing machine-readable instructions, at least for a time in a non-transient state, on a digital processing apparatus.
  • a computer readable medium may be embodied by a compact disk, digital-video disk, a blu-ray disc, a magnetic tape, a Bernoulli drive, a magnetic disk, flash memory, integrated circuits, or other digital processing apparatus memory device.
  • the storage device may be any type of memory device, including a volatile storage device or non-volatile storage device, configured to store data.
  • non-volatile memory examples include flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon-oxide based sub-10 nanometer process memory, graphene memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), Resistive random-access memory (RRAM), programmable metallization cell (PMC), conductive-bridging RAM (CBRAM), magneto-resistive RAM (MRAM), dynamic RAM (DRAM), phase change RAM (PRAM), phase change memory or other non-volatile solid-state storage media.
  • the non-volatile memory may comprise magnetic media, optical media, or other types of non-volatile storage media.
  • the non-volatile storage device may include a hard disk drive, an optical storage drive, or the like.
  • the non-volatile memory is referred to herein as a “memory device,” a “recording device” or a “storage device” in various embodiments, the non-volatile memory may more generally include a non-volatile recording media capable of recording data, the non-volatile recording media may be referred to as a non-volatile memory media, a non-volatile storage media, or the like. Further, the non-volatile storage device, in various embodiments, may include a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, or the like.
  • the storage device may be any other storage device that may be configured to store data at a non-block based granularity.
  • the storage device may be connected to or in communication with a backing store.
  • the storage device may be configured to operate as a memory cache for storing data that is stored on the backing store.
  • the storage device may be configured to operate as a backing store or main storage device.
  • the storage device may be connected to or in communication with other similar storage devices.
  • the backing store may be any type of backing store, such as a hard disk drive or other type of non-volatile storage device.
  • the access speed (or “seek time”) of hard disk drives is generally limited due to the mechanical components of the drives.
  • the access speed of memory devices such as flash devices is generally much faster than the access speed of hard disk drives.
  • the storage device is a memory cache
  • at least some of the data on the backing store may be stored (or “cached”) on the storage device to allow an operating system or other application to quickly access the data from the storage device rather than the backing store.
  • the storage device may not be a memory cache, but may be an additional backing store or other non-volatile storage device configured store applications and/or data associated with the computing device, and the backing store may also store applications and/or data associated with the computing device.
  • Object-based programming use objects to describe states and operations. Because so many applications use object-based programming, interactions between applications and storage devices that are block-based typically require additional programming and operating system resources, including an object store on top of the block abstraction that allows the operating system and other applications to interact with the block-based storage device. Because flash memory devices do not necessarily have to operate at a block granularity, operating the flash memory devices at a granularity that is more compatible with applications that operate at an object granularity may improve the speed and efficiency of the operating system and storage device.
  • a storage device that is configured to operate at a block granularity or at an object-level granularity may eliminate the need for an additional object store on top of storage layers for the storage device.
  • Performing operations on the storage device at an operation-specific granularity includes performing the operations for the specific size of data associated with the operation.
  • the object data associated with the operation may have any size, and an object-level granularity corresponds to the size of the data (such as the object size/length), rather than to a predetermined block size.
  • FIG. 1 depicts a schematic diagram of one embodiment of a computing device 102 in a network system 100 .
  • the depicted network system 100 includes various components, described in more detail below, that are capable of performing the functions and operations described herein.
  • at least some of the components of the network system 100 are implemented on the computing device 102 .
  • the functionality of one or more components of the network system may be implemented by computer program instructions stored and executed on the computing device 102 .
  • the network system 100 may be implemented in a clustered environment or network 128 with additional computer devices.
  • the computing device 102 may include various components, including a processor 104 (such as a CPU), input/output devices 106 , a memory device 108 , a storage manager 112 , an object store 120 , a block storage layer 114 , a device driver 122 , and a disk controller 116 .
  • the computing device 102 includes a backing store 118 .
  • the backing store 118 is not contained within the computing device 102 , but may be a standalone backing store 118 or part of another computing device 102 or system.
  • the computing device 102 may also include or be connected to one or more storage devices 122 configured to act as a memory cache or as a primary storage device.
  • Some or all of the components of the network system 100 may be stored on a single computing device 102 or on a network 128 of computing devices 102 , including a wired and/or wireless communication network.
  • the network system 100 may include more or fewer components or subsystems than those depicted herein. In some embodiments, the network system 100 may be used to implement the methods described herein.
  • the illustrated network system 100 also includes a client application 110 .
  • the client application 110 uses object-based programming.
  • the client application 110 may be any application that submits access requests to the backing store 118 to perform read/write/erase operations on the backing store 118 .
  • the client application 110 may also submit access requests to the storage device 122 to perform operations on the storage device 122 .
  • the client application 110 may be an operating system (OS), a file system, a database, or some other application capable of submitting access requests to the backing store 118 .
  • OS operating system
  • the client application 110 operates in conjunction with the storage manager 112 to access data from either the storage device 122 or the backing store 118 .
  • the storage manager 112 accesses the backing store 118 via the block storage layer 114 .
  • the storage manager 112 may be implemented via software in some embodiments.
  • the block storage layer 114 may be implemented in a device driver 120 , a volume manager or driver interface.
  • the block storage layer 114 provides support to the storage manager for block-based file systems, including traditional file systems, database systems, and other software designed for magnetic disk drives.
  • the block storage layer 114 may provide support to the storage manager 112 for the backing store 118 and other block-based storage devices.
  • the computing device 102 may include a disk controller 116 between the block storage layer 114 and the backing store 118 to allow the block storage layer 114 to correctly locate data or specific sectors on the backing store 118 .
  • the backing store 118 is a block-based backing store 118 , such that an object store 120 is built on top of the block storage layer 114 so that the client application 110 is able to interface with the backing store 118 .
  • the storage manager 112 accesses the storage device 122 via a device driver 120 or other driver interface.
  • the storage device 122 may operate at a non-block granularity.
  • the device driver 120 may interface with the storage device to perform object-based storage for the storage device 122 . In one embodiment, at least some of the operations for object-based storage are implemented at each of the storage device 122 and the device driver 120 .
  • the storage device 122 may include a hardware device manager, such as a controller 124 , that provides at least some of the functionality for object-based storage.
  • the hardware device manager is a hardware storage device manager.
  • the hardware device manager is a hardware memory device manager.
  • the hardware device manager may comprise a device driver 120 configured to control a storage device 122 .
  • the hardware device manager may comprise a device driver 120 configured to control a non-volatile memory device (not illustrated).
  • the controller 124 may be a device interface for interacting with the device driver 120 .
  • the controller 124 may include hardware, firmware, device driver and/or software implementations, or any combination thereof.
  • the storage manager 112 accesses the storage device via the driver 120 .
  • the controller 124 on the storage device 122 exposes direct access to memory elements 126 on the storage device 122 to the device driver 120 .
  • the controller 124 maintains a log structure on the storage device 122 and presents the log structure to the device driver 120 .
  • the device driver 120 may cooperate with hardware support offered by the controller 124 corresponding to the storage device 122 .
  • the device driver 120 may provide support for any type of storage granularity, including an object-level granularity, which may include mapping physical addresses for the memory elements 126 to logical addresses or virtual addresses.
  • object-level granularity may reduce programming requirements or operating system resources needed to interact with the storage device 122 because object-level granularity performs the operations associated with access requests at a granularity or size for the specific data associated with the access requests. For example, an object operation may be performed directly on the storage device 122 at a granularity that corresponds to the size of the object of the object operation, rather than at a granularity that corresponds to a predetermined block size for block-based storage media. Implementing such functions at the device driver 120 also eliminates the need for a separate address translation layer at the controller 124 on the storage device 122 .
  • Address translation for the backing store 118 or storage device 122 may include operating independently of an existing operating system and file system to map physical addresses such as physical block addresses (PBAs) of the memory elements 126 to the logical block addresses (LBAs) in an organized structure.
  • PBAs physical block addresses
  • LBAs logical block addresses
  • the address translation for example at the device driver 120 or block storage layer 114 , operates in conjunction with an existing operating system on the computing device 102 to map the physical addresses of the memory elements 126 or backing store 118 to the LBAs.
  • the LBAs allow storage manager 112 to maintain a logical organization for the storage device while potentially storing related data in different physical locations in the storage device.
  • the device driver 120 may also manage where data is written so that data is written to the correct locations in the storage device 122 based on where the storage device 122 has been cleaned or erased, so that subsequent access requests to the data are directed to the correct physical locations in the storage device 122 .
  • the storage manager 112 or an address translation layer also may map the LBAs to PBAs on the backing store 118 , in an embodiment in which the backing store 118 is not a block-based storage device. This may allow the ATL to manage and track the data on the backing store 118 . In one embodiment, the ATL maps an LBA to a single PBA of the backing store 118 .
  • the device driver 120 manages storing allocation information for each object within the storage device 122 .
  • Each object corresponds to a virtual location presented by the device driver 120 to the operating system and higher level software layers.
  • access requests are processed at an object-level or operation-specific granularity, rather than predetermined blocks.
  • the granularity corresponds to a physical address (or group of physical addresses) of the memory elements 126 associated with the operation.
  • the device driver 120 may translate the logical address presented by the client application 110 to one or more physical addresses of the corresponding memory elements 126 .
  • the device driver 120 or storage manager 112 may perform additional mapping if needed. In order to facilitate these mappings, the device driver 120 may manage various data structures.
  • the device driver 120 may manage a table (such as an indirection table) for tracking the location and size of each object on the storage device 122 .
  • the device driver 120 may manage the objects in a log-structured manner.
  • the indirection table and/or log structure for the storage device 122 may be stored on the computing device 102 (for example, in memory 108 ) or on the storage device 122 .
  • the storage device 122 may be any kind of storage device 122 .
  • the storage device 122 may be a non-volatile storage device in which data stored on the storage device 122 persists across reboots, such that on reboot of the storage device 122 , the data may need to be invalidated for various reasons. These reasons may include, but are not limited to, changes in the data for the corresponding locations on the backing store and/or storing information related to the ATL in volatile memory which is erased during a reboot.
  • memory elements 126 in the storage device 122 for storing data are organized in an array or in multiple arrays.
  • the storage device 122 may be a volatile storage device or a caching device implemented using any known caching technology.
  • the memory elements 126 are cells that are part of an integrated circuit (IC) package or chip. Each chip may include one or more die, and each die includes an array of memory elements 126 .
  • the storage device 122 may be used for storing data associated with the computing device 102 or other computing devices 102 connected to a network 128 .
  • the computing device 102 is shown with two storage devices 122 , other embodiments of the computing device 102 may include one or more than one storage device 122 .
  • multiple storage devices 122 may be implemented at various locations within the nodes of the network 128 .
  • Embodiments of the network 128 may provide dedicated or shared memory resources for one or more of the computing devices 102 , though other implementations of storage/memory resources or capacity may be used in conjunction with the network 128 .
  • the memory elements 126 may be operated in a variety of modes. In general, solid-state memory elements 126 can be set to different programmable states that correspond to different bits or bit combinations. In a specific example, the memory elements 126 may be operated in a single level cell (SLC) mode to store a single bit of data. In another example, the memory elements 126 may be operated in a multiple level cell (MLC) mode to store two or more bits of data. In another example, the memory elements 126 may be MLC memory elements configured to operate in an SLC mode. In other embodiments, the storage device 122 includes other types of memory elements 126 .
  • SLC single level cell
  • MLC multiple level cell
  • MLC multiple level cell
  • the memory elements 126 may be MLC memory elements configured to operate in an SLC mode.
  • the storage device 122 includes other types of memory elements 126 .
  • the components of the network system 100 are shown separately, one or more components may provide some or all of the functionality of other components in the network system 100 .
  • the storage manager 112 is depicted between the client application 110 and the block storage layer 114 and device driver 120 , some or all of the functionality of the storage manager 112 may be implemented at the client application 110 or at either the block storage layer 114 or the device driver 120 .
  • some or all of the functionality of the block storage layer 114 and device driver 120 may be implemented at the storage manager 112 .
  • the components of the computing device 102 may be different than shown in FIG. 1 while being configured to perform the operations described herein.
  • the controller 124 on the storage device 122 interfaces with the device driver 120 to perform the operations for storing data corresponding to access requests from the client application 110 at an object-level or operation-specific granularity.
  • the operation-specific granularity is determined by the data associated with the access request.
  • the data may correspond to an object associated with the client application 110 .
  • the data is stored on the storage device 122 or accessed from the storage device 120 (or other operation associated with the access request, such as creating or destroying objects) at an object-level granularity, rather than a block granularity as with block-based storage devices.
  • the device driver 120 and controller 124 may be able to perform various functions associated with storing objects on the storage device 122 .
  • the functions may include object operations such as: creating an object with an associated object identifier; destroying an object stored on the storage device 122 ; reading an object from the storage device 122 based on the associated object identifier and a size of the object; and writing data associated with an object already present on the storage device 122 based on the object identifier and a size of the object.
  • the functions may include maintaining an indirection table that may be used to track the location and sizes of the objects on the storage device 122 .
  • the functions may include performing read/write operations on the storage device 122 at an arbitrary granularity, as described in accordance with the object operations.
  • the functions may include garbage collection on the storage device 122 to maintain the log structure of the storage device 122 by eliminating dead objects and consolidating (or compacting) live objects on the storage device 122 .
  • Dead objects may include objects that are no longer used or referenced by the client application 110 .
  • Live objects may include valid data for objects used or referenced by the client application 110 .
  • the storage device 122 may also include dirty objects. Dirty objects may be objects that are new, modified, or deleted, but that have not been committed to the storage device 122 or backing store 118 .
  • the functions may include performing read-modify-write operations on object data stored on the storage device.
  • FIG. 2 depicts a schematic diagram of one embodiment 200 of a non-volatile storage device 122 that includes a non-volatile storage device controller 124 .
  • the storage device controller 124 is the storage device controller of FIG. 1 .
  • the non-volatile storage device controller 124 may include a number of storage controllers 0 -N 204 a - n , each controlling non-volatile storage media 205 . In the depicted embodiment, two non-volatile controllers are shown: non-volatile controller 0 204 a and storage controller N 204 n , and each controlling respective non-volatile storage media 205 a - n .
  • storage controller 0 204 a controls a data channel so that the attached non-volatile storage media 205 a stores data.
  • Storage controller N 204 n controls an index metadata channel associated with the stored data and the associated non-volatile storage media 205 n stores index metadata.
  • the non-volatile storage device controller 124 includes a single non-volatile controller 204 a with a single non-volatile storage media 205 a .
  • At least one non-volatile controller 204 is a field-programmable gate array (“FPGA”) and controller functions are programmed into the FPGA.
  • the storage controller 204 includes components specifically designed as a storage controller 204 , such as an application-specific integrated circuit (“ASIC”) or custom logic solution.
  • ASIC application-specific integrated circuit
  • Each storage controller 204 typically includes a write data pipeline 301 and a read data pipeline 303 , which are describe further in relation to FIG. 3 .
  • at least one storage controller 204 is made up of a combination FPGA, ASIC, and custom logic components.
  • the non-volatile storage media 205 is an array of non-volatile non-volatile storage elements 216 , 218 , 220 , arranged in banks 214 , and accessed in parallel through a bi-directional storage input/output (“I/O”) bus 210 .
  • the storage I/O bus 210 in one embodiment, is capable of unidirectional communication at any one time. For example, when data is being written to the non-volatile storage media 205 , data cannot be read from the non-volatile storage media 205 . In another embodiment, data can flow both directions simultaneously.
  • bi-directional refers to a data pathway that can have data flowing in only one direction at a time, but when data flowing one direction on the bi-directional data bus is stopped, data can flow in the opposite direction on the bi-directional data bus.
  • a non-volatile storage element (e.g., SSS 0 . 0 216 a ) is typically configured as a chip (a package of one or more dies) or a die on a circuit board.
  • a non-volatile storage element (e.g., 216 a ) operates independently or semi-independently of other non-volatile storage elements (e.g., 218 a ) even if these several elements are packaged together in a chip package, a stack of chip packages, or some other package element.
  • a row of non-volatile storage elements 216 a , 216 b , 216 m is designated as a bank 214 .
  • n there may be “n” banks 214 a - n and “m” non-volatile storage elements 216 a - m , 218 a - m , 220 a - m per bank in an array of n ⁇ m non-volatile storage elements 216 , 218 , 220 in a non-volatile storage media 205 .
  • a non-volatile storage media 205 a includes twenty non-volatile storage elements 216 a - 216 m per bank 214 with eight banks 214 .
  • the non-volatile storage media 205 a includes twenty-four non-volatile storage elements 216 a - 216 m per bank 214 with eight banks 214 .
  • one or more additional columns (P) may also be addressed and operated in parallel with other non-volatile storage elements 216 a , 216 b , 216 m for one or more rows.
  • the added P columns in one embodiment, store parity data for the portions of an ECC chunk (i.e., an ECC codeword) that span m storage elements for a particular bank.
  • each non-volatile storage element 216 , 218 , 220 includes single-level cell (“SLC”) devices. In another embodiment, each non-volatile storage element 216 , 218 , 220 includes multi-level cell (“MLC”) devices.
  • SLC single-level cell
  • MLC multi-level cell
  • non-volatile storage elements that share a common line 211 on the storage I/O bus 210 a are packaged together.
  • a non-volatile storage element 216 , 218 , 220 may have one or more dies per package with one or more packages stacked vertically and each die may be accessed independently.
  • a non-volatile storage element e.g., SSS 0 . 0 216 a
  • SSS 0 . 0 216 a may have one or more virtual dies per die and one or more dies per package and one or more packages stacked vertically and each virtual die may be accessed independently.
  • a non-volatile storage element SSS 0 . 0 216 a may have one or more virtual dies per die and one or more dies per package with some or all of the one or more dies stacked vertically and each virtual die may be accessed independently.
  • two dies are stacked vertically with four stacks per group to form eight storage elements (e.g., SSS 0 . 0 -SSS 8 . 0 ) 216 a , 218 a . . . 220 a , each in a separate bank 214 a , 214 b . . . 214 n .
  • 24 storage elements e.g., SSS 0 . 0 -SSS 0 . 24
  • 216 a , 216 b , . . . 216 m form a logical bank 214 a so that each of the eight logical banks has 24 storage elements (e.g., SSS 0 .
  • Data is sent to the non-volatile storage media 205 over the storage I/O bus 210 to all storage elements of a particular group of storage elements (SSS 0 . 0 -SSS 8 . 0 ) 216 a , 218 a , 220 a .
  • the storage control bus 212 a is used to select a particular bank (e.g., Bank 0 214 a ) so that the data received over the storage I/O bus 210 connected to all banks 214 is written just to the selected bank 214 a.
  • the storage I/O bus 210 includes one or more independent I/O buses ( 210 a.a - m . . . 210 n.a - m ) in which the non-volatile storage elements within each column share one of the independent I/O buses that are connected to each non-volatile storage element 216 , 218 , 220 in parallel.
  • one independent I/O bus 210 a.a of the storage I/O bus 210 a may be physically connected to a first non-volatile storage element 216 a , 218 a , 220 a of each bank 214 a - n .
  • a second independent I/O bus 210 a.b of the storage I/O bus 210 b may be physically connected to a second non-volatile storage element 216 b , 218 b , 220 b of each bank 214 a - n .
  • Each non-volatile storage element 216 a , 216 b , 216 m in a bank 214 a (a row of non-volatile storage elements as illustrated in FIG. 2 ) may be accessed simultaneously and/or in parallel.
  • non-volatile storage elements 216 , 218 , 220 include stacked packages of dies, all packages in a particular stack are physically connected to the same independent I/O bus.
  • Simultaneously also includes near simultaneous access where devices are accessed at slightly different intervals to avoid switching noise. Simultaneously is used in this context to be distinguished from a sequential or serial access in which commands and/or data are sent individually one after the other.
  • banks 214 a - n are independently selected using the storage control bus 212 .
  • a bank 214 is selected using a chip enable or chip select. Where both chip select and chip enable are available, the storage control bus 212 may select one package within a stack of packages. In other embodiments, other commands are used by the storage control bus 212 to individually select one package within a stack of packages.
  • Non-volatile storage elements 216 , 218 , 220 may also be selected through a combination of control signals and address information transmitted on storage I/O bus 210 and the storage control bus 212 .
  • a physical address is sent on the storage I/O bus 210 and is followed by the packet.
  • the physical address contains enough information for the non-volatile storage element 216 to direct the packet to the designated location. Since all storage elements in a column of storage elements (e.g., SSS 0 . 0 -SSS N. 0 216 a , 218 a , . . . 220 a ) are connected to the same independent I/O bus (e.g., 210 .
  • the bank 214 a that includes the non-volatile storage element SSS 0 . 0 216 a with the correct location where the data packet is to be written is selected by the storage control bus 212 a and other banks 214 b . . . 214 n of the non-volatile storage 110 a are deselected.
  • a read command on the storage I/O bus 210 requires a signal on the storage control bus 212 to select a single bank 214 a and the appropriate location within that bank 214 a .
  • a read command reads an entire set of addresses, and because there are multiple non-volatile storage elements 216 a , 216 b , . . . 216 m in parallel in a bank 214 a , an entire logical group of addresses is read with a read command.
  • the read command may be broken into subcommands, as will be explained below with respect to bank interleave.
  • an entire logical group of addresses may be written to the non-volatile storage elements 216 a , 216 b , .
  • the group of addresses read from or written to the non-volatile storage elements 216 a , 216 b , . . . 216 m correspond to the particular operation and a size of the object corresponding to the operation.
  • An erase command may be sent out to erase a group of addresses corresponding to an object over the storage I/O bus 210 with a particular erase address to erase a particular group of addresses.
  • storage controller 204 a may send an erase command over the parallel paths (independent I/O buses 210 a - n.a - m ) of the storage I/O bus 210 to erase a logical group of addresses, each with a particular address to erase a particular group of addresses.
  • a particular bank e.g., Bank 0 214 a
  • no particular bank e.g., Bank 0 214 a
  • the storage control bus 212 or all of the banks are selected to enable erasure of similarly addressed locations in all of the banks (Banks 1 -N 214 b - n ) in parallel.
  • Other commands may also be sent to a particular location using a combination of the storage I/O bus 210 and the storage control bus 212 .
  • One of skill in the art will recognize other ways to select a particular storage location using the bi-directional storage I/O bus 210 and the storage control bus 212 .
  • packets are written sequentially to the non-volatile storage media 205 .
  • storage controller 204 a streams packets to storage write buffers of a bank 214 a of storage elements 216 and, when the buffers are full, the packets are programmed to a designated logical location.
  • Storage controller 204 a then refills the storage write buffers with packets and, when full, the packets are written to the next logical location.
  • the next logical location may be in the same bank 214 a or another bank (e.g., 214 b ).
  • This process continues, logical location after logical location, typically until the addresses corresponding to an object for the particular operation are erased.
  • the streaming may continue across logical boundaries for multiple objects.
  • the read/write/erase operations may result in operations being performed on varying numbers of non-volatile storage elements 216 a , 216 b , . . . 216 m according to the objects associated with the access requests.
  • a read, modify, write operation data packets associated with requested data are located and read in a read operation.
  • Data segments of the modified requested data that have been modified are not written to the location from which they are read. Instead, the modified data segments are again converted to data packets and then written sequentially to the next available location according to a log structure.
  • the index entries for the respective data packets are modified to point to the packets that contain the modified data segments.
  • the entry or entries in the index for data packets associated with the same requested data that have not been modified will include pointers to original location of the unmodified data packets.
  • the original requested data is maintained, for example to maintain a previous version of the requested data, the original requested data will have pointers in the index to all data packets as originally written.
  • the new requested data may have pointers in the index to some of the original data packets and pointers to the modified data packets in the logical location that is currently being written.
  • the index includes an entry for the original requested data mapped to a number of packets stored in the non-volatile storage media 205 .
  • a new copy of the requested data is created and a new entry is created in the index mapping the new copy of the requested data to the original packets.
  • the new copy of the requested data is also written to the non-volatile storage media 205 with its location mapped to the new entry in the index.
  • the new copy of the requested data packets may be used to identify the packets within the original requested data that are referenced in case changes have been made in the original requested data that have not been propagated to the copy of the requested data and the index is lost or corrupted.
  • the non-volatile storage device controller 124 also includes a data bus 207 , a local bus 206 , a buffer controller 208 , buffers 0 -N 222 a - n , a master controller 224 , a direct memory access (“DMA”) controller 226 , a memory controller 228 , a dynamic memory array 230 , a static random memory array 232 , a management controller 234 , a management bus 236 , a bridge 238 to a system bus 240 , and miscellaneous logic 242 , which are described below.
  • DMA direct memory access
  • the system bus 240 is coupled to one or more network interface cards (“NICs”) 244 , some of which may include remote DMA (“RDMA”) controllers 246 , one or more central processing unit (“CPU”) 248 , one or more external memory controllers 250 and associated external memory arrays 252 , one or more storage controllers 254 , peer controllers 256 , and application specific processors 258 , which are described below.
  • NICs network interface cards
  • RDMA remote DMA
  • CPU central processing unit
  • external memory controllers 250 and associated external memory arrays 252 one or more storage controllers 254
  • peer controllers 256 peer controllers 256
  • application specific processors 258 application specific processors
  • the storage controller(s) 104 communicate data to the non-volatile storage media 205 over a storage I/O bus 210 .
  • the storage I/O bus 210 is an array of busses, one for each column of storage elements 216 , 218 , 220 spanning the banks 214 .
  • the term “storage I/O bus” may refer to one storage I/O bus 210 or an array of independent data busses wherein individual data busses of the array independently communicate different data relative to one another.
  • each storage I/O bus 210 accessing a column of storage elements may include a logical-to-physical mapping for storage divisions (e.g., erase blocks) accessed in a column of storage elements 216 a , 218 a , 220 a .
  • This mapping (or bad block remapping) allows a logical address mapped to a physical address of a storage division to be remapped to a different storage division if the first storage division fails, partially fails, is inaccessible, or has some other problem.
  • Data may also be communicated to the storage controller(s) 104 from a requesting device 155 through the system bus 240 , bridge 238 , local bus 206 , buffer(s) 222 , and finally over a data bus 207 .
  • the data bus 207 typically is connected to one or more buffers 222 a - n controlled with a buffer controller 208 .
  • the buffer controller 208 typically controls transfer of data from the local bus 206 to the buffers 222 and through the data bus 207 to the pipeline input buffer 306 and output buffer 330 .
  • the buffer controller 208 typically controls how data arriving from a requesting device can be temporarily stored in a buffer 222 and then transferred onto a data bus 207 , or vice versa, to account for different clock domains, to prevent data collisions, etc.
  • the buffer controller 208 typically works in conjunction with the master controller 224 to coordinate data flow. As data arrives, the data will arrive on the system bus 240 , be transferred to the local bus 206 through a bridge 238 .
  • the data is transferred from the local bus 206 to one or more data buffers 222 as directed by the master controller 224 and the buffer controller 208 .
  • the data then flows out of the buffer(s) 222 to the data bus 207 , through a non-volatile controller 204 , and on to the non-volatile storage media 205 such as NAND flash or other storage media.
  • data and associated out-of-band metadata (“metadata”) arriving with the data is communicated using one or more data channels having one or more storage controllers 104 a - 104 n ⁇ 1 and associated non-volatile storage media 205 a - 110 n ⁇ 1 while at least one channel (storage controller 204 n , non-volatile storage media 205 n ) is dedicated to in-band metadata, such as index information and other metadata generated internally to the non-volatile storage device 122 .
  • in-band metadata such as index information and other metadata generated internally to the non-volatile storage device 122 .
  • the local bus 206 is typically a bidirectional bus or set of busses that allows for communication of data and commands between devices internal to the non-volatile storage device controller 124 and between devices internal to the non-volatile storage device 122 and devices 244 - 258 connected to the system bus 240 .
  • the bridge 238 facilitates communication between the local bus 206 and system bus 240 .
  • One of skill in the art will recognize other embodiments such as ring structures or switched star configurations and functions of buses 240 , 206 , 204 , 210 and bridges 238 .
  • the system bus 240 is typically a bus of a host computing system 114 or other device in which the non-volatile storage device 122 is installed or connected.
  • the system bus 240 may be a PCI-e bus, a Serial Advanced Technology Attachment (“serial ATA”) bus, parallel ATA, or the like.
  • the system bus 240 is an external bus such as small computer system interface (“SCSI”), FireWire, Fiber Channel, USB, PCIe-AS, or the like.
  • SCSI small computer system interface
  • FireWire FireWire
  • Fiber Channel USB
  • PCIe-AS PCIe-AS
  • the non-volatile storage device 122 may be packaged to fit internally to a device or as an externally connected device.
  • the non-volatile storage device controller 124 includes a master controller 224 that controls higher-level functions within the non-volatile storage device 122 .
  • the master controller 224 controls data flow by interpreting object requests and other requests, directs creation of indexes to map object identifiers associated with data to physical locations of associated data, coordinating DMA requests, etc. Many of the functions described herein are controlled wholly or in part by the master controller 224 .
  • the master controller 224 uses embedded controller(s). In another embodiment, the master controller 224 uses local memory such as a dynamic memory array 230 (dynamic random access memory “DRAM”), a static memory array 232 (static random access memory “SRAM”), etc. In one embodiment, the local memory is controlled using the master controller 224 . In another embodiment, the master controller 224 accesses the local memory via a memory controller 228 . In another embodiment, the master controller 224 runs a Linux server and may support various common server interfaces, such as the World Wide Web, hyper-text markup language (“HTML”), etc. In another embodiment, the master controller 224 uses a nano-processor. The master controller 224 may be constructed using programmable or standard logic, or any combination of controller types listed above. One skilled in the art will recognize many embodiments for the master controller 224 .
  • DRAM dynamic random access memory
  • SRAM static memory array
  • the local memory is controlled using the master controller 224 .
  • the master controller 224 accesses the local memory via a memory controller 2
  • the master controller 224 divides the work load among internal controllers, such as the storage controllers 104 a - n .
  • the master controller 224 may divide an object to be written to the data storage devices (e.g., non-volatile storage media 205 a - n ) so that a portion of the object is stored on each of the attached data storage devices. This feature is a performance enhancement allowing quicker storage and access to an object.
  • the master controller 224 is implemented using an FPGA.
  • the firmware within the master controller 224 may be updated through the management bus 236 , the system bus 240 over a network connected to a NIC 244 or other device connected to the system bus 240 .
  • the master controller 224 coordinates with NIC controllers 244 and embedded RDMA controllers 246 to deliver just-in-time RDMA transfers of data and command sets.
  • NIC controller 244 may be hidden behind a non-transparent port to enable the use of custom drivers.
  • a driver 120 on a host computing system 114 may have access to the computer network 116 through an I/O memory driver using a standard stack API and operating in conjunction with NICs 244 .
  • the master controller 224 is also a redundant array of independent drive (“RAID”) controller. Where the data storage device/non-volatile storage device 122 is networked with one or more other data storage devices/non-volatile storage devices 102 , the master controller 224 may be a RAID controller for single tier RAID, multi-tier RAID, progressive RAID, etc. The master controller 224 also allows some objects to be stored in a RAID array and other objects to be stored without RAID. In another embodiment, the master controller 224 may be a distributed RAID controller element. In another embodiment, the master controller 224 may include many RAID, distributed RAID, and other functions as described elsewhere.
  • RAID redundant array of independent drive
  • the master controller 224 coordinates with single or redundant network managers (e.g., switches) to establish routing, to balance bandwidth utilization, failover, etc.
  • the master controller 224 coordinates with integrated application specific logic (via local bus 206 ) and associated driver software.
  • the master controller 224 coordinates with attached application specific processors 258 or logic (via the external system bus 240 ) and associated driver software.
  • the master controller 224 coordinates with remote application specific logic (via the computer network 116 ) and associated driver software.
  • the master controller 224 coordinates with the local bus 206 or external bus attached hard disk drive (“HDD”) storage controller.
  • HDD hard disk drive
  • the master controller 224 communicates with one or more storage controllers 254 where the storage device/non-volatile storage device 122 may appear as a storage device connected through a SCSI bus, Internet SCSI (“iSCSI”), fiber channel, etc. Meanwhile the storage device/non-volatile storage device 122 may autonomously manage objects and may appear as an object file system or distributed object file system.
  • the master controller 224 may also be accessed by peer controllers 256 and/or application specific processors 258 .
  • the master controller 224 coordinates with an autonomous integrated management controller to periodically validate FPGA code and/or controller software, validate FPGA code while running (reset) and/or validate controller software during power on (reset), support external reset requests, support reset requests due to watchdog timeouts, and support voltage, current, power, temperature, and other environmental measurements and setting of threshold interrupts.
  • the master controller 224 manages garbage collection to free erase blocks for reuse.
  • the master controller 224 manages wear leveling.
  • the master controller 224 allows the data storage device/non-volatile storage device 122 to be partitioned into multiple logical devices and allows partition-based media encryption.
  • the master controller 224 supports a storage controller 204 with advanced, multi-bit ECC correction.
  • a master controller 224 in a storage controller 124 , or more specifically in a non-volatile storage device 122 .
  • the non-volatile storage device controller 124 includes a memory controller 228 , which controls a dynamic random memory array 230 and/or a static random memory array 232 .
  • the memory controller 228 may be independent or integrated with the master controller 224 .
  • the memory controller 228 typically controls volatile memory of some type, such as DRAM (dynamic random memory array 230 ) and SRAM (static random memory array 232 ).
  • the memory controller 228 also controls other memory types such as electrically erasable programmable read only memory (“EEPROM”), etc.
  • EEPROM electrically erasable programmable read only memory
  • the memory controller 228 controls two or more memory types and the memory controller 228 may include more than one controller.
  • the memory controller 228 controls as much SRAM 232 as is feasible and by DRAM 230 to supplement the SRAM 232 .
  • the object index is stored in memory 230 , 232 and then periodically off-loaded to a channel of the non-volatile storage media 205 n or other non-volatile memory.
  • the memory controller 228 dynamic memory array 230
  • static memory array 232 static memory array
  • the non-volatile storage device controller 124 includes a DMA controller 226 that controls DMA operations between the storage device/non-volatile storage device 122 and one or more external memory controllers 250 and associated external memory arrays 252 and CPUs 248 .
  • the external memory controllers 250 and external memory arrays 252 are called external because they are external to the storage device/non-volatile storage device 122 .
  • the DMA controller 226 may also control RDMA operations with requesting devices through a NIC 244 and associated RDMA controller 246 .
  • the non-volatile storage device controller 124 includes a management controller 234 connected to a management bus 236 .
  • the management controller 234 manages environmental metrics and status of the storage device/non-volatile storage device 122 .
  • the management controller 234 may monitor device temperature, fan speed, power supply settings, etc. over the management bus 236 .
  • the management controller 234 may support the reading and programming of erasable programmable read only memory (“EEPROM”) for storage of FPGA code and controller software.
  • EEPROM erasable programmable read only memory
  • the management bus 236 is connected to the various components within the storage device/non-volatile storage device 122 .
  • the management controller 234 may communicate alerts, interrupts, etc.
  • the management bus 236 is an Inter-Integrated Circuit (“I2C”) bus.
  • I2C Inter-Integrated Circuit
  • the non-volatile storage device controller 124 includes miscellaneous logic 242 that may be customized for a specific application. Typically, where the non-volatile device controller 124 or master controller 224 is/are configured using a FPGA or other configurable controller, custom logic may be included based on a particular application, customer requirement, storage requirement, etc.
  • controller 124 of FIG. 2 While the controller 124 of FIG. 2 is shown, other embodiments of a controller 124 may be used to implement the operations for object-based storage on a storage device 122 .
  • FIG. 3 depicts a schematic diagram of one embodiment 300 of the storage controller 204 of FIG. 2 with a write data pipeline 301 , a read data pipeline 303 and a throughput management apparatus 122 in a non-volatile storage device 122 .
  • the embodiment 300 includes a data bus 207 , a local bus 206 , and buffer control 208 , which are substantially similar to those described in relation to the non-volatile storage device controller 124 of FIG. 2 .
  • the write data pipeline 301 includes a packetizer 302 and an error-correcting code (“ECC”) generator 304 .
  • ECC error-correcting code
  • the write data pipeline 301 includes an input buffer 306 , a write synchronization buffer 308 , a write program module 310 , a compression module 312 , an encryption module 314 , a garbage collector bypass 316 (with a portion within the read data pipeline 303 ), a media encryption module 318 , and a write buffer 320 .
  • the read data pipeline 303 includes a read synchronization buffer 328 , an ECC correction module 322 , a depacketizer 324 , an alignment module 326 , and an output buffer 330 .
  • the read data pipeline 303 may include a media decryption module 332 , a portion of the garbage collector bypass 316 , a decryption module 334 , a decompression module 336 , and a read program module 338 .
  • the storage controller 204 may also include control and status registers 340 and control queues 342 , a bank interleave controller 344 , a synchronization buffer 346 , a storage bus controller 348 , and a multiplexer (“MUX”) 350 .
  • MUX multiplexer
  • the write data pipeline 301 includes a packetizer 302 that receives a data or metadata segment to be written to the non-volatile storage, either directly or indirectly through another write data pipeline 301 stage, and creates one or more packets sized for the non-volatile storage media 205 .
  • the data or metadata segment is typically part of a data structure such as an object, but may also include an entire data structure. In another embodiment, the data segment is part of a block of data, but may also include an entire block of data.
  • a set of data such as a data structure is received from a computer such as the host computing system 114 , or other computer or device and is transmitted to the non-volatile storage device 122 in data segments streamed to the non-volatile storage device 122 .
  • a data segment may also be known by another name, such as data parcel, but as referenced herein includes all or a portion of a data structure or data block.
  • Each data structure is stored as one or more packets.
  • Each data structure may have one or more container packets.
  • Each packet contains a header.
  • the header may include a header type field. Type fields may include data, attribute, metadata, data segment delimiters (multi-packet), data structures, data linkages, and the like.
  • the header may also include information regarding the size of the packet, such as the number of bytes of data included in the packet. The length of the packet may be established by the packet type.
  • the header may include information that establishes the relationship of the packet to a data structure. An example might be the use of an offset in a data packet header to identify the location of the data segment within the data structure.
  • One of skill in the art will recognize other information that may be included in a header added to data by a packetizer 302 and other information that may be added to a data packet.
  • Each packet includes a header and possibly data from the data or metadata segment.
  • the header of each packet includes pertinent information to relate the packet to the data structure to which the packet belongs.
  • the header may include an object identifier or other data structure identifier and offset that indicate the data segment, object, data structure or data block from which the data packet was formed.
  • the header may also include a logical address used by the storage bus controller 348 to store the packet.
  • the header may also include information regarding the size of the packet, such as the number of bytes included in the packet.
  • the header may also include a sequence number that identifies where the data segment belongs with respect to other packets within the data structure when reconstructing the data segment or data structure.
  • the header may include a header type field.
  • Type fields may include data, data structure attributes, metadata, data segment delimiters (multi-packet), data structure types, data structure linkages, and the like.
  • data segment delimiters multi-packet
  • data structure types data structure linkages, and the like.
  • packetizer 302 One of skill in the art will recognize other information that may be included in a header added to data or metadata by a packetizer 302 and other information that may be added to a packet.
  • the write data pipeline 301 includes an ECC generator 304 that that generates one or more error-correcting codes (“ECC”) for the one or more packets received from the packetizer 302 .
  • the write data pipeline 301 does not include an ECC generator 304 .
  • the ECC generator 304 typically uses an error-correcting algorithm to generate ECC check bits, which are stored with the one or more data packets.
  • the ECC codes generated by the ECC generator 304 together with the one or more data packets associated with the ECC codes include an ECC chunk.
  • the ECC data stored with the one or more data packets is used to detect and to correct errors introduced into the data through transmission and storage.
  • packets are streamed into the ECC generator 304 as un-encoded blocks of length N.
  • a syndrome of length S is calculated, appended, and output as an encoded block of length N+S.
  • the value of N and S are dependent upon the characteristics of the ECC algorithm, which is selected to achieve specific performance, efficiency, and robustness metrics.
  • there is no fixed relationship between the ECC blocks and the packets the packet may include more than one ECC block; the ECC block may include more than one packet; and a first packet may end anywhere within the ECC block and a second packet may begin after the end of the first packet within the same ECC block.
  • ECC algorithms are not dynamically modified.
  • the ECC data stored with the data packets is robust enough to correct errors in more than two bits.
  • the non-volatile storage media 205 can be extended. For example, if flash memory is used as the storage medium in the non-volatile storage media 205 , the flash memory may be written approximately 100,000 times without error per erase cycle. This usage limit may be extended using a robust ECC algorithm. Having the ECC generator 304 and corresponding ECC correction module 322 onboard the non-volatile storage device 122 , the non-volatile storage device 122 can internally correct errors and has a longer useful life than if a less robust ECC algorithm is used, such as single bit correction.
  • the ECC generator 304 may use a less robust algorithm and may correct single-bit or double-bit errors.
  • the non-volatile storage device 110 may include less reliable storage such as multi-level cell (“MLC”) flash in order to increase capacity, which storage may not be sufficiently reliable without more robust ECC algorithms.
  • MLC multi-level cell
  • the write pipeline 301 includes an input buffer 306 that receives a data segment to be written to the non-volatile storage media 205 and stores the incoming data segments until the next stage of the write data pipeline 301 , such as the packetizer 302 (or other stage for a more complex write data pipeline 301 ) is ready to process the next data segment.
  • the input buffer 306 typically allows for discrepancies between the rate data segments are received and processed by the write data pipeline 301 using an appropriately sized data buffer.
  • the input buffer 306 also allows the data bus 207 to transfer data to the write data pipeline 301 at rates greater than can be sustained by the write data pipeline 301 in order to improve efficiency of operation of the data bus 207 .
  • a buffering function is performed elsewhere, such as in the non-volatile storage device 122 but outside the write data pipeline 301 , in the host computing system 114 , such as within a network interface card (“NIC”), or at another device, for example when using remote direct memory access (“RDMA”).
  • NIC network interface card
  • RDMA remote direct memory access
  • the write data pipeline 301 also includes a write synchronization buffer 308 that buffers packets received from the ECC generator 304 prior to writing the packets to the non-volatile storage media 205 .
  • the write synchronization buffer 308 is located at a boundary between a local clock domain and a non-volatile storage clock domain and provides buffering to account for the clock domain differences.
  • synchronous non-volatile storage media 205 may be used and synchronization buffers 308 328 may be eliminated.
  • the write data pipeline 301 also includes a media encryption module 318 that receives the one or more packets from the packetizer 302 , either directly or indirectly, and encrypts the one or more packets using an encryption key unique to the non-volatile storage device 122 prior to sending the packets to the ECC generator 304 .
  • the entire packet is encrypted, including the headers.
  • headers are not encrypted.
  • encryption key is understood to mean a secret encryption key that is managed externally from a storage controller 204 .
  • the media encryption module 318 and corresponding media decryption module 332 provide a level of security for data stored in the non-volatile storage media 205 .
  • data is encrypted with the media encryption module 318
  • the non-volatile storage media 205 is connected to a different storage controller 204 , non-volatile storage device 122 , or server, the contents of the non-volatile storage media 205 typically could not be read without use of the same encryption key used during the write of the data to the non-volatile storage media 205 without significant effort.
  • the non-volatile storage device 122 does not store the encryption key in non-volatile storage and allows no external access to the encryption key.
  • the encryption key is provided to the storage controller 204 during initialization.
  • the non-volatile storage device 122 may use and store a non-secret cryptographic nonce that is used in conjunction with an encryption key. A different nonce may be stored with every packet. Data segments may be split between multiple packets with unique nonces for the purpose of improving protection by the encryption algorithm.
  • the encryption key may be received from a host computing system 114 , a server, key manager, or other device that manages the encryption key to be used by the storage controller 204 .
  • the non-volatile storage media 205 may have two or more partitions and the storage controller 204 behaves as though it was two or more storage controllers 104 , each operating on a single partition within the non-volatile storage media 205 .
  • a unique media encryption key may be used with each partition.
  • the write data pipeline 301 also includes an encryption module 314 that encrypts a data or metadata segment received from the input buffer 306 , either directly or indirectly, prior sending the data segment to the packetizer 302 , the data segment encrypted using an encryption key received in conjunction with the data segment.
  • the encryption keys used by the encryption module 314 to encrypt data may not be common to all data stored within the non-volatile storage device 122 but may vary on an per data structure basis and received in conjunction with receiving data segments as described below. For example, an encryption key for a data segment to be encrypted by the encryption module 314 may be received with the data segment or may be received as part of a command to write a data structure to which the data segment belongs.
  • the storage device 122 may use and store a non-secret cryptographic nonce in each data structure packet that is used in conjunction with the encryption key.
  • a different nonce may be stored with every packet.
  • Data segments may be split between multiple packets with unique nonces for the purpose of improving protection by the encryption algorithm.
  • the encryption key may be received from a host computing device 102 , another computer, key manager, or other device that holds the encryption key to be used to encrypt the data segment.
  • encryption keys are transferred to the storage controller 204 from one of a non-volatile storage device 122 , host computing device 102 , computer, or other external agent, which has the ability to execute industry standard methods to securely transfer and protect private and public keys.
  • the encryption module 314 encrypts a first packet with a first encryption key received in conjunction with the packet and encrypts a second packet with a second encryption key received in conjunction with the second packet. In another embodiment, the encryption module 314 encrypts a first packet with a first encryption key received in conjunction with the packet and passes a second data packet on to the next stage without encryption.
  • the encryption module 314 included in the write data pipeline 301 of the non-volatile storage device 122 allows data structure-by-data structure or segment-by-segment data encryption without a single file system or other external system to keep track of the different encryption keys used to store corresponding data structures or data segments.
  • Each requesting device 155 or related key manager independently manages encryption keys used to encrypt only the data structures or data segments sent by the requesting device 155 .
  • the encryption module 314 may encrypt the one or more packets using an encryption key unique to the non-volatile storage device 122 .
  • the encryption module 314 may perform this media encryption independently, or in addition to the encryption described above.
  • the entire packet is encrypted, including the headers.
  • headers are not encrypted.
  • the media encryption by the encryption module 314 provides a level of security for data stored in the non-volatile storage media 205 .
  • non-volatile storage media 205 is connected to a different storage controller 204 , non-volatile storage device 122 , or host computing system 114 , the contents of the non-volatile storage media 205 typically could not be read without use of the same encryption key used during the write of the data to the non-volatile storage media 205 without significant effort.
  • the write data pipeline 301 includes a compression module 312 that compresses the data for metadata segment prior to sending the data segment to the packetizer 302 .
  • the compression module 312 typically compresses a data or metadata segment using a compression routine known to those of skill in the art to reduce the storage size of the segment. For example, if a data segment includes a string of 512 zeros, the compression module 312 may replace the 512 zeros with code or token indicating the 512 zeros where the code is much more compact than the space taken by the 512 zeros.
  • the compression module 312 compresses a first segment with a first compression routine and passes along a second segment without compression. In another embodiment, the compression module 312 compresses a first segment with a first compression routine and compresses the second segment with a second compression routine. Having this flexibility within the non-volatile storage device 122 is beneficial so that computing devices 102 or other devices writing data to the non-volatile storage device 122 may each specify a compression routine or so that one can specify a compression routine while another specifies no compression. Selection of compression routines may also be selected according to default settings on a per data structure type or data structure class basis.
  • a first data structure of a specific data structure may be able to override default compression routine settings and a second data structure of the same data structure class and data structure type may use the default compression routine and a third data structure of the same data structure class and data structure type may use no compression.
  • the write data pipeline 301 includes a garbage collector bypass 316 that receives data segments from the read data pipeline 303 as part of a data bypass in a garbage collection system.
  • a garbage collection system also referred to as a “groomer” or grooming operation
  • groomer typically marks packets that are no longer valid, typically because the packet is marked for deletion or has been modified and the modified data is stored in a different location.
  • the garbage collection system determines that a particular section (e.g., an erase block) of storage may be recovered. This determination may be due to a lack of available storage capacity, the percentage of data marked as invalid reaching a threshold, a consolidation of valid data, an error detection rate for that section of storage reaching a threshold, or improving performance based on data distribution, etc. Numerous factors may be considered by a garbage collection algorithm to determine when a section of storage is to be recovered.
  • the garbage collector bypass 316 allows packets to be read into the read data pipeline 303 and then transferred directly to the write data pipeline 301 without being routed out of the storage controller 204 .
  • the garbage collector bypass 316 is part of an autonomous garbage collector system that operates within the non-volatile storage device 122 . This allows the non-volatile storage device 122 to manage data so that data is systematically spread throughout the non-volatile storage media 205 to improve performance, data reliability and to avoid overuse and underuse of any one location or area of the non-volatile storage media 205 and to lengthen the useful life of the non-volatile storage media 205 .
  • the garbage collector bypass 316 coordinates insertion of segments into the write data pipeline 106 with other segments being written by computing devices 102 or other devices.
  • the garbage collector bypass 316 is before the packetizer 302 in the write data pipeline 301 and after the depacketizer 324 in the read data pipeline 303 , but may also be located elsewhere in the read and write data pipelines 106 , 108 .
  • the garbage collector bypass 316 may be used during a flush of the write pipeline 303 to fill the remainder of the particular section of storage in order to improve the efficiency of storage within the non-volatile storage media 205 and thereby reduce the frequency of garbage collection.
  • Grooming may include refreshing data stored on the non-volatile storage media 205 .
  • Data stored on the non-volatile storage media 205 may degrade over time.
  • the storage controller 204 may include a groomer that identifies “stale” data on the non-volatile storage device 122 (data that has not been modified and/or moved for a pre-determined time), and refreshes the stale data by re-writing the data to a different storage location.
  • the garbage collection system, groomer, and/or garbage collection bypass 316 may be temporarily disabled to allow data to be stored contiguously on physical storage locations of the non-volatile storage device 122 . Disabling the garbage collection system and/or bypass 316 may ensure that data in the write data pipeline 301 is not interleaved with other data. For example, and discussed below, garbage collection and/or the garbage collection bypass 316 may be disabled when storing data pertaining to an atomic storage request.
  • the garbage collection and/or groomer may be restricted to a certain portion of the physical storage space of the non-volatile storage device.
  • storage metadata such as the reverse index described below, may be periodically persisted to a non-volatile storage location.
  • the garbage collection and/or grooming may be restricted to operating on portions of the non-volatile storage media that correspond to the persisted storage metadata.
  • the write data pipeline 301 includes a write buffer 320 that buffers data for efficient write operations.
  • the write buffer 320 includes enough capacity for packets to fill at least one logical page in the non-volatile storage media 205 . This allows a write operation to send an entire logical page of data to the non-volatile storage media 205 without interruption.
  • By sizing the write buffer 320 of the write data pipeline 301 and buffers within the read data pipeline 303 to be the same capacity or larger than a storage write buffer within the non-volatile storage media 205 writing and reading data is more efficient since a single write command may be crafted to send a full logical page of data to the non-volatile storage media 205 instead of multiple commands.
  • the non-volatile storage media 205 may be used for other read operations. This is advantageous because other non-volatile devices with a smaller write buffer or no write buffer may tie up the non-volatile storage when data is written to a storage write buffer and data flowing into the storage write buffer stalls. Read operations will be blocked until the entire storage write buffer is filled and programmed.
  • Another approach for systems without a write buffer or a small write buffer is to flush the storage write buffer that is not full in order to enable reads.
  • the write buffer 320 is a ping-pong buffer where one side of the buffer is filled and then designated for transfer at an appropriate time while the other side of the ping-pong buffer is being filled.
  • the write buffer 320 includes a first-in first-out (“FIFO”) register with a capacity of more than a logical page of data segments.
  • FIFO first-in first-out
  • the write data pipeline 301 includes a write program module 310 with one or more user-definable functions within the write data pipeline 301 .
  • the write program module 310 allows a user to customize the write data pipeline 301 .
  • a user may customize the write data pipeline 301 based on a particular data requirement or application.
  • the storage controller 204 is an FPGA
  • the user may program the write data pipeline 301 with custom commands and functions relatively easily.
  • a user may also use the write program module 310 to include custom functions with an ASIC, however, customizing an ASIC may be more difficult than with an FPGA.
  • the write program module 310 may include buffers and bypass mechanisms to allow a first data segment to execute in the write program module 310 while a second data segment may continue through the write data pipeline 301 .
  • the write program module 310 may include a processor core that can be programmed through software.
  • write program module 310 is shown between the input buffer 306 and the compression module 312 , however, the write program module 310 could be anywhere in the write data pipeline 301 and may be distributed among the various stages 302 - 320 . In addition, there may be multiple write program modules 310 distributed among the various states 302 - 320 that are programmed and operate independently. In addition, the order of the stages 302 - 320 may be altered. One of skill in the art will recognize workable alterations to the order of the stages 302 - 320 based on particular user requirements.
  • the read data pipeline 303 includes an ECC correction module 322 that determines if a data error exists in ECC blocks a requested packet received from the non-volatile storage media 205 by using ECC stored with each ECC block of the requested packet. The ECC correction module 322 then corrects any errors in the requested packet if any error exists and the errors are correctable using the ECC. For example, if the ECC can detect an error in six bits but can only correct three bit errors, the ECC correction module 322 corrects ECC blocks of the requested packet with up to three bits in error. The ECC correction module 322 corrects the bits in error by changing the bits in error to the correct one or zero state so that the requested data packet is identical to when it was written to the non-volatile storage media 205 and the ECC was generated for the packet.
  • the ECC correction module 322 determines that the requested packets contains more bits in error than the ECC can correct, the ECC correction module 322 cannot correct the errors in the corrupted ECC blocks of the requested packet and sends an interrupt.
  • the ECC correction module 322 sends an interrupt with a message indicating that the requested packet is in error.
  • the message may include information that the ECC correction module 322 cannot correct the errors or the inability of the ECC correction module 322 to correct the errors may be implied.
  • the ECC correction module 322 sends the corrupted ECC blocks of the requested packet with the interrupt and/or the message.
  • a corrupted ECC block or portion of a corrupted ECC block of the requested packet that cannot be corrected by the ECC correction module 322 is read by the master controller 224 , corrected, and returned to the ECC correction module 322 for further processing by the read data pipeline 303 .
  • a corrupted ECC block or portion of a corrupted ECC block of the requested packet is sent to the device requesting the data.
  • the requesting device 155 may correct the ECC block or replace the data using another copy, such as a backup or mirror copy, and then may use the replacement data of the requested data packet or return it to the read data pipeline 303 .
  • the requesting device 155 may use header information in the requested packet in order to identify data required to replace the corrupted requested packet or to replace the data structure to which the packet belongs.
  • the storage controller 204 stores data using some type of RAID and is able to recover the corrupted data.
  • the ECC correction module 322 sends an interrupt and/or message and the receiving device fails the read operation associated with the requested data packet.
  • One of skill in the art will recognize other options and actions to be taken as a result of the ECC correction module 322 determining that one or more ECC blocks of the requested packet are corrupted and that the ECC correction module 322 cannot correct the errors.
  • the read data pipeline 303 includes a depacketizer 324 that receives ECC blocks of the requested packet from the ECC correction module 322 , directly or indirectly, and checks and removes one or more packet headers.
  • the depacketizer 324 may validate the packet headers by checking packet identifiers, data length, data location, etc. within the headers.
  • the header includes a hash code that can be used to validate that the packet delivered to the read data pipeline 303 is the requested packet.
  • the depacketizer 324 also removes the headers from the requested packet added by the packetizer 302 .
  • the depacketizer 324 may directed to not operate on certain packets but pass these forward without modification.
  • An example might be a container label that is requested during the course of a rebuild process where the header information is required for index reconstruction. Further examples include the transfer of packets of various types destined for use within the non-volatile storage device 122 . In another embodiment, the depacketizer 324 operation may be packet type dependent.
  • the read data pipeline 303 includes an alignment module 326 that receives data from the depacketizer 324 and removes unwanted data.
  • a read command sent to the non-volatile storage media 205 retrieves a packet of data.
  • a device requesting the data may not require all data within the retrieved packet and the alignment module 326 removes the unwanted data.
  • the alignment module 326 re-formats the data as data segments of a data structure in a form compatible with a device requesting the data segment prior to forwarding the data segment to the next stage.
  • the alignment module 326 uses received data to format the data into data segments suitable to be sent to the requesting device 155 and joined to form a response. For example, data from a portion of a first data packet may be combined with data from a portion of a second data packet. If a data segment is larger than a data requested by the requesting device 155 , the alignment module 326 may discard the unwanted data.
  • the read data pipeline 303 includes a read synchronization buffer 328 that buffers one or more requested packets read from the non-volatile storage media 205 prior to processing by the read data pipeline 303 .
  • the read synchronization buffer 328 is at the boundary between the non-volatile storage clock domain and the local bus clock domain and provides buffering to account for the clock domain differences.
  • the read data pipeline 303 includes an output buffer 330 that receives requested packets from the alignment module 326 and stores the packets prior to transmission to the requesting device 155 .
  • the output buffer 330 accounts for differences between when data segments are received from stages of the read data pipeline 303 and when the data segments are transmitted to other parts of the storage controller 204 or to the requesting device 155 .
  • the output buffer 330 also allows the data bus 207 to receive data from the read data pipeline 303 at rates greater than can be sustained by the read data pipeline 303 in order to improve efficiency of operation of the data bus 207 .
  • the read data pipeline 303 includes a media decryption module 332 that receives one or more encrypted requested packets from the ECC correction module 322 and decrypts the one or more requested packets using the encryption key unique to the non-volatile storage device 122 prior to sending the one or more requested packets to the depacketizer 324 .
  • the encryption key used to decrypt data by the media decryption module 332 is identical to the encryption key used by the media encryption module 318 .
  • the non-volatile storage media 205 may have two or more partitions and the storage controller 204 behaves as though it was two or more storage controllers 104 each operating on a single partition within the non-volatile storage media 205 . In this embodiment, a unique media encryption key may be used with each partition.
  • the read data pipeline 303 includes a decryption module 334 that decrypts a data segment formatted by the depacketizer 324 prior to sending the data segment to the output buffer 330 .
  • the data segment may be decrypted using an encryption key received in conjunction with the read request that initiates retrieval of the requested packet received by the read synchronization buffer 328 .
  • the decryption module 334 may decrypt a first packet with an encryption key received in conjunction with the read request for the first packet and then may decrypt a second packet with a different encryption key or may pass the second packet on to the next stage of the read data pipeline 303 without decryption.
  • the nonce When the packet was stored with a non-secret cryptographic nonce, the nonce is used in conjunction with an encryption key to decrypt the data packet.
  • the encryption key may be received from a host computing system 114 , a client, key manager, or other device that manages the encryption key to be used by the storage controller 204 .
  • the read data pipeline 303 includes a decompression module 336 that decompresses a data segment formatted by the depacketizer 324 .
  • the decompression module 336 uses compression information stored in one or both of the packet header and the container label to select a complementary routine to that used to compress the data by the compression module 312 .
  • the decompression routine used by the decompression module 336 is dictated by the device requesting the data segment being decompressed.
  • the decompression module 336 selects a decompression routine according to default settings on a per data structure type or data structure class basis.
  • a first packet of a first object may be able to override a default decompression routine and a second packet of a second data structure of the same data structure class and data structure type may use the default decompression routine and a third packet of a third data structure of the same data structure class and data structure type may use no decompression.
  • the read data pipeline 303 includes a read program module 338 that includes one or more user-definable functions within the read data pipeline 303 .
  • the read program module 338 has similar characteristics to the write program module 310 and allows a user to provide custom functions to the read data pipeline 303 .
  • the read program module 338 may be located as shown in FIG. 3 , may be located in another position within the read data pipeline 303 , or may include multiple parts in multiple locations within the read data pipeline 303 . Additionally, there may be multiple read program modules 338 within multiple locations within the read data pipeline 303 that operate independently.
  • One of skill in the art will recognize other forms of a read program module 338 within a read data pipeline 303 .
  • the stages of the read data pipeline 303 may be rearranged and one of skill in the art will recognize other orders of stages within the read data pipeline 303 .
  • the storage controller 204 includes control and status registers 340 and corresponding control queues 342 .
  • the control and status registers 340 and control queues 342 facilitate control and sequencing commands and subcommands associated with data processed in the write and read data pipelines 106 , 108 .
  • a data segment in the packetizer 302 may have one or more corresponding control commands or instructions in a control queue 342 associated with the ECC generator 304 .
  • As the data segment is packetized, some of the instructions or commands may be executed within the packetizer 302 .
  • Other commands or instructions may be passed to the next control queue 342 through the control and status registers 340 as the newly formed data packet created from the data segment is passed to the next stage.
  • Commands or instructions may be simultaneously loaded into the control queues 342 for a packet being forwarded to the write data pipeline 301 with each pipeline stage pulling the appropriate command or instruction as the respective packet is executed by that stage.
  • commands or instructions may be simultaneously loaded into the control queues 342 for a packet being requested from the read data pipeline 303 with each pipeline stage pulling the appropriate command or instruction as the respective packet is executed by that stage.
  • One of skill in the art will recognize other features and functions of control and status registers 340 and control queues 342 .
  • the storage controller 204 and or non-volatile storage device 122 may also include a bank interleave controller 344 , a synchronization buffer 346 , a storage bus controller 348 , and a multiplexer (“MUX”) 350 .
  • a bank interleave controller 344 may also include a bank interleave controller 344 , a synchronization buffer 346 , a storage bus controller 348 , and a multiplexer (“MUX”) 350 .
  • MUX multiplexer
  • FIG. 4A depicts a schematic diagram of one embodiment of a log structure 400 in a memory storage device 122 . While the log structure 400 is described in conjunction with the storage device 122 of FIG. 1 , the log structure 400 may be used in conjunction with any type of storage device 122 or memory device. Alternatively, the storage device 122 may be used in conjunction with any storage media in a log-structured manner or that is configured to perform operations according to an object-based storage system.
  • a log structure allows program operations to be performed quickly because changes to a set of data in one location of the storage device 122 are written to a different location (that is first erased) on the same storage device 122 , rather than the first location.
  • the storage device 122 may be used in conjunction with storage media organized in a structure other than a log structure.
  • a non-log-structured storage device may include phase change memory or a write-in-place non-volatile storage media.
  • Write-in-place storage media may include a storage medium that is able to make changes to data stored at a location on the storage medium and write the modified data back to the same location on the storage medium.
  • a write-out-of-place storage medium is configured to modify data stored on the storage medium and write the modified data to a different location on the storage medium, such as in a log-structured medium.
  • the log structure 400 is configured to store objects received from a client application 110 in the order that the objects are received to be written to the storage device 122 .
  • the size of each object 402 may be different, according to the data associated with a write operation.
  • each new object may be added to the log structure 400 at the end of the previously stored object. For example, as shown in FIG. 4A , a first object 402 having a first size is created and stored at the beginning 408 of the log structure 400 on the storage device 122 . When a second object 404 is created, the second object 404 is placed after the first object 402 on the storage device 122 . Additional objects are then added to the log structure 400 in the order received by the storage device 122 .
  • the objects shown in FIG. 4A may be any type of objects, including live objects, dead objects and/or dirty objects.
  • the storage device 122 is configured to store data in a log-structured manner, the objects do not need to be stored in blocks, as with a traditional block-based storage device. Additionally, the storage device 122 is capable of retrieving (or otherwise modify) data associated with the stored objects by tracking the object identifier, location, and size of each object in a table 406 , as shown in FIG. 4B .
  • the table 406 is stored on the storage device 122 .
  • the table 406 is stored in memory 108 on the computing device 102 .
  • the table 406 is stored in another location accessible to the storage device 122 or device driver 120 .
  • a structure other than a table may be used to store tracking information for each object on the storage device 122 . For example, a tree structure may be used to store the tracking information. Other structures configured to store such tracking information may also be used.
  • the storage device 122 determines the starting address where the object will be stored.
  • the starting address may already be known based on where an append point (or location where the previous object ends) is currently pointing.
  • a size of the object is used to determine the ending address for the object using the starting address.
  • the starting address may be stored with the size of the object in the table 406 .
  • the starting and ending addresses for the object are stored in the table 406 .
  • the storage device 122 finds the object in the table 406 and erases the entry associated with the object from the table 406 .
  • destroyed (or dead) objects are erased from the storage device 122 during garbage collection, as described in more detail below.
  • the storage device 122 accesses the table 406 and determines or otherwise identifies the starting address and size associated with the object from the table 406 .
  • the starting address and size are used to determine the ending address, and the storage device 122 reads the data stored at all of the addresses from the starting address to the ending address and returns the data to the computing device 102 .
  • the starting and ending addresses for the object are stored in the table 406 .
  • the storage device 122 accesses the table 406 and determines the starting address and size associated with the object from the table 406 . If the data of the write operation associated with the object has the same size as the object stored on the storage device 122 , the new data may then be written to the storage device 122 in a new location (for example, the append point ( 504 , shown in FIG. 5 ) of the log structure 400 , which may correspond to the end of the last object stored on the log structure 400 ) according to the log structure 400 of the storage device 122 , the location information in the table 406 is updated with the new location of the object, and the previous size information from the table 406 is used. If the new data from the write operation does not have the same size as the object stored on the storage device 122 , the new data is written to the storage device 122 and the location and size information are updated in the table 406 .
  • a new location for example, the append point ( 504 , shown in FIG. 5 ) of the log structure 400 , which may correspond to
  • FIG. 5 depicts a schematic diagram 500 of garbage collection in a log structure 400 on a memory device. While the garbage collection is described in conjunction with the log structure 400 shown in FIG. 5 , the garbage collection may be used in conjunction with any storage device 122 operating in a log-structured manner. Alternatively, the storage device 122 may use any suitable garbage collection methods.
  • the garbage collection is performed in a log-structured manner to maximize the lifetime of the memory elements 126 and to minimize fragmentation of data on the storage device 122 .
  • the storage device 122 is configured to perform operations for objects within the log structure 400 to clean up old objects stored on the storage device 122 and reclaim unused space. These operations allow the objects to be moved within the log structure 400 and the information stored in the table 406 for the corresponding objects may be updated accordingly.
  • a “read” operation retrieves live objects 502 (having valid data that has been committed to the storage device 122 or to a backing store 118 associated with the storage device 122 in a caching system) for the group of addresses from the storage device 122 , a “modify” operation adjusts the size of live objects (for example, by modifying the size or grouping the live objects together), and the “write” operation writes the modified live objects back to the storage device 122 at the current append point 504 in the log structure 400 .
  • the live objects 502 are fragmented in the log structure 400 prior to garbage collection, and are compacted (or placed together) after garbage collection.
  • the “write” operation may also write any dirty objects that may fit in the group of addresses for which garbage collection is being performed. After garbage collection is performed, the corresponding entries in the table 406 are updated with the new information for each object that was written to the group of addresses on the storage device 122 .
  • a remap operation may be used to remap objects to different locations to reduce fragmentation and to manage non-volatile memories such as NAND flash memory.
  • the remap operation may be performed on old, stale, and/or unused objects.
  • the remap operation may be performed on dead objects so that the storage space may be erased and reclaimed.
  • an object is read from the storage device 122 , the size of the object may be determined in order to set a size attribute in metadata for the object, and the object is written back to the storage device 122 .
  • the size attributes of the object may be changed (larger or smaller) before writing the object back to the storage device 122 .
  • the object size is not determined and a copy of the object in volatile memory may be used to create a new version of the object that is written to the storage device 122 .
  • writing the object back to the storage device includes storing the object at the append point 504 of the log structure 400 and invalidating the previous copy of the object. This may be done in NAND flash memory, for example, with a TRIM command that informs the storage device 122 that the previous object is no longer being used and may be erased.
  • FIG. 6 depicts a flow chart diagram of one embodiment of a method 600 for object based storage on a storage device 122 .
  • the method 600 is shown and described with operations of the computing device 102 of FIG. 1 , other embodiments of the method 600 may be implemented with other computing devices 102 .
  • the method 600 includes receiving 602 a memory access command to a memory storage device 122 from an application.
  • the storage device 122 is configured to provide native support for object storage, as described herein.
  • the application may be the client application 110 described in FIG. 1 .
  • the operations for the method 600 are performed partially or entirely at a hardware device manager, such as a driver 120 or controller 122 .
  • the method 600 also includes identifying 604 a physical address on the storage device 122 .
  • the physical address is mapped directly to an object identifier associated with the memory access command according to an object store interface for the storage device 122 .
  • the physical address is mapped directly to the object identifier in an absence of a block-based translation layer or other intermediate address translation layer or intermediate mapping layer for the storage device 122 .
  • the object store interface provides native object storage functionality on the storage device 122 . Providing direct mapping between the physical address and the object identifier allows the elimination of additional abstraction between the application and the storage device 122 .
  • the object identifier includes a virtual memory address.
  • the method 600 also includes performing 606 an operation associated with the memory access command for data stored at the physical address.
  • the storage device 122 is configured to process the memory access command at an operation-specific granularity.
  • processing the memory access command includes performing an operation associated with the memory access command.
  • the physical address has an arbitrary granularity associated with an object corresponding to the object identifier. Each operation may be performed at an object-level granularity according to the specific access command to the storage device 122 , such that access to the storage device 122 is based on the size of the object associated with the operation, rather than a predetermined block size.
  • the storage device 122 may be configured to create objects, destroy objects, read objects, and write objects on the storage device 122 , for example, such that each operation only accesses a number of physical addresses on the storage device 122 according to the size of each object for each operation.
  • a create object command 608 creates an object of a specific size on the storage device 122 .
  • a destroy object command 610 destroys a particular object stored on the storage device 122 , for example, by removing a reference or pointer to the object.
  • a write object command 612 writes data to the storage device 122 for a particular object that has been created on the storage device 122 .
  • Writing to an object that is already written on the storage device 122 may result in the object being written to the current append point 504 of a log structure 400 on the storage device 122 .
  • the previous version of the object may then be invalidated, for example via a TRIM command in NAND flash, and the space taken by the previous version may be reclaimed by the storage device 122 .
  • a read object command 614 reads data corresponding to a particular object from the storage device 122 .
  • the method 600 stores and maintain 616 an index such as a table 406 configured to track a location and a size of object data on the storage device 122 .
  • the object data corresponds to the object identifier.
  • the table 406 may be stored on the storage device 122 , the computing device 102 , or another storage device.
  • the table 406 may include an entry for each of the objects stored on the storage device 122 .
  • the entries may include information describing the location (such as a first address) of each object and a size of each object. The location and size information may allow the storage device 122 to find and modify stored objects.
  • the method 600 includes performing garbage collection according to a log structure 400 of the storage device 122 .
  • the garbage collection is performed by reading data from a group of physical addresses on the storage device 122 that correspond to live objects. The data for the live objects is grouped together, and written back to the group of physical addresses.
  • the garbage collection is performed by remapping data stored at a first physical address on the storage device 122 to a second physical address on the storage device 122 .
  • the method includes receiving an object operation from an application at a hardware device manager.
  • the object operation includes an object identifier.
  • the method includes performing the object operation directly on a storage device. A physical address for the object corresponding to the object identifier is mapped directly to the object identifier in an index managed by the hardware device manager.
  • Other embodiments of the method are described herein. Embodiments of a device and a system are also described herein.
  • the memory access command is an object operation that is performed directly on the storage device.
  • the object operation may be a write operation that includes writing object data to the storage device at a new physical address and mapping a physical address associated with the object identifier in the index to the new physical address.
  • the object operation may be a read operation that includes identifying, via an index (such as a table), the physical address corresponding to the object stored on the non-volatile storage device.
  • the object operation is a delete operation that includes invalidating data corresponding to a deleted object on the storage device and removing, from the index, the object identifier corresponding to the deleted object.
  • An embodiment of the network system includes at least one processor coupled directly or indirectly to memory elements through a system bus such as a data, address, and/or control bus.
  • the memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.
  • an embodiment of a computer program product includes a computer useable storage medium to store a computer readable program that, when executed on a computer, causes the computer to perform operations, as described herein.
  • Embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment containing both hardware and software elements.
  • the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc.
  • embodiments of the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system.
  • a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
  • the computer-useable or computer-readable medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device), or a propagation medium.
  • Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk.
  • Current examples of optical disks include a compact disk with read only memory (CD-ROM), a compact disk with read/write (CD-R/W), and a digital video disk (DVD).
  • I/O devices can be coupled to the system either directly or through intervening I/O controllers.
  • network adapters also may be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or memory devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the currently available types of network adapters.

Abstract

The method includes receiving an object operation from an application at a hardware device manager. The object operation includes an object identifier. The method includes performing the object operation directly on a storage device. A physical address for the object corresponding to the object identifier is mapped directly to the object identifier in an index managed by the hardware device manager.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of priority of U.S. patent application Ser. No. 12/098,433, filed on Apr. 6, 2008 and entitled “Apparatus, System, and Method for Converting a Storage Request into an Append Data Storage Command,” which is a continuation-in-part of and claims priority to U.S. patent application Ser. No. 11/952,098, filed on Dec. 6, 2007 and entitled “Apparatus, System, and Method for Servicing Object Requests within a Storage Controller” all of which are incorporated by reference herein. This application also claims the benefit of priority of U.S. patent application Ser. No. 11/952,098, filed Dec. 6, 2007 and entitled “Apparatus, System, and Method for Servicing Object Requests within a Storage Controller,” which is a continuation-in-part of and claims priority to U.S. Provisional Patent Application No. 60/873,111, filed on Dec. 6, 2006 and entitled “Elemental Blade System” and U.S. Provisional Patent Application No. 60/974,470, filed Sep. 22, 2007 and entitled “Apparatus, System, and Method for Object-Oriented Solid-State Storage” all of which are incorporated by reference herein.
  • BACKGROUND
  • Many types of electronic storage media use a block-based approach for storing or accessing data on the storage media. A block-based approach can improve performance time for certain types of storage devices, such as magnetic disk drives or other drives that include mechanical movement for reading/writing/erasing data stored on the storage devices. Due to the mechanical movement, random access to the storage devices is more time expensive than sequential access. Block-based approaches typically write data to physically sequential addresses on the storage devices to reduce access time.
  • Block-based approaches also typically access blocks of a predetermined size, regardless of whether the data being written to or read from the storage devices fills an entire block. Additionally, applications often use objects (which may vary greatly in size) as a basis of programming. Object based programming frequently uses an object store on top of the block storage layer or other block abstraction to be able to store and track the location of each object on the storage device.
  • For low latency storage devices such as flash memory, which are able to handle random access to the devices quickly, block-based approaches may not be necessary to optimize the access speed of the flash memory. However, many flash memory devices still use a block-based approach, which introduces unnecessary programming and operating system resource overheads because of the need to maintain tables and to perform read-modify-writes necessary for garbage collection and for compacting live objects to minimize fragmentation of data on the storage device.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 depicts a schematic diagram of one embodiment of a computing device in a network system.
  • FIG. 2 depicts a schematic diagram of one embodiment of a non-volatile storage device.
  • FIG. 3 depicts a schematic diagram of one embodiment of a storage controller.
  • FIG. 4A depicts a schematic diagram of one embodiment of a log structure in a memory device.
  • FIG. 4B depicts a schematic diagram of one embodiment of a table.
  • FIG. 5 depicts a schematic diagram of garbage collection in a log structure on a memory device.
  • FIG. 6 depicts a flow chart diagram of one embodiment of a method for object based storage on a memory device.
  • Throughout the description, similar reference numbers may be used to identify similar elements.
  • DETAILED DESCRIPTION
  • It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
  • The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
  • Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment of the invention. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.
  • Reference to a computer readable medium may take any physical form capable of storing machine-readable instructions, at least for a time in a non-transient state, on a digital processing apparatus. A computer readable medium may be embodied by a compact disk, digital-video disk, a blu-ray disc, a magnetic tape, a Bernoulli drive, a magnetic disk, flash memory, integrated circuits, or other digital processing apparatus memory device.
  • Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.
  • Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
  • While many embodiments are described herein, at least some of the described embodiments facilitate object based storage on a storage device (also referred to herein as a memory device or a memory storage device). The storage device may be any type of memory device, including a volatile storage device or non-volatile storage device, configured to store data. Examples of non-volatile memory include flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon-oxide based sub-10 nanometer process memory, graphene memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), Resistive random-access memory (RRAM), programmable metallization cell (PMC), conductive-bridging RAM (CBRAM), magneto-resistive RAM (MRAM), dynamic RAM (DRAM), phase change RAM (PRAM), phase change memory or other non-volatile solid-state storage media. In other embodiments, the non-volatile memory may comprise magnetic media, optical media, or other types of non-volatile storage media. For example, in those embodiments, the non-volatile storage device may include a hard disk drive, an optical storage drive, or the like.
  • While the non-volatile memory is referred to herein as a “memory device,” a “recording device” or a “storage device” in various embodiments, the non-volatile memory may more generally include a non-volatile recording media capable of recording data, the non-volatile recording media may be referred to as a non-volatile memory media, a non-volatile storage media, or the like. Further, the non-volatile storage device, in various embodiments, may include a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, or the like. In other embodiments, the storage device may be any other storage device that may be configured to store data at a non-block based granularity. The storage device may be connected to or in communication with a backing store. The storage device may be configured to operate as a memory cache for storing data that is stored on the backing store. The storage device may be configured to operate as a backing store or main storage device. The storage device may be connected to or in communication with other similar storage devices.
  • The backing store may be any type of backing store, such as a hard disk drive or other type of non-volatile storage device. The access speed (or “seek time”) of hard disk drives is generally limited due to the mechanical components of the drives. The access speed of memory devices such as flash devices is generally much faster than the access speed of hard disk drives. In an embodiment in which the storage device is a memory cache, at least some of the data on the backing store may be stored (or “cached”) on the storage device to allow an operating system or other application to quickly access the data from the storage device rather than the backing store. In other embodiments, the storage device may not be a memory cache, but may be an additional backing store or other non-volatile storage device configured store applications and/or data associated with the computing device, and the backing store may also store applications and/or data associated with the computing device.
  • Many applications use object-based languages as a basis of programming. Object-based programming use objects to describe states and operations. Because so many applications use object-based programming, interactions between applications and storage devices that are block-based typically require additional programming and operating system resources, including an object store on top of the block abstraction that allows the operating system and other applications to interact with the block-based storage device. Because flash memory devices do not necessarily have to operate at a block granularity, operating the flash memory devices at a granularity that is more compatible with applications that operate at an object granularity may improve the speed and efficiency of the operating system and storage device. Specifically, a storage device that is configured to operate at a block granularity or at an object-level granularity may eliminate the need for an additional object store on top of storage layers for the storage device. Performing operations on the storage device at an operation-specific granularity includes performing the operations for the specific size of data associated with the operation. For example, the object data associated with the operation may have any size, and an object-level granularity corresponds to the size of the data (such as the object size/length), rather than to a predetermined block size.
  • FIG. 1 depicts a schematic diagram of one embodiment of a computing device 102 in a network system 100. The depicted network system 100 includes various components, described in more detail below, that are capable of performing the functions and operations described herein. In one embodiment, at least some of the components of the network system 100 are implemented on the computing device 102. For example, the functionality of one or more components of the network system may be implemented by computer program instructions stored and executed on the computing device 102. The network system 100 may be implemented in a clustered environment or network 128 with additional computer devices. The computing device 102 may include various components, including a processor 104 (such as a CPU), input/output devices 106, a memory device 108, a storage manager 112, an object store 120, a block storage layer 114, a device driver 122, and a disk controller 116. In some embodiments, the computing device 102 includes a backing store 118. In other embodiments, the backing store 118 is not contained within the computing device 102, but may be a standalone backing store 118 or part of another computing device 102 or system. The computing device 102 may also include or be connected to one or more storage devices 122 configured to act as a memory cache or as a primary storage device. Some or all of the components of the network system 100 may be stored on a single computing device 102 or on a network 128 of computing devices 102, including a wired and/or wireless communication network. The network system 100 may include more or fewer components or subsystems than those depicted herein. In some embodiments, the network system 100 may be used to implement the methods described herein.
  • The illustrated network system 100 also includes a client application 110. In one embodiment, the client application 110 uses object-based programming. The client application 110 may be any application that submits access requests to the backing store 118 to perform read/write/erase operations on the backing store 118. The client application 110 may also submit access requests to the storage device 122 to perform operations on the storage device 122. For example, the client application 110 may be an operating system (OS), a file system, a database, or some other application capable of submitting access requests to the backing store 118. In general, the client application 110 operates in conjunction with the storage manager 112 to access data from either the storage device 122 or the backing store 118. In one embodiment, the storage manager 112 accesses the backing store 118 via the block storage layer 114. The storage manager 112 may be implemented via software in some embodiments. The block storage layer 114 may be implemented in a device driver 120, a volume manager or driver interface. The block storage layer 114 provides support to the storage manager for block-based file systems, including traditional file systems, database systems, and other software designed for magnetic disk drives. Thus, the block storage layer 114 may provide support to the storage manager 112 for the backing store 118 and other block-based storage devices. The computing device 102 may include a disk controller 116 between the block storage layer 114 and the backing store 118 to allow the block storage layer 114 to correctly locate data or specific sectors on the backing store 118.
  • In one embodiment, the backing store 118 is a block-based backing store 118, such that an object store 120 is built on top of the block storage layer 114 so that the client application 110 is able to interface with the backing store 118. In one embodiment, the storage manager 112 accesses the storage device 122 via a device driver 120 or other driver interface. The storage device 122 may operate at a non-block granularity. The device driver 120 may interface with the storage device to perform object-based storage for the storage device 122. In one embodiment, at least some of the operations for object-based storage are implemented at each of the storage device 122 and the device driver 120.
  • The storage device 122 may include a hardware device manager, such as a controller 124, that provides at least some of the functionality for object-based storage. In certain embodiments, the hardware device manager is a hardware storage device manager. In other embodiments, the hardware device manager is a hardware memory device manager. In certain embodiments, the hardware device manager may comprise a device driver 120 configured to control a storage device 122. In other embodiments, the hardware device manager may comprise a device driver 120 configured to control a non-volatile memory device (not illustrated).
  • The controller 124 may be a device interface for interacting with the device driver 120. The controller 124 may include hardware, firmware, device driver and/or software implementations, or any combination thereof. In one embodiment, the storage manager 112 accesses the storage device via the driver 120. The controller 124 on the storage device 122 exposes direct access to memory elements 126 on the storage device 122 to the device driver 120. In another embodiment, the controller 124 maintains a log structure on the storage device 122 and presents the log structure to the device driver 120. The device driver 120 may cooperate with hardware support offered by the controller 124 corresponding to the storage device 122. In one embodiment, the device driver 120 may provide support for any type of storage granularity, including an object-level granularity, which may include mapping physical addresses for the memory elements 126 to logical addresses or virtual addresses. Object-level granularity may reduce programming requirements or operating system resources needed to interact with the storage device 122 because object-level granularity performs the operations associated with access requests at a granularity or size for the specific data associated with the access requests. For example, an object operation may be performed directly on the storage device 122 at a granularity that corresponds to the size of the object of the object operation, rather than at a granularity that corresponds to a predetermined block size for block-based storage media. Implementing such functions at the device driver 120 also eliminates the need for a separate address translation layer at the controller 124 on the storage device 122.
  • Address translation for the backing store 118 or storage device 122 may include operating independently of an existing operating system and file system to map physical addresses such as physical block addresses (PBAs) of the memory elements 126 to the logical block addresses (LBAs) in an organized structure. In other embodiments, the address translation, for example at the device driver 120 or block storage layer 114, operates in conjunction with an existing operating system on the computing device 102 to map the physical addresses of the memory elements 126 or backing store 118 to the LBAs. The LBAs allow storage manager 112 to maintain a logical organization for the storage device while potentially storing related data in different physical locations in the storage device. The device driver 120 may also manage where data is written so that data is written to the correct locations in the storage device 122 based on where the storage device 122 has been cleaned or erased, so that subsequent access requests to the data are directed to the correct physical locations in the storage device 122.
  • The storage manager 112 or an address translation layer (ATL) also may map the LBAs to PBAs on the backing store 118, in an embodiment in which the backing store 118 is not a block-based storage device. This may allow the ATL to manage and track the data on the backing store 118. In one embodiment, the ATL maps an LBA to a single PBA of the backing store 118.
  • In another embodiment, the device driver 120 manages storing allocation information for each object within the storage device 122. Each object corresponds to a virtual location presented by the device driver 120 to the operating system and higher level software layers. Within the storage device 122, access requests are processed at an object-level or operation-specific granularity, rather than predetermined blocks. The granularity corresponds to a physical address (or group of physical addresses) of the memory elements 126 associated with the operation. Using this addressing approach, the device driver 120 may translate the logical address presented by the client application 110 to one or more physical addresses of the corresponding memory elements 126. The device driver 120 or storage manager 112 may perform additional mapping if needed. In order to facilitate these mappings, the device driver 120 may manage various data structures. For example, the device driver 120 may manage a table (such as an indirection table) for tracking the location and size of each object on the storage device 122. The device driver 120 may manage the objects in a log-structured manner. In various embodiments, the indirection table and/or log structure for the storage device 122 may be stored on the computing device 102 (for example, in memory 108) or on the storage device 122.
  • The storage device 122 may be any kind of storage device 122. The storage device 122 may be a non-volatile storage device in which data stored on the storage device 122 persists across reboots, such that on reboot of the storage device 122, the data may need to be invalidated for various reasons. These reasons may include, but are not limited to, changes in the data for the corresponding locations on the backing store and/or storing information related to the ATL in volatile memory which is erased during a reboot.
  • In one embodiment, memory elements 126 in the storage device 122 for storing data are organized in an array or in multiple arrays. The storage device 122 may be a volatile storage device or a caching device implemented using any known caching technology. In some embodiments, the memory elements 126 are cells that are part of an integrated circuit (IC) package or chip. Each chip may include one or more die, and each die includes an array of memory elements 126.
  • The storage device 122 may be used for storing data associated with the computing device 102 or other computing devices 102 connected to a network 128. Although the computing device 102 is shown with two storage devices 122, other embodiments of the computing device 102 may include one or more than one storage device 122. Similarly, multiple storage devices 122 may be implemented at various locations within the nodes of the network 128. Embodiments of the network 128 may provide dedicated or shared memory resources for one or more of the computing devices 102, though other implementations of storage/memory resources or capacity may be used in conjunction with the network 128.
  • The memory elements 126 may be operated in a variety of modes. In general, solid-state memory elements 126 can be set to different programmable states that correspond to different bits or bit combinations. In a specific example, the memory elements 126 may be operated in a single level cell (SLC) mode to store a single bit of data. In another example, the memory elements 126 may be operated in a multiple level cell (MLC) mode to store two or more bits of data. In another example, the memory elements 126 may be MLC memory elements configured to operate in an SLC mode. In other embodiments, the storage device 122 includes other types of memory elements 126.
  • Although the components of the network system 100 are shown separately, one or more components may provide some or all of the functionality of other components in the network system 100. For example, while the storage manager 112 is depicted between the client application 110 and the block storage layer 114 and device driver 120, some or all of the functionality of the storage manager 112 may be implemented at the client application 110 or at either the block storage layer 114 or the device driver 120. Conversely, some or all of the functionality of the block storage layer 114 and device driver 120 may be implemented at the storage manager 112. Alternatively, the components of the computing device 102 may be different than shown in FIG. 1 while being configured to perform the operations described herein.
  • In one embodiment, the controller 124 on the storage device 122 interfaces with the device driver 120 to perform the operations for storing data corresponding to access requests from the client application 110 at an object-level or operation-specific granularity. The operation-specific granularity is determined by the data associated with the access request. The data may correspond to an object associated with the client application 110. In such an embodiment, the data is stored on the storage device 122 or accessed from the storage device 120 (or other operation associated with the access request, such as creating or destroying objects) at an object-level granularity, rather than a block granularity as with block-based storage devices.
  • To operate at an object-level granularity, the device driver 120 and controller 124 may be able to perform various functions associated with storing objects on the storage device 122. For example, the functions may include object operations such as: creating an object with an associated object identifier; destroying an object stored on the storage device 122; reading an object from the storage device 122 based on the associated object identifier and a size of the object; and writing data associated with an object already present on the storage device 122 based on the object identifier and a size of the object. The functions may include maintaining an indirection table that may be used to track the location and sizes of the objects on the storage device 122. The functions may include performing read/write operations on the storage device 122 at an arbitrary granularity, as described in accordance with the object operations. The functions may include garbage collection on the storage device 122 to maintain the log structure of the storage device 122 by eliminating dead objects and consolidating (or compacting) live objects on the storage device 122. Dead objects may include objects that are no longer used or referenced by the client application 110. Live objects may include valid data for objects used or referenced by the client application 110. In some embodiments, the storage device 122 may also include dirty objects. Dirty objects may be objects that are new, modified, or deleted, but that have not been committed to the storage device 122 or backing store 118. To perform garbage collection, the functions may include performing read-modify-write operations on object data stored on the storage device.
  • FIG. 2 depicts a schematic diagram of one embodiment 200 of a non-volatile storage device 122 that includes a non-volatile storage device controller 124. In one embodiment, the storage device controller 124 is the storage device controller of FIG. 1. The non-volatile storage device controller 124 may include a number of storage controllers 0-N 204 a-n, each controlling non-volatile storage media 205. In the depicted embodiment, two non-volatile controllers are shown: non-volatile controller 0 204 a and storage controller N 204 n, and each controlling respective non-volatile storage media 205 a-n. In the depicted embodiment, storage controller 0 204 a controls a data channel so that the attached non-volatile storage media 205 a stores data. Storage controller N 204 n controls an index metadata channel associated with the stored data and the associated non-volatile storage media 205 n stores index metadata. In an alternate embodiment, the non-volatile storage device controller 124 includes a single non-volatile controller 204 a with a single non-volatile storage media 205 a. In another embodiment, there are a plurality of storage controllers 104 a-n and associated non-volatile storage media 205 a-n. In one embodiment, one or more non-volatile controllers 104 a-104 n−1, coupled to their associated non-volatile storage media 205 a-110 n−1, control data while at least one storage controller 204 n, coupled to its associated non-volatile storage media 205 n, controls index metadata.
  • In one embodiment, at least one non-volatile controller 204 is a field-programmable gate array (“FPGA”) and controller functions are programmed into the FPGA. In another embodiment, the storage controller 204 includes components specifically designed as a storage controller 204, such as an application-specific integrated circuit (“ASIC”) or custom logic solution. Each storage controller 204 typically includes a write data pipeline 301 and a read data pipeline 303, which are describe further in relation to FIG. 3. In another embodiment, at least one storage controller 204 is made up of a combination FPGA, ASIC, and custom logic components.
  • The non-volatile storage media 205 is an array of non-volatile non-volatile storage elements 216, 218, 220, arranged in banks 214, and accessed in parallel through a bi-directional storage input/output (“I/O”) bus 210. The storage I/O bus 210, in one embodiment, is capable of unidirectional communication at any one time. For example, when data is being written to the non-volatile storage media 205, data cannot be read from the non-volatile storage media 205. In another embodiment, data can flow both directions simultaneously. However bi-directional, as used herein with respect to a data bus, refers to a data pathway that can have data flowing in only one direction at a time, but when data flowing one direction on the bi-directional data bus is stopped, data can flow in the opposite direction on the bi-directional data bus.
  • A non-volatile storage element (e.g., SSS 0.0 216 a) is typically configured as a chip (a package of one or more dies) or a die on a circuit board. As depicted, a non-volatile storage element (e.g., 216 a) operates independently or semi-independently of other non-volatile storage elements (e.g., 218 a) even if these several elements are packaged together in a chip package, a stack of chip packages, or some other package element. As depicted, a row of non-volatile storage elements 216 a, 216 b, 216 m is designated as a bank 214. As depicted, there may be “n” banks 214 a-n and “m” non-volatile storage elements 216 a-m, 218 a-m, 220 a-m per bank in an array of n×m non-volatile storage elements 216, 218, 220 in a non-volatile storage media 205. Of course, different embodiments may include different values for n and m. In one embodiment, a non-volatile storage media 205 a includes twenty non-volatile storage elements 216 a-216 m per bank 214 with eight banks 214. In one embodiment, the non-volatile storage media 205 a includes twenty-four non-volatile storage elements 216 a-216 m per bank 214 with eight banks 214. In addition to the n×m storage elements 216 a-216 m, 218 a-218 m, 220 a-220 m, one or more additional columns (P) may also be addressed and operated in parallel with other non-volatile storage elements 216 a, 216 b, 216 m for one or more rows. The added P columns in one embodiment, store parity data for the portions of an ECC chunk (i.e., an ECC codeword) that span m storage elements for a particular bank. In one embodiment, each non-volatile storage element 216, 218, 220 includes single-level cell (“SLC”) devices. In another embodiment, each non-volatile storage element 216, 218, 220 includes multi-level cell (“MLC”) devices.
  • In one embodiment, non-volatile storage elements that share a common line 211 on the storage I/O bus 210 a (e.g., 216 b, 218 b, 220 b) are packaged together. In one embodiment, a non-volatile storage element 216, 218, 220 may have one or more dies per package with one or more packages stacked vertically and each die may be accessed independently. In another embodiment, a non-volatile storage element (e.g., SSS 0.0 216 a) may have one or more virtual dies per die and one or more dies per package and one or more packages stacked vertically and each virtual die may be accessed independently. In another embodiment, a non-volatile storage element SSS 0.0 216 a may have one or more virtual dies per die and one or more dies per package with some or all of the one or more dies stacked vertically and each virtual die may be accessed independently.
  • In one embodiment, two dies are stacked vertically with four stacks per group to form eight storage elements (e.g., SSS 0.0-SSS 8.0) 216 a, 218 a . . . 220 a, each in a separate bank 214 a, 214 b . . . 214 n. In another embodiment, 24 storage elements (e.g., SSS 0.0-SSS 0.24) 216 a, 216 b, . . . 216 m form a logical bank 214 a so that each of the eight logical banks has 24 storage elements (e.g., SSS0.0-SSS 8.24) 216, 218, 220. Data is sent to the non-volatile storage media 205 over the storage I/O bus 210 to all storage elements of a particular group of storage elements (SSS 0.0-SSS 8.0) 216 a, 218 a, 220 a. The storage control bus 212 a is used to select a particular bank (e.g., Bank 0 214 a) so that the data received over the storage I/O bus 210 connected to all banks 214 is written just to the selected bank 214 a.
  • In one embodiment, the storage I/O bus 210 includes one or more independent I/O buses (210 a.a-m . . . 210 n.a-m) in which the non-volatile storage elements within each column share one of the independent I/O buses that are connected to each non-volatile storage element 216, 218, 220 in parallel. For example, one independent I/O bus 210 a.a of the storage I/O bus 210 a may be physically connected to a first non-volatile storage element 216 a, 218 a, 220 a of each bank 214 a-n. A second independent I/O bus 210 a.b of the storage I/O bus 210 b may be physically connected to a second non-volatile storage element 216 b, 218 b, 220 b of each bank 214 a-n. Each non-volatile storage element 216 a, 216 b, 216 m in a bank 214 a (a row of non-volatile storage elements as illustrated in FIG. 2) may be accessed simultaneously and/or in parallel. In one embodiment, where non-volatile storage elements 216, 218, 220 include stacked packages of dies, all packages in a particular stack are physically connected to the same independent I/O bus. As used herein, “simultaneously” also includes near simultaneous access where devices are accessed at slightly different intervals to avoid switching noise. Simultaneously is used in this context to be distinguished from a sequential or serial access in which commands and/or data are sent individually one after the other.
  • Typically, banks 214 a-n are independently selected using the storage control bus 212. In one embodiment, a bank 214 is selected using a chip enable or chip select. Where both chip select and chip enable are available, the storage control bus 212 may select one package within a stack of packages. In other embodiments, other commands are used by the storage control bus 212 to individually select one package within a stack of packages. Non-volatile storage elements 216, 218, 220 may also be selected through a combination of control signals and address information transmitted on storage I/O bus 210 and the storage control bus 212.
  • Typically, when a packet is written to a particular location within a non-volatile storage element 216, wherein the packet is intended to be written to a location which is specific to a particular storage element of a particular bank, a physical address is sent on the storage I/O bus 210 and is followed by the packet. The physical address contains enough information for the non-volatile storage element 216 to direct the packet to the designated location. Since all storage elements in a column of storage elements (e.g., SSS 0.0-SSS N.0 216 a, 218 a, . . . 220 a) are connected to the same independent I/O bus (e.g., 210.a.a) of the storage I/O bus 210 a, to reach the proper location and to avoid writing the data packet to similarly addressed locations in the column of storage elements (SSS 0.0-SSS N.0 216 a, 218 a, . . . 220 a), the bank 214 a that includes the non-volatile storage element SSS 0.0 216 a with the correct location where the data packet is to be written is selected by the storage control bus 212 a and other banks 214 b . . . 214 n of the non-volatile storage 110 a are deselected.
  • Similarly, satisfying a read command on the storage I/O bus 210 requires a signal on the storage control bus 212 to select a single bank 214 a and the appropriate location within that bank 214 a. In one embodiment, a read command reads an entire set of addresses, and because there are multiple non-volatile storage elements 216 a, 216 b, . . . 216 m in parallel in a bank 214 a, an entire logical group of addresses is read with a read command. However, the read command may be broken into subcommands, as will be explained below with respect to bank interleave. Similarly, an entire logical group of addresses may be written to the non-volatile storage elements 216 a, 216 b, . . . 216 m of a bank 214 a in a write operation. The group of addresses read from or written to the non-volatile storage elements 216 a, 216 b, . . . 216 m correspond to the particular operation and a size of the object corresponding to the operation.
  • An erase command may be sent out to erase a group of addresses corresponding to an object over the storage I/O bus 210 with a particular erase address to erase a particular group of addresses. Typically, storage controller 204 a may send an erase command over the parallel paths (independent I/O buses 210 a-n.a-m) of the storage I/O bus 210 to erase a logical group of addresses, each with a particular address to erase a particular group of addresses. Simultaneously, a particular bank (e.g., Bank 0 214 a) is selected over the storage control bus 212 to prevent erasure of similarly addressed locations in non-selected banks (e.g., Banks 1-N 214 b-n). Alternatively, no particular bank (e.g., Bank 0 214 a) is selected over the storage control bus 212 (or all of the banks are selected) to enable erasure of similarly addressed locations in all of the banks (Banks 1-N 214 b-n) in parallel. Other commands may also be sent to a particular location using a combination of the storage I/O bus 210 and the storage control bus 212. One of skill in the art will recognize other ways to select a particular storage location using the bi-directional storage I/O bus 210 and the storage control bus 212.
  • In one embodiment, packets are written sequentially to the non-volatile storage media 205. For example, storage controller 204 a streams packets to storage write buffers of a bank 214 a of storage elements 216 and, when the buffers are full, the packets are programmed to a designated logical location. Storage controller 204 a then refills the storage write buffers with packets and, when full, the packets are written to the next logical location. The next logical location may be in the same bank 214 a or another bank (e.g., 214 b). This process continues, logical location after logical location, typically until the addresses corresponding to an object for the particular operation are erased. In another embodiment, the streaming may continue across logical boundaries for multiple objects. The read/write/erase operations may result in operations being performed on varying numbers of non-volatile storage elements 216 a, 216 b, . . . 216 m according to the objects associated with the access requests.
  • In a read, modify, write operation, data packets associated with requested data are located and read in a read operation. Data segments of the modified requested data that have been modified are not written to the location from which they are read. Instead, the modified data segments are again converted to data packets and then written sequentially to the next available location according to a log structure. The index entries for the respective data packets are modified to point to the packets that contain the modified data segments. The entry or entries in the index for data packets associated with the same requested data that have not been modified will include pointers to original location of the unmodified data packets. Thus, if the original requested data is maintained, for example to maintain a previous version of the requested data, the original requested data will have pointers in the index to all data packets as originally written. The new requested data may have pointers in the index to some of the original data packets and pointers to the modified data packets in the logical location that is currently being written.
  • In a copy operation, the index includes an entry for the original requested data mapped to a number of packets stored in the non-volatile storage media 205. When a copy is made, a new copy of the requested data is created and a new entry is created in the index mapping the new copy of the requested data to the original packets. The new copy of the requested data is also written to the non-volatile storage media 205 with its location mapped to the new entry in the index. The new copy of the requested data packets may be used to identify the packets within the original requested data that are referenced in case changes have been made in the original requested data that have not been propagated to the copy of the requested data and the index is lost or corrupted.
  • In various embodiments, the non-volatile storage device controller 124 also includes a data bus 207, a local bus 206, a buffer controller 208, buffers 0-N 222 a-n, a master controller 224, a direct memory access (“DMA”) controller 226, a memory controller 228, a dynamic memory array 230, a static random memory array 232, a management controller 234, a management bus 236, a bridge 238 to a system bus 240, and miscellaneous logic 242, which are described below. In other embodiments, the system bus 240 is coupled to one or more network interface cards (“NICs”) 244, some of which may include remote DMA (“RDMA”) controllers 246, one or more central processing unit (“CPU”) 248, one or more external memory controllers 250 and associated external memory arrays 252, one or more storage controllers 254, peer controllers 256, and application specific processors 258, which are described below. The components 244-258 connected to the system bus 240 may be located in the host computing system 114 or may be other devices.
  • Typically, the storage controller(s) 104 communicate data to the non-volatile storage media 205 over a storage I/O bus 210. In a typical embodiment where the non-volatile storage is arranged in banks 214 and each bank 214 includes multiple storage elements 216 a, 216 b, 216 m accessed in parallel, the storage I/O bus 210 is an array of busses, one for each column of storage elements 216, 218, 220 spanning the banks 214. As used herein, the term “storage I/O bus” may refer to one storage I/O bus 210 or an array of independent data busses wherein individual data busses of the array independently communicate different data relative to one another. In one embodiment, each storage I/O bus 210 accessing a column of storage elements (e.g., 216 a, 218 a, 220 a) may include a logical-to-physical mapping for storage divisions (e.g., erase blocks) accessed in a column of storage elements 216 a, 218 a, 220 a. This mapping (or bad block remapping) allows a logical address mapped to a physical address of a storage division to be remapped to a different storage division if the first storage division fails, partially fails, is inaccessible, or has some other problem.
  • Data may also be communicated to the storage controller(s) 104 from a requesting device 155 through the system bus 240, bridge 238, local bus 206, buffer(s) 222, and finally over a data bus 207. The data bus 207 typically is connected to one or more buffers 222 a-n controlled with a buffer controller 208. The buffer controller 208 typically controls transfer of data from the local bus 206 to the buffers 222 and through the data bus 207 to the pipeline input buffer 306 and output buffer 330. The buffer controller 208 typically controls how data arriving from a requesting device can be temporarily stored in a buffer 222 and then transferred onto a data bus 207, or vice versa, to account for different clock domains, to prevent data collisions, etc. The buffer controller 208 typically works in conjunction with the master controller 224 to coordinate data flow. As data arrives, the data will arrive on the system bus 240, be transferred to the local bus 206 through a bridge 238.
  • Typically, the data is transferred from the local bus 206 to one or more data buffers 222 as directed by the master controller 224 and the buffer controller 208. The data then flows out of the buffer(s) 222 to the data bus 207, through a non-volatile controller 204, and on to the non-volatile storage media 205 such as NAND flash or other storage media. In one embodiment, data and associated out-of-band metadata (“metadata”) arriving with the data is communicated using one or more data channels having one or more storage controllers 104 a-104 n−1 and associated non-volatile storage media 205 a-110 n−1 while at least one channel (storage controller 204 n, non-volatile storage media 205 n) is dedicated to in-band metadata, such as index information and other metadata generated internally to the non-volatile storage device 122.
  • The local bus 206 is typically a bidirectional bus or set of busses that allows for communication of data and commands between devices internal to the non-volatile storage device controller 124 and between devices internal to the non-volatile storage device 122 and devices 244-258 connected to the system bus 240. The bridge 238 facilitates communication between the local bus 206 and system bus 240. One of skill in the art will recognize other embodiments such as ring structures or switched star configurations and functions of buses 240, 206, 204, 210 and bridges 238.
  • The system bus 240 is typically a bus of a host computing system 114 or other device in which the non-volatile storage device 122 is installed or connected. In one embodiment, the system bus 240 may be a PCI-e bus, a Serial Advanced Technology Attachment (“serial ATA”) bus, parallel ATA, or the like. In another embodiment, the system bus 240 is an external bus such as small computer system interface (“SCSI”), FireWire, Fiber Channel, USB, PCIe-AS, or the like. The non-volatile storage device 122 may be packaged to fit internally to a device or as an externally connected device.
  • The non-volatile storage device controller 124 includes a master controller 224 that controls higher-level functions within the non-volatile storage device 122. The master controller 224, in various embodiments, controls data flow by interpreting object requests and other requests, directs creation of indexes to map object identifiers associated with data to physical locations of associated data, coordinating DMA requests, etc. Many of the functions described herein are controlled wholly or in part by the master controller 224.
  • In one embodiment, the master controller 224 uses embedded controller(s). In another embodiment, the master controller 224 uses local memory such as a dynamic memory array 230 (dynamic random access memory “DRAM”), a static memory array 232 (static random access memory “SRAM”), etc. In one embodiment, the local memory is controlled using the master controller 224. In another embodiment, the master controller 224 accesses the local memory via a memory controller 228. In another embodiment, the master controller 224 runs a Linux server and may support various common server interfaces, such as the World Wide Web, hyper-text markup language (“HTML”), etc. In another embodiment, the master controller 224 uses a nano-processor. The master controller 224 may be constructed using programmable or standard logic, or any combination of controller types listed above. One skilled in the art will recognize many embodiments for the master controller 224.
  • In one embodiment, where the storage device/non-volatile storage device controller 124 manages multiple data storage devices/non-volatile storage media 205 a-n, the master controller 224 divides the work load among internal controllers, such as the storage controllers 104 a-n. For example, the master controller 224 may divide an object to be written to the data storage devices (e.g., non-volatile storage media 205 a-n) so that a portion of the object is stored on each of the attached data storage devices. This feature is a performance enhancement allowing quicker storage and access to an object. In one embodiment, the master controller 224 is implemented using an FPGA. In another embodiment, the firmware within the master controller 224 may be updated through the management bus 236, the system bus 240 over a network connected to a NIC 244 or other device connected to the system bus 240.
  • In one embodiment, the master controller 224 coordinates with NIC controllers 244 and embedded RDMA controllers 246 to deliver just-in-time RDMA transfers of data and command sets. NIC controller 244 may be hidden behind a non-transparent port to enable the use of custom drivers. Also, a driver 120 on a host computing system 114 may have access to the computer network 116 through an I/O memory driver using a standard stack API and operating in conjunction with NICs 244.
  • In one embodiment, the master controller 224 is also a redundant array of independent drive (“RAID”) controller. Where the data storage device/non-volatile storage device 122 is networked with one or more other data storage devices/non-volatile storage devices 102, the master controller 224 may be a RAID controller for single tier RAID, multi-tier RAID, progressive RAID, etc. The master controller 224 also allows some objects to be stored in a RAID array and other objects to be stored without RAID. In another embodiment, the master controller 224 may be a distributed RAID controller element. In another embodiment, the master controller 224 may include many RAID, distributed RAID, and other functions as described elsewhere.
  • In one embodiment, the master controller 224 coordinates with single or redundant network managers (e.g., switches) to establish routing, to balance bandwidth utilization, failover, etc. In another embodiment, the master controller 224 coordinates with integrated application specific logic (via local bus 206) and associated driver software. In another embodiment, the master controller 224 coordinates with attached application specific processors 258 or logic (via the external system bus 240) and associated driver software. In another embodiment, the master controller 224 coordinates with remote application specific logic (via the computer network 116) and associated driver software. In another embodiment, the master controller 224 coordinates with the local bus 206 or external bus attached hard disk drive (“HDD”) storage controller.
  • In one embodiment, the master controller 224 communicates with one or more storage controllers 254 where the storage device/non-volatile storage device 122 may appear as a storage device connected through a SCSI bus, Internet SCSI (“iSCSI”), fiber channel, etc. Meanwhile the storage device/non-volatile storage device 122 may autonomously manage objects and may appear as an object file system or distributed object file system. The master controller 224 may also be accessed by peer controllers 256 and/or application specific processors 258.
  • In another embodiment, the master controller 224 coordinates with an autonomous integrated management controller to periodically validate FPGA code and/or controller software, validate FPGA code while running (reset) and/or validate controller software during power on (reset), support external reset requests, support reset requests due to watchdog timeouts, and support voltage, current, power, temperature, and other environmental measurements and setting of threshold interrupts. In another embodiment, the master controller 224 manages garbage collection to free erase blocks for reuse. In another embodiment, the master controller 224 manages wear leveling. In another embodiment, the master controller 224 allows the data storage device/non-volatile storage device 122 to be partitioned into multiple logical devices and allows partition-based media encryption. In yet another embodiment, the master controller 224 supports a storage controller 204 with advanced, multi-bit ECC correction. One of skill in the art will recognize other features and functions of a master controller 224 in a storage controller 124, or more specifically in a non-volatile storage device 122.
  • In one embodiment, the non-volatile storage device controller 124 includes a memory controller 228, which controls a dynamic random memory array 230 and/or a static random memory array 232. As stated above, the memory controller 228 may be independent or integrated with the master controller 224. The memory controller 228 typically controls volatile memory of some type, such as DRAM (dynamic random memory array 230) and SRAM (static random memory array 232). In other examples, the memory controller 228 also controls other memory types such as electrically erasable programmable read only memory (“EEPROM”), etc. In other embodiments, the memory controller 228 controls two or more memory types and the memory controller 228 may include more than one controller. Typically, the memory controller 228 controls as much SRAM 232 as is feasible and by DRAM 230 to supplement the SRAM 232.
  • In one embodiment, the object index is stored in memory 230, 232 and then periodically off-loaded to a channel of the non-volatile storage media 205 n or other non-volatile memory. One of skill in the art will recognize other uses and configurations of the memory controller 228, dynamic memory array 230, and static memory array 232.
  • In one embodiment, the non-volatile storage device controller 124 includes a DMA controller 226 that controls DMA operations between the storage device/non-volatile storage device 122 and one or more external memory controllers 250 and associated external memory arrays 252 and CPUs 248. Note that the external memory controllers 250 and external memory arrays 252 are called external because they are external to the storage device/non-volatile storage device 122. In addition, the DMA controller 226 may also control RDMA operations with requesting devices through a NIC 244 and associated RDMA controller 246.
  • In one embodiment, the non-volatile storage device controller 124 includes a management controller 234 connected to a management bus 236. Typically, the management controller 234 manages environmental metrics and status of the storage device/non-volatile storage device 122. The management controller 234 may monitor device temperature, fan speed, power supply settings, etc. over the management bus 236. The management controller 234 may support the reading and programming of erasable programmable read only memory (“EEPROM”) for storage of FPGA code and controller software. Typically, the management bus 236 is connected to the various components within the storage device/non-volatile storage device 122. The management controller 234 may communicate alerts, interrupts, etc. over the local bus 206 or may include a separate connection to a system bus 240 or other bus. In one embodiment, the management bus 236 is an Inter-Integrated Circuit (“I2C”) bus. One of skill in the art will recognize other related functions and uses of a management controller 234 connected to components of the storage device/non-volatile storage device 122 by a management bus 236.
  • In one embodiment, the non-volatile storage device controller 124 includes miscellaneous logic 242 that may be customized for a specific application. Typically, where the non-volatile device controller 124 or master controller 224 is/are configured using a FPGA or other configurable controller, custom logic may be included based on a particular application, customer requirement, storage requirement, etc.
  • While the controller 124 of FIG. 2 is shown, other embodiments of a controller 124 may be used to implement the operations for object-based storage on a storage device 122.
  • FIG. 3 depicts a schematic diagram of one embodiment 300 of the storage controller 204 of FIG. 2 with a write data pipeline 301, a read data pipeline 303 and a throughput management apparatus 122 in a non-volatile storage device 122. The embodiment 300 includes a data bus 207, a local bus 206, and buffer control 208, which are substantially similar to those described in relation to the non-volatile storage device controller 124 of FIG. 2. The write data pipeline 301 includes a packetizer 302 and an error-correcting code (“ECC”) generator 304. In other embodiments, the write data pipeline 301 includes an input buffer 306, a write synchronization buffer 308, a write program module 310, a compression module 312, an encryption module 314, a garbage collector bypass 316 (with a portion within the read data pipeline 303), a media encryption module 318, and a write buffer 320. The read data pipeline 303 includes a read synchronization buffer 328, an ECC correction module 322, a depacketizer 324, an alignment module 326, and an output buffer 330. In other embodiments, the read data pipeline 303 may include a media decryption module 332, a portion of the garbage collector bypass 316, a decryption module 334, a decompression module 336, and a read program module 338. The storage controller 204 may also include control and status registers 340 and control queues 342, a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350. The components of the non-volatile controller 204 and associated write data pipeline 301 and read data pipeline 303 are described below. In other embodiments, synchronous non-volatile storage media 205 may be used and synchronization buffers 308, 328 may be eliminated.
  • The write data pipeline 301 includes a packetizer 302 that receives a data or metadata segment to be written to the non-volatile storage, either directly or indirectly through another write data pipeline 301 stage, and creates one or more packets sized for the non-volatile storage media 205. The data or metadata segment is typically part of a data structure such as an object, but may also include an entire data structure. In another embodiment, the data segment is part of a block of data, but may also include an entire block of data. Typically, a set of data such as a data structure is received from a computer such as the host computing system 114, or other computer or device and is transmitted to the non-volatile storage device 122 in data segments streamed to the non-volatile storage device 122. A data segment may also be known by another name, such as data parcel, but as referenced herein includes all or a portion of a data structure or data block.
  • Each data structure is stored as one or more packets. Each data structure may have one or more container packets. Each packet contains a header. The header may include a header type field. Type fields may include data, attribute, metadata, data segment delimiters (multi-packet), data structures, data linkages, and the like. The header may also include information regarding the size of the packet, such as the number of bytes of data included in the packet. The length of the packet may be established by the packet type. The header may include information that establishes the relationship of the packet to a data structure. An example might be the use of an offset in a data packet header to identify the location of the data segment within the data structure. One of skill in the art will recognize other information that may be included in a header added to data by a packetizer 302 and other information that may be added to a data packet.
  • Each packet includes a header and possibly data from the data or metadata segment. The header of each packet includes pertinent information to relate the packet to the data structure to which the packet belongs. For example, the header may include an object identifier or other data structure identifier and offset that indicate the data segment, object, data structure or data block from which the data packet was formed. The header may also include a logical address used by the storage bus controller 348 to store the packet. The header may also include information regarding the size of the packet, such as the number of bytes included in the packet. The header may also include a sequence number that identifies where the data segment belongs with respect to other packets within the data structure when reconstructing the data segment or data structure. The header may include a header type field. Type fields may include data, data structure attributes, metadata, data segment delimiters (multi-packet), data structure types, data structure linkages, and the like. One of skill in the art will recognize other information that may be included in a header added to data or metadata by a packetizer 302 and other information that may be added to a packet.
  • In one embodiment, the write data pipeline 301 includes an ECC generator 304 that that generates one or more error-correcting codes (“ECC”) for the one or more packets received from the packetizer 302. In other embodiments, the write data pipeline 301 does not include an ECC generator 304. The ECC generator 304 typically uses an error-correcting algorithm to generate ECC check bits, which are stored with the one or more data packets. The ECC codes generated by the ECC generator 304 together with the one or more data packets associated with the ECC codes include an ECC chunk. The ECC data stored with the one or more data packets is used to detect and to correct errors introduced into the data through transmission and storage. In one embodiment, packets are streamed into the ECC generator 304 as un-encoded blocks of length N. A syndrome of length S is calculated, appended, and output as an encoded block of length N+S. The value of N and S are dependent upon the characteristics of the ECC algorithm, which is selected to achieve specific performance, efficiency, and robustness metrics. In one embodiment, there is no fixed relationship between the ECC blocks and the packets; the packet may include more than one ECC block; the ECC block may include more than one packet; and a first packet may end anywhere within the ECC block and a second packet may begin after the end of the first packet within the same ECC block. In one embodiment, ECC algorithms are not dynamically modified. In one embodiment, the ECC data stored with the data packets is robust enough to correct errors in more than two bits.
  • Beneficially, using a robust ECC algorithm allowing more than single bit correction or even double bit correction allows the life of the non-volatile storage media 205 to be extended. For example, if flash memory is used as the storage medium in the non-volatile storage media 205, the flash memory may be written approximately 100,000 times without error per erase cycle. This usage limit may be extended using a robust ECC algorithm. Having the ECC generator 304 and corresponding ECC correction module 322 onboard the non-volatile storage device 122, the non-volatile storage device 122 can internally correct errors and has a longer useful life than if a less robust ECC algorithm is used, such as single bit correction. However, in other embodiments the ECC generator 304 may use a less robust algorithm and may correct single-bit or double-bit errors. In another embodiment, the non-volatile storage device 110 may include less reliable storage such as multi-level cell (“MLC”) flash in order to increase capacity, which storage may not be sufficiently reliable without more robust ECC algorithms.
  • In one embodiment, the write pipeline 301 includes an input buffer 306 that receives a data segment to be written to the non-volatile storage media 205 and stores the incoming data segments until the next stage of the write data pipeline 301, such as the packetizer 302 (or other stage for a more complex write data pipeline 301) is ready to process the next data segment. The input buffer 306 typically allows for discrepancies between the rate data segments are received and processed by the write data pipeline 301 using an appropriately sized data buffer. The input buffer 306 also allows the data bus 207 to transfer data to the write data pipeline 301 at rates greater than can be sustained by the write data pipeline 301 in order to improve efficiency of operation of the data bus 207. Typically, when the write data pipeline 301 does not include an input buffer 306, a buffering function is performed elsewhere, such as in the non-volatile storage device 122 but outside the write data pipeline 301, in the host computing system 114, such as within a network interface card (“NIC”), or at another device, for example when using remote direct memory access (“RDMA”).
  • In another embodiment, the write data pipeline 301 also includes a write synchronization buffer 308 that buffers packets received from the ECC generator 304 prior to writing the packets to the non-volatile storage media 205. The write synchronization buffer 308 is located at a boundary between a local clock domain and a non-volatile storage clock domain and provides buffering to account for the clock domain differences. In other embodiments, synchronous non-volatile storage media 205 may be used and synchronization buffers 308 328 may be eliminated.
  • In one embodiment, the write data pipeline 301 also includes a media encryption module 318 that receives the one or more packets from the packetizer 302, either directly or indirectly, and encrypts the one or more packets using an encryption key unique to the non-volatile storage device 122 prior to sending the packets to the ECC generator 304. Typically, the entire packet is encrypted, including the headers. In another embodiment, headers are not encrypted. In this document, encryption key is understood to mean a secret encryption key that is managed externally from a storage controller 204.
  • The media encryption module 318 and corresponding media decryption module 332 provide a level of security for data stored in the non-volatile storage media 205. For example, where data is encrypted with the media encryption module 318, if the non-volatile storage media 205 is connected to a different storage controller 204, non-volatile storage device 122, or server, the contents of the non-volatile storage media 205 typically could not be read without use of the same encryption key used during the write of the data to the non-volatile storage media 205 without significant effort.
  • In a typical embodiment, the non-volatile storage device 122 does not store the encryption key in non-volatile storage and allows no external access to the encryption key. The encryption key is provided to the storage controller 204 during initialization. The non-volatile storage device 122 may use and store a non-secret cryptographic nonce that is used in conjunction with an encryption key. A different nonce may be stored with every packet. Data segments may be split between multiple packets with unique nonces for the purpose of improving protection by the encryption algorithm.
  • The encryption key may be received from a host computing system 114, a server, key manager, or other device that manages the encryption key to be used by the storage controller 204. In another embodiment, the non-volatile storage media 205 may have two or more partitions and the storage controller 204 behaves as though it was two or more storage controllers 104, each operating on a single partition within the non-volatile storage media 205. In this embodiment, a unique media encryption key may be used with each partition.
  • In another embodiment, the write data pipeline 301 also includes an encryption module 314 that encrypts a data or metadata segment received from the input buffer 306, either directly or indirectly, prior sending the data segment to the packetizer 302, the data segment encrypted using an encryption key received in conjunction with the data segment. The encryption keys used by the encryption module 314 to encrypt data may not be common to all data stored within the non-volatile storage device 122 but may vary on an per data structure basis and received in conjunction with receiving data segments as described below. For example, an encryption key for a data segment to be encrypted by the encryption module 314 may be received with the data segment or may be received as part of a command to write a data structure to which the data segment belongs. The storage device 122 may use and store a non-secret cryptographic nonce in each data structure packet that is used in conjunction with the encryption key. A different nonce may be stored with every packet. Data segments may be split between multiple packets with unique nonces for the purpose of improving protection by the encryption algorithm.
  • The encryption key may be received from a host computing device 102, another computer, key manager, or other device that holds the encryption key to be used to encrypt the data segment. In one embodiment, encryption keys are transferred to the storage controller 204 from one of a non-volatile storage device 122, host computing device 102, computer, or other external agent, which has the ability to execute industry standard methods to securely transfer and protect private and public keys.
  • In one embodiment, the encryption module 314 encrypts a first packet with a first encryption key received in conjunction with the packet and encrypts a second packet with a second encryption key received in conjunction with the second packet. In another embodiment, the encryption module 314 encrypts a first packet with a first encryption key received in conjunction with the packet and passes a second data packet on to the next stage without encryption. Beneficially, the encryption module 314 included in the write data pipeline 301 of the non-volatile storage device 122 allows data structure-by-data structure or segment-by-segment data encryption without a single file system or other external system to keep track of the different encryption keys used to store corresponding data structures or data segments. Each requesting device 155 or related key manager independently manages encryption keys used to encrypt only the data structures or data segments sent by the requesting device 155.
  • In one embodiment, the encryption module 314 may encrypt the one or more packets using an encryption key unique to the non-volatile storage device 122. The encryption module 314 may perform this media encryption independently, or in addition to the encryption described above. Typically, the entire packet is encrypted, including the headers. In another embodiment, headers are not encrypted. The media encryption by the encryption module 314 provides a level of security for data stored in the non-volatile storage media 205. For example, where data is encrypted with media encryption unique to the specific non-volatile storage device 122, if the non-volatile storage media 205 is connected to a different storage controller 204, non-volatile storage device 122, or host computing system 114, the contents of the non-volatile storage media 205 typically could not be read without use of the same encryption key used during the write of the data to the non-volatile storage media 205 without significant effort.
  • In another embodiment, the write data pipeline 301 includes a compression module 312 that compresses the data for metadata segment prior to sending the data segment to the packetizer 302. The compression module 312 typically compresses a data or metadata segment using a compression routine known to those of skill in the art to reduce the storage size of the segment. For example, if a data segment includes a string of 512 zeros, the compression module 312 may replace the 512 zeros with code or token indicating the 512 zeros where the code is much more compact than the space taken by the 512 zeros.
  • In one embodiment, the compression module 312 compresses a first segment with a first compression routine and passes along a second segment without compression. In another embodiment, the compression module 312 compresses a first segment with a first compression routine and compresses the second segment with a second compression routine. Having this flexibility within the non-volatile storage device 122 is beneficial so that computing devices 102 or other devices writing data to the non-volatile storage device 122 may each specify a compression routine or so that one can specify a compression routine while another specifies no compression. Selection of compression routines may also be selected according to default settings on a per data structure type or data structure class basis. For example, a first data structure of a specific data structure may be able to override default compression routine settings and a second data structure of the same data structure class and data structure type may use the default compression routine and a third data structure of the same data structure class and data structure type may use no compression.
  • In one embodiment, the write data pipeline 301 includes a garbage collector bypass 316 that receives data segments from the read data pipeline 303 as part of a data bypass in a garbage collection system. A garbage collection system (also referred to as a “groomer” or grooming operation) typically marks packets that are no longer valid, typically because the packet is marked for deletion or has been modified and the modified data is stored in a different location. At some point, the garbage collection system determines that a particular section (e.g., an erase block) of storage may be recovered. This determination may be due to a lack of available storage capacity, the percentage of data marked as invalid reaching a threshold, a consolidation of valid data, an error detection rate for that section of storage reaching a threshold, or improving performance based on data distribution, etc. Numerous factors may be considered by a garbage collection algorithm to determine when a section of storage is to be recovered.
  • Once a section of storage has been marked for recovery, valid packets in the section typically must be relocated. The garbage collector bypass 316 allows packets to be read into the read data pipeline 303 and then transferred directly to the write data pipeline 301 without being routed out of the storage controller 204. In one embodiment, the garbage collector bypass 316 is part of an autonomous garbage collector system that operates within the non-volatile storage device 122. This allows the non-volatile storage device 122 to manage data so that data is systematically spread throughout the non-volatile storage media 205 to improve performance, data reliability and to avoid overuse and underuse of any one location or area of the non-volatile storage media 205 and to lengthen the useful life of the non-volatile storage media 205.
  • The garbage collector bypass 316 coordinates insertion of segments into the write data pipeline 106 with other segments being written by computing devices 102 or other devices. In the depicted embodiment, the garbage collector bypass 316 is before the packetizer 302 in the write data pipeline 301 and after the depacketizer 324 in the read data pipeline 303, but may also be located elsewhere in the read and write data pipelines 106, 108. The garbage collector bypass 316 may be used during a flush of the write pipeline 303 to fill the remainder of the particular section of storage in order to improve the efficiency of storage within the non-volatile storage media 205 and thereby reduce the frequency of garbage collection.
  • Grooming may include refreshing data stored on the non-volatile storage media 205. Data stored on the non-volatile storage media 205 may degrade over time. The storage controller 204 may include a groomer that identifies “stale” data on the non-volatile storage device 122 (data that has not been modified and/or moved for a pre-determined time), and refreshes the stale data by re-writing the data to a different storage location.
  • In some embodiments, the garbage collection system, groomer, and/or garbage collection bypass 316 may be temporarily disabled to allow data to be stored contiguously on physical storage locations of the non-volatile storage device 122. Disabling the garbage collection system and/or bypass 316 may ensure that data in the write data pipeline 301 is not interleaved with other data. For example, and discussed below, garbage collection and/or the garbage collection bypass 316 may be disabled when storing data pertaining to an atomic storage request.
  • In some embodiments, the garbage collection and/or groomer may be restricted to a certain portion of the physical storage space of the non-volatile storage device. For example, storage metadata, such as the reverse index described below, may be periodically persisted to a non-volatile storage location. The garbage collection and/or grooming may be restricted to operating on portions of the non-volatile storage media that correspond to the persisted storage metadata.
  • In one embodiment, the write data pipeline 301 includes a write buffer 320 that buffers data for efficient write operations. Typically, the write buffer 320 includes enough capacity for packets to fill at least one logical page in the non-volatile storage media 205. This allows a write operation to send an entire logical page of data to the non-volatile storage media 205 without interruption. By sizing the write buffer 320 of the write data pipeline 301 and buffers within the read data pipeline 303 to be the same capacity or larger than a storage write buffer within the non-volatile storage media 205, writing and reading data is more efficient since a single write command may be crafted to send a full logical page of data to the non-volatile storage media 205 instead of multiple commands.
  • While the write buffer 320 is being filled, the non-volatile storage media 205 may be used for other read operations. This is advantageous because other non-volatile devices with a smaller write buffer or no write buffer may tie up the non-volatile storage when data is written to a storage write buffer and data flowing into the storage write buffer stalls. Read operations will be blocked until the entire storage write buffer is filled and programmed. Another approach for systems without a write buffer or a small write buffer is to flush the storage write buffer that is not full in order to enable reads.
  • In one embodiment, the write buffer 320 is a ping-pong buffer where one side of the buffer is filled and then designated for transfer at an appropriate time while the other side of the ping-pong buffer is being filled. In another embodiment, the write buffer 320 includes a first-in first-out (“FIFO”) register with a capacity of more than a logical page of data segments. One of skill in the art will recognize other write buffer 320 configurations that allow a logical page of data to be stored prior to writing the data to the non-volatile storage media 205.
  • In one embodiment, the write data pipeline 301 includes a write program module 310 with one or more user-definable functions within the write data pipeline 301. The write program module 310 allows a user to customize the write data pipeline 301. A user may customize the write data pipeline 301 based on a particular data requirement or application. Where the storage controller 204 is an FPGA, the user may program the write data pipeline 301 with custom commands and functions relatively easily. A user may also use the write program module 310 to include custom functions with an ASIC, however, customizing an ASIC may be more difficult than with an FPGA. The write program module 310 may include buffers and bypass mechanisms to allow a first data segment to execute in the write program module 310 while a second data segment may continue through the write data pipeline 301. In another embodiment, the write program module 310 may include a processor core that can be programmed through software.
  • Note that the write program module 310 is shown between the input buffer 306 and the compression module 312, however, the write program module 310 could be anywhere in the write data pipeline 301 and may be distributed among the various stages 302-320. In addition, there may be multiple write program modules 310 distributed among the various states 302-320 that are programmed and operate independently. In addition, the order of the stages 302-320 may be altered. One of skill in the art will recognize workable alterations to the order of the stages 302-320 based on particular user requirements.
  • The read data pipeline 303 includes an ECC correction module 322 that determines if a data error exists in ECC blocks a requested packet received from the non-volatile storage media 205 by using ECC stored with each ECC block of the requested packet. The ECC correction module 322 then corrects any errors in the requested packet if any error exists and the errors are correctable using the ECC. For example, if the ECC can detect an error in six bits but can only correct three bit errors, the ECC correction module 322 corrects ECC blocks of the requested packet with up to three bits in error. The ECC correction module 322 corrects the bits in error by changing the bits in error to the correct one or zero state so that the requested data packet is identical to when it was written to the non-volatile storage media 205 and the ECC was generated for the packet.
  • If the ECC correction module 322 determines that the requested packets contains more bits in error than the ECC can correct, the ECC correction module 322 cannot correct the errors in the corrupted ECC blocks of the requested packet and sends an interrupt. In one embodiment, the ECC correction module 322 sends an interrupt with a message indicating that the requested packet is in error. The message may include information that the ECC correction module 322 cannot correct the errors or the inability of the ECC correction module 322 to correct the errors may be implied. In another embodiment, the ECC correction module 322 sends the corrupted ECC blocks of the requested packet with the interrupt and/or the message.
  • In one embodiment, a corrupted ECC block or portion of a corrupted ECC block of the requested packet that cannot be corrected by the ECC correction module 322 is read by the master controller 224, corrected, and returned to the ECC correction module 322 for further processing by the read data pipeline 303. In one embodiment, a corrupted ECC block or portion of a corrupted ECC block of the requested packet is sent to the device requesting the data. The requesting device 155 may correct the ECC block or replace the data using another copy, such as a backup or mirror copy, and then may use the replacement data of the requested data packet or return it to the read data pipeline 303. The requesting device 155 may use header information in the requested packet in order to identify data required to replace the corrupted requested packet or to replace the data structure to which the packet belongs. In another embodiment, the storage controller 204 stores data using some type of RAID and is able to recover the corrupted data. In another embodiment, the ECC correction module 322 sends an interrupt and/or message and the receiving device fails the read operation associated with the requested data packet. One of skill in the art will recognize other options and actions to be taken as a result of the ECC correction module 322 determining that one or more ECC blocks of the requested packet are corrupted and that the ECC correction module 322 cannot correct the errors.
  • The read data pipeline 303 includes a depacketizer 324 that receives ECC blocks of the requested packet from the ECC correction module 322, directly or indirectly, and checks and removes one or more packet headers. The depacketizer 324 may validate the packet headers by checking packet identifiers, data length, data location, etc. within the headers. In one embodiment, the header includes a hash code that can be used to validate that the packet delivered to the read data pipeline 303 is the requested packet. The depacketizer 324 also removes the headers from the requested packet added by the packetizer 302. The depacketizer 324 may directed to not operate on certain packets but pass these forward without modification. An example might be a container label that is requested during the course of a rebuild process where the header information is required for index reconstruction. Further examples include the transfer of packets of various types destined for use within the non-volatile storage device 122. In another embodiment, the depacketizer 324 operation may be packet type dependent.
  • The read data pipeline 303 includes an alignment module 326 that receives data from the depacketizer 324 and removes unwanted data. In one embodiment, a read command sent to the non-volatile storage media 205 retrieves a packet of data. A device requesting the data may not require all data within the retrieved packet and the alignment module 326 removes the unwanted data.
  • The alignment module 326 re-formats the data as data segments of a data structure in a form compatible with a device requesting the data segment prior to forwarding the data segment to the next stage. Typically, as data is processed by the read data pipeline 303, the size of data segments or packets changes at various stages. The alignment module 326 uses received data to format the data into data segments suitable to be sent to the requesting device 155 and joined to form a response. For example, data from a portion of a first data packet may be combined with data from a portion of a second data packet. If a data segment is larger than a data requested by the requesting device 155, the alignment module 326 may discard the unwanted data.
  • In one embodiment, the read data pipeline 303 includes a read synchronization buffer 328 that buffers one or more requested packets read from the non-volatile storage media 205 prior to processing by the read data pipeline 303. The read synchronization buffer 328 is at the boundary between the non-volatile storage clock domain and the local bus clock domain and provides buffering to account for the clock domain differences.
  • In another embodiment, the read data pipeline 303 includes an output buffer 330 that receives requested packets from the alignment module 326 and stores the packets prior to transmission to the requesting device 155. The output buffer 330 accounts for differences between when data segments are received from stages of the read data pipeline 303 and when the data segments are transmitted to other parts of the storage controller 204 or to the requesting device 155. The output buffer 330 also allows the data bus 207 to receive data from the read data pipeline 303 at rates greater than can be sustained by the read data pipeline 303 in order to improve efficiency of operation of the data bus 207.
  • In one embodiment, the read data pipeline 303 includes a media decryption module 332 that receives one or more encrypted requested packets from the ECC correction module 322 and decrypts the one or more requested packets using the encryption key unique to the non-volatile storage device 122 prior to sending the one or more requested packets to the depacketizer 324. Typically, the encryption key used to decrypt data by the media decryption module 332 is identical to the encryption key used by the media encryption module 318. In another embodiment, the non-volatile storage media 205 may have two or more partitions and the storage controller 204 behaves as though it was two or more storage controllers 104 each operating on a single partition within the non-volatile storage media 205. In this embodiment, a unique media encryption key may be used with each partition.
  • In another embodiment, the read data pipeline 303 includes a decryption module 334 that decrypts a data segment formatted by the depacketizer 324 prior to sending the data segment to the output buffer 330. The data segment may be decrypted using an encryption key received in conjunction with the read request that initiates retrieval of the requested packet received by the read synchronization buffer 328. The decryption module 334 may decrypt a first packet with an encryption key received in conjunction with the read request for the first packet and then may decrypt a second packet with a different encryption key or may pass the second packet on to the next stage of the read data pipeline 303 without decryption. When the packet was stored with a non-secret cryptographic nonce, the nonce is used in conjunction with an encryption key to decrypt the data packet. The encryption key may be received from a host computing system 114, a client, key manager, or other device that manages the encryption key to be used by the storage controller 204.
  • In another embodiment, the read data pipeline 303 includes a decompression module 336 that decompresses a data segment formatted by the depacketizer 324. In one embodiment, the decompression module 336 uses compression information stored in one or both of the packet header and the container label to select a complementary routine to that used to compress the data by the compression module 312. In another embodiment, the decompression routine used by the decompression module 336 is dictated by the device requesting the data segment being decompressed. In another embodiment, the decompression module 336 selects a decompression routine according to default settings on a per data structure type or data structure class basis. A first packet of a first object may be able to override a default decompression routine and a second packet of a second data structure of the same data structure class and data structure type may use the default decompression routine and a third packet of a third data structure of the same data structure class and data structure type may use no decompression.
  • In another embodiment, the read data pipeline 303 includes a read program module 338 that includes one or more user-definable functions within the read data pipeline 303. The read program module 338 has similar characteristics to the write program module 310 and allows a user to provide custom functions to the read data pipeline 303. The read program module 338 may be located as shown in FIG. 3, may be located in another position within the read data pipeline 303, or may include multiple parts in multiple locations within the read data pipeline 303. Additionally, there may be multiple read program modules 338 within multiple locations within the read data pipeline 303 that operate independently. One of skill in the art will recognize other forms of a read program module 338 within a read data pipeline 303. As with the write data pipeline 301, the stages of the read data pipeline 303 may be rearranged and one of skill in the art will recognize other orders of stages within the read data pipeline 303.
  • The storage controller 204 includes control and status registers 340 and corresponding control queues 342. The control and status registers 340 and control queues 342 facilitate control and sequencing commands and subcommands associated with data processed in the write and read data pipelines 106, 108. For example, a data segment in the packetizer 302 may have one or more corresponding control commands or instructions in a control queue 342 associated with the ECC generator 304. As the data segment is packetized, some of the instructions or commands may be executed within the packetizer 302. Other commands or instructions may be passed to the next control queue 342 through the control and status registers 340 as the newly formed data packet created from the data segment is passed to the next stage.
  • Commands or instructions may be simultaneously loaded into the control queues 342 for a packet being forwarded to the write data pipeline 301 with each pipeline stage pulling the appropriate command or instruction as the respective packet is executed by that stage. Similarly, commands or instructions may be simultaneously loaded into the control queues 342 for a packet being requested from the read data pipeline 303 with each pipeline stage pulling the appropriate command or instruction as the respective packet is executed by that stage. One of skill in the art will recognize other features and functions of control and status registers 340 and control queues 342.
  • The storage controller 204 and or non-volatile storage device 122 may also include a bank interleave controller 344, a synchronization buffer 346, a storage bus controller 348, and a multiplexer (“MUX”) 350.
  • FIG. 4A depicts a schematic diagram of one embodiment of a log structure 400 in a memory storage device 122. While the log structure 400 is described in conjunction with the storage device 122 of FIG. 1, the log structure 400 may be used in conjunction with any type of storage device 122 or memory device. Alternatively, the storage device 122 may be used in conjunction with any storage media in a log-structured manner or that is configured to perform operations according to an object-based storage system.
  • For NAND flash memory, a log structure allows program operations to be performed quickly because changes to a set of data in one location of the storage device 122 are written to a different location (that is first erased) on the same storage device 122, rather than the first location. Although not shown herein, the storage device 122 may be used in conjunction with storage media organized in a structure other than a log structure. For example, a non-log-structured storage device may include phase change memory or a write-in-place non-volatile storage media. Write-in-place storage media may include a storage medium that is able to make changes to data stored at a location on the storage medium and write the modified data back to the same location on the storage medium. A write-out-of-place storage medium is configured to modify data stored on the storage medium and write the modified data to a different location on the storage medium, such as in a log-structured medium.
  • In one embodiment, the log structure 400 is configured to store objects received from a client application 110 in the order that the objects are received to be written to the storage device 122. The size of each object 402 may be different, according to the data associated with a write operation. In one embodiment, because the log structure 400 is configured to store objects received in the order that they are received, each new object may be added to the log structure 400 at the end of the previously stored object. For example, as shown in FIG. 4A, a first object 402 having a first size is created and stored at the beginning 408 of the log structure 400 on the storage device 122. When a second object 404 is created, the second object 404 is placed after the first object 402 on the storage device 122. Additional objects are then added to the log structure 400 in the order received by the storage device 122. The objects shown in FIG. 4A may be any type of objects, including live objects, dead objects and/or dirty objects.
  • Because the storage device 122 is configured to store data in a log-structured manner, the objects do not need to be stored in blocks, as with a traditional block-based storage device. Additionally, the storage device 122 is capable of retrieving (or otherwise modify) data associated with the stored objects by tracking the object identifier, location, and size of each object in a table 406, as shown in FIG. 4B. In one embodiment, the table 406 is stored on the storage device 122. In another embodiment, the table 406 is stored in memory 108 on the computing device 102. In another embodiment, the table 406 is stored in another location accessible to the storage device 122 or device driver 120. In other embodiments, a structure other than a table may be used to store tracking information for each object on the storage device 122. For example, a tree structure may be used to store the tracking information. Other structures configured to store such tracking information may also be used.
  • In one embodiment, when an object is created on the storage device 122, the storage device 122 determines the starting address where the object will be stored. In a log structure 400, the starting address may already be known based on where an append point (or location where the previous object ends) is currently pointing. A size of the object is used to determine the ending address for the object using the starting address. The starting address may be stored with the size of the object in the table 406. In another embodiment, the starting and ending addresses for the object are stored in the table 406. In one embodiment, when an object is “destroyed” or erased, the storage device 122 finds the object in the table 406 and erases the entry associated with the object from the table 406. In another embodiment, destroyed (or dead) objects are erased from the storage device 122 during garbage collection, as described in more detail below.
  • In one embodiment, when a read operation is received for a specific object, the storage device 122 accesses the table 406 and determines or otherwise identifies the starting address and size associated with the object from the table 406. The starting address and size are used to determine the ending address, and the storage device 122 reads the data stored at all of the addresses from the starting address to the ending address and returns the data to the computing device 102. In another embodiment, the starting and ending addresses for the object are stored in the table 406.
  • In one embodiment, when a write operation is received for a specific object stored on the storage device 122, the storage device 122 accesses the table 406 and determines the starting address and size associated with the object from the table 406. If the data of the write operation associated with the object has the same size as the object stored on the storage device 122, the new data may then be written to the storage device 122 in a new location (for example, the append point (504, shown in FIG. 5) of the log structure 400, which may correspond to the end of the last object stored on the log structure 400) according to the log structure 400 of the storage device 122, the location information in the table 406 is updated with the new location of the object, and the previous size information from the table 406 is used. If the new data from the write operation does not have the same size as the object stored on the storage device 122, the new data is written to the storage device 122 and the location and size information are updated in the table 406.
  • In one example, the operations for creating, destroying, reading, and writing objects are shown below:
      • 1. ObjectCreate: Creates an object and returns a 64-bit object identifier (ObjID). The syntax is:
        • ObjID ObjectCreate(size_t size)
      • 2. ObjectDestroy: Destroys an object from the system. The syntax is:
        • void ObjectDestroy(ObjID oid)
      • 3. ObjectRead: Reads an object from the flash memory device into the memory of the application. The syntax is:
        • int ObjectRead(ObjID oid, char** buffer, size_t* size)
      • where ObjID is the 64-bit object identifier and buffer is the location where the object is to be placed once read from the storage device. The argument buffer is a placeholder for the actual pointer to the object in the volatile memory for an application. Such an interface allows a software developer to create objects without keeping track of the size of the objects. The object is read from the storage device, the size of the read object is placed in the size argument, and the pointer to the object is returned in buffer.
      • 4. ObjectWrite: Writes an object from the memory of an application to the storage device. The syntax is:
        • int ObjectWrite(ObjID oid, char* buffer, size_t size)
      • The size argument allows the application to change the size of the object. Otherwise, the size argument is ignored and the previous size of the object is used.
  • While the above examples illustrate one embodiment of the operations for creating, destroying, reading, and writing objects on the storage device 122, other embodiments of the operations may use other syntaxes, arguments or methods for accessing and altering data on the storage device 122.
  • FIG. 5 depicts a schematic diagram 500 of garbage collection in a log structure 400 on a memory device. While the garbage collection is described in conjunction with the log structure 400 shown in FIG. 5, the garbage collection may be used in conjunction with any storage device 122 operating in a log-structured manner. Alternatively, the storage device 122 may use any suitable garbage collection methods.
  • In one embodiment, when the driver 120 or controller 124 performs garbage collection on the storage device 122, the garbage collection is performed in a log-structured manner to maximize the lifetime of the memory elements 126 and to minimize fragmentation of data on the storage device 122. To perform such garbage collection, the storage device 122 is configured to perform operations for objects within the log structure 400 to clean up old objects stored on the storage device 122 and reclaim unused space. These operations allow the objects to be moved within the log structure 400 and the information stored in the table 406 for the corresponding objects may be updated accordingly.
  • For example, in garbage collection for a group of addresses on the storage device 122, a “read” operation retrieves live objects 502 (having valid data that has been committed to the storage device 122 or to a backing store 118 associated with the storage device 122 in a caching system) for the group of addresses from the storage device 122, a “modify” operation adjusts the size of live objects (for example, by modifying the size or grouping the live objects together), and the “write” operation writes the modified live objects back to the storage device 122 at the current append point 504 in the log structure 400. As shown in FIG. 5, the live objects 502 are fragmented in the log structure 400 prior to garbage collection, and are compacted (or placed together) after garbage collection. The “write” operation may also write any dirty objects that may fit in the group of addresses for which garbage collection is being performed. After garbage collection is performed, the corresponding entries in the table 406 are updated with the new information for each object that was written to the group of addresses on the storage device 122.
  • In another embodiment, a remap operation may be used to remap objects to different locations to reduce fragmentation and to manage non-volatile memories such as NAND flash memory. The remap operation may be performed on old, stale, and/or unused objects. The remap operation may be performed on dead objects so that the storage space may be erased and reclaimed. For example, during the remap operation, an object is read from the storage device 122, the size of the object may be determined in order to set a size attribute in metadata for the object, and the object is written back to the storage device 122. In one embodiment, because the object size is variable, the size attributes of the object may be changed (larger or smaller) before writing the object back to the storage device 122. In one embodiment, the object size is not determined and a copy of the object in volatile memory may be used to create a new version of the object that is written to the storage device 122. In one embodiment, writing the object back to the storage device includes storing the object at the append point 504 of the log structure 400 and invalidating the previous copy of the object. This may be done in NAND flash memory, for example, with a TRIM command that informs the storage device 122 that the previous object is no longer being used and may be erased.
  • FIG. 6 depicts a flow chart diagram of one embodiment of a method 600 for object based storage on a storage device 122. Although the method 600 is shown and described with operations of the computing device 102 of FIG. 1, other embodiments of the method 600 may be implemented with other computing devices 102.
  • In one embodiment, the method 600 includes receiving 602 a memory access command to a memory storage device 122 from an application. The storage device 122 is configured to provide native support for object storage, as described herein. The application may be the client application 110 described in FIG. 1. In one embodiment, the operations for the method 600 are performed partially or entirely at a hardware device manager, such as a driver 120 or controller 122.
  • The method 600 also includes identifying 604 a physical address on the storage device 122. The physical address is mapped directly to an object identifier associated with the memory access command according to an object store interface for the storage device 122. In one embodiment, the physical address is mapped directly to the object identifier in an absence of a block-based translation layer or other intermediate address translation layer or intermediate mapping layer for the storage device 122. The object store interface provides native object storage functionality on the storage device 122. Providing direct mapping between the physical address and the object identifier allows the elimination of additional abstraction between the application and the storage device 122. In one embodiment, the object identifier includes a virtual memory address.
  • The method 600 also includes performing 606 an operation associated with the memory access command for data stored at the physical address. The storage device 122 is configured to process the memory access command at an operation-specific granularity. In one embodiment, processing the memory access command includes performing an operation associated with the memory access command. The physical address has an arbitrary granularity associated with an object corresponding to the object identifier. Each operation may be performed at an object-level granularity according to the specific access command to the storage device 122, such that access to the storage device 122 is based on the size of the object associated with the operation, rather than a predetermined block size. The storage device 122 may be configured to create objects, destroy objects, read objects, and write objects on the storage device 122, for example, such that each operation only accesses a number of physical addresses on the storage device 122 according to the size of each object for each operation. A create object command 608 creates an object of a specific size on the storage device 122. A destroy object command 610 destroys a particular object stored on the storage device 122, for example, by removing a reference or pointer to the object. A write object command 612 writes data to the storage device 122 for a particular object that has been created on the storage device 122. Writing to an object that is already written on the storage device 122 may result in the object being written to the current append point 504 of a log structure 400 on the storage device 122. The previous version of the object may then be invalidated, for example via a TRIM command in NAND flash, and the space taken by the previous version may be reclaimed by the storage device 122. A read object command 614 reads data corresponding to a particular object from the storage device 122.
  • In one embodiment, the method 600 stores and maintain 616 an index such as a table 406 configured to track a location and a size of object data on the storage device 122. The object data corresponds to the object identifier. The table 406 may be stored on the storage device 122, the computing device 102, or another storage device. The table 406 may include an entry for each of the objects stored on the storage device 122. The entries may include information describing the location (such as a first address) of each object and a size of each object. The location and size information may allow the storage device 122 to find and modify stored objects.
  • In one embodiment, the method 600 includes performing garbage collection according to a log structure 400 of the storage device 122. In one embodiment, the garbage collection is performed by reading data from a group of physical addresses on the storage device 122 that correspond to live objects. The data for the live objects is grouped together, and written back to the group of physical addresses. In another embodiment, the garbage collection is performed by remapping data stored at a first physical address on the storage device 122 to a second physical address on the storage device 122.
  • While many embodiments are described herein, some embodiments relate to a method. The method includes receiving an object operation from an application at a hardware device manager. The object operation includes an object identifier. The method includes performing the object operation directly on a storage device. A physical address for the object corresponding to the object identifier is mapped directly to the object identifier in an index managed by the hardware device manager. Other embodiments of the method are described herein. Embodiments of a device and a system are also described herein.
  • In one embodiment of the method, the memory access command is an object operation that is performed directly on the storage device. The object operation may be a write operation that includes writing object data to the storage device at a new physical address and mapping a physical address associated with the object identifier in the index to the new physical address. The object operation may be a read operation that includes identifying, via an index (such as a table), the physical address corresponding to the object stored on the non-volatile storage device. In one embodiment, the object operation is a delete operation that includes invalidating data corresponding to a deleted object on the storage device and removing, from the index, the object identifier corresponding to the deleted object.
  • An embodiment of the network system includes at least one processor coupled directly or indirectly to memory elements through a system bus such as a data, address, and/or control bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.
  • It should also be noted that at least some of the operations for the methods may be implemented using software instructions stored on a computer useable storage medium for execution by a computer. As an example, an embodiment of a computer program product includes a computer useable storage medium to store a computer readable program that, when executed on a computer, causes the computer to perform operations, as described herein.
  • Embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment containing both hardware and software elements. In one embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc.
  • Furthermore, embodiments of the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
  • The computer-useable or computer-readable medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device), or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include a compact disk with read only memory (CD-ROM), a compact disk with read/write (CD-R/W), and a digital video disk (DVD).
  • Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Additionally, network adapters also may be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or memory devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the currently available types of network adapters.
  • Although the operations of the method(s) herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operations may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be implemented in an intermittent and/or alternating manner.
  • In the above description, specific details of various embodiments are provided. However, some embodiments may be practiced with less than all of these specific details. In other instances, certain methods, procedures, components, structures, and/or functions are described in no more detail than to enable the various embodiments of the invention, for the sake of brevity and clarity.
  • Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.

Claims (23)

What is claimed is:
1. A method, comprising:
receiving an object operation from an application at a hardware storage device manager, wherein the object operation comprises an object identifier; and
performing the object operation directly on a storage device, wherein a physical address for the object corresponding to the object identifier is mapped directly to the object identifier in an index managed by the hardware storage device manager.
2. The method of claim 1, wherein the physical address is mapped directly to the object identifier in an absence of a block-based translation layer for the storage device.
3. The method of claim 1, wherein the object operation is a write operation comprising:
writing object data to the storage device at a new physical address; and
mapping an address for the object identifier in the index to the new physical address.
4. The method of claim 1, wherein the object operation is a read operation comprising identifying, via the index, the physical address corresponding to the object stored on the storage device.
5. The method of claim 1, wherein the object operation is a delete operation comprising:
invalidating data corresponding to a deleted object on the storage device; and
removing, from the index, the object identifier corresponding to the deleted object.
6. The method of claim 1, wherein the storage device stores data in a log structure, wherein the physical address corresponds to an append point of the log structure.
7. The method of claim 1, wherein the index comprises a table configured to track a location and a size of object data on the storage device, wherein the object data corresponds to the object identifier.
8. The method of claim 1, wherein the physical address comprises an arbitrary granularity associated with the object corresponding to the object identifier.
9. The method of claim 1, further comprising performing garbage collection according to a log structure of the storage device by:
reading data from a group of physical addresses on the storage device, wherein the data corresponds to live objects comprising valid data stored on the storage device;
grouping the data for the live objects together; and
writing the grouped data back to the storage device.
10. The method of claim 1, further comprising performing garbage collection by remapping data stored at a first physical address on the storage device to a second physical address on the storage device.
11. The method of claim 10, wherein the storage device is configured to create objects, destroy objects, read objects, and write objects on the storage device.
12. The method of claim 1, wherein the object identifier comprises a virtual storage address.
13. A non-volatile memory device, comprising:
a plurality of memory elements configured to store data, wherein the memory elements comprise corresponding physical addresses;
a hardware device manager configured to:
receive an object operation comprising an identifier corresponding to an object stored on the non-volatile memory device; and
performing the object operation directly on the non-volatile memory device by:
writing object data to one or more physical addresses on the non-volatile memory device; and
mapping, in an index, an address for the identifier corresponding to the object directly to the one or more physical addresses on the non-volatile memory device.
14. The device of claim 13, wherein the one or more physical addresses correlate directly to the identifier in an absence of a block-based translation layer for the non-volatile memory device.
15. The device of claim 13, wherein the index comprises a table configured to track a location and a size of object data on the non-volatile memory device, wherein the object data corresponds to the identifier.
16. The device of claim 13, wherein the one or more physical addresses comprise an arbitrary granularity associated with the object.
17. The device of claim 13, wherein the hardware device manager is further configured to perform garbage collection according to a log structure of the non-volatile memory device by:
reading data from a group of physical addresses on the non-volatile memory device, wherein the data corresponds to live objects comprising valid data stored on the non-volatile memory device;
compacting the data for the live objects together; and
writing the compacted data back to the non-volatile memory device.
18. The device of claim 13, wherein the hardware device manager is further configured to perform garbage collection by remapping data stored at a first physical address on the non-volatile memory device to a second physical address on the non-volatile memory device.
19. The device of claim 13, wherein the hardware device manager is further configured to provide native support for object storage, wherein the hardware device manager is configured to create objects, destroy objects, read objects, and write objects stored on the non-volatile memory device.
20. The device of claim 19, wherein the object operation for object data stored at a location on the non-volatile memory device comprises a place holder argument for a pointer to at least one physical address of the location, wherein the pointer is output based on a size of the object data.
21. A system, comprising:
a driver interface configured to communicate with a recording device interface of a non-volatile recording device, wherein the driver interface is configured to:
submit an object operation associated with an application, wherein the object operation is associated with an object identifier;
performing a read operation directly on the non-volatile recording device by identifying an address for the object identifier from an index, wherein the address is mapped directly to one or more physical addresses on the non-volatile recording device, wherein the one or more physical addresses correspond to object data for the object identifier.
22. The system of claim 21, wherein the one or more physical addresses are mapped directly to the object identifier in an absence of a block-based translation layer for the storage device.
23. The system of claim 21, wherein the index comprises a table configured to store a size and the one or more physical addresses of the object data on the storage device.
US13/835,109 2006-12-06 2013-03-15 Object-based memory storage Abandoned US20130205114A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/835,109 US20130205114A1 (en) 2006-12-06 2013-03-15 Object-based memory storage

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US87311106P 2006-12-06 2006-12-06
US97447007P 2007-09-22 2007-09-22
US11/952,098 US20080140724A1 (en) 2006-12-06 2007-12-06 Apparatus, system, and method for servicing object requests within a storage controller
US12/098,433 US8151082B2 (en) 2007-12-06 2008-04-06 Apparatus, system, and method for converting a storage request into an append data storage command
US13/835,109 US20130205114A1 (en) 2006-12-06 2013-03-15 Object-based memory storage

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/098,433 Continuation US8151082B2 (en) 2006-12-06 2008-04-06 Apparatus, system, and method for converting a storage request into an append data storage command

Publications (1)

Publication Number Publication Date
US20130205114A1 true US20130205114A1 (en) 2013-08-08

Family

ID=40722854

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/098,433 Active 2029-08-26 US8151082B2 (en) 2006-12-06 2008-04-06 Apparatus, system, and method for converting a storage request into an append data storage command
US13/835,109 Abandoned US20130205114A1 (en) 2006-12-06 2013-03-15 Object-based memory storage

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/098,433 Active 2029-08-26 US8151082B2 (en) 2006-12-06 2008-04-06 Apparatus, system, and method for converting a storage request into an append data storage command

Country Status (6)

Country Link
US (2) US8151082B2 (en)
EP (1) EP2271978B1 (en)
JP (1) JP5431453B2 (en)
KR (2) KR101804034B1 (en)
CN (1) CN102084332B (en)
WO (1) WO2009126581A1 (en)

Cited By (187)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140379889A1 (en) * 2013-06-19 2014-12-25 Hewlett-Packard Development Company, L.P. Autonomous metric tracking and adjustment
US9176808B2 (en) * 2012-01-09 2015-11-03 Samsung Electronics Co., Ltd. Storage device and nonvolatile memory device and operating method thereof
US20150324294A1 (en) * 2013-01-31 2015-11-12 Hitachi, Ltd. Storage system and cache control method
US20150355706A1 (en) * 2014-06-05 2015-12-10 Fujitsu Limited Electronic device and method for controlling electronic device
WO2015187487A1 (en) * 2014-06-05 2015-12-10 Micron Technology, Inc. Virtual address table
US20160054939A1 (en) * 2014-08-21 2016-02-25 Datrium, Inc. Alternate Storage Arrangement in a Distributed Data Storage System with Key-Based Addressing
US20160210077A1 (en) * 2015-01-20 2016-07-21 Ultrata Llc Trans-cloud object based memory
US9430191B2 (en) 2013-11-08 2016-08-30 Micron Technology, Inc. Division operations for memory
US9437256B2 (en) 2013-09-19 2016-09-06 Micron Technology, Inc. Data shifting
US9449674B2 (en) 2014-06-05 2016-09-20 Micron Technology, Inc. Performing logical operations using sensing circuitry
US9449675B2 (en) 2013-10-31 2016-09-20 Micron Technology, Inc. Apparatuses and methods for identifying an extremum value stored in an array of memory cells
US9455020B2 (en) 2014-06-05 2016-09-27 Micron Technology, Inc. Apparatuses and methods for performing an exclusive or operation using sensing circuitry
US9466340B2 (en) 2013-07-26 2016-10-11 Micron Technology, Inc. Apparatuses and methods for performing compare operations using sensing circuitry
US9472265B2 (en) 2013-03-04 2016-10-18 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9496023B2 (en) 2014-06-05 2016-11-15 Micron Technology, Inc. Comparison operations on logical representations of values in memory
US20160334996A1 (en) * 2015-05-15 2016-11-17 ScaleFlux In-flash immutable object processing
US9530475B2 (en) 2013-08-30 2016-12-27 Micron Technology, Inc. Independently addressable memory array address spaces
WO2016209667A1 (en) * 2015-06-23 2016-12-29 Western Digital Technologies, Inc. Data management for object based storage
US20170048318A1 (en) * 2012-04-17 2017-02-16 Nimbix, Inc. System and method for managing heterogeneous data for cloud computing applications
US9583163B2 (en) 2015-02-03 2017-02-28 Micron Technology, Inc. Loop structure for operations in memory
US9589607B2 (en) 2013-08-08 2017-03-07 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9589602B2 (en) 2014-09-03 2017-03-07 Micron Technology, Inc. Comparison operations in memory
US9659610B1 (en) 2016-05-18 2017-05-23 Micron Technology, Inc. Apparatuses and methods for shifting data
US9659605B1 (en) 2016-04-20 2017-05-23 Micron Technology, Inc. Apparatuses and methods for performing corner turn operations using sensing circuitry
US9697876B1 (en) 2016-03-01 2017-07-04 Micron Technology, Inc. Vertical bit vector shift in memory
US9704541B2 (en) 2015-06-12 2017-07-11 Micron Technology, Inc. Simulating access lines
US9704540B2 (en) 2014-06-05 2017-07-11 Micron Technology, Inc. Apparatuses and methods for parity determination using sensing circuitry
US9711207B2 (en) 2014-06-05 2017-07-18 Micron Technology, Inc. Performing logical operations using sensing circuitry
US9711206B2 (en) 2014-06-05 2017-07-18 Micron Technology, Inc. Performing logical operations using sensing circuitry
US9740607B2 (en) 2014-09-03 2017-08-22 Micron Technology, Inc. Swap operations in memory
US9741399B2 (en) 2015-03-11 2017-08-22 Micron Technology, Inc. Data shift by elements of a vector in memory
US9747960B2 (en) 2014-12-01 2017-08-29 Micron Technology, Inc. Apparatuses and methods for converting a mask to an index
US9747961B2 (en) 2014-09-03 2017-08-29 Micron Technology, Inc. Division operations in memory
US9761300B1 (en) 2016-11-22 2017-09-12 Micron Technology, Inc. Data shift apparatuses and methods
US9767864B1 (en) 2016-07-21 2017-09-19 Micron Technology, Inc. Apparatuses and methods for storing a data value in a sensing circuitry element
US9779784B2 (en) 2014-10-29 2017-10-03 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9779019B2 (en) 2014-06-05 2017-10-03 Micron Technology, Inc. Data storage layout
US9786335B2 (en) 2014-06-05 2017-10-10 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
CN107247674A (en) * 2017-06-16 2017-10-13 深圳市万普拉斯科技有限公司 Memory block type processing approach, device, electronic equipment and readable storage medium storing program for executing
US9794343B2 (en) 2012-04-17 2017-10-17 Nimbix, Inc. Reconfigurable cloud computing
US9805772B1 (en) 2016-10-20 2017-10-31 Micron Technology, Inc. Apparatuses and methods to selectively perform logical operations
US9804981B2 (en) * 2014-10-22 2017-10-31 Huawei Technologies Co., Ltd. Method, controller, and system for service flow control in object-based storage system
US9818459B2 (en) 2016-04-19 2017-11-14 Micron Technology, Inc. Invert operations using sensing circuitry
US9830999B2 (en) 2014-06-05 2017-11-28 Micron Technology, Inc. Comparison operations in memory
US9836218B2 (en) 2014-10-03 2017-12-05 Micron Technology, Inc. Computing reduction and prefix sum operations in memory
US9847110B2 (en) 2014-09-03 2017-12-19 Micron Technology, Inc. Apparatuses and methods for storing a data value in multiple columns of an array corresponding to digits of a vector
US9870322B2 (en) 2015-11-12 2018-01-16 International Business Machines Corporation Memory mapping for object-based storage devices
US9886210B2 (en) 2015-06-09 2018-02-06 Ultrata, Llc Infinite memory fabric hardware implementation with router
US9892767B2 (en) 2016-02-12 2018-02-13 Micron Technology, Inc. Data gathering in memory
US9898252B2 (en) 2014-09-03 2018-02-20 Micron Technology, Inc. Multiplication operations in memory
US9899070B2 (en) 2016-02-19 2018-02-20 Micron Technology, Inc. Modified decode for corner turn
US9898253B2 (en) 2015-03-11 2018-02-20 Micron Technology, Inc. Division operations on variable length elements in memory
US9904515B2 (en) 2014-09-03 2018-02-27 Micron Technology, Inc. Multiplication operations in memory
US9905276B2 (en) 2015-12-21 2018-02-27 Micron Technology, Inc. Control of sensing components in association with performing operations
US9910637B2 (en) 2016-03-17 2018-03-06 Micron Technology, Inc. Signed division in memory
US9921777B2 (en) 2015-06-22 2018-03-20 Micron Technology, Inc. Apparatuses and methods for data transfer from sensing circuitry to a controller
US9934856B2 (en) 2014-03-31 2018-04-03 Micron Technology, Inc. Apparatuses and methods for comparing data patterns in memory
US9940026B2 (en) 2014-10-03 2018-04-10 Micron Technology, Inc. Multidimensional contiguous memory allocation
US9952925B2 (en) 2016-01-06 2018-04-24 Micron Technology, Inc. Error code calculation on sensing circuitry
US9959923B2 (en) 2015-04-16 2018-05-01 Micron Technology, Inc. Apparatuses and methods to reverse data stored in memory
US9965185B2 (en) 2015-01-20 2018-05-08 Ultrata, Llc Utilization of a distributed index to provide object memory fabric coherency
US9972367B2 (en) 2016-07-21 2018-05-15 Micron Technology, Inc. Shifting data in sensing circuitry
US9971541B2 (en) 2016-02-17 2018-05-15 Micron Technology, Inc. Apparatuses and methods for data movement
US9971542B2 (en) 2015-06-09 2018-05-15 Ultrata, Llc Infinite memory fabric streams and APIs
US9973566B2 (en) 2013-11-17 2018-05-15 Nimbix, Inc. Dynamic creation and execution of containerized applications in cloud computing
US9990181B2 (en) 2016-08-03 2018-06-05 Micron Technology, Inc. Apparatuses and methods for random number generation
US9997212B1 (en) 2017-04-24 2018-06-12 Micron Technology, Inc. Accessing data in memory
US9996479B2 (en) 2015-08-17 2018-06-12 Micron Technology, Inc. Encryption of executables in computational memory
US9997232B2 (en) 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
US10013197B1 (en) 2017-06-01 2018-07-03 Micron Technology, Inc. Shift skip
US10014034B2 (en) 2016-10-06 2018-07-03 Micron Technology, Inc. Shifting data in sensing circuitry
US10032493B2 (en) 2015-01-07 2018-07-24 Micron Technology, Inc. Longest element length determination in memory
US10037785B2 (en) 2016-07-08 2018-07-31 Micron Technology, Inc. Scan chain operation in sensing circuitry
US10043570B1 (en) 2017-04-17 2018-08-07 Micron Technology, Inc. Signed element compare in memory
US10042608B2 (en) 2016-05-11 2018-08-07 Micron Technology, Inc. Signed division in memory
US10049054B2 (en) 2015-04-01 2018-08-14 Micron Technology, Inc. Virtual register file
US10049721B1 (en) 2017-03-27 2018-08-14 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10049707B2 (en) 2016-06-03 2018-08-14 Micron Technology, Inc. Shifting data
US10048888B2 (en) 2016-02-10 2018-08-14 Micron Technology, Inc. Apparatuses and methods for partitioned parallel data movement
US10061590B2 (en) 2015-01-07 2018-08-28 Micron Technology, Inc. Generating and executing a control flow
US10068664B1 (en) 2017-05-19 2018-09-04 Micron Technology, Inc. Column repair in memory
US10068652B2 (en) 2014-09-03 2018-09-04 Micron Technology, Inc. Apparatuses and methods for determining population count
US10074416B2 (en) 2016-03-28 2018-09-11 Micron Technology, Inc. Apparatuses and methods for data movement
US10074407B2 (en) 2014-06-05 2018-09-11 Micron Technology, Inc. Apparatuses and methods for performing invert operations using sensing circuitry
US10073635B2 (en) 2014-12-01 2018-09-11 Micron Technology, Inc. Multiple endianness compatibility
US10073786B2 (en) 2015-05-28 2018-09-11 Micron Technology, Inc. Apparatuses and methods for compute enabled cache
US10120740B2 (en) 2016-03-22 2018-11-06 Micron Technology, Inc. Apparatus and methods for debugging on a memory device
US10140104B2 (en) 2015-04-14 2018-11-27 Micron Technology, Inc. Target architecture determination
US10147467B2 (en) 2017-04-17 2018-12-04 Micron Technology, Inc. Element value comparison in memory
US10147480B2 (en) 2014-10-24 2018-12-04 Micron Technology, Inc. Sort operation in memory
US10146537B2 (en) 2015-03-13 2018-12-04 Micron Technology, Inc. Vector population count determination in memory
US10153008B2 (en) 2016-04-20 2018-12-11 Micron Technology, Inc. Apparatuses and methods for performing corner turn operations using sensing circuitry
US10152271B1 (en) 2017-06-07 2018-12-11 Micron Technology, Inc. Data replication
US10163467B2 (en) 2014-10-16 2018-12-25 Micron Technology, Inc. Multiple endianness compatibility
US10162005B1 (en) 2017-08-09 2018-12-25 Micron Technology, Inc. Scan chain operations
US10185674B2 (en) 2017-03-22 2019-01-22 Micron Technology, Inc. Apparatus and methods for in data path compute operations
US10199088B2 (en) 2016-03-10 2019-02-05 Micron Technology, Inc. Apparatuses and methods for cache invalidate
US10223208B2 (en) 2013-08-13 2019-03-05 Sandisk Technologies Llc Annotated atomic write
US10235063B2 (en) 2015-12-08 2019-03-19 Ultrata, Llc Memory fabric operations and coherency using fault tolerant objects
US10235207B2 (en) 2016-09-30 2019-03-19 Nimbix, Inc. Method and system for preemptible coprocessing
US10236038B2 (en) 2017-05-15 2019-03-19 Micron Technology, Inc. Bank to bank data transfer
US10241676B2 (en) 2015-12-08 2019-03-26 Ultrata, Llc Memory fabric software implementation
US10262701B2 (en) 2017-06-07 2019-04-16 Micron Technology, Inc. Data transfer between subarrays in memory
US10268389B2 (en) 2017-02-22 2019-04-23 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10289542B2 (en) 2015-02-06 2019-05-14 Micron Technology, Inc. Apparatuses and methods for memory device as a store for block program instructions
US20190155747A1 (en) * 2017-11-22 2019-05-23 Arm Limited Performing maintenance operations
US10303632B2 (en) 2016-07-26 2019-05-28 Micron Technology, Inc. Accessing status information
US10318168B2 (en) 2017-06-19 2019-06-11 Micron Technology, Inc. Apparatuses and methods for simultaneous in data path compute operations
US10332586B1 (en) 2017-12-19 2019-06-25 Micron Technology, Inc. Apparatuses and methods for subrow addressing
US10346092B2 (en) 2017-08-31 2019-07-09 Micron Technology, Inc. Apparatuses and methods for in-memory operations using timing circuitry
US10365851B2 (en) 2015-03-12 2019-07-30 Micron Technology, Inc. Apparatuses and methods for data movement
US10373666B2 (en) 2016-11-08 2019-08-06 Micron Technology, Inc. Apparatuses and methods for compute components formed over an array of memory cells
US10379772B2 (en) 2016-03-16 2019-08-13 Micron Technology, Inc. Apparatuses and methods for operations using compressed and decompressed data
US10382540B2 (en) 2014-05-29 2019-08-13 Sandisk Technologies Llc Synchronizing storage state information
US10387046B2 (en) 2016-06-22 2019-08-20 Micron Technology, Inc. Bank to bank data transfer
US10387058B2 (en) 2016-09-29 2019-08-20 Micron Technology, Inc. Apparatuses and methods to change data category values
US10388360B2 (en) 2016-07-19 2019-08-20 Micron Technology, Inc. Utilization of data stored in an edge section of an array
US10388393B2 (en) 2016-03-22 2019-08-20 Micron Technology, Inc. Apparatus and methods for debugging on a host and memory device
US10387299B2 (en) 2016-07-20 2019-08-20 Micron Technology, Inc. Apparatuses and methods for transferring data
US10403352B2 (en) 2017-02-22 2019-09-03 Micron Technology, Inc. Apparatuses and methods for compute in data path
US10402340B2 (en) 2017-02-21 2019-09-03 Micron Technology, Inc. Memory array page table walk
US10409739B2 (en) 2017-10-24 2019-09-10 Micron Technology, Inc. Command selection policy
US10416927B2 (en) 2017-08-31 2019-09-17 Micron Technology, Inc. Processing in memory
US10423353B2 (en) 2016-11-11 2019-09-24 Micron Technology, Inc. Apparatuses and methods for memory alignment
US10430244B2 (en) 2016-03-28 2019-10-01 Micron Technology, Inc. Apparatuses and methods to determine timing of operations
US10437557B2 (en) 2018-01-31 2019-10-08 Micron Technology, Inc. Determination of a match between data values stored by several arrays
US10440341B1 (en) 2018-06-07 2019-10-08 Micron Technology, Inc. Image processor formed in an array of memory cells
US10453502B2 (en) 2016-04-04 2019-10-22 Micron Technology, Inc. Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions
US10468087B2 (en) 2016-07-28 2019-11-05 Micron Technology, Inc. Apparatuses and methods for operations in a self-refresh state
US10466928B2 (en) 2016-09-15 2019-11-05 Micron Technology, Inc. Updating a register in memory
US10474581B2 (en) 2016-03-25 2019-11-12 Micron Technology, Inc. Apparatuses and methods for cache operations
US10483978B1 (en) 2018-10-16 2019-11-19 Micron Technology, Inc. Memory device processing
US10496286B2 (en) 2015-02-06 2019-12-03 Micron Technology, Inc. Apparatuses and methods for parallel writing to multiple memory device structures
US10522199B2 (en) 2015-02-06 2019-12-31 Micron Technology, Inc. Apparatuses and methods for scatter and gather
US10522212B2 (en) 2015-03-10 2019-12-31 Micron Technology, Inc. Apparatuses and methods for shift decisions
US10522210B2 (en) 2017-12-14 2019-12-31 Micron Technology, Inc. Apparatuses and methods for subarray addressing
US10529409B2 (en) 2016-10-13 2020-01-07 Micron Technology, Inc. Apparatuses and methods to perform logical operations using sensing circuitry
US10534553B2 (en) 2017-08-30 2020-01-14 Micron Technology, Inc. Memory array accessibility
US10607665B2 (en) 2016-04-07 2020-03-31 Micron Technology, Inc. Span mask generation
US10606587B2 (en) 2016-08-24 2020-03-31 Micron Technology, Inc. Apparatus and methods related to microcode instructions indicating instruction types
US10614875B2 (en) 2018-01-30 2020-04-07 Micron Technology, Inc. Logical operations using memory cells
CN111181760A (en) * 2019-09-02 2020-05-19 腾讯科技(深圳)有限公司 Network fault detection method and device, computer readable medium and electronic equipment
US10698628B2 (en) 2015-06-09 2020-06-30 Ultrata, Llc Infinite memory fabric hardware implementation with memory
US10725696B2 (en) 2018-04-12 2020-07-28 Micron Technology, Inc. Command selection policy with read priority
US10733089B2 (en) 2016-07-20 2020-08-04 Micron Technology, Inc. Apparatuses and methods for write address tracking
US10741239B2 (en) 2017-08-31 2020-08-11 Micron Technology, Inc. Processing in memory device including a row address strobe manager
US10809923B2 (en) 2015-12-08 2020-10-20 Ultrata, Llc Object memory interfaces across shared links
US10831673B2 (en) 2017-11-22 2020-11-10 Arm Limited Memory address translation
US10838899B2 (en) 2017-03-21 2020-11-17 Micron Technology, Inc. Apparatuses and methods for in-memory data switching networks
US10853262B2 (en) 2016-11-29 2020-12-01 Arm Limited Memory address translation using stored key entries
US10866904B2 (en) 2017-11-22 2020-12-15 Arm Limited Data storage for multiple data types
US10942843B2 (en) 2017-04-25 2021-03-09 Micron Technology, Inc. Storing data elements of different lengths in respective adjacent rows or columns according to memory shapes
US10956439B2 (en) 2016-02-19 2021-03-23 Micron Technology, Inc. Data transfer with a bit vector operation device
US10956071B2 (en) * 2018-10-01 2021-03-23 Western Digital Technologies, Inc. Container key value store for data storage devices
US10977033B2 (en) 2016-03-25 2021-04-13 Micron Technology, Inc. Mask patterns generated in memory from seed vectors
US11016905B1 (en) 2019-11-13 2021-05-25 Western Digital Technologies, Inc. Storage class memory access
US11029951B2 (en) 2016-08-15 2021-06-08 Micron Technology, Inc. Smallest or largest value element determination
US11074988B2 (en) 2016-03-22 2021-07-27 Micron Technology, Inc. Apparatus and methods for debugging on a host and memory device
US11086521B2 (en) 2015-01-20 2021-08-10 Ultrata, Llc Object memory data flow instruction execution
US11175915B2 (en) 2018-10-10 2021-11-16 Micron Technology, Inc. Vector registers implemented in memory
US11184446B2 (en) 2018-12-05 2021-11-23 Micron Technology, Inc. Methods and apparatus for incentivizing participation in fog networks
US11194477B2 (en) 2018-01-31 2021-12-07 Micron Technology, Inc. Determination of a match between data values stored by three or more arrays
US11222260B2 (en) 2017-03-22 2022-01-11 Micron Technology, Inc. Apparatuses and methods for operating neural networks
US11227641B1 (en) 2020-07-21 2022-01-18 Micron Technology, Inc. Arithmetic operations in memory
US11249921B2 (en) 2020-05-06 2022-02-15 Western Digital Technologies, Inc. Page modification encoding and caching
US11263146B2 (en) * 2020-06-05 2022-03-01 Vmware, Inc. Efficient accessing methods for bypassing second layer mapping of data blocks in file systems of distributed data systems
US11262919B2 (en) * 2020-06-05 2022-03-01 Vmware, Inc. Efficient segment cleaning employing remapping of data blocks in log-structured file systems of distributed data systems
US11269514B2 (en) 2015-12-08 2022-03-08 Ultrata, Llc Memory fabric software implementation
US11334497B2 (en) * 2020-06-05 2022-05-17 Vmware, Inc. Efficient segment cleaning employing local copying of data blocks in log-structured file systems of distributed data systems
US11360768B2 (en) 2019-08-14 2022-06-14 Micron Technolgy, Inc. Bit string operations in memory
US11392497B1 (en) * 2020-11-25 2022-07-19 Amazon Technologies, Inc. Low latency access to data sets using shared data set portions
US11398264B2 (en) 2019-07-08 2022-07-26 Micron Technology, Inc. Methods and apparatus for dynamically adjusting performance of partitioned memory
US11397688B2 (en) 2018-10-10 2022-07-26 Micron Technology, Inc. Coherent memory access
US11416417B2 (en) 2014-08-25 2022-08-16 Western Digital Technologies, Inc. Method and apparatus to generate zero content over garbage data when encryption parameters are changed
US11449577B2 (en) 2019-11-20 2022-09-20 Micron Technology, Inc. Methods and apparatus for performing video processing matrix operations within a memory array
US11507544B2 (en) 2020-06-05 2022-11-22 Vmware, Inc. Efficient erasure-coded storage in distributed data systems
US20220382726A1 (en) * 2013-11-12 2022-12-01 Dropbox, Inc. Content Item Purging
US11550713B1 (en) 2020-11-25 2023-01-10 Amazon Technologies, Inc. Garbage collection in distributed systems using life cycled storage roots
US11593270B1 (en) 2020-11-25 2023-02-28 Amazon Technologies, Inc. Fast distributed caching using erasure coded object parts
US11714675B2 (en) 2019-06-20 2023-08-01 Amazon Technologies, Inc. Virtualization-based transaction handling in an on-demand network code execution system
US11714682B1 (en) 2020-03-03 2023-08-01 Amazon Technologies, Inc. Reclaiming computing resources in an on-demand code execution system
US11836516B2 (en) 2018-07-25 2023-12-05 Amazon Technologies, Inc. Reducing execution times in an on-demand network code execution system using saved machine states
US11853385B2 (en) 2019-12-05 2023-12-26 Micron Technology, Inc. Methods and apparatus for performing diversity matrix operations within a memory array
US11861386B1 (en) 2019-03-22 2024-01-02 Amazon Technologies, Inc. Application gateways in an on-demand network code execution system
US11875173B2 (en) 2018-06-25 2024-01-16 Amazon Technologies, Inc. Execution of auxiliary functions in an on-demand network code execution system
US11943093B1 (en) 2018-11-20 2024-03-26 Amazon Technologies, Inc. Network connection recovery after virtual machine transition in an on-demand network code execution system
US11967361B2 (en) 2022-01-31 2024-04-23 Micron Technology, Inc. Comparison operations in memory

Families Citing this family (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8443134B2 (en) 2006-12-06 2013-05-14 Fusion-Io, Inc. Apparatus, system, and method for graceful cache device degradation
US8706968B2 (en) 2007-12-06 2014-04-22 Fusion-Io, Inc. Apparatus, system, and method for redundant write caching
US9104599B2 (en) 2007-12-06 2015-08-11 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for destaging cached data
US8489817B2 (en) 2007-12-06 2013-07-16 Fusion-Io, Inc. Apparatus, system, and method for caching data
US8019940B2 (en) 2006-12-06 2011-09-13 Fusion-Io, Inc. Apparatus, system, and method for a front-end, distributed raid
CN101178933B (en) * 2007-12-05 2010-07-28 苏州壹世通科技有限公司 Flash memory array device
US7836226B2 (en) 2007-12-06 2010-11-16 Fusion-Io, Inc. Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US9519540B2 (en) 2007-12-06 2016-12-13 Sandisk Technologies Llc Apparatus, system, and method for destaging cached data
US8694750B2 (en) * 2008-12-19 2014-04-08 Nvidia Corporation Method and system for data structure management
US9208108B2 (en) * 2008-12-19 2015-12-08 Nvidia Corporation Method and system for improved flash controller commands selection
US8732350B2 (en) * 2008-12-19 2014-05-20 Nvidia Corporation Method and system for improving direct memory access offload
US8055816B2 (en) * 2009-04-09 2011-11-08 Micron Technology, Inc. Memory controllers, memory systems, solid state drives and methods for processing a number of commands
US8468293B2 (en) 2009-07-24 2013-06-18 Apple Inc. Restore index page
WO2011013125A1 (en) 2009-07-27 2011-02-03 Storwize Ltd. Method and system for transformation of logical data objects for storage
WO2011021237A1 (en) * 2009-08-20 2011-02-24 Hitachi,Ltd. Storage subsystem and its data processing method
US8484414B2 (en) * 2009-08-31 2013-07-09 Hitachi, Ltd. Storage system having plurality of flash packages
CN102696010B (en) 2009-09-08 2016-03-23 才智知识产权控股公司(2) For by the device of data cache on solid storage device, system and method
KR101689420B1 (en) 2009-09-09 2016-12-23 샌디스크 테크놀로지스 엘엘씨 Apparatus, system, and method for power reduction management in a storage device
US9122579B2 (en) 2010-01-06 2015-09-01 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for a storage layer
US9223514B2 (en) 2009-09-09 2015-12-29 SanDisk Technologies, Inc. Erase suspend/resume for memory
WO2011031903A2 (en) 2009-09-09 2011-03-17 Fusion-Io, Inc. Apparatus, system, and method for allocating storage
US8683293B2 (en) * 2009-12-16 2014-03-25 Nvidia Corporation Method and system for fast two bit error correction
US20110161553A1 (en) * 2009-12-30 2011-06-30 Nvidia Corporation Memory device wear-leveling techniques
US9594675B2 (en) * 2009-12-31 2017-03-14 Nvidia Corporation Virtualization of chip enables
JP5066209B2 (en) 2010-03-18 2012-11-07 株式会社東芝 Controller, data storage device, and program
US9582431B2 (en) * 2010-03-22 2017-02-28 Seagate Technology Llc Storage address space to NVM address, span, and length mapping/converting
US9507827B1 (en) * 2010-03-25 2016-11-29 Excalibur Ip, Llc Encoding and accessing position data
US8577986B2 (en) 2010-04-02 2013-11-05 Microsoft Corporation Mapping RDMA semantics to high speed storage
WO2011143628A2 (en) 2010-05-13 2011-11-17 Fusion-Io, Inc. Apparatus, system, and method for conditional and atomic storage operations
US8725934B2 (en) 2011-12-22 2014-05-13 Fusion-Io, Inc. Methods and appratuses for atomic storage operations
EP2598996B1 (en) 2010-07-28 2019-07-10 SanDisk Technologies LLC Apparatus, system, and method for conditional and atomic storage operations
US8850114B2 (en) 2010-09-07 2014-09-30 Daniel L Rosenband Storage array controller for flash-based storage devices
US8984216B2 (en) 2010-09-09 2015-03-17 Fusion-Io, Llc Apparatus, system, and method for managing lifetime of a storage device
US20130205105A1 (en) * 2010-09-21 2013-08-08 Mitsubishi Electric Corporation Dma controller and data readout device
US9465728B2 (en) 2010-11-03 2016-10-11 Nvidia Corporation Memory controller adaptable to multiple memory devices
US10817421B2 (en) 2010-12-13 2020-10-27 Sandisk Technologies Llc Persistent data structures
US9218278B2 (en) 2010-12-13 2015-12-22 SanDisk Technologies, Inc. Auto-commit memory
US10817502B2 (en) 2010-12-13 2020-10-27 Sandisk Technologies Llc Persistent memory management
US9208071B2 (en) 2010-12-13 2015-12-08 SanDisk Technologies, Inc. Apparatus, system, and method for accessing memory
WO2012083308A2 (en) 2010-12-17 2012-06-21 Fusion-Io, Inc. Apparatus, system, and method for persistent data management on a non-volatile storage media
US8966184B2 (en) 2011-01-31 2015-02-24 Intelligent Intellectual Property Holdings 2, LLC. Apparatus, system, and method for managing eviction of data
US9201677B2 (en) 2011-05-23 2015-12-01 Intelligent Intellectual Property Holdings 2 Llc Managing data input/output operations
US9003104B2 (en) 2011-02-15 2015-04-07 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for a file-level cache
US8874823B2 (en) 2011-02-15 2014-10-28 Intellectual Property Holdings 2 Llc Systems and methods for managing data input/output operations
US9141527B2 (en) 2011-02-25 2015-09-22 Intelligent Intellectual Property Holdings 2 Llc Managing cache pools
WO2012129191A2 (en) 2011-03-18 2012-09-27 Fusion-Io, Inc. Logical interfaces for contextual storage
US9563555B2 (en) 2011-03-18 2017-02-07 Sandisk Technologies Llc Systems and methods for storage allocation
US9298550B2 (en) * 2011-05-09 2016-03-29 Cleversafe, Inc. Assigning a dispersed storage network address range in a maintenance free storage container
WO2012168960A1 (en) * 2011-06-07 2012-12-13 Hitachi, Ltd. Semiconductor storage apparatus and method of controlling semiconductor storage apparatus
US20120324143A1 (en) 2011-06-15 2012-12-20 Data Design Corporation Methods and apparatus for data access by a reprogrammable circuit module
US9417894B1 (en) 2011-06-15 2016-08-16 Ryft Systems, Inc. Methods and apparatus for a tablet computer system incorporating a reprogrammable circuit module
CN102882699B (en) * 2011-07-14 2015-07-29 华为技术有限公司 The distribution method of fringe node and device and fringe node controller
CN102916902B (en) * 2011-08-03 2017-09-15 南京中兴软件有限责任公司 Date storage method and device
US8700834B2 (en) * 2011-09-06 2014-04-15 Western Digital Technologies, Inc. Systems and methods for an enhanced controller architecture in data storage systems
US8806156B2 (en) 2011-09-13 2014-08-12 Hitachi, Ltd. Volume groups storing multiple generations of data in flash memory packages
US8593866B2 (en) 2011-11-11 2013-11-26 Sandisk Technologies Inc. Systems and methods for operating multi-bank nonvolatile memory
US8966172B2 (en) 2011-11-15 2015-02-24 Pavilion Data Systems, Inc. Processor agnostic data storage in a PCIE based shared storage enviroment
US9430286B2 (en) 2011-12-12 2016-08-30 International Business Machines Corporation Authorizing distributed task processing in a distributed storage network
US20130238900A1 (en) 2011-12-12 2013-09-12 Cleversafe, Inc. Dispersed storage network secure hierarchical file directory
US8898542B2 (en) * 2011-12-12 2014-11-25 Cleversafe, Inc. Executing partial tasks in a distributed storage and task network
US10176045B2 (en) 2011-12-12 2019-01-08 International Business Machines Corporation Internet based shared memory in a distributed computing system
US10133662B2 (en) 2012-06-29 2018-11-20 Sandisk Technologies Llc Systems, methods, and interfaces for managing persistent data of atomic storage operations
US9274937B2 (en) 2011-12-22 2016-03-01 Longitude Enterprise Flash S.A.R.L. Systems, methods, and interfaces for vector input/output operations
US9767032B2 (en) 2012-01-12 2017-09-19 Sandisk Technologies Llc Systems and methods for cache endurance
US9251086B2 (en) 2012-01-24 2016-02-02 SanDisk Technologies, Inc. Apparatus, system, and method for managing a cache
US9116812B2 (en) 2012-01-27 2015-08-25 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for a de-duplication cache
US10359972B2 (en) 2012-08-31 2019-07-23 Sandisk Technologies Llc Systems, methods, and interfaces for adaptive persistence
US9652182B2 (en) 2012-01-31 2017-05-16 Pavilion Data Systems, Inc. Shareable virtual non-volatile storage device for a server
US9020912B1 (en) * 2012-02-20 2015-04-28 F5 Networks, Inc. Methods for accessing data in a compressed file system and devices thereof
US9053008B1 (en) 2012-03-26 2015-06-09 Western Digital Technologies, Inc. Systems and methods for providing inline parameter service in data storage devices
US8935203B1 (en) 2012-03-29 2015-01-13 Amazon Technologies, Inc. Environment-sensitive distributed data management
US8918392B1 (en) * 2012-03-29 2014-12-23 Amazon Technologies, Inc. Data storage mapping and management
US8930364B1 (en) 2012-03-29 2015-01-06 Amazon Technologies, Inc. Intelligent data integration
US8832234B1 (en) 2012-03-29 2014-09-09 Amazon Technologies, Inc. Distributed data storage controller
WO2013174443A1 (en) * 2012-05-25 2013-11-28 Huawei Technologies Co., Ltd. A multi-client multi memory controller in a high speed distributed memory system
CN103455280B (en) 2012-05-31 2016-12-14 国际商业机器公司 For performing the method and system of memory copy
US10339056B2 (en) 2012-07-03 2019-07-02 Sandisk Technologies Llc Systems, methods and apparatus for cache transfers
US9612966B2 (en) 2012-07-03 2017-04-04 Sandisk Technologies Llc Systems, methods and apparatus for a virtual machine cache
US10509776B2 (en) 2012-09-24 2019-12-17 Sandisk Technologies Llc Time sequence data management
US10318495B2 (en) 2012-09-24 2019-06-11 Sandisk Technologies Llc Snapshots for a non-volatile device
US9329991B2 (en) 2013-01-22 2016-05-03 Seagate Technology Llc Translation layer partitioned between host and controller
KR101628436B1 (en) * 2013-02-01 2016-06-09 단국대학교 산학협력단 Method for processing data of virtual machine
US9842053B2 (en) 2013-03-15 2017-12-12 Sandisk Technologies Llc Systems and methods for persistent cache logging
US10558561B2 (en) 2013-04-16 2020-02-11 Sandisk Technologies Llc Systems and methods for storage metadata management
US10102144B2 (en) * 2013-04-16 2018-10-16 Sandisk Technologies Llc Systems, methods and interfaces for data virtualization
US9842128B2 (en) 2013-08-01 2017-12-12 Sandisk Technologies Llc Systems and methods for atomic storage operations
US10019320B2 (en) 2013-10-18 2018-07-10 Sandisk Technologies Llc Systems and methods for distributed atomic storage operations
US10073630B2 (en) 2013-11-08 2018-09-11 Sandisk Technologies Llc Systems and methods for log coordination
US9213600B2 (en) 2013-11-11 2015-12-15 Seagate Technology Llc Dynamic per-decoder control of log likelihood ratio and decoding parameters
KR102252419B1 (en) * 2014-01-09 2021-05-14 한국전자통신연구원 System and method for efficient address translation on Flash memory device
US9712619B2 (en) 2014-11-04 2017-07-18 Pavilion Data Systems, Inc. Virtual non-volatile memory express drive
US9565269B2 (en) 2014-11-04 2017-02-07 Pavilion Data Systems, Inc. Non-volatile memory express over ethernet
US10423339B2 (en) * 2015-02-02 2019-09-24 Western Digital Technologies, Inc. Logical block address mapping for hard disk drives
US9946607B2 (en) 2015-03-04 2018-04-17 Sandisk Technologies Llc Systems and methods for storage error management
KR101614650B1 (en) 2015-03-05 2016-04-21 홍익대학교 산학협력단 Method for executing executable file and computing apparatus
CN105515855B (en) * 2015-12-04 2018-10-30 浪潮(北京)电子信息产业有限公司 The daily record playback optimization method and device deleted directly is entangled in a kind of cloud storage system
CN105677250B (en) * 2016-01-04 2019-07-12 北京百度网讯科技有限公司 The update method and updating device of object data in object storage system
KR102533389B1 (en) * 2016-02-24 2023-05-17 삼성전자주식회사 Data storage device for increasing lifetime of device and raid system including the same
KR102611638B1 (en) * 2016-09-27 2023-12-08 삼성전자주식회사 Method of operating storage device and data storage system including storage device
US10394454B2 (en) * 2017-01-13 2019-08-27 Arm Limited Partitioning of memory system resources or performance monitoring
CN108345427B (en) * 2017-01-25 2020-09-04 杭州海康威视数字技术股份有限公司 Hard disk data storage method and device
US10769035B2 (en) * 2017-04-28 2020-09-08 International Business Machines Corporation Key-value index recovery by log feed caching
US10152422B1 (en) 2017-06-13 2018-12-11 Seagate Technology Llc Page-based method for optimizing cache metadata updates
US10547683B2 (en) * 2017-06-26 2020-01-28 Christopher Squires Object based storage systems that utilize direct memory access
US20190095340A1 (en) * 2017-09-28 2019-03-28 Hewlett Packard Enterprise Development Lp Discontiguous storage and contiguous retrieval of logically partitioned data
US10474528B2 (en) 2017-10-02 2019-11-12 Western Digital Technologies, Inc. Redundancy coding stripe based on coordinated internal address scheme across multiple devices
US10379948B2 (en) 2017-10-02 2019-08-13 Western Digital Technologies, Inc. Redundancy coding stripe based on internal addresses of storage devices
CN107888657B (en) * 2017-10-11 2020-11-06 上海交通大学 Low latency distributed storage system
US10725941B2 (en) 2018-06-30 2020-07-28 Western Digital Technologies, Inc. Multi-device storage system with hosted services on peer storage devices
US10409511B1 (en) 2018-06-30 2019-09-10 Western Digital Technologies, Inc. Multi-device storage system with distributed read/write processing
US10901848B2 (en) 2018-08-03 2021-01-26 Western Digital Technologies, Inc. Storage systems with peer data recovery
US10824526B2 (en) 2018-08-03 2020-11-03 Western Digital Technologies, Inc. Using failed storage device in peer-to-peer storage system to perform storage-centric task
US10592144B2 (en) 2018-08-03 2020-03-17 Western Digital Technologies, Inc. Storage system fabric with multichannel compute complex
US10831603B2 (en) 2018-08-03 2020-11-10 Western Digital Technologies, Inc. Rebuild assist using failed storage device
US10649843B2 (en) 2018-08-03 2020-05-12 Western Digital Technologies, Inc. Storage systems with peer data scrub
US10877810B2 (en) 2018-09-29 2020-12-29 Western Digital Technologies, Inc. Object storage system with metadata operation priority processing
CN109656474B (en) * 2018-11-15 2022-02-15 金蝶软件(中国)有限公司 Data storage method and device, computer equipment and storage medium
CN109597571B (en) * 2018-11-15 2022-02-15 金蝶软件(中国)有限公司 Data storage method, data reading method, data storage device, data reading device and computer equipment
KR20200076923A (en) * 2018-12-20 2020-06-30 에스케이하이닉스 주식회사 Storage device, controller and operating method of storage device thereof
US11182258B2 (en) 2019-01-04 2021-11-23 Western Digital Technologies, Inc. Data rebuild using dynamic peer work allocation
KR102225196B1 (en) * 2019-11-06 2021-03-09 알리페이 (항저우) 인포메이션 테크놀로지 씨오., 엘티디. Consensus of shared blockchain data storage based on error correction codes
US11089141B2 (en) * 2020-01-08 2021-08-10 Bank Of America Corporation Method and system for data prioritization communication
EP4147135A1 (en) * 2020-05-28 2023-03-15 Huawei Technologies Co., Ltd. Method and system for direct memory access
CN114026548A (en) * 2020-05-28 2022-02-08 华为技术有限公司 Method and system for direct memory access
US11468017B2 (en) 2020-07-24 2022-10-11 Capital Thought Holdings L.L.C. Data storage system and method
US11636069B2 (en) 2020-07-24 2023-04-25 Capital Thought Holdings L.L.C. Data storage system and method
KR20220042673A (en) 2020-09-28 2022-04-05 에스케이하이닉스 주식회사 Controller, operation method thereof, and memory system including the same
CN112350947B (en) * 2020-10-23 2022-07-29 杭州迪普信息技术有限公司 Message matching decision tree updating method and device
US11749335B2 (en) * 2020-11-03 2023-09-05 Jianzhong Bi Host and its memory module and memory controller
US11847100B2 (en) 2020-11-19 2023-12-19 Alibaba Group Holding Limited Distributed file system servicing random-access operations
CN112925568B (en) * 2021-03-28 2022-07-26 杭州迪普信息技术有限公司 Data transmission method and control device between modules

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325523A (en) * 1991-04-10 1994-06-28 International Business Machines Corporation Method for deleting objects from library resident optical disks by accumulating pending delete requests
US6535949B1 (en) * 1999-04-19 2003-03-18 Research In Motion Limited Portable electronic device having a log-structured file system in flash memory
US6697797B1 (en) * 2000-04-28 2004-02-24 Micro Data Base Systems, Inc. Method and apparatus for tracking data in a database, employing last-known location registers
US20050149472A1 (en) * 2003-12-24 2005-07-07 Ivan Schreter Reorganization-free mapping of objects in databases using a mapping chain
US20070043900A1 (en) * 2005-08-20 2007-02-22 Samsung Electronics Co., Ltd. Flash memory management method and flash memory system
US7720864B1 (en) * 2004-03-25 2010-05-18 Symantec Operating Corporation Expiration of access tokens for quiescing a distributed system

Family Cites Families (130)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4290105A (en) * 1979-04-02 1981-09-15 American Newspaper Publishers Association Method and apparatus for testing membership in a set through hash coding with allowable errors
NL8201847A (en) * 1982-05-06 1983-12-01 Philips Nv DEVICE FOR PROTECTION AGAINST UNAUTHORIZED READING OF PROGRAM WORDS TO BE MEMORIZED IN A MEMORY.
US7190617B1 (en) * 1989-04-13 2007-03-13 Sandisk Corporation Flash EEprom system
US5544347A (en) * 1990-09-24 1996-08-06 Emc Corporation Data storage system controlled remote data mirroring with respectively maintained data indices
US5325509A (en) * 1991-03-05 1994-06-28 Zitel Corporation Method of operating a cache memory including determining desirability of cache ahead or cache behind based on a number of available I/O operations
US5481708A (en) * 1992-06-05 1996-01-02 Borland International, Inc. System and methods for optimizing object-oriented compilations
US5404485A (en) * 1993-03-08 1995-04-04 M-Systems Flash Disk Pioneers Ltd. Flash file system
JP2784440B2 (en) * 1993-04-14 1998-08-06 インターナショナル・ビジネス・マシーンズ・コーポレイション Data page transfer control method
US5504882A (en) * 1994-06-20 1996-04-02 International Business Machines Corporation Fault tolerant data storage subsystem employing hierarchically arranged controllers
JP3732869B2 (en) 1995-06-07 2006-01-11 株式会社日立製作所 External storage device
US5754563A (en) * 1995-09-11 1998-05-19 Ecc Technologies, Inc. Byte-parallel system for implementing reed-solomon error-correcting codes
GB2291991A (en) * 1995-09-27 1996-02-07 Memory Corp Plc Disk drive emulation with a block-erasable memory
JP3363292B2 (en) * 1995-10-12 2003-01-08 株式会社日立製作所 Database management system
US5778070A (en) * 1996-06-28 1998-07-07 Intel Corporation Method and apparatus for protecting flash memory
US6424872B1 (en) * 1996-08-23 2002-07-23 Fieldbus Foundation Block oriented control system
US6038619A (en) * 1997-05-29 2000-03-14 International Business Machines Corporation Disk drive initiated data transfers responsive to sequential or near sequential read or write requests
US6311256B2 (en) * 1997-06-30 2001-10-30 Emc Corporation Command insertion and reordering at the same storage controller
US5893086A (en) * 1997-07-11 1999-04-06 International Business Machines Corporation Parallel file system and method with extensible hashing
US6298401B1 (en) * 1997-08-11 2001-10-02 Seagate Technology Llc Object oriented storage device having a disc drive controller providing an interface exposing methods which are invoked to access objects stored in a storage media
JPH1185589A (en) * 1997-09-12 1999-03-30 Toshiba Corp Information storage device and managing data reconstructing method to be applied to the same
US6374336B1 (en) 1997-12-24 2002-04-16 Avid Technology, Inc. Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner
US6415373B1 (en) 1997-12-24 2002-07-02 Avid Technology, Inc. Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner
US6725331B1 (en) * 1998-01-07 2004-04-20 Emc Corporation Method and apparatus for managing the dynamic assignment resources in a data storage system
US6112319A (en) 1998-02-20 2000-08-29 Micron Electronics, Inc. Method and system for verifying the accuracy of stored data
US6170063B1 (en) * 1998-03-07 2001-01-02 Hewlett-Packard Company Method for performing atomic, concurrent read and write operations on multiple storage devices
US6157963A (en) * 1998-03-24 2000-12-05 Lsi Logic Corp. System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients
US6526482B1 (en) 1998-04-01 2003-02-25 Hewlett-Packard Company Method of and apparatus for tracking appended data on storage medium
JP2000047891A (en) * 1998-05-29 2000-02-18 Toshiba Corp Device and method for controlling input/output for computer system and storage medium storing the programmed method
US6883063B2 (en) * 1998-06-30 2005-04-19 Emc Corporation Method and apparatus for initializing logical objects in a data storage system
US6374266B1 (en) * 1998-07-28 2002-04-16 Ralph Shnelvar Method and apparatus for storing information in a data processing system
JP2000122814A (en) * 1998-10-15 2000-04-28 Hitachi Ltd Method and device for secondarily storing expanded network connection
US7043568B1 (en) * 1998-11-12 2006-05-09 Klingman Edwin E Configuration selection for USB device controller
US6601151B1 (en) * 1999-02-08 2003-07-29 Sun Microsystems, Inc. Apparatus and method for handling memory access requests in a data processing system
US6347341B1 (en) * 1999-02-22 2002-02-12 International Business Machines Corporation Computer program product used for exchange and transfer of data having a siga vector and utilizing a queued direct input-output device
AU4061700A (en) * 1999-04-01 2000-10-23 Lexar Media, Inc. Space management for managing high capacity nonvolatile memory
US6105076A (en) * 1999-04-23 2000-08-15 International Business Machines Corporation Method, system, and program for performing data transfer operations on user data
US6341289B1 (en) * 1999-05-06 2002-01-22 International Business Machines Corporation Object identity and partitioning for user defined extents
WO2001031512A2 (en) 1999-10-25 2001-05-03 Infolibria, Inc. Fast indexing of web objects
US6405201B1 (en) 1999-12-02 2002-06-11 Sun Microsystems, Inc. Method and apparatus for reducing network traffic for remote file append operations
US20060161725A1 (en) * 2005-01-20 2006-07-20 Lee Charles C Multiple function flash memory system
US6779080B2 (en) 2000-01-11 2004-08-17 International Business Machines Corporation Serial data storage system with automatically adjusted data protection to implement worm media with limited overwrite allowing write appending
US6823398B1 (en) * 2000-03-31 2004-11-23 Dphi Acquisitions, Inc. File system management embedded in a storage device
US6643748B1 (en) * 2000-04-20 2003-11-04 Microsoft Corporation Programmatic masking of storage units
US6404647B1 (en) * 2000-08-24 2002-06-11 Hewlett-Packard Co. Solid-state mass memory storage device
US7155559B1 (en) * 2000-08-25 2006-12-26 Lexar Media, Inc. Flash memory architecture with separate storage of overhead and user data
GB0022670D0 (en) * 2000-09-15 2000-11-01 Astrazeneca Ab Molecules
US7039727B2 (en) * 2000-10-17 2006-05-02 Microsoft Corporation System and method for controlling mass storage class digital imaging devices
SE0004736D0 (en) * 2000-12-20 2000-12-20 Ericsson Telefon Ab L M Mapping system and method
US6871295B2 (en) * 2001-01-29 2005-03-22 Adaptec, Inc. Dynamic data recovery
US6802023B2 (en) * 2001-03-15 2004-10-05 Hewlett-Packard Development Company, L.P. Redundant controller data storage system having hot insertion system and method
US6779045B2 (en) * 2001-03-21 2004-08-17 Intel Corporation System and apparatus for increasing the number of operations per transmission for a media management system
US20030061296A1 (en) * 2001-09-24 2003-03-27 International Business Machines Corporation Memory semantic storage I/O
GB0123416D0 (en) * 2001-09-28 2001-11-21 Memquest Ltd Non-volatile memory control
US6823417B2 (en) * 2001-10-01 2004-11-23 Hewlett-Packard Development Company, L.P. Memory controller for memory card manages file allocation table
US6754800B2 (en) * 2001-11-14 2004-06-22 Sun Microsystems, Inc. Methods and apparatus for implementing host-based object storage schemes
US6839819B2 (en) * 2001-12-28 2005-01-04 Storage Technology Corporation Data management appliance
US6850969B2 (en) * 2002-03-27 2005-02-01 International Business Machined Corporation Lock-free file system
US7013364B2 (en) * 2002-05-27 2006-03-14 Hitachi, Ltd. Storage subsystem having plural storage systems and storage selector for selecting one of the storage systems to process an access request
US7082495B2 (en) * 2002-06-27 2006-07-25 Microsoft Corporation Method and apparatus to reduce power consumption and improve read/write performance of hard disk drives using non-volatile memory
US7051152B1 (en) * 2002-08-07 2006-05-23 Nvidia Corporation Method and system of improving disk access time by compression
US7882081B2 (en) * 2002-08-30 2011-02-01 Netapp, Inc. Optimized disk repository for the storage and retrieval of mostly sequential data
US20040054867A1 (en) * 2002-09-13 2004-03-18 Paulus Stravers Translation lookaside buffer
US7340566B2 (en) * 2002-10-21 2008-03-04 Microsoft Corporation System and method for initializing a memory device from block oriented NAND flash
US6996676B2 (en) * 2002-11-14 2006-02-07 International Business Machines Corporation System and method for implementing an adaptive replacement cache policy
US20040098544A1 (en) * 2002-11-15 2004-05-20 Gaither Blaine D. Method and apparatus for managing a memory system
US7093101B2 (en) * 2002-11-21 2006-08-15 Microsoft Corporation Dynamic data structures for tracking file system free space in a flash memory device
EP1435576B1 (en) * 2003-01-03 2013-03-20 Austria Card Plastikkarten und Ausweissysteme GmbH Method and apparatus for block-oriented memory management provided in smart card controllers
JP2004227098A (en) * 2003-01-20 2004-08-12 Hitachi Ltd Control method of storage device controller and storage device controller
US7065618B1 (en) 2003-02-14 2006-06-20 Google Inc. Leasing scheme for data-modifying operations
US7107419B1 (en) 2003-02-14 2006-09-12 Google Inc. Systems and methods for performing record append operations
JP4233564B2 (en) 2003-03-10 2009-03-04 シャープ株式会社 Data processing apparatus, data processing program and recording medium
US8041878B2 (en) * 2003-03-19 2011-10-18 Samsung Electronics Co., Ltd. Flash file system
JP2004310621A (en) * 2003-04-10 2004-11-04 Hitachi Ltd File access method, and program for file access in storage system
US7412449B2 (en) * 2003-05-23 2008-08-12 Sap Aktiengesellschaft File object storage and retrieval using hashing techniques
US7263607B2 (en) * 2003-06-12 2007-08-28 Microsoft Corporation Categorizing electronic messages based on trust between electronic messaging entities
US7243203B2 (en) * 2003-06-13 2007-07-10 Sandisk 3D Llc Pipeline circuit for low latency memory
US7237141B2 (en) * 2003-06-19 2007-06-26 Lsi Corporation Method for recovering data from a redundant storage object
US20040268359A1 (en) * 2003-06-27 2004-12-30 Hanes David H. Computer-readable medium, method and computer system for processing input/output requests
US7373514B2 (en) 2003-07-23 2008-05-13 Intel Corporation High-performance hashing system
US7096321B2 (en) * 2003-10-21 2006-08-22 International Business Machines Corporation Method and system for a cache replacement technique with adaptive skipping
US7412583B2 (en) 2003-11-14 2008-08-12 International Business Machines Corporation Virtual incremental storage method
US7162571B2 (en) * 2003-12-09 2007-01-09 Emc Corporation Methods and apparatus for parsing a content address to facilitate selection of a physical storage location in a data storage system
US7822790B2 (en) * 2003-12-23 2010-10-26 International Business Machines Corporation Relative positioning and access of memory objects
JP4401788B2 (en) 2004-01-06 2010-01-20 株式会社日立製作所 Storage controller
US7305520B2 (en) * 2004-01-30 2007-12-04 Hewlett-Packard Development Company, L.P. Storage system with capability to allocate virtual storage segments among a plurality of controllers
JP2005293774A (en) 2004-04-02 2005-10-20 Hitachi Global Storage Technologies Netherlands Bv Control method of disk unit
JP4168003B2 (en) * 2004-04-09 2008-10-22 日立マクセル株式会社 Method for recording information on a plurality of information recording media and method for reproducing information from a plurality of recording media
US7788460B2 (en) * 2004-04-13 2010-08-31 Intel Corporation Defragmenting objects in a storage medium
US7224545B2 (en) 2004-04-15 2007-05-29 Quantum Corporation Methods and systems for overwrite protected storage media
US7725628B1 (en) 2004-04-20 2010-05-25 Lexar Media, Inc. Direct secondary device interface by a host
US20050240713A1 (en) * 2004-04-22 2005-10-27 V-Da Technology Flash memory device with ATA/ATAPI/SCSI or proprietary programming interface on PCI express
US7523343B2 (en) * 2004-04-30 2009-04-21 Microsoft Corporation Real-time file system repairs
US7644239B2 (en) 2004-05-03 2010-01-05 Microsoft Corporation Non-volatile memory cache performance improvement
WO2005114374A2 (en) * 2004-05-21 2005-12-01 Computer Associates Think, Inc. Object-based storage
US7386890B2 (en) * 2004-06-30 2008-06-10 Intel Corporation Method and apparatus to preserve a hash value of an executable module
US7386700B2 (en) * 2004-07-30 2008-06-10 Sandisk Il Ltd Virtual-to-physical address translation in a flash file system
JP4315876B2 (en) * 2004-08-17 2009-08-19 富士通株式会社 File management program, file management method, and file management apparatus
US20060075057A1 (en) * 2004-08-30 2006-04-06 International Business Machines Corporation Remote direct memory access system and method
KR100645058B1 (en) * 2004-11-03 2006-11-10 삼성전자주식회사 Memory managing technique capable of improving data reliability
WO2006052888A2 (en) 2004-11-05 2006-05-18 Trusted Data Corporation Dynamically expandable and contractible fault-tolerant storage system permitting variously sized storage devices and method
US7778984B2 (en) * 2004-11-19 2010-08-17 Microsoft Corporation System and method for a distributed object store
US7487320B2 (en) 2004-12-15 2009-02-03 International Business Machines Corporation Apparatus and system for dynamically allocating main memory among a plurality of applications
JP3810425B2 (en) * 2004-12-16 2006-08-16 松下電器産業株式会社 Falsification detection data generation method, and falsification detection method and apparatus
KR100662256B1 (en) * 2004-12-20 2006-12-28 한국전자통신연구원 Object-based Storage Device and its control method for having low process load
US7254672B1 (en) 2004-12-30 2007-08-07 Storage Technology Corporation Translation device driver for translating between disk device driver and tape device driver commands
US7620773B2 (en) * 2005-04-15 2009-11-17 Microsoft Corporation In-line non volatile memory disk read cache and write buffer
JP2006331158A (en) 2005-05-27 2006-12-07 Hitachi Ltd Storage system
US7590799B2 (en) * 2005-06-16 2009-09-15 Seagate Technology Llc OSD deterministic object fragmentation optimization in a disc drive
JP3976764B2 (en) * 2005-06-16 2007-09-19 株式会社ルネサステクノロジ Semiconductor disk device
US7533330B2 (en) * 2005-06-27 2009-05-12 Seagate Technology Llc Redundancy for storage data structures
US20070028051A1 (en) * 2005-08-01 2007-02-01 Arm Limited Time and power reduction in cache accesses
US7409489B2 (en) 2005-08-03 2008-08-05 Sandisk Corporation Scheduling of reclaim operations in non-volatile memory
US7552271B2 (en) 2005-08-03 2009-06-23 Sandisk Corporation Nonvolatile memory with block management
JP5008845B2 (en) * 2005-09-01 2012-08-22 株式会社日立製作所 Storage system, storage apparatus and control method thereof
US20070061597A1 (en) * 2005-09-14 2007-03-15 Micky Holtzman Secure yet flexible system architecture for secure devices with flash mass storage memory
US7979394B2 (en) * 2005-09-20 2011-07-12 Teradata Us, Inc. Method of managing storage and retrieval of data objects
US7529905B2 (en) 2005-10-13 2009-05-05 Sandisk Corporation Method of storing transformed units of data in a memory system having fixed sized storage blocks
US20070100893A1 (en) 2005-10-31 2007-05-03 Sigmatel, Inc. System and method for accessing data from a memory device
US7366808B2 (en) * 2005-11-23 2008-04-29 Hitachi, Ltd. System, method and apparatus for multiple-protocol-accessible OSD storage subsystem
US20070156998A1 (en) 2005-12-21 2007-07-05 Gorobets Sergey A Methods for memory allocation in non-volatile memories with a directly mapped file storage system
KR100746033B1 (en) * 2006-02-17 2007-08-06 삼성전자주식회사 Apparatus and method for measuring integrity
US20070233937A1 (en) * 2006-03-31 2007-10-04 Coulson Richard L Reliability of write operations to a non-volatile memory
US8453147B2 (en) * 2006-06-05 2013-05-28 Cisco Technology, Inc. Techniques for reducing thread overhead for systems with multiple multi-threaded processors
US8250316B2 (en) * 2006-06-06 2012-08-21 Seagate Technology Llc Write caching random data and sequential data simultaneously
US8307148B2 (en) * 2006-06-23 2012-11-06 Microsoft Corporation Flash management techniques
US7650458B2 (en) * 2006-06-23 2010-01-19 Microsoft Corporation Flash memory driver
US7519830B2 (en) * 2006-08-03 2009-04-14 Motorola, Inc. Secure storage of data
US20080077767A1 (en) * 2006-09-27 2008-03-27 Khosravi Hormuzd M Method and apparatus for secure page swapping in virtual memory systems
US8161353B2 (en) 2007-12-06 2012-04-17 Fusion-Io, Inc. Apparatus, system, and method for validating that a correct data segment is read from a data storage device
KR20220053586A (en) 2019-09-09 2022-04-29 바르트실라 노르웨이 에이에스 Marine Vessel Propellers, Propeller Blades and Installation Methods of Marine Vessel Propellers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325523A (en) * 1991-04-10 1994-06-28 International Business Machines Corporation Method for deleting objects from library resident optical disks by accumulating pending delete requests
US6535949B1 (en) * 1999-04-19 2003-03-18 Research In Motion Limited Portable electronic device having a log-structured file system in flash memory
US6697797B1 (en) * 2000-04-28 2004-02-24 Micro Data Base Systems, Inc. Method and apparatus for tracking data in a database, employing last-known location registers
US20050149472A1 (en) * 2003-12-24 2005-07-07 Ivan Schreter Reorganization-free mapping of objects in databases using a mapping chain
US7720864B1 (en) * 2004-03-25 2010-05-18 Symantec Operating Corporation Expiration of access tokens for quiescing a distributed system
US20070043900A1 (en) * 2005-08-20 2007-02-22 Samsung Electronics Co., Ltd. Flash memory management method and flash memory system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Michael Burrows et al, On line Data Compression in a Log Structured File system, April 15 1992 *
Oman, PS Stand-Alone and Multi-DEvices Share Common Driver, IBM March 31 2005 *
SCSI Object Based Storage Device Command (OSD), T10/1355-D, July 30 2004 *

Cited By (472)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9176808B2 (en) * 2012-01-09 2015-11-03 Samsung Electronics Co., Ltd. Storage device and nonvolatile memory device and operating method thereof
US9794343B2 (en) 2012-04-17 2017-10-17 Nimbix, Inc. Reconfigurable cloud computing
US11283868B2 (en) 2012-04-17 2022-03-22 Agarik Sas System and method for scheduling computer tasks
US10142417B2 (en) * 2012-04-17 2018-11-27 Nimbix, Inc. System and method for managing heterogeneous data for cloud computing applications
US11290534B2 (en) 2012-04-17 2022-03-29 Agarik Sas System and method for scheduling computer tasks
US20170048318A1 (en) * 2012-04-17 2017-02-16 Nimbix, Inc. System and method for managing heterogeneous data for cloud computing applications
US20150324294A1 (en) * 2013-01-31 2015-11-12 Hitachi, Ltd. Storage system and cache control method
US9367469B2 (en) * 2013-01-31 2016-06-14 Hitachi, Ltd. Storage system and cache control method
US9472265B2 (en) 2013-03-04 2016-10-18 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US11276439B2 (en) 2013-03-04 2022-03-15 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US10431264B2 (en) 2013-03-04 2019-10-01 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9892766B2 (en) 2013-03-04 2018-02-13 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US11727963B2 (en) 2013-03-04 2023-08-15 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US10796733B2 (en) 2013-03-04 2020-10-06 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US10153009B2 (en) 2013-03-04 2018-12-11 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9959913B2 (en) 2013-03-04 2018-05-01 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9143403B2 (en) * 2013-06-19 2015-09-22 Hewlett-Packard Development Company, L.P. Autonomous metric tracking and adjustment
US20140379889A1 (en) * 2013-06-19 2014-12-25 Hewlett-Packard Development Company, L.P. Autonomous metric tracking and adjustment
US10643673B2 (en) 2013-07-26 2020-05-05 Micron Technology, Inc. Apparatuses and methods for performing compare operations using sensing circuitry
US9466340B2 (en) 2013-07-26 2016-10-11 Micron Technology, Inc. Apparatuses and methods for performing compare operations using sensing circuitry
US9799378B2 (en) 2013-07-26 2017-10-24 Micron Technology, Inc. Apparatuses and methods for performing compare operations using sensing circuitry
US10056122B2 (en) 2013-07-26 2018-08-21 Micron Technology, Inc. Apparatuses and methods for performing compare operations using sensing circuitry
US10186303B2 (en) 2013-08-08 2019-01-22 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US10535384B2 (en) 2013-08-08 2020-01-14 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9899068B2 (en) 2013-08-08 2018-02-20 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9589607B2 (en) 2013-08-08 2017-03-07 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US10878863B2 (en) 2013-08-08 2020-12-29 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US11495274B2 (en) 2013-08-08 2022-11-08 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US10223208B2 (en) 2013-08-13 2019-03-05 Sandisk Technologies Llc Annotated atomic write
US9530475B2 (en) 2013-08-30 2016-12-27 Micron Technology, Inc. Independently addressable memory array address spaces
US9830955B2 (en) 2013-09-19 2017-11-28 Micron Technology, Inc. Data shifting
US10043556B2 (en) 2013-09-19 2018-08-07 Micron Technology, Inc. Data shifting
US9437256B2 (en) 2013-09-19 2016-09-06 Micron Technology, Inc. Data shifting
US9449675B2 (en) 2013-10-31 2016-09-20 Micron Technology, Inc. Apparatuses and methods for identifying an extremum value stored in an array of memory cells
US10579336B2 (en) 2013-11-08 2020-03-03 Micron Technology, Inc. Division operations for memory
US10055196B2 (en) 2013-11-08 2018-08-21 Micron Technology, Inc. Division operations for memory
US9430191B2 (en) 2013-11-08 2016-08-30 Micron Technology, Inc. Division operations for memory
US20220382726A1 (en) * 2013-11-12 2022-12-01 Dropbox, Inc. Content Item Purging
US11223672B2 (en) 2013-11-17 2022-01-11 Agarik Sas System and method for using a container logic structure to control computing operations
US9973566B2 (en) 2013-11-17 2018-05-15 Nimbix, Inc. Dynamic creation and execution of containerized applications in cloud computing
US11064014B2 (en) 2013-11-17 2021-07-13 Nimbix, Inc. System and method for batch computing
US11621998B2 (en) 2013-11-17 2023-04-04 Agarik Sas Dynamic creation and execution of containerized applications in cloud computing
US10726919B2 (en) 2014-03-31 2020-07-28 Micron Technology, Inc. Apparatuses and methods for comparing data patterns in memory
US9934856B2 (en) 2014-03-31 2018-04-03 Micron Technology, Inc. Apparatuses and methods for comparing data patterns in memory
US11393531B2 (en) 2014-03-31 2022-07-19 Micron Technology, Inc. Apparatuses and methods for comparing data patterns in memory
US10452268B2 (en) 2014-04-18 2019-10-22 Ultrata, Llc Utilization of a distributed index to provide object memory fabric coherency
US10382540B2 (en) 2014-05-29 2019-08-13 Sandisk Technologies Llc Synchronizing storage state information
US9704540B2 (en) 2014-06-05 2017-07-11 Micron Technology, Inc. Apparatuses and methods for parity determination using sensing circuitry
US10304519B2 (en) 2014-06-05 2019-05-28 Micron Technology, Inc. Apparatuses and methods for performing an exclusive or operation using sensing circuitry
US10090041B2 (en) 2014-06-05 2018-10-02 Micro Technology, Inc. Performing logical operations using sensing circuitry
US11205497B2 (en) 2014-06-05 2021-12-21 Micron Technology, Inc. Comparison operations in memory
US9830999B2 (en) 2014-06-05 2017-11-28 Micron Technology, Inc. Comparison operations in memory
US9786335B2 (en) 2014-06-05 2017-10-10 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US20150355706A1 (en) * 2014-06-05 2015-12-10 Fujitsu Limited Electronic device and method for controlling electronic device
WO2015187487A1 (en) * 2014-06-05 2015-12-10 Micron Technology, Inc. Virtual address table
US10074407B2 (en) 2014-06-05 2018-09-11 Micron Technology, Inc. Apparatuses and methods for performing invert operations using sensing circuitry
US9449674B2 (en) 2014-06-05 2016-09-20 Micron Technology, Inc. Performing logical operations using sensing circuitry
US10210911B2 (en) 2014-06-05 2019-02-19 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry in a memory device
US9455020B2 (en) 2014-06-05 2016-09-27 Micron Technology, Inc. Apparatuses and methods for performing an exclusive or operation using sensing circuitry
US9779019B2 (en) 2014-06-05 2017-10-03 Micron Technology, Inc. Data storage layout
US10249350B2 (en) 2014-06-05 2019-04-02 Micron Technology, Inc. Apparatuses and methods for parity determination using sensing circuitry
US10255193B2 (en) 2014-06-05 2019-04-09 Micron Technology, Inc. Virtual address table
US9496023B2 (en) 2014-06-05 2016-11-15 Micron Technology, Inc. Comparison operations on logical representations of values in memory
US10839892B2 (en) 2014-06-05 2020-11-17 Micron Technology, Inc. Comparison operations in memory
US10839867B2 (en) 2014-06-05 2020-11-17 Micron Technology, Inc. Apparatuses and methods for parity determination using sensing circuitry
US10290344B2 (en) 2014-06-05 2019-05-14 Micron Technology, Inc. Performing logical operations using sensing circuitry
US11238920B2 (en) 2014-06-05 2022-02-01 Micron Technology, Inc. Comparison operations in memory
US9910787B2 (en) 2014-06-05 2018-03-06 Micron Technology, Inc. Virtual address table
US10754787B2 (en) 2014-06-05 2020-08-25 Micron Technology, Inc. Virtual address table
US10734038B2 (en) 2014-06-05 2020-08-04 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US11120850B2 (en) 2014-06-05 2021-09-14 Micron Technology, Inc. Performing logical operations using sensing circuitry
US10360147B2 (en) * 2014-06-05 2019-07-23 Micron Technology, Inc. Data storage layout
US10381065B2 (en) 2014-06-05 2019-08-13 Micron Technology, Inc. Performing logical operations using sensing circuitry
US11422933B2 (en) 2014-06-05 2022-08-23 Micron Technology, Inc. Data storage layout
US10424350B2 (en) 2014-06-05 2019-09-24 Micron Technology, Inc. Performing logical operations using sensing circuitry
US10453499B2 (en) 2014-06-05 2019-10-22 Micron Technology, Inc. Apparatuses and methods for performing an in-place inversion using sensing circuitry
US10490257B2 (en) 2014-06-05 2019-11-26 Micron Technology, Inc. Comparison operations in memory
US11355178B2 (en) 2014-06-05 2022-06-07 Micron Technology, Inc. Apparatuses and methods for performing an exclusive or operation using sensing circuitry
US9741427B2 (en) 2014-06-05 2017-08-22 Micron Technology, Inc. Performing logical operations using sensing circuitry
US10593418B2 (en) 2014-06-05 2020-03-17 Micron Technology, Inc. Comparison operations in memory
US9711206B2 (en) 2014-06-05 2017-07-18 Micron Technology, Inc. Performing logical operations using sensing circuitry
US10522211B2 (en) 2014-06-05 2019-12-31 Micron Technology, Inc. Performing logical operations using sensing circuitry
US9711207B2 (en) 2014-06-05 2017-07-18 Micron Technology, Inc. Performing logical operations using sensing circuitry
US20160054939A1 (en) * 2014-08-21 2016-02-25 Datrium, Inc. Alternate Storage Arrangement in a Distributed Data Storage System with Key-Based Addressing
US10514982B2 (en) * 2014-08-21 2019-12-24 Datrium, Inc. Alternate storage arrangement in a distributed data storage system with key-based addressing
US11416417B2 (en) 2014-08-25 2022-08-16 Western Digital Technologies, Inc. Method and apparatus to generate zero content over garbage data when encryption parameters are changed
US9589602B2 (en) 2014-09-03 2017-03-07 Micron Technology, Inc. Comparison operations in memory
US9940985B2 (en) 2014-09-03 2018-04-10 Micron Technology, Inc. Comparison operations in memory
US9779789B2 (en) 2014-09-03 2017-10-03 Micron Technology, Inc. Comparison operations in memory
US9898252B2 (en) 2014-09-03 2018-02-20 Micron Technology, Inc. Multiplication operations in memory
US10157126B2 (en) 2014-09-03 2018-12-18 Micron Technology, Inc. Swap operations in memory
US10705798B2 (en) 2014-09-03 2020-07-07 Micron Technology, Inc. Multiplication operations in memory
US10559360B2 (en) 2014-09-03 2020-02-11 Micron Technology, Inc. Apparatuses and methods for determining population count
US10861563B2 (en) 2014-09-03 2020-12-08 Micron Technology, Inc. Apparatuses and methods for determining population count
US9847110B2 (en) 2014-09-03 2017-12-19 Micron Technology, Inc. Apparatuses and methods for storing a data value in multiple columns of an array corresponding to digits of a vector
US10068652B2 (en) 2014-09-03 2018-09-04 Micron Technology, Inc. Apparatuses and methods for determining population count
US10409554B2 (en) 2014-09-03 2019-09-10 Micron Technology, Inc. Multiplication operations in memory
US10409555B2 (en) 2014-09-03 2019-09-10 Micron Technology, Inc. Multiplication operations in memory
US9940981B2 (en) 2014-09-03 2018-04-10 Micron Technology, Inc. Division operations in memory
US10032491B2 (en) 2014-09-03 2018-07-24 Micron Technology, Inc. Apparatuses and methods for storing a data value in multiple columns
US9740607B2 (en) 2014-09-03 2017-08-22 Micron Technology, Inc. Swap operations in memory
US10713011B2 (en) 2014-09-03 2020-07-14 Micron Technology, Inc. Multiplication operations in memory
US9747961B2 (en) 2014-09-03 2017-08-29 Micron Technology, Inc. Division operations in memory
US9904515B2 (en) 2014-09-03 2018-02-27 Micron Technology, Inc. Multiplication operations in memory
US9940026B2 (en) 2014-10-03 2018-04-10 Micron Technology, Inc. Multidimensional contiguous memory allocation
US11768600B2 (en) 2014-10-03 2023-09-26 Micron Technology, Inc. Computing reduction and prefix sum operations in memory
US9836218B2 (en) 2014-10-03 2017-12-05 Micron Technology, Inc. Computing reduction and prefix sum operations in memory
US10540093B2 (en) 2014-10-03 2020-01-21 Micron Technology, Inc. Multidimensional contiguous memory allocation
US10261691B2 (en) 2014-10-03 2019-04-16 Micron Technology, Inc. Computing reduction and prefix sum operations in memory
US10956043B2 (en) 2014-10-03 2021-03-23 Micron Technology, Inc. Computing reduction and prefix sum operations in memory
US10163467B2 (en) 2014-10-16 2018-12-25 Micron Technology, Inc. Multiple endianness compatibility
US10593377B2 (en) 2014-10-16 2020-03-17 Micron Technology, Inc. Multiple endianness compatibility
US10984842B2 (en) 2014-10-16 2021-04-20 Micron Technology, Inc. Multiple endianness compatibility
US20180018293A1 (en) * 2014-10-22 2018-01-18 Huawei Technologies Co.,Ltd. Method, controller, and system for service flow control in object-based storage system
US9984013B2 (en) * 2014-10-22 2018-05-29 Huawei Technologies Co., Ltd. Method, controller, and system for service flow control in object-based storage system
US9804981B2 (en) * 2014-10-22 2017-10-31 Huawei Technologies Co., Ltd. Method, controller, and system for service flow control in object-based storage system
US10685699B2 (en) 2014-10-24 2020-06-16 Micron Technology, Inc. Sort operation in memory
US11315626B2 (en) 2014-10-24 2022-04-26 Micron Technology, Inc. Sort operation in memory
US10147480B2 (en) 2014-10-24 2018-12-04 Micron Technology, Inc. Sort operation in memory
US10529387B2 (en) 2014-10-29 2020-01-07 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US10074406B2 (en) 2014-10-29 2018-09-11 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9779784B2 (en) 2014-10-29 2017-10-03 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US10073635B2 (en) 2014-12-01 2018-09-11 Micron Technology, Inc. Multiple endianness compatibility
US10387055B2 (en) 2014-12-01 2019-08-20 Micron Technology, Inc. Multiple endianness compatibility
US10983706B2 (en) 2014-12-01 2021-04-20 Micron Technology, Inc. Multiple endianness compatibility
US10037786B2 (en) 2014-12-01 2018-07-31 Micron Technology, Inc. Apparatuses and methods for converting a mask to an index
US10460773B2 (en) 2014-12-01 2019-10-29 Micron Technology, Inc. Apparatuses and methods for converting a mask to an index
US9747960B2 (en) 2014-12-01 2017-08-29 Micron Technology, Inc. Apparatuses and methods for converting a mask to an index
US10593376B2 (en) 2015-01-07 2020-03-17 Micron Technology, Inc. Longest element length determination in memory
US10032493B2 (en) 2015-01-07 2018-07-24 Micron Technology, Inc. Longest element length determination in memory
US10782980B2 (en) 2015-01-07 2020-09-22 Micron Technology, Inc. Generating and executing a control flow
US11726791B2 (en) 2015-01-07 2023-08-15 Micron Technology, Inc. Generating and executing a control flow
US10984841B2 (en) 2015-01-07 2021-04-20 Micron Technology, Inc. Longest element length determination in memory
US11334362B2 (en) 2015-01-07 2022-05-17 Micron Technology, Inc. Generating and executing a control flow
US10061590B2 (en) 2015-01-07 2018-08-28 Micron Technology, Inc. Generating and executing a control flow
US20160210077A1 (en) * 2015-01-20 2016-07-21 Ultrata Llc Trans-cloud object based memory
US20160210076A1 (en) * 2015-01-20 2016-07-21 Ultrata Llc Object based memory fabric
US10768814B2 (en) 2015-01-20 2020-09-08 Ultrata, Llc Distributed index for fault tolerant object memory fabric
US11782601B2 (en) 2015-01-20 2023-10-10 Ultrata, Llc Object memory instruction set
US11579774B2 (en) 2015-01-20 2023-02-14 Ultrata, Llc Object memory data flow triggers
US20220100370A1 (en) * 2015-01-20 2022-03-31 Ultrata, Llc Object memory data flow instruction execution
US20160210078A1 (en) * 2015-01-20 2016-07-21 Ultrata Llc Universal single level object memory address space
US9965185B2 (en) 2015-01-20 2018-05-08 Ultrata, Llc Utilization of a distributed index to provide object memory fabric coherency
US11126350B2 (en) 2015-01-20 2021-09-21 Ultrata, Llc Utilization of a distributed index to provide object memory fabric coherency
US11775171B2 (en) 2015-01-20 2023-10-03 Ultrata, Llc Utilization of a distributed index to provide object memory fabric coherency
US20160210079A1 (en) * 2015-01-20 2016-07-21 Ultrata Llc Object memory fabric performance acceleration
US9971506B2 (en) 2015-01-20 2018-05-15 Ultrata, Llc Distributed index for fault tolerant object memory fabric
US11755202B2 (en) 2015-01-20 2023-09-12 Ultrata, Llc Managing meta-data in an object memory fabric
US11086521B2 (en) 2015-01-20 2021-08-10 Ultrata, Llc Object memory data flow instruction execution
US11573699B2 (en) 2015-01-20 2023-02-07 Ultrata, Llc Distributed index for fault tolerant object memory fabric
US11755201B2 (en) 2015-01-20 2023-09-12 Ultrata, Llc Implementation of an object memory centric cloud
US11768602B2 (en) * 2015-01-20 2023-09-26 Ultrata, Llc Object memory data flow instruction execution
US9583163B2 (en) 2015-02-03 2017-02-28 Micron Technology, Inc. Loop structure for operations in memory
US10176851B2 (en) 2015-02-03 2019-01-08 Micron Technology, Inc. Loop structure for operations in memory
US10942652B2 (en) 2015-02-06 2021-03-09 Micron Technology, Inc. Apparatuses and methods for parallel writing to multiple memory device structures
US10964358B2 (en) 2015-02-06 2021-03-30 Micron Technology, Inc. Apparatuses and methods for scatter and gather
US11482260B2 (en) 2015-02-06 2022-10-25 Micron Technology, Inc. Apparatuses and methods for scatter and gather
US10496286B2 (en) 2015-02-06 2019-12-03 Micron Technology, Inc. Apparatuses and methods for parallel writing to multiple memory device structures
US11263123B2 (en) 2015-02-06 2022-03-01 Micron Technology, Inc. Apparatuses and methods for memory device as a store for program instructions
US10522199B2 (en) 2015-02-06 2019-12-31 Micron Technology, Inc. Apparatuses and methods for scatter and gather
US10817414B2 (en) 2015-02-06 2020-10-27 Micron Technology, Inc. Apparatuses and methods for memory device as a store for block program instructions
US11681440B2 (en) 2015-02-06 2023-06-20 Micron Technology, Inc. Apparatuses and methods for parallel writing to multiple memory device structures
US10289542B2 (en) 2015-02-06 2019-05-14 Micron Technology, Inc. Apparatuses and methods for memory device as a store for block program instructions
US10522212B2 (en) 2015-03-10 2019-12-31 Micron Technology, Inc. Apparatuses and methods for shift decisions
US11107520B2 (en) 2015-03-10 2021-08-31 Micron Technology, Inc. Apparatuses and methods for shift decisions
US9741399B2 (en) 2015-03-11 2017-08-22 Micron Technology, Inc. Data shift by elements of a vector in memory
US9898253B2 (en) 2015-03-11 2018-02-20 Micron Technology, Inc. Division operations on variable length elements in memory
US9928887B2 (en) 2015-03-11 2018-03-27 Micron Technology, Inc. Data shift by elements of a vector in memory
US10365851B2 (en) 2015-03-12 2019-07-30 Micron Technology, Inc. Apparatuses and methods for data movement
US10936235B2 (en) 2015-03-12 2021-03-02 Micron Technology, Inc. Apparatuses and methods for data movement
US11614877B2 (en) 2015-03-12 2023-03-28 Micron Technology, Inc. Apparatuses and methods for data movement
US11663005B2 (en) 2015-03-13 2023-05-30 Micron Technology, Inc. Vector population count determination via comparsion iterations in memory
US10896042B2 (en) 2015-03-13 2021-01-19 Micron Technology, Inc. Vector population count determination via comparison iterations in memory
US10146537B2 (en) 2015-03-13 2018-12-04 Micron Technology, Inc. Vector population count determination in memory
US10963398B2 (en) 2015-04-01 2021-03-30 Micron Technology, Inc. Virtual register file
US10049054B2 (en) 2015-04-01 2018-08-14 Micron Technology, Inc. Virtual register file
US11782688B2 (en) 2015-04-14 2023-10-10 Micron Technology, Inc. Target architecture determination
US11237808B2 (en) 2015-04-14 2022-02-01 Micron Technology, Inc. Target architecture determination
US10795653B2 (en) 2015-04-14 2020-10-06 Micron Technology, Inc. Target architecture determination
US10140104B2 (en) 2015-04-14 2018-11-27 Micron Technology, Inc. Target architecture determination
US10878884B2 (en) 2015-04-16 2020-12-29 Micron Technology, Inc. Apparatuses and methods to reverse data stored in memory
US10418092B2 (en) 2015-04-16 2019-09-17 Micron Technology, Inc. Apparatuses and methods to reverse data stored in memory
US9959923B2 (en) 2015-04-16 2018-05-01 Micron Technology, Inc. Apparatuses and methods to reverse data stored in memory
US20160334996A1 (en) * 2015-05-15 2016-11-17 ScaleFlux In-flash immutable object processing
US9946461B2 (en) * 2015-05-15 2018-04-17 ScaleFlux, Inc. In-flash immutable object processing
US11599475B2 (en) 2015-05-28 2023-03-07 Micron Technology, Inc. Apparatuses and methods for compute enabled cache
US10073786B2 (en) 2015-05-28 2018-09-11 Micron Technology, Inc. Apparatuses and methods for compute enabled cache
US10372612B2 (en) 2015-05-28 2019-08-06 Micron Technology, Inc. Apparatuses and methods for compute enabled cache
US10970218B2 (en) 2015-05-28 2021-04-06 Micron Technology, Inc. Apparatuses and methods for compute enabled cache
US11733904B2 (en) 2015-06-09 2023-08-22 Ultrata, Llc Infinite memory fabric hardware implementation with router
US10235084B2 (en) 2015-06-09 2019-03-19 Ultrata, Llc Infinite memory fabric streams and APIS
US10922005B2 (en) 2015-06-09 2021-02-16 Ultrata, Llc Infinite memory fabric streams and APIs
US10698628B2 (en) 2015-06-09 2020-06-30 Ultrata, Llc Infinite memory fabric hardware implementation with memory
US10430109B2 (en) 2015-06-09 2019-10-01 Ultrata, Llc Infinite memory fabric hardware implementation with router
US11231865B2 (en) 2015-06-09 2022-01-25 Ultrata, Llc Infinite memory fabric hardware implementation with router
US11256438B2 (en) 2015-06-09 2022-02-22 Ultrata, Llc Infinite memory fabric hardware implementation with memory
US9971542B2 (en) 2015-06-09 2018-05-15 Ultrata, Llc Infinite memory fabric streams and APIs
US9886210B2 (en) 2015-06-09 2018-02-06 Ultrata, Llc Infinite memory fabric hardware implementation with router
US10431263B2 (en) 2015-06-12 2019-10-01 Micron Technology, Inc. Simulating access lines
US9990966B2 (en) 2015-06-12 2018-06-05 Micron Technology, Inc. Simulating access lines
US9704541B2 (en) 2015-06-12 2017-07-11 Micron Technology, Inc. Simulating access lines
US9921777B2 (en) 2015-06-22 2018-03-20 Micron Technology, Inc. Apparatuses and methods for data transfer from sensing circuitry to a controller
US10157019B2 (en) 2015-06-22 2018-12-18 Micron Technology, Inc. Apparatuses and methods for data transfer from sensing circuitry to a controller
US11106389B2 (en) 2015-06-22 2021-08-31 Micron Technology, Inc. Apparatuses and methods for data transfer from sensing circuitry to a controller
WO2016209667A1 (en) * 2015-06-23 2016-12-29 Western Digital Technologies, Inc. Data management for object based storage
US10089023B2 (en) 2015-06-23 2018-10-02 Western Digital Technologies, Inc. Data management for object based storage
US9996479B2 (en) 2015-08-17 2018-06-12 Micron Technology, Inc. Encryption of executables in computational memory
US11625336B2 (en) 2015-08-17 2023-04-11 Micron Technology, Inc. Encryption of executables in computational memory
US10691620B2 (en) 2015-08-17 2020-06-23 Micron Technology, Inc. Encryption of executables in computational memory
US9928000B2 (en) 2015-11-12 2018-03-27 International Business Machines Corporation Memory mapping for object-based storage devices
US9870322B2 (en) 2015-11-12 2018-01-16 International Business Machines Corporation Memory mapping for object-based storage devices
US10235063B2 (en) 2015-12-08 2019-03-19 Ultrata, Llc Memory fabric operations and coherency using fault tolerant objects
US11281382B2 (en) 2015-12-08 2022-03-22 Ultrata, Llc Object memory interfaces across shared links
US10248337B2 (en) 2015-12-08 2019-04-02 Ultrata, Llc Object memory interfaces across shared links
US10241676B2 (en) 2015-12-08 2019-03-26 Ultrata, Llc Memory fabric software implementation
US11899931B2 (en) 2015-12-08 2024-02-13 Ultrata, Llc Memory fabric software implementation
US10895992B2 (en) 2015-12-08 2021-01-19 Ultrata Llc Memory fabric operations and coherency using fault tolerant objects
US10809923B2 (en) 2015-12-08 2020-10-20 Ultrata, Llc Object memory interfaces across shared links
US11269514B2 (en) 2015-12-08 2022-03-08 Ultrata, Llc Memory fabric software implementation
US9905276B2 (en) 2015-12-21 2018-02-27 Micron Technology, Inc. Control of sensing components in association with performing operations
US10236037B2 (en) 2015-12-21 2019-03-19 Micron Technology, Inc. Data transfer in sensing components
US11340983B2 (en) 2016-01-06 2022-05-24 Micron Technology, Inc. Error code calculation on sensing circuitry
US9952925B2 (en) 2016-01-06 2018-04-24 Micron Technology, Inc. Error code calculation on sensing circuitry
US11593200B2 (en) 2016-01-06 2023-02-28 Micron Technology, Inc. Error code calculation on sensing circuitry
US10152374B2 (en) 2016-01-06 2018-12-11 Micron Technology, Inc. Error code calculation on sensing circuitry
US10423486B2 (en) 2016-01-06 2019-09-24 Micron Technology, Inc. Error code calculation on sensing circuitry
US10949299B2 (en) 2016-01-06 2021-03-16 Micron Technology, Inc. Error code calculation on sensing circuitry
US10048888B2 (en) 2016-02-10 2018-08-14 Micron Technology, Inc. Apparatuses and methods for partitioned parallel data movement
US10915263B2 (en) 2016-02-10 2021-02-09 Micron Technology, Inc. Apparatuses and methods for partitioned parallel data movement
US10324654B2 (en) 2016-02-10 2019-06-18 Micron Technology, Inc. Apparatuses and methods for partitioned parallel data movement
US11513713B2 (en) 2016-02-10 2022-11-29 Micron Technology, Inc. Apparatuses and methods for partitioned parallel data movement
US9892767B2 (en) 2016-02-12 2018-02-13 Micron Technology, Inc. Data gathering in memory
US10026459B2 (en) 2016-02-12 2018-07-17 Micron Technology, Inc. Data gathering in memory
US9971541B2 (en) 2016-02-17 2018-05-15 Micron Technology, Inc. Apparatuses and methods for data movement
US11010085B2 (en) 2016-02-17 2021-05-18 Micron Technology, Inc. Apparatuses and methods for data movement
US11614878B2 (en) 2016-02-17 2023-03-28 Micron Technology, Inc. Apparatuses and methods for data movement
US10353618B2 (en) 2016-02-17 2019-07-16 Micron Technology, Inc. Apparatuses and methods for data movement
US10217499B2 (en) 2016-02-19 2019-02-26 Micron Technology, Inc. Modified decode for corner turn
US10783942B2 (en) 2016-02-19 2020-09-22 Micron Technology, Inc. Modified decode for corner turn
US10956439B2 (en) 2016-02-19 2021-03-23 Micron Technology, Inc. Data transfer with a bit vector operation device
US11816123B2 (en) 2016-02-19 2023-11-14 Micron Technology, Inc. Data transfer with a bit vector operation device
US9899070B2 (en) 2016-02-19 2018-02-20 Micron Technology, Inc. Modified decode for corner turn
US9697876B1 (en) 2016-03-01 2017-07-04 Micron Technology, Inc. Vertical bit vector shift in memory
US9947376B2 (en) 2016-03-01 2018-04-17 Micron Technology, Inc. Vertical bit vector shift in memory
US10902906B2 (en) 2016-03-10 2021-01-26 Micron Technology, Inc. Apparatuses and methods for logic/memory devices
US10262721B2 (en) 2016-03-10 2019-04-16 Micron Technology, Inc. Apparatuses and methods for cache invalidate
US10878883B2 (en) 2016-03-10 2020-12-29 Micron Technology, Inc. Apparatuses and methods for cache invalidate
US10199088B2 (en) 2016-03-10 2019-02-05 Micron Technology, Inc. Apparatuses and methods for cache invalidate
US10559347B2 (en) 2016-03-10 2020-02-11 Micron Technology, Inc. Processing in memory (PIM) capable memory device having timing circuitry to control timing of operations
US11915741B2 (en) 2016-03-10 2024-02-27 Lodestar Licensing Group Llc Apparatuses and methods for logic/memory devices
US11594274B2 (en) 2016-03-10 2023-02-28 Micron Technology, Inc. Processing in memory (PIM)capable memory device having timing circuity to control timing of operations
US9997232B2 (en) 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
US11314429B2 (en) 2016-03-16 2022-04-26 Micron Technology, Inc. Apparatuses and methods for operations using compressed and decompressed data
US10379772B2 (en) 2016-03-16 2019-08-13 Micron Technology, Inc. Apparatuses and methods for operations using compressed and decompressed data
US9910637B2 (en) 2016-03-17 2018-03-06 Micron Technology, Inc. Signed division in memory
US10409557B2 (en) 2016-03-17 2019-09-10 Micron Technology, Inc. Signed division in memory
US10817360B2 (en) 2016-03-22 2020-10-27 Micron Technology, Inc. Apparatus and methods for debugging on a memory device
US10120740B2 (en) 2016-03-22 2018-11-06 Micron Technology, Inc. Apparatus and methods for debugging on a memory device
US10388393B2 (en) 2016-03-22 2019-08-20 Micron Technology, Inc. Apparatus and methods for debugging on a host and memory device
US11074988B2 (en) 2016-03-22 2021-07-27 Micron Technology, Inc. Apparatus and methods for debugging on a host and memory device
US11126557B2 (en) 2016-03-25 2021-09-21 Micron Technology, Inc. Apparatuses and methods for cache operations
US10474581B2 (en) 2016-03-25 2019-11-12 Micron Technology, Inc. Apparatuses and methods for cache operations
US11775296B2 (en) 2016-03-25 2023-10-03 Micron Technology, Inc. Mask patterns generated in memory from seed vectors
US11693783B2 (en) 2016-03-25 2023-07-04 Micron Technology, Inc. Apparatuses and methods for cache operations
US10977033B2 (en) 2016-03-25 2021-04-13 Micron Technology, Inc. Mask patterns generated in memory from seed vectors
US10482948B2 (en) 2016-03-28 2019-11-19 Micron Technology, Inc. Apparatuses and methods for data movement
US10074416B2 (en) 2016-03-28 2018-09-11 Micron Technology, Inc. Apparatuses and methods for data movement
US11016811B2 (en) 2016-03-28 2021-05-25 Micron Technology, Inc. Apparatuses and methods to determine timing of operations
US10698734B2 (en) 2016-03-28 2020-06-30 Micron Technology, Inc. Apparatuses and methods to determine timing of operations
US10430244B2 (en) 2016-03-28 2019-10-01 Micron Technology, Inc. Apparatuses and methods to determine timing of operations
US10453502B2 (en) 2016-04-04 2019-10-22 Micron Technology, Inc. Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions
US11557326B2 (en) 2016-04-04 2023-01-17 Micron Techology, Inc. Memory power coordination
US11107510B2 (en) 2016-04-04 2021-08-31 Micron Technology, Inc. Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions
US10607665B2 (en) 2016-04-07 2020-03-31 Micron Technology, Inc. Span mask generation
US11437079B2 (en) 2016-04-07 2022-09-06 Micron Technology, Inc. Span mask generation
US10134453B2 (en) 2016-04-19 2018-11-20 Micron Technology, Inc. Invert operations using sensing circuitry
US9818459B2 (en) 2016-04-19 2017-11-14 Micron Technology, Inc. Invert operations using sensing circuitry
US10643674B2 (en) 2016-04-19 2020-05-05 Micron Technology, Inc. Invert operations using sensing circuitry
US10699756B2 (en) 2016-04-20 2020-06-30 Micron Technology, Inc. Apparatuses and methods for performing corner turn operations using sensing circuitry
US9990967B2 (en) 2016-04-20 2018-06-05 Micron Technology, Inc. Apparatuses and methods for performing corner turn operations using sensing circuitry
US10153008B2 (en) 2016-04-20 2018-12-11 Micron Technology, Inc. Apparatuses and methods for performing corner turn operations using sensing circuitry
US9659605B1 (en) 2016-04-20 2017-05-23 Micron Technology, Inc. Apparatuses and methods for performing corner turn operations using sensing circuitry
US10540144B2 (en) 2016-05-11 2020-01-21 Micron Technology, Inc. Signed division in memory
US10042608B2 (en) 2016-05-11 2018-08-07 Micron Technology, Inc. Signed division in memory
US9659610B1 (en) 2016-05-18 2017-05-23 Micron Technology, Inc. Apparatuses and methods for shifting data
US9899064B2 (en) 2016-05-18 2018-02-20 Micron Technology, Inc. Apparatuses and methods for shifting data
US10311922B2 (en) 2016-06-03 2019-06-04 Micron Technology, Inc. Shifting data
US10658017B2 (en) 2016-06-03 2020-05-19 Micron Technology, Inc. Shifting data
US10049707B2 (en) 2016-06-03 2018-08-14 Micron Technology, Inc. Shifting data
US10387046B2 (en) 2016-06-22 2019-08-20 Micron Technology, Inc. Bank to bank data transfer
US10929023B2 (en) 2016-06-22 2021-02-23 Micron Technology, Inc. Bank to bank data transfer
US11755206B2 (en) 2016-06-22 2023-09-12 Micron Technology, Inc. Bank to bank data transfer
US10037785B2 (en) 2016-07-08 2018-07-31 Micron Technology, Inc. Scan chain operation in sensing circuitry
US10388334B2 (en) 2016-07-08 2019-08-20 Micron Technology, Inc. Scan chain operation in sensing circuitry
US11468944B2 (en) 2016-07-19 2022-10-11 Micron Technology, Inc. Utilization of data stored in an edge section of an array
US10699772B2 (en) 2016-07-19 2020-06-30 Micron Technology, Inc. Utilization of instructions stored in an edge section of an array of memory cells
US10388360B2 (en) 2016-07-19 2019-08-20 Micron Technology, Inc. Utilization of data stored in an edge section of an array
US10387299B2 (en) 2016-07-20 2019-08-20 Micron Technology, Inc. Apparatuses and methods for transferring data
US10929283B2 (en) 2016-07-20 2021-02-23 Micron Technology, Inc. Apparatuses and methods for transferring data
US11513945B2 (en) 2016-07-20 2022-11-29 Micron Technology, Inc. Apparatuses and methods for transferring data using a cache
US10733089B2 (en) 2016-07-20 2020-08-04 Micron Technology, Inc. Apparatuses and methods for write address tracking
US10839870B2 (en) 2016-07-21 2020-11-17 Micron Technology, Inc. Apparatuses and methods for storing a data value in a sensing circuitry element
US9767864B1 (en) 2016-07-21 2017-09-19 Micron Technology, Inc. Apparatuses and methods for storing a data value in a sensing circuitry element
US10789996B2 (en) 2016-07-21 2020-09-29 Micron Technology, Inc. Shifting data in sensing circuitry
US9966116B2 (en) 2016-07-21 2018-05-08 Micron Technology, Inc. Apparatuses and methods for storing a data value in a sensing circuitry element
US9972367B2 (en) 2016-07-21 2018-05-15 Micron Technology, Inc. Shifting data in sensing circuitry
US10242722B2 (en) 2016-07-21 2019-03-26 Micron Technology, Inc. Shifting data in sensing circuitry
US10360949B2 (en) 2016-07-21 2019-07-23 Micron Technology, Inc. Apparatuses and methods for storing a data value in a sensing circuitry element
US10303632B2 (en) 2016-07-26 2019-05-28 Micron Technology, Inc. Accessing status information
US10725952B2 (en) 2016-07-26 2020-07-28 Micron Technology, Inc. Accessing status information
US11664064B2 (en) 2016-07-28 2023-05-30 Micron Technology, Inc. Apparatuses and methods for operations in a self-refresh state
US10468087B2 (en) 2016-07-28 2019-11-05 Micron Technology, Inc. Apparatuses and methods for operations in a self-refresh state
US11282563B2 (en) 2016-07-28 2022-03-22 Micron Technology, Inc. Apparatuses and methods for operations in a self-refresh state
US9990181B2 (en) 2016-08-03 2018-06-05 Micron Technology, Inc. Apparatuses and methods for random number generation
US10387121B2 (en) 2016-08-03 2019-08-20 Micron Technology, Inc. Apparatuses and methods for random number generation
US10152304B2 (en) 2016-08-03 2018-12-11 Micron Technology, Inc. Apparatuses and methods for random number generation
US11029951B2 (en) 2016-08-15 2021-06-08 Micron Technology, Inc. Smallest or largest value element determination
US11526355B2 (en) 2016-08-15 2022-12-13 Micron Technology, Inc. Smallest or largest value element determination
US11061671B2 (en) 2016-08-24 2021-07-13 Micron Technology, Inc. Apparatus and methods related to microcode instructions indicating instruction types
US10606587B2 (en) 2016-08-24 2020-03-31 Micron Technology, Inc. Apparatus and methods related to microcode instructions indicating instruction types
US11842191B2 (en) 2016-08-24 2023-12-12 Micron Technology, Inc. Apparatus and methods related to microcode instructions indicating instruction types
US11055026B2 (en) 2016-09-15 2021-07-06 Micron Technology, Inc. Updating a register in memory
US11625194B2 (en) 2016-09-15 2023-04-11 Micron Technology, Inc. Updating a register in memory
US10466928B2 (en) 2016-09-15 2019-11-05 Micron Technology, Inc. Updating a register in memory
US10725680B2 (en) 2016-09-29 2020-07-28 Micron Technology, Inc. Apparatuses and methods to change data category values
US10976943B2 (en) 2016-09-29 2021-04-13 Micron Technology, Inc. Apparatuses and methods to change data category values
US10387058B2 (en) 2016-09-29 2019-08-20 Micron Technology, Inc. Apparatuses and methods to change data category values
US11422720B2 (en) 2016-09-29 2022-08-23 Micron Technology, Inc. Apparatuses and methods to change data category values
US10235207B2 (en) 2016-09-30 2019-03-19 Nimbix, Inc. Method and system for preemptible coprocessing
US10242721B2 (en) 2016-10-06 2019-03-26 Micron Technology, Inc. Shifting data in sensing circuitry
US10014034B2 (en) 2016-10-06 2018-07-03 Micron Technology, Inc. Shifting data in sensing circuitry
US10971214B2 (en) 2016-10-13 2021-04-06 Micron Technology, Inc. Apparatuses and methods to perform logical operations using sensing circuitry
US10529409B2 (en) 2016-10-13 2020-01-07 Micron Technology, Inc. Apparatuses and methods to perform logical operations using sensing circuitry
US10600473B2 (en) 2016-10-13 2020-03-24 Micron Technology, Inc. Apparatuses and methods to perform logical operations using sensing circuitry
US9805772B1 (en) 2016-10-20 2017-10-31 Micron Technology, Inc. Apparatuses and methods to selectively perform logical operations
US10388333B2 (en) 2016-10-20 2019-08-20 Micron Technology, Inc. Apparatuses and methods to selectively perform logical operations
US10854247B2 (en) 2016-10-20 2020-12-01 Micron Technology, Inc. Apparatuses and methods to selectively perform logical operations
US11238914B2 (en) 2016-11-08 2022-02-01 Micron Technology, Inc. Apparatuses and methods for compute components formed over an array of memory cells
US10373666B2 (en) 2016-11-08 2019-08-06 Micron Technology, Inc. Apparatuses and methods for compute components formed over an array of memory cells
US10854269B2 (en) 2016-11-08 2020-12-01 Micron Technology, Inc. Apparatuses and methods for compute components formed over an array of memory cells
US11048428B2 (en) 2016-11-11 2021-06-29 Micron Technology, Inc. Apparatuses and methods for memory alignment
US10423353B2 (en) 2016-11-11 2019-09-24 Micron Technology, Inc. Apparatuses and methods for memory alignment
US11693576B2 (en) 2016-11-11 2023-07-04 Micron Technology, Inc. Apparatuses and methods for memory alignment
US9940990B1 (en) 2016-11-22 2018-04-10 Micron Technology, Inc. Data shift apparatuses and methods
US9761300B1 (en) 2016-11-22 2017-09-12 Micron Technology, Inc. Data shift apparatuses and methods
US10853262B2 (en) 2016-11-29 2020-12-01 Arm Limited Memory address translation using stored key entries
US11182304B2 (en) 2017-02-21 2021-11-23 Micron Technology, Inc. Memory array page table walk
US11663137B2 (en) 2017-02-21 2023-05-30 Micron Technology, Inc. Memory array page table walk
US10402340B2 (en) 2017-02-21 2019-09-03 Micron Technology, Inc. Memory array page table walk
US11011220B2 (en) 2017-02-22 2021-05-18 Micron Technology, Inc. Apparatuses and methods for compute in data path
US10915249B2 (en) 2017-02-22 2021-02-09 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10403352B2 (en) 2017-02-22 2019-09-03 Micron Technology, Inc. Apparatuses and methods for compute in data path
US10540097B2 (en) 2017-02-22 2020-01-21 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US11682449B2 (en) 2017-02-22 2023-06-20 Micron Technology, Inc. Apparatuses and methods for compute in data path
US10268389B2 (en) 2017-02-22 2019-04-23 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US11474965B2 (en) 2017-03-21 2022-10-18 Micron Technology, Inc. Apparatuses and methods for in-memory data switching networks
US10838899B2 (en) 2017-03-21 2020-11-17 Micron Technology, Inc. Apparatuses and methods for in-memory data switching networks
US11048652B2 (en) 2017-03-22 2021-06-29 Micron Technology, Inc. Apparatus and methods for in data path compute operations
US10185674B2 (en) 2017-03-22 2019-01-22 Micron Technology, Inc. Apparatus and methods for in data path compute operations
US10817442B2 (en) 2017-03-22 2020-10-27 Micron Technology, Inc. Apparatus and methods for in data path compute operations
US11222260B2 (en) 2017-03-22 2022-01-11 Micron Technology, Inc. Apparatuses and methods for operating neural networks
US10452578B2 (en) 2017-03-22 2019-10-22 Micron Technology, Inc. Apparatus and methods for in data path compute operations
US11769053B2 (en) 2017-03-22 2023-09-26 Micron Technology, Inc. Apparatuses and methods for operating neural networks
US11550742B2 (en) 2017-03-22 2023-01-10 Micron Technology, Inc. Apparatus and methods for in data path compute operations
US10446221B2 (en) 2017-03-27 2019-10-15 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US11410717B2 (en) 2017-03-27 2022-08-09 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10878885B2 (en) 2017-03-27 2020-12-29 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10049721B1 (en) 2017-03-27 2018-08-14 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10147467B2 (en) 2017-04-17 2018-12-04 Micron Technology, Inc. Element value comparison in memory
US10043570B1 (en) 2017-04-17 2018-08-07 Micron Technology, Inc. Signed element compare in memory
US10622034B2 (en) 2017-04-17 2020-04-14 Micron Technology, Inc. Element value comparison in memory
US10304502B2 (en) 2017-04-24 2019-05-28 Micron Technology, Inc. Accessing data in memory
US10147468B2 (en) 2017-04-24 2018-12-04 Micron Technology, Inc. Accessing data in memory
US9997212B1 (en) 2017-04-24 2018-06-12 Micron Technology, Inc. Accessing data in memory
US10942843B2 (en) 2017-04-25 2021-03-09 Micron Technology, Inc. Storing data elements of different lengths in respective adjacent rows or columns according to memory shapes
US11494296B2 (en) 2017-04-25 2022-11-08 Micron Technology, Inc. Memory shapes
US10796736B2 (en) 2017-05-15 2020-10-06 Micron Technology, Inc. Bank to bank data transfer
US10236038B2 (en) 2017-05-15 2019-03-19 Micron Technology, Inc. Bank to bank data transfer
US11514957B2 (en) 2017-05-15 2022-11-29 Micron Technology, Inc. Bank to bank data transfer
US10068664B1 (en) 2017-05-19 2018-09-04 Micron Technology, Inc. Column repair in memory
US10418123B2 (en) 2017-05-19 2019-09-17 Micron Technology, Inc. Column repair in memory
US10496310B2 (en) 2017-06-01 2019-12-03 Micron Technology, Inc. Shift skip
US10013197B1 (en) 2017-06-01 2018-07-03 Micron Technology, Inc. Shift skip
US11526293B2 (en) 2017-06-07 2022-12-13 Micron Technology, Inc. Data replication
US10152271B1 (en) 2017-06-07 2018-12-11 Micron Technology, Inc. Data replication
US10878856B2 (en) 2017-06-07 2020-12-29 Micron Technology, Inc. Data transfer between subarrays in memory
US10510381B2 (en) 2017-06-07 2019-12-17 Micron Technology, Inc. Data transfer between subarrays in memory
US10262701B2 (en) 2017-06-07 2019-04-16 Micron Technology, Inc. Data transfer between subarrays in memory
US10776037B2 (en) 2017-06-07 2020-09-15 Micron Technology, Inc. Data replication
US11137934B2 (en) 2017-06-16 2021-10-05 Oneplus Technology (Shenzhen) Co., Ltd. Memory block type processing method applicable to electronic device electronic device and non-transitory computer readable storage medium
CN107247674A (en) * 2017-06-16 2017-10-13 深圳市万普拉斯科技有限公司 Memory block type processing approach, device, electronic equipment and readable storage medium storing program for executing
US10318168B2 (en) 2017-06-19 2019-06-11 Micron Technology, Inc. Apparatuses and methods for simultaneous in data path compute operations
US11372550B2 (en) 2017-06-19 2022-06-28 Micron Technology, Inc. Apparatuses and methods for simultaneous in data path compute operations
US11693561B2 (en) 2017-06-19 2023-07-04 Micron Technology, Inc. Apparatuses and methods for simultaneous in data path compute operations
US10795582B2 (en) 2017-06-19 2020-10-06 Micron Technology, Inc. Apparatuses and methods for simultaneous in data path compute operations
US10712389B2 (en) 2017-08-09 2020-07-14 Micron Technology, Inc. Scan chain operations
US10162005B1 (en) 2017-08-09 2018-12-25 Micron Technology, Inc. Scan chain operations
US10534553B2 (en) 2017-08-30 2020-01-14 Micron Technology, Inc. Memory array accessibility
US11886715B2 (en) 2017-08-30 2024-01-30 Lodestar Licensing Group Llc Memory array accessibility
US11182085B2 (en) 2017-08-30 2021-11-23 Micron Technology, Inc. Memory array accessibility
US10346092B2 (en) 2017-08-31 2019-07-09 Micron Technology, Inc. Apparatuses and methods for in-memory operations using timing circuitry
US10741239B2 (en) 2017-08-31 2020-08-11 Micron Technology, Inc. Processing in memory device including a row address strobe manager
US10628085B2 (en) 2017-08-31 2020-04-21 Micron Technology, Inc. Processing in memory
US11016706B2 (en) 2017-08-31 2021-05-25 Micron Technology, Inc. Apparatuses for in-memory operations
US11894045B2 (en) 2017-08-31 2024-02-06 Lodestar Licensing Group, Llc Processing in memory implementing VLIW controller
US11586389B2 (en) 2017-08-31 2023-02-21 Micron Technology, Inc. Processing in memory
US11675538B2 (en) 2017-08-31 2023-06-13 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US11163495B2 (en) 2017-08-31 2021-11-02 Micron Technology, Inc. Processing in memory
US10416927B2 (en) 2017-08-31 2019-09-17 Micron Technology, Inc. Processing in memory
US11276457B2 (en) 2017-08-31 2022-03-15 Micron Technology, Inc. Processing in memory
US11288214B2 (en) 2017-10-24 2022-03-29 Micron Technology, Inc. Command selection policy
US10409739B2 (en) 2017-10-24 2019-09-10 Micron Technology, Inc. Command selection policy
US10831682B2 (en) 2017-10-24 2020-11-10 Micron Technology, Inc. Command selection policy
US10866904B2 (en) 2017-11-22 2020-12-15 Arm Limited Data storage for multiple data types
US20190155747A1 (en) * 2017-11-22 2019-05-23 Arm Limited Performing maintenance operations
US10929308B2 (en) * 2017-11-22 2021-02-23 Arm Limited Performing maintenance operations
US10831673B2 (en) 2017-11-22 2020-11-10 Arm Limited Memory address translation
US10522210B2 (en) 2017-12-14 2019-12-31 Micron Technology, Inc. Apparatuses and methods for subarray addressing
US10867662B2 (en) 2017-12-14 2020-12-15 Micron Technology, Inc. Apparatuses and methods for subarray addressing
US10741241B2 (en) 2017-12-14 2020-08-11 Micron Technology, Inc. Apparatuses and methods for subarray addressing in a memory device
US10332586B1 (en) 2017-12-19 2019-06-25 Micron Technology, Inc. Apparatuses and methods for subrow addressing
US10438653B2 (en) 2017-12-19 2019-10-08 Micron Technology, Inc. Apparatuses and methods for subrow addressing
US10839890B2 (en) 2017-12-19 2020-11-17 Micron Technology, Inc. Apparatuses and methods for subrow addressing
US11404109B2 (en) 2018-01-30 2022-08-02 Micron Technology, Inc. Logical operations using memory cells
US10614875B2 (en) 2018-01-30 2020-04-07 Micron Technology, Inc. Logical operations using memory cells
US10725736B2 (en) 2018-01-31 2020-07-28 Micron Technology, Inc. Determination of a match between data values stored by several arrays
US10437557B2 (en) 2018-01-31 2019-10-08 Micron Technology, Inc. Determination of a match between data values stored by several arrays
US10908876B2 (en) 2018-01-31 2021-02-02 Micron Technology, Inc. Determination of a match between data values stored by several arrays
US11194477B2 (en) 2018-01-31 2021-12-07 Micron Technology, Inc. Determination of a match between data values stored by three or more arrays
US10725696B2 (en) 2018-04-12 2020-07-28 Micron Technology, Inc. Command selection policy with read priority
US10877694B2 (en) 2018-04-12 2020-12-29 Micron Technology, Inc. Command selection policy with read priority
US11593027B2 (en) 2018-04-12 2023-02-28 Micron Technology, Inc. Command selection policy with read priority
US10897605B2 (en) 2018-06-07 2021-01-19 Micron Technology, Inc. Image processor formed in an array of memory cells
US11445157B2 (en) 2018-06-07 2022-09-13 Micron Technology, Inc. Image processor formed in an array of memory cells
US10440341B1 (en) 2018-06-07 2019-10-08 Micron Technology, Inc. Image processor formed in an array of memory cells
US11875173B2 (en) 2018-06-25 2024-01-16 Amazon Technologies, Inc. Execution of auxiliary functions in an on-demand network code execution system
US11836516B2 (en) 2018-07-25 2023-12-05 Amazon Technologies, Inc. Reducing execution times in an on-demand network code execution system using saved machine states
US10956071B2 (en) * 2018-10-01 2021-03-23 Western Digital Technologies, Inc. Container key value store for data storage devices
US11397688B2 (en) 2018-10-10 2022-07-26 Micron Technology, Inc. Coherent memory access
US11620228B2 (en) 2018-10-10 2023-04-04 Micron Technology, Inc. Coherent memory access
US11175915B2 (en) 2018-10-10 2021-11-16 Micron Technology, Inc. Vector registers implemented in memory
US11556339B2 (en) 2018-10-10 2023-01-17 Micron Technology, Inc. Vector registers implemented in memory
US10581434B1 (en) 2018-10-16 2020-03-03 Micron Technology, Inc. Memory device processing
US10483978B1 (en) 2018-10-16 2019-11-19 Micron Technology, Inc. Memory device processing
US11050425B2 (en) 2018-10-16 2021-06-29 Micron Technology, Inc. Memory device processing
US11728813B2 (en) 2018-10-16 2023-08-15 Micron Technology, Inc. Memory device processing
US11943093B1 (en) 2018-11-20 2024-03-26 Amazon Technologies, Inc. Network connection recovery after virtual machine transition in an on-demand network code execution system
US11184446B2 (en) 2018-12-05 2021-11-23 Micron Technology, Inc. Methods and apparatus for incentivizing participation in fog networks
US11861386B1 (en) 2019-03-22 2024-01-02 Amazon Technologies, Inc. Application gateways in an on-demand network code execution system
US11714675B2 (en) 2019-06-20 2023-08-01 Amazon Technologies, Inc. Virtualization-based transaction handling in an on-demand network code execution system
US11398264B2 (en) 2019-07-08 2022-07-26 Micron Technology, Inc. Methods and apparatus for dynamically adjusting performance of partitioned memory
US11709673B2 (en) 2019-08-14 2023-07-25 Micron Technology, Inc. Bit string operations in memory
US11360768B2 (en) 2019-08-14 2022-06-14 Micron Technolgy, Inc. Bit string operations in memory
US11714640B2 (en) 2019-08-14 2023-08-01 Micron Technology, Inc. Bit string operations in memory
CN111181760A (en) * 2019-09-02 2020-05-19 腾讯科技(深圳)有限公司 Network fault detection method and device, computer readable medium and electronic equipment
US11016905B1 (en) 2019-11-13 2021-05-25 Western Digital Technologies, Inc. Storage class memory access
US11928177B2 (en) 2019-11-20 2024-03-12 Micron Technology, Inc. Methods and apparatus for performing video processing matrix operations within a memory array
US11449577B2 (en) 2019-11-20 2022-09-20 Micron Technology, Inc. Methods and apparatus for performing video processing matrix operations within a memory array
US11853385B2 (en) 2019-12-05 2023-12-26 Micron Technology, Inc. Methods and apparatus for performing diversity matrix operations within a memory array
US11714682B1 (en) 2020-03-03 2023-08-01 Amazon Technologies, Inc. Reclaiming computing resources in an on-demand code execution system
US11249921B2 (en) 2020-05-06 2022-02-15 Western Digital Technologies, Inc. Page modification encoding and caching
US11263146B2 (en) * 2020-06-05 2022-03-01 Vmware, Inc. Efficient accessing methods for bypassing second layer mapping of data blocks in file systems of distributed data systems
US11334497B2 (en) * 2020-06-05 2022-05-17 Vmware, Inc. Efficient segment cleaning employing local copying of data blocks in log-structured file systems of distributed data systems
US11262919B2 (en) * 2020-06-05 2022-03-01 Vmware, Inc. Efficient segment cleaning employing remapping of data blocks in log-structured file systems of distributed data systems
US11507544B2 (en) 2020-06-05 2022-11-22 Vmware, Inc. Efficient erasure-coded storage in distributed data systems
US11727964B2 (en) 2020-07-21 2023-08-15 Micron Technology, Inc. Arithmetic operations in memory
US11227641B1 (en) 2020-07-21 2022-01-18 Micron Technology, Inc. Arithmetic operations in memory
US11593270B1 (en) 2020-11-25 2023-02-28 Amazon Technologies, Inc. Fast distributed caching using erasure coded object parts
US11550713B1 (en) 2020-11-25 2023-01-10 Amazon Technologies, Inc. Garbage collection in distributed systems using life cycled storage roots
US11392497B1 (en) * 2020-11-25 2022-07-19 Amazon Technologies, Inc. Low latency access to data sets using shared data set portions
US11968280B1 (en) 2021-11-24 2024-04-23 Amazon Technologies, Inc. Controlling ingestion of streaming data to serverless function executions
US11967361B2 (en) 2022-01-31 2024-04-23 Micron Technology, Inc. Comparison operations in memory

Also Published As

Publication number Publication date
US20090150605A1 (en) 2009-06-11
JP5431453B2 (en) 2014-03-05
KR20110039418A (en) 2011-04-18
EP2271978A1 (en) 2011-01-12
WO2009126581A1 (en) 2009-10-15
US8151082B2 (en) 2012-04-03
EP2271978B1 (en) 2015-10-21
JP2011517820A (en) 2011-06-16
CN102084332A (en) 2011-06-01
KR101628675B1 (en) 2016-06-09
KR101804034B1 (en) 2017-12-01
CN102084332B (en) 2015-01-07
KR20160007669A (en) 2016-01-20

Similar Documents

Publication Publication Date Title
US11640359B2 (en) Systems and methods for identifying storage resources that are not in use
US20130205114A1 (en) Object-based memory storage
US9483404B2 (en) Write admittance policy for a memory cache
US20190073296A1 (en) Systems and Methods for Persistent Address Space Management
US10013354B2 (en) Apparatus, system, and method for atomic storage operations
US8898376B2 (en) Apparatus, system, and method for grouping data stored on an array of solid-state storage elements
US9176810B2 (en) Bit error reduction through varied data positioning
US8725934B2 (en) Methods and appratuses for atomic storage operations
US8074011B2 (en) Apparatus, system, and method for storage space recovery after reaching a read count limit
US9645758B2 (en) Apparatus, system, and method for indexing data of an append-only, log-based structure
EP2802991B1 (en) Systems and methods for managing cache admission

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUSION-IO, INC., UTAH

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BADAM, ANIRUDH;NELLANS, DAVID;WIPFEL, ROBERT;SIGNING DATES FROM 20130418 TO 20130806;REEL/FRAME:030968/0484

AS Assignment

Owner name: FUSION-IO, LLC, DELAWARE

Free format text: CHANGE OF NAME;ASSIGNOR:FUSION-IO, INC;REEL/FRAME:034838/0091

Effective date: 20141217

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: SANDISK TECHNOLOGIES, INC., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUSION-IO, LLC;REEL/FRAME:035168/0366

Effective date: 20150219

AS Assignment

Owner name: SANDISK TECHNOLOGIES, INC., TEXAS

Free format text: CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO'S 13/925,410 AND 61/663,464 PREVIOUSLY RECORDED AT REEL: 035168 FRAME: 0366. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:FUSION-IO, LLC;REEL/FRAME:035603/0582

Effective date: 20150219

Owner name: FUSION-IO, LLC, DELAWARE

Free format text: CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO'S 13/925,410 AND 61/663,464 PREVIOUSLY RECORDED AT REEL: 034838 FRAME: 0091. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:FUSION-IO, INC;REEL/FRAME:035603/0748

Effective date: 20141217

AS Assignment

Owner name: SANDISK TECHNOLOGIES, INC., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LONGITUDE ENTERPRISE FLASH SARL;REEL/FRAME:038324/0628

Effective date: 20160318

AS Assignment

Owner name: SANDISK TECHNOLOGIES LLC, TEXAS

Free format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038809/0672

Effective date: 20160516