US20130189839A1 - Method to form silicide contact in trenches - Google Patents
Method to form silicide contact in trenches Download PDFInfo
- Publication number
- US20130189839A1 US20130189839A1 US13/614,812 US201213614812A US2013189839A1 US 20130189839 A1 US20130189839 A1 US 20130189839A1 US 201213614812 A US201213614812 A US 201213614812A US 2013189839 A1 US2013189839 A1 US 2013189839A1
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- Prior art keywords
- layer
- semiconductor layer
- forming
- contact
- metallic
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- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 29
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- 239000004065 semiconductor Substances 0.000 claims abstract description 83
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- 238000005229 chemical vapour deposition Methods 0.000 description 7
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 229910052769 Ytterbium Inorganic materials 0.000 description 3
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- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
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- 238000005530 etching Methods 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
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- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
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- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention generally relates to the field of semiconductors, and more particularly relates to forming silicide contacts for a semiconductor device.
- Silicide contacts are of specific importance to integrated circuits, including those having complementary metal oxide semiconductor (CMOS) devices, because of the need to reduce the electrical resistance of the contacts (particularly at the source/drain and gate regions) in order to increase chip performance.
- Silicides are metal compounds that are thermally stable and provide for low electrical resistivity at the silicon/metal interface. Reducing contact resistance improves device speed, therefore increasing device performance.
- a method for forming silicide contacts comprises forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer.
- the semiconductor layer comprises source/drain regions.
- Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions.
- a second semiconductor layer is deposited/formed within the contact trenches.
- a metallic layer is deposited/formed on the second semiconductor layer for formation of a silicide layer/region.
- a conductive contact layer is formed/formed on the metallic or silicide layer/region to fill the contact trenches.
- FIG. 1 is a cross-sectional view of a semiconductor structure after a dielectric layer has been formed on a semiconductor substrate according to one embodiment of the present invention
- FIG. 2 is a cross-sectional view of the semiconductor structure after contact regions have been formed in the dielectric layer according to one embodiment of the present invention
- FIG. 3 is a cross-sectional view of the semiconductor structure after a semiconductor layer and a metallic layer have been formed in the contact regions according to one embodiment of the present invention
- FIG. 4 is a cross-sectional view of the semiconductor structure after a conductive contact layer and conductive fill material layer and a metallic layer have been formed in the contact regions according to one embodiment of the present invention
- FIG. 5 is a cross-sectional view of the semiconductor structure after a planarization process has been performed on the structure shown in FIG. 4 according to one embodiment of the present invention
- FIG. 6 is an operational flow diagram illustrating one process for forming silicide contacts according to one embodiment of the present invention.
- the terms “a” or “an”, as used herein, are defined as one as or more than one.
- the term plurality, as used herein, is defined as two as or more than two. Plural and singular terms are the same unless expressly stated otherwise.
- the term another, as used herein, is defined as at least a second or more.
- the terms including and/or having, as used herein, are defined as comprising (i.e., open language).
- the term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
- program, software application, and the like as used herein are defined as a sequence of instructions designed for execution on a computer system.
- a program, computer program, or software application may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.
- silicide contacts are of specific importance to integrated circuits.
- most conventional processes for forming silicide contacts experience a certain amount of consumption of the substrate during silicide formation.
- nickel and its alloys are commonly used for silicides, where nickel to silicon consumption ratio is, for example, approximately 1.8. Such consumption can be a serious issue when the substrate material is limited.
- SOI silicon-on-insulator
- Another drawback of conventional processes is that selectively etching excessive silicide can be challenging for various metals. Therefore, one or more embodiments of the present invention forms contact regions that comprises a semiconductor layer formed within the contact regions. This semiconductor layer is formed on source/drain regions within the underlying semiconductor layer (active region).
- a metallic layer is formed on the second semiconductor layer.
- a conductive contact layer is formed on the metallic or silicide layer.
- FIGS. 1-5 illustrate an example of a process for forming silicide contacts for a semiconductor device according to one embodiment of the present invention. It should be noted that the following process discussed below is applicable to both nFET and pFET devices. It should also be noted that one or more embodiments of the present invention are applicable to both bulk substrate devices and SOI devices.
- a handle substrate 102 there is provided a handle substrate 102 , a buried insulator layer (e.g., buried oxide (BOX)) 104 , and a top semiconductor layer 106 .
- the handle substrate 102 can be a semiconductor substrate comprising a single crystalline semiconductor material such as single crystalline silicon, a polycrystalline semiconductor material, an amorphous semiconductor material, or a stack thereof.
- the thickness of the handle substrate 102 can be, for example, from 50 microns to 1,000 microns, although lesser and greater thicknesses can also be employed.
- a buried insulator layer 104 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
- the thickness of the buried insulator layer 104 can be, for example, form 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.
- the thickness of the top semiconductor layer 106 can be, for example, from 3 nm to 80 nm, and typically from 5 nm to 10 nm, although lesser and greater thicknesses can also be employed.
- the top semiconductor layer 106 can comprise any semiconducting material, including but not limited to Si (silicon), strained Si, SiC (silicon carbide), Ge (geranium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), GaSb (gallium antimonide), or any combination thereof, as well as other III/V or II/VI compound semiconductors and alloys thereof.
- FIG. 1 shows that the top semiconductor layer 106 includes various single crystalline semiconductor portions, which can comprise, for example, a body/channel region 108 , a source extension region 110 , a drain extension region 112 , a planar source region 114 , and a planar drain region 116 .
- Shallow trench isolation structures 118 can be formed in the top semiconductor layer 106 employing conventional fabrication methods.
- the shallow trench isolation structures 118 can be formed by trenches extending from the top surface of the top semiconductor layer 106 at least to the top surface of the buried insulator layer 104 , filling the trenches with a dielectric material, and removing excess dielectric material from above the top surface of the top semiconductor layer 106 .
- the various single crystalline semiconductor portions ( 108 , 110 , 112 , 114 , 116 ) in the top semiconductor layer 106 can be formed by introducing electrical dopants such as B, Ga, In, P, As, and/or Sb by ion implantation, plasma doping, and/or gas phase doping employing various masking structures as known in the art.
- electrical dopants such as B, Ga, In, P, As, and/or Sb
- a gate stack structure 120 and gate spacer 122 are formed before implanting electrical dopants into various portions of the top semiconductor layer 106 .
- the gate stack 120 is formed on the semiconductor layer 106 over the body region 108 .
- the gate stack 120 comprises a gate dielectric 124 and a gate conductor 126 .
- a gate polysilicon cap 128 is deposited on the gate conductor layer 126 , such as through LPCVD or silicon sputtering. It should be noted that instead of first forming the gate stack 120 , a replacement (dummy) gate structure can be formed to act as a place holder for the gate stack, which is formed during a subsequent processing step.
- the gate stack 120 can be formed by depositing a stack of a gate dielectric material and a gate conductor material on the top semiconductor layer 106 . This stack is then patterned and etched to form the gate dielectric 124 and the overlying gate conductor 126 on a portion of the top semiconductor layer 106 .
- the gate dielectric 124 of this embodiment is a conventional dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof) that is formed by thermal conversion of a top portion of the active region and/or by chemical vapor deposition (CVD).
- the gate dielectric 124 is a high-k dielectric material (such as hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, titanium dioxide, strontium titanate, lanthanum aluminate, yttrium oxide, an alloy thereof, or a silicate thereof) that is formed by CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), or physical vapor deposition (PVD).
- the gate dielectric may comprise any suitable combination of those dielectric materials.
- the gate conductor 126 is a semiconductor (e.g., polysilicon) gate layer and/or a metal gate layer.
- the gate dielectric 124 can be a conventional dielectric material and the gate conductor 126 can be a semiconductor gate layer.
- the gate dielectric 124 can be a high-k dielectric material and the gate conductor 126 can be a metal gate layer of a conductive refractory metal nitride (such as tantalum nitride, titanium nitride, tungsten nitride, titanium aluminum nitride, triazacyclononane, or an alloy thereof).
- the gate conductor 126 comprises a stack of a metal gate layer and a semiconductor gate layer.
- the gate stack 120 can also include a work function metallic layer as well.
- the gate stack 120 can be formed atop an optional chemical oxide layer (not shown) (also referred to herein as an “interfacial layer”), which is formed on an exposed semiconductor surface of the body portion 108 of the top semiconductor layer 106 .
- the gate spacer 122 comprises a dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride or any combination of these).
- the gate spacer 122 is formed on gate stack 120 and on a portion of the top semiconductor layer 106 .
- a reactive-ion etch process is used to remove the dielectric material on horizontal surfaces such as the top of the gate stack 120 , the STI regions 118 , and portions of the top semiconductor layer 106 to form a gate spacer only on the sidewall of the gate structure 106 .
- the gate spacer material can be etched such that the gate spacer 122 also resides on top of the gate structure 106 as well.
- a dielectric layer 130 (e.g., an oxide layer, nitride layer, low-k material or any suitable combination of those materials) is then formed over the entire structure, as shown in FIG. 1 .
- portions of the dielectric layer 130 over the source/drain regions 114 , 116 are removed (e.g., through a dry etch such as RIE and/or a wet etch using HF) so as to create contact regions such as trenches/openings 232 and 234 exposing a portion of the source/drain regions 114 , 116 , as shown in FIG. 2 .
- a semiconductor material is deposited and a contact trench semiconductor layer 336 is formed on the exposed portion of the source/drain regions 114 , 116 , inner sidewalls of the contact trenches 232 , 234 , and a top surface of the dielectric layer 130 , as shown in FIG. 3 .
- the contact trench semiconductor layer 336 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.
- the contact trench semiconductor layer 336 comprises any semiconducting material, including but not limited to Si, strained Si, SiC, Ge, SiGe, SiGeC, Si alloys, Ge alloys, GaAs, InAs, InP, GaSb, or any combination thereof, as well as other III/V or II/VI compound semiconductors and alloys thereof.
- the contact trench semiconductor layer 336 can be formed with a thickness ranging from, for example, 1-10 nm.
- a metal/metallic material is deposited and a contact trench metallic layer 338 is formed on the contact trench semiconductor layer 336 .
- the contact trench metallic layer 338 is formed on the inner sidewalls of the contact trench semiconductor layer 336 , a bottom (horizontal) portion of the contact trench semiconductor layer 336 (which is formed on the source/drain regions 114 , 116 ), and a top surface of the contact trench semiconductor layer 336 , as shown in FIG. 3 .
- the contact trench metallic layer 338 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.
- the contact trench metallic layer 338 comprises a metallic material, including but not limited to nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), rare earth metals (e.g., Erbium (Er), Ytterbium (Yt), etc.), silicides (or germanides) of these materials, or an alloy or any combination thereof.
- the contact trench metallic layer 338 can be formed with a thickness ranging from, for example, 1-10 nm. It should be noted that, in one embodiment, the thickness of the metallic layer 338 can be adjusted such that the semiconductor layer 336 is consumed during the silicide reaction process provided subsequent thermal treatment.
- an optional thin layer of impurities (e.g., Sulfur (S), Selenium (Se), etc.), dopants (e.g., Boron (B), Arsenic (As), Phosphorous (P), Antimony (Sb), Gallium (Ga), Aluminum (Al), etc.), band edge materials (e.g., Pt, Er, Yb, Al, etc.) can be formed on the source/drain region 114 , 116 of the top semiconductor layer 106 prior to forming the contact trench semiconductor layer 336 .
- This optional thin layer modifies the Schottky barrier height (SBH) of the contact trench semiconductor layer 336 for reducing contact resistance.
- SBH Schottky barrier height
- an optional conductive contact liner 440 (e.g., a titanium nitride liner, tantalum nitride liner, etc.) is formed on the contact trench metallic layer 338 .
- the optional conductive contact liner 440 is formed on the inner sidewalls of the contact trench metallic layer 338 , a bottom (horizontal) portion of the contact trench metallic layer 338 (which is formed on the bottom portion of the contact trench semiconductor layer 336 ), and a top surface of the contact trench metallic layer 338 , as shown in FIG. 4 .
- a conductive fill material layer 442 (e.g., a metal, such as tungsten, copper, aluminum, or any other conventional contact material) is deposited in the remaining portion of the contact trenches 232 , 234 until the contact trenches 232 , 234 are filled, as shown in FIG. 4 .
- the conductive fill material layer 442 is formed on the inner sidewalls of the conductive contact liner 440 , a bottom (horizontal) portion of the conductive contact liner 440 (which is formed on the bottom portion of the contact trench metallic layer 338 ), and a top surface of the conductive contact liner 440 , as shown in FIG. 4 .
- silicide germanide
- This anneal can also be performed after the contact trench metallic layer 338 has been formed and prior to forming the conductive contact liner 440 .
- optional impurities e.g., Sulfur (S), Selenium (Se), etc.
- dopants e.g., Boron (B), Arsenic (As), Phosphorous (P), Antimony (Sb), Gallium (Ga), Aluminum (Al), etc.
- band edge materials e.g., Pt, Er, Yb, Al, etc.
- the impurities can be thermally diffused to the silicide (germanide) substrate interface to reduce contact resistance.
- the contact trench semiconductor layer 336 , contact trench metallic layer 338 , conductive contact liner 440 , and conductive fill material layer 442 are then planarized utilizing any conventional process such as, but not limited to, chemical mechanical polishing (CMP) or RIE, where the dielectric layer 130 is used as a stop layer.
- CMP chemical mechanical polishing
- RIE etching
- FIG. 6 is an operational flow diagram illustrating one process for forming silicide contacts according to one embodiment of the present invention.
- the operational flow diagram begins at step 602 and flows directly to step 604 . It should be noted that each of the steps shown in FIG. 6 has been discussed in greater detail above with respect to FIGS. 1-5 .
- a dielectric layer 130 is formed over a top semiconductor layer 106 , the gate spacer 122 , and the gate structure 120 .
- Contact trenches 232 , 234 , at step 606 are formed in the dielectric layer 130 so as to expose at least a portion of the source/drain regions 114 , 116 .
- a contact trench semiconductor layer 336 is formed within the contact trenches 232 , 234 .
- a contact trench metallic layer 338 is formed on the contact trench semiconductor layer 336 .
- An optional conductive contact liner 440 is formed on the contact trench metallic layer 338 .
- a conductive fill material layer 442 is formed in the remaining portion of the contact trenches 232 , 234 .
- Conventional fabrication processes are performed to complete the device. The control flow then exits at step 618 .
- the circuit as described above is part of the design for an integrated circuit chip.
- the chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly.
- the stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer.
- the photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare chip, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product or electronic device that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard, or other input device, and a central processor.
Abstract
Description
- This application is continuation of and claims priority from U.S. patent application Ser. No. 13/356,090 filed on Jan. 23, 2012, now ______, the disclosure of which is hereby incorporated by reference in its entirety.
- The present invention generally relates to the field of semiconductors, and more particularly relates to forming silicide contacts for a semiconductor device.
- Silicide contacts are of specific importance to integrated circuits, including those having complementary metal oxide semiconductor (CMOS) devices, because of the need to reduce the electrical resistance of the contacts (particularly at the source/drain and gate regions) in order to increase chip performance. Silicides are metal compounds that are thermally stable and provide for low electrical resistivity at the silicon/metal interface. Reducing contact resistance improves device speed, therefore increasing device performance.
- In one embodiment, a method for forming silicide contacts is disclosed. The method comprises forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is deposited/formed within the contact trenches. A metallic layer is deposited/formed on the second semiconductor layer for formation of a silicide layer/region. A conductive contact layer is formed/formed on the metallic or silicide layer/region to fill the contact trenches. These layers outside the contact trenches are mechanically removed.
- The accompanying figures where like reference numerals refer to identical or functionally similar elements throughout the separate views, and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention, in which:
-
FIG. 1 is a cross-sectional view of a semiconductor structure after a dielectric layer has been formed on a semiconductor substrate according to one embodiment of the present invention; -
FIG. 2 is a cross-sectional view of the semiconductor structure after contact regions have been formed in the dielectric layer according to one embodiment of the present invention; -
FIG. 3 is a cross-sectional view of the semiconductor structure after a semiconductor layer and a metallic layer have been formed in the contact regions according to one embodiment of the present invention; -
FIG. 4 is a cross-sectional view of the semiconductor structure after a conductive contact layer and conductive fill material layer and a metallic layer have been formed in the contact regions according to one embodiment of the present invention; -
FIG. 5 is a cross-sectional view of the semiconductor structure after a planarization process has been performed on the structure shown inFIG. 4 according to one embodiment of the present invention; -
FIG. 6 is an operational flow diagram illustrating one process for forming silicide contacts according to one embodiment of the present invention. - As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention.
- The terms “a” or “an”, as used herein, are defined as one as or more than one. The term plurality, as used herein, is defined as two as or more than two. Plural and singular terms are the same unless expressly stated otherwise. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The terms program, software application, and the like as used herein, are defined as a sequence of instructions designed for execution on a computer system. A program, computer program, or software application may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.
- As discussed above, silicide contacts are of specific importance to integrated circuits. However, most conventional processes for forming silicide contacts experience a certain amount of consumption of the substrate during silicide formation. In conventional transistors, nickel and its alloys are commonly used for silicides, where nickel to silicon consumption ratio is, for example, approximately 1.8. Such consumption can be a serious issue when the substrate material is limited. One example is the thin silicon-on-insulator (SOI) device. Another drawback of conventional processes is that selectively etching excessive silicide can be challenging for various metals. Therefore, one or more embodiments of the present invention forms contact regions that comprises a semiconductor layer formed within the contact regions. This semiconductor layer is formed on source/drain regions within the underlying semiconductor layer (active region). A metallic layer is formed on the second semiconductor layer. A conductive contact layer is formed on the metallic or silicide layer. By forming a semiconductor layer on the source/drain regions silicon from the underlying semiconductor layer is not consumed when silicide/germanide regions are formed. Another advantage is that band edge silicide/germanide is obtainable. A further advantage is that the silicide/contact integration process of various embodiments allows for silicide integration using rare earth materials.
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FIGS. 1-5 illustrate an example of a process for forming silicide contacts for a semiconductor device according to one embodiment of the present invention. It should be noted that the following process discussed below is applicable to both nFET and pFET devices. It should also be noted that one or more embodiments of the present invention are applicable to both bulk substrate devices and SOI devices. As shown inFIG. 1 , there is provided ahandle substrate 102, a buried insulator layer (e.g., buried oxide (BOX)) 104, and atop semiconductor layer 106. Thehandle substrate 102 can be a semiconductor substrate comprising a single crystalline semiconductor material such as single crystalline silicon, a polycrystalline semiconductor material, an amorphous semiconductor material, or a stack thereof. The thickness of thehandle substrate 102 can be, for example, from 50 microns to 1,000 microns, although lesser and greater thicknesses can also be employed. A buriedinsulator layer 104 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. - The thickness of the buried
insulator layer 104 can be, for example, form 50 nm to 500 nm, although lesser and greater thicknesses can also be employed. The thickness of thetop semiconductor layer 106 can be, for example, from 3 nm to 80 nm, and typically from 5 nm to 10 nm, although lesser and greater thicknesses can also be employed. Thetop semiconductor layer 106 can comprise any semiconducting material, including but not limited to Si (silicon), strained Si, SiC (silicon carbide), Ge (geranium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), GaSb (gallium antimonide), or any combination thereof, as well as other III/V or II/VI compound semiconductors and alloys thereof. -
FIG. 1 shows that thetop semiconductor layer 106 includes various single crystalline semiconductor portions, which can comprise, for example, a body/channel region 108, asource extension region 110, adrain extension region 112, aplanar source region 114, and aplanar drain region 116. Shallowtrench isolation structures 118 can be formed in thetop semiconductor layer 106 employing conventional fabrication methods. For example, the shallowtrench isolation structures 118 can be formed by trenches extending from the top surface of thetop semiconductor layer 106 at least to the top surface of the buriedinsulator layer 104, filling the trenches with a dielectric material, and removing excess dielectric material from above the top surface of thetop semiconductor layer 106. - The various single crystalline semiconductor portions (108, 110, 112, 114, 116) in the
top semiconductor layer 106 can be formed by introducing electrical dopants such as B, Ga, In, P, As, and/or Sb by ion implantation, plasma doping, and/or gas phase doping employing various masking structures as known in the art. Before implanting electrical dopants into various portions of thetop semiconductor layer 106, agate stack structure 120 andgate spacer 122 are formed. Thegate stack 120 is formed on thesemiconductor layer 106 over thebody region 108. In one embodiment, thegate stack 120 comprises agate dielectric 124 and agate conductor 126. In the illustrated embodiment, agate polysilicon cap 128 is deposited on thegate conductor layer 126, such as through LPCVD or silicon sputtering. It should be noted that instead of first forming thegate stack 120, a replacement (dummy) gate structure can be formed to act as a place holder for the gate stack, which is formed during a subsequent processing step. - The
gate stack 120 can be formed by depositing a stack of a gate dielectric material and a gate conductor material on thetop semiconductor layer 106. This stack is then patterned and etched to form thegate dielectric 124 and theoverlying gate conductor 126 on a portion of thetop semiconductor layer 106. Thegate dielectric 124 of this embodiment is a conventional dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof) that is formed by thermal conversion of a top portion of the active region and/or by chemical vapor deposition (CVD). In an alternative embodiment, thegate dielectric 124 is a high-k dielectric material (such as hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, titanium dioxide, strontium titanate, lanthanum aluminate, yttrium oxide, an alloy thereof, or a silicate thereof) that is formed by CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), or physical vapor deposition (PVD). Alternatively, the gate dielectric may comprise any suitable combination of those dielectric materials. - The
gate conductor 126 is a semiconductor (e.g., polysilicon) gate layer and/or a metal gate layer. For example, thegate dielectric 124 can be a conventional dielectric material and thegate conductor 126 can be a semiconductor gate layer. Alternatively, thegate dielectric 124 can be a high-k dielectric material and thegate conductor 126 can be a metal gate layer of a conductive refractory metal nitride (such as tantalum nitride, titanium nitride, tungsten nitride, titanium aluminum nitride, triazacyclononane, or an alloy thereof). In a further embodiment, thegate conductor 126 comprises a stack of a metal gate layer and a semiconductor gate layer. Thegate stack 120 can also include a work function metallic layer as well. In yet a further embodiment, thegate stack 120 can be formed atop an optional chemical oxide layer (not shown) (also referred to herein as an “interfacial layer”), which is formed on an exposed semiconductor surface of thebody portion 108 of thetop semiconductor layer 106. - The
gate spacer 122 comprises a dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride or any combination of these). Thegate spacer 122 is formed ongate stack 120 and on a portion of thetop semiconductor layer 106. In one embodiment, a reactive-ion etch process is used to remove the dielectric material on horizontal surfaces such as the top of thegate stack 120, theSTI regions 118, and portions of thetop semiconductor layer 106 to form a gate spacer only on the sidewall of thegate structure 106. However, the gate spacer material can be etched such that thegate spacer 122 also resides on top of thegate structure 106 as well. - A dielectric layer 130 (e.g., an oxide layer, nitride layer, low-k material or any suitable combination of those materials) is then formed over the entire structure, as shown in
FIG. 1 . Next, portions of thedielectric layer 130 over the source/drain regions openings drain regions FIG. 2 . A semiconductor material is deposited and a contacttrench semiconductor layer 336 is formed on the exposed portion of the source/drain regions contact trenches dielectric layer 130, as shown inFIG. 3 . The contacttrench semiconductor layer 336 can be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The contacttrench semiconductor layer 336 comprises any semiconducting material, including but not limited to Si, strained Si, SiC, Ge, SiGe, SiGeC, Si alloys, Ge alloys, GaAs, InAs, InP, GaSb, or any combination thereof, as well as other III/V or II/VI compound semiconductors and alloys thereof. The contacttrench semiconductor layer 336 can be formed with a thickness ranging from, for example, 1-10 nm. - A metal/metallic material is deposited and a contact trench
metallic layer 338 is formed on the contacttrench semiconductor layer 336. For example, the contact trenchmetallic layer 338 is formed on the inner sidewalls of the contacttrench semiconductor layer 336, a bottom (horizontal) portion of the contact trench semiconductor layer 336 (which is formed on the source/drain regions 114, 116), and a top surface of the contacttrench semiconductor layer 336, as shown inFIG. 3 . The contact trenchmetallic layer 338 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The contact trenchmetallic layer 338 comprises a metallic material, including but not limited to nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), rare earth metals (e.g., Erbium (Er), Ytterbium (Yt), etc.), silicides (or germanides) of these materials, or an alloy or any combination thereof. The contact trenchmetallic layer 338 can be formed with a thickness ranging from, for example, 1-10 nm. It should be noted that, in one embodiment, the thickness of themetallic layer 338 can be adjusted such that thesemiconductor layer 336 is consumed during the silicide reaction process provided subsequent thermal treatment. - It should be noted that in one embodiment, an optional thin layer (interlayer) of impurities (e.g., Sulfur (S), Selenium (Se), etc.), dopants (e.g., Boron (B), Arsenic (As), Phosphorous (P), Antimony (Sb), Gallium (Ga), Aluminum (Al), etc.), band edge materials (e.g., Pt, Er, Yb, Al, etc.) can be formed on the source/
drain region top semiconductor layer 106 prior to forming the contacttrench semiconductor layer 336. This optional thin layer modifies the Schottky barrier height (SBH) of the contacttrench semiconductor layer 336 for reducing contact resistance. - After the contact trench
metallic layer 338 has been formed, an optional conductive contact liner 440 (e.g., a titanium nitride liner, tantalum nitride liner, etc.) is formed on the contact trenchmetallic layer 338. For example, the optionalconductive contact liner 440 is formed on the inner sidewalls of the contact trenchmetallic layer 338, a bottom (horizontal) portion of the contact trench metallic layer 338 (which is formed on the bottom portion of the contact trench semiconductor layer 336), and a top surface of the contact trenchmetallic layer 338, as shown inFIG. 4 . Then, a conductive fill material layer 442 (e.g., a metal, such as tungsten, copper, aluminum, or any other conventional contact material) is deposited in the remaining portion of thecontact trenches contact trenches FIG. 4 . The conductivefill material layer 442 is formed on the inner sidewalls of theconductive contact liner 440, a bottom (horizontal) portion of the conductive contact liner 440 (which is formed on the bottom portion of the contact trench metallic layer 338), and a top surface of theconductive contact liner 440, as shown inFIG. 4 . - An anneal is then optionally performed to form silicide (germanide) resulting from the reaction of the contact trench
metallic layer 338 with the contacttrench semiconductor layer 336. It should be noted that this anneal can also be performed after the contact trenchmetallic layer 338 has been formed and prior to forming theconductive contact liner 440. - It should be noted that, in one embodiment, optional impurities (e.g., Sulfur (S), Selenium (Se), etc.), dopants (e.g., Boron (B), Arsenic (As), Phosphorous (P), Antimony (Sb), Gallium (Ga), Aluminum (Al), etc.), band edge materials (e.g., Pt, Er, Yb, Al, etc.) are supplied on the
metallic layer 338 or the formed silicide (germanide), e.g. by ion implantation or other deposition methods. The impurities can be thermally diffused to the silicide (germanide) substrate interface to reduce contact resistance. - The contact
trench semiconductor layer 336, contact trenchmetallic layer 338,conductive contact liner 440, and conductivefill material layer 442 are then planarized utilizing any conventional process such as, but not limited to, chemical mechanical polishing (CMP) or RIE, where thedielectric layer 130 is used as a stop layer. The resulting structure is shown inFIG. 5 . Conventional processes are the performed to complete the fabrication process. -
FIG. 6 is an operational flow diagram illustrating one process for forming silicide contacts according to one embodiment of the present invention. InFIG. 6 , the operational flow diagram begins atstep 602 and flows directly to step 604. It should be noted that each of the steps shown inFIG. 6 has been discussed in greater detail above with respect toFIGS. 1-5 . After agate structure 120,gate spacer 122, and source/drain regions dielectric layer 130, atstep 604, is formed over atop semiconductor layer 106, thegate spacer 122, and thegate structure 120. Contacttrenches step 606, are formed in thedielectric layer 130 so as to expose at least a portion of the source/drain regions - A contact
trench semiconductor layer 336, atstep 608, is formed within thecontact trenches metallic layer 338, atstep 610, is formed on the contacttrench semiconductor layer 336. An optionalconductive contact liner 440, atstep 612 is formed on the contact trenchmetallic layer 338. A conductivefill material layer 442, atstep 614, is formed in the remaining portion of thecontact trenches step 616, are performed to complete the device. The control flow then exits atstep 618. - It should be noted that some features of the present invention may be used in an embodiment thereof without use of other features of the present invention. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples, and exemplary embodiments of the present invention, and not a limitation thereof.
- It should be understood that these embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
- The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- The methods as discussed above are used in the fabrication of integrated circuit chips.
- The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product or electronic device that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard, or other input device, and a central processor.
- Although specific embodiments of the invention have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the invention. The scope of the invention is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.
Claims (7)
Priority Applications (1)
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US13/614,812 US20130189839A1 (en) | 2012-01-23 | 2012-09-13 | Method to form silicide contact in trenches |
Applications Claiming Priority (2)
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US13/356,090 US9059096B2 (en) | 2012-01-23 | 2012-01-23 | Method to form silicide contact in trenches |
US13/614,812 US20130189839A1 (en) | 2012-01-23 | 2012-09-13 | Method to form silicide contact in trenches |
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US13/356,090 Continuation US9059096B2 (en) | 2012-01-23 | 2012-01-23 | Method to form silicide contact in trenches |
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US13/356,090 Expired - Fee Related US9059096B2 (en) | 2012-01-23 | 2012-01-23 | Method to form silicide contact in trenches |
US13/614,812 Abandoned US20130189839A1 (en) | 2012-01-23 | 2012-09-13 | Method to form silicide contact in trenches |
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Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140183434A1 (en) * | 2013-01-03 | 2014-07-03 | Samsung Electronics Co., Ltd. | Variable resistance memory devices and methods of forming the same |
US20150021714A1 (en) * | 2013-07-22 | 2015-01-22 | GlobalFoundries, Inc. | Integrated circuits having a metal gate structure and methods for fabricating the same |
US9443848B1 (en) | 2015-09-24 | 2016-09-13 | International Business Machines Corporation | Methods for contact formation for 10 nanometers and beyond with minimal mask counts |
US20170103948A1 (en) * | 2015-10-12 | 2017-04-13 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of fabricating the same |
US20170170023A1 (en) * | 2015-12-10 | 2017-06-15 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device |
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US20220157991A1 (en) * | 2019-08-30 | 2022-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Method |
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Families Citing this family (11)
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US9484431B1 (en) * | 2015-07-29 | 2016-11-01 | International Business Machines Corporation | Pure boron for silicide contact |
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Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100052166A1 (en) * | 2008-08-26 | 2010-03-04 | Niloy Mukherjee | Sandwiched metal structure silicidation for enhanced contact |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020045307A1 (en) | 1997-07-03 | 2002-04-18 | Jorge Kittl | Method of forming a silicide layer using metallic impurities and pre-amorphization |
US6518626B1 (en) * | 2000-02-22 | 2003-02-11 | Micron Technology, Inc. | Method of forming low dielectric silicon oxynitride spacer films highly selective of etchants |
US6511905B1 (en) * | 2002-01-04 | 2003-01-28 | Promos Technologies Inc. | Semiconductor device with Si-Ge layer-containing low resistance, tunable contact |
US6858487B2 (en) | 2003-01-02 | 2005-02-22 | United Microelectronics Corp. | Method of manufacturing a semiconductor device |
TW588433B (en) | 2003-03-25 | 2004-05-21 | Nanya Technology Corp | Method of forming metal plug |
BE1015721A3 (en) | 2003-10-17 | 2005-07-05 | Imec Inter Uni Micro Electr | METHOD FOR REDUCING THE CONTACT RESISTANCE OF THE CONNECTION AREAS OF A SEMICONDUCTOR DEVICE. |
US7598545B2 (en) | 2005-04-21 | 2009-10-06 | International Business Machines Corporation | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices |
US20060246720A1 (en) | 2005-04-28 | 2006-11-02 | Chii-Ming Wu | Method to improve thermal stability of silicides with additives |
US20070141798A1 (en) | 2005-12-20 | 2007-06-21 | Intel Corporation | Silicide layers in contacts for high-k/metal gate transistors |
KR100821082B1 (en) | 2006-12-15 | 2008-04-08 | 동부일렉트로닉스 주식회사 | The fabricating method of semiconductor device |
US7897513B2 (en) | 2007-06-28 | 2011-03-01 | Texas Instruments Incorporated | Method for forming a metal silicide |
-
2012
- 2012-01-23 US US13/356,090 patent/US9059096B2/en not_active Expired - Fee Related
- 2012-09-13 US US13/614,812 patent/US20130189839A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100052166A1 (en) * | 2008-08-26 | 2010-03-04 | Niloy Mukherjee | Sandwiched metal structure silicidation for enhanced contact |
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US10276675B2 (en) | 2015-02-10 | 2019-04-30 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
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US9812329B2 (en) * | 2015-12-10 | 2017-11-07 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device |
US20170170023A1 (en) * | 2015-12-10 | 2017-06-15 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device |
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US10395981B2 (en) * | 2017-10-25 | 2019-08-27 | Globalfoundries Inc. | Semiconductor device including a leveling dielectric fill material |
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US20220157991A1 (en) * | 2019-08-30 | 2022-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device and Method |
US11949013B2 (en) * | 2019-08-30 | 2024-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
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