US20130167102A1 - Adaptive patterning for panelized packaging - Google Patents
Adaptive patterning for panelized packaging Download PDFInfo
- Publication number
- US20130167102A1 US20130167102A1 US13/775,425 US201313775425A US2013167102A1 US 20130167102 A1 US20130167102 A1 US 20130167102A1 US 201313775425 A US201313775425 A US 201313775425A US 2013167102 A1 US2013167102 A1 US 2013167102A1
- Authority
- US
- United States
- Prior art keywords
- device units
- pattern
- unit
- specific pattern
- rdl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000059 patterning Methods 0.000 title claims abstract description 52
- 230000003044 adaptive effect Effects 0.000 title claims abstract description 36
- 238000004806 packaging method and process Methods 0.000 title description 8
- 238000000034 method Methods 0.000 claims abstract description 36
- 238000013461 design Methods 0.000 claims description 47
- 238000007689 inspection Methods 0.000 claims description 9
- 230000003287 optical effect Effects 0.000 claims description 7
- 230000008676 import Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 238000005259 measurement Methods 0.000 description 6
- 238000000748 compression moulding Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000005272 metallurgy Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- G06F17/5077—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/2105—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
- H01L2224/221—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/8212—Aligning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Definitions
- Embodiments of the present disclosure relate to the field of panelized packaging.
- WLP fan-out wafer level packaging
- WLCSP wafer level chip scale package
- BGA Ball grid array
- An aspect of the disclosure relates to an adaptive patterning method that may comprise measuring a position of each of a plurality of device units of a panel, creating a unique unit-specific pattern for each of the respective plurality of device units based upon the measured position for each of the respective device units, and forming the unique unit-specific patterns over each of the plurality of device units, wherein each unit-specific pattern is aligned with the respective device unit.
- the unique unit-specific pattern may be selected from the group consisting of a first via pattern, a capture pad, a conductive interconnect, and an interconnecting trace pattern.
- the interconnecting trace pattern may be a redistribution layer (RDL) pattern comprising a die interconnect capture pad, a via capture pad, and a RDL pattern trace.
- the unique unit-specific pattern may be a redistribution layer (RDL) pattern comprising at least one of a RDL pattern trace and a capture pad.
- the unique unit-specific pattern may be formed over each of the plurality of device units with a mask-less patterning system.
- Creating the unique unit-specific pattern for each of the plurality of device units based upon the measured position for each of the respective device units may comprise calculating a delta-value between the measured position and the reference position for each of the respective plurality of device units, and adjusting a position of the unique unit-specific pattern by the same delta-value from reference position of the unique unit-specific pattern for at least one of the plurality of device units.
- the unique unit-specific pattern may be a via, and the position of the formed via may have a different x-y position as compared to the reference position of the via for the at least one of the plurality of device units.
- the unique unit-specific pattern may comprise an RDL pattern, and the position of the formed RDL pattern may have a different x-y position or orientation as compared to the reference position of the RDL pattern for the at least one of the plurality of device units.
- the unique unit-specific pattern may be an RDL pattern, and the position of the formed RDL pattern may have a different design than a reference RDL pattern.
- the plurality of device units of the panel may be arranged in a plurality of modules such that each module includes at least two device units, creating the unique unit-specific pattern for each of the respective device units may comprise creating a module-specific pattern for each of the respective plurality of device units based upon the measured position for each of the respective device units, and forming the unique unit-specific patterns over each of the plurality of device units may comprise forming the module-specific patterns over each of the plurality of device units, wherein each module-specific pattern is aligned with the respective at least two device units within the respective module.
- the statistical average of the misalignment between the plurality of device units and the respective package outlines may be greater than the statistical average of the misalignment between the plurality of device units and the build-up layer.
- the statistical averages of the misalignment of the plurality of device units may be measured with respect to at least one of a first via pattern, a capture pad, a conductive interconnect, and an interconnecting trace pattern, of each device unit and a point on an edge of the package outline.
- An aspect of the disclosure relates to an adaptive patterning system that may comprise an inspection tool to measure a position of a plurality of device units on a panel, and create a file containing the measured position of each of the plurality of device units, design software that creates a unit-specific pattern design for each of the plurality of device units based upon the measured position of each of the plurality of device units, and a patterning machine to import the unit-specific pattern design and form a patterned feature over each of the plurality of device units.
- the design software may adjust an x-y position or rotation of the patterned feature.
- the design software may create the unit-specific pattern design by selecting from a discrete number of design options or dynamically generating the unit-specific pattern.
- FIG. 1A illustrates a top view of a reconstituted wafer in accordance with embodiments.
- FIGS. 1B-1D illustrate a top view of a plurality of packages or modules arranged in a reconstituted wafer in accordance with embodiments.
- FIG. 2A illustrates a top view of a fan-out WLP in accordance with embodiments.
- FIG. 2B illustrates a cross-sectional side view of a fan-out WLP in accordance with embodiments.
- FIG. 3A illustrates a top view of the actual position of a package die having a different x-y position than that of the nominal, reference position in accordance with embodiments.
- FIG. 3B illustrates a top view of the actual position of a package die having a different orientation than that of the nominal, reference orientation in accordance with embodiments.
- FIG. 4 illustrates an RDL pattern in accordance with embodiments.
- FIG. 5A illustrates a portion of panel design in accordance with embodiments.
- FIG. 5B illustrates a misaligned die unit in accordance with embodiments.
- FIG. 6 illustrates a discrete plurality of different design options in accordance with embodiments.
- FIG. 7 illustrates an adaptive patterning system in accordance with embodiments.
- Embodiments of the present disclosure disclose methods and systems to improve panelized packaging.
- misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the misalignment for each individual device unit and adjusting the position or design of a feature in the build-up layer for each respective device unit utilizing a mask-less patterning technique.
- the terms “over,” “between,” and “on” as used herein refer to a relative position of one layer with respect to other layers.
- One layer deposited or disposed above or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
- One layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers.
- a first layer “on” a second layer is in contact with that second layer.
- a plurality of device units may be assembled and molded to create a panel, or reticulated wafer.
- Device units may be active device units such as dies, and may also be passive device units such as an integrated passive network, or a discrete passive device unit such as a capacitor, resistor, or inductor.
- the device units may be pre-packaged, though pre-packaging is not required.
- the pre-packages may contain single or a plurality of device units and other components. The panel is inspected to measure the true position for each device unit in the panel.
- the measured position may include an x-y position and/or orientation of at least one feature from each device unit with respect to a global fiducial(s) on the panel.
- a unit-specific pattern for each individual device unit is then created based upon the measured position for each respective individual device unit, and provided to a laser, direct write imaging system or other mask-less patterning system.
- the unit-specific patterns are then formed over each of the plurality of device units so that each unit-specific pattern is aligned with the respective device unit.
- creating the pattern relates to adjusting the position or design of a unit detail pattern in a chip scale package (CSP) build-up structure to align with the measured position of each device unit in the panel.
- the unit detail pattern is a first via pattern, a capture pad, or an interconnecting trace pattern that may or may not be associated with a redistribution layer (RDL).
- RDL redistribution layer
- the position of a first via pattern can be adjusted so that it is formed in alignment with the measured position of each device unit in the panel.
- an RDL layer, including at least a capture pad for the first via may be adjusted or designed to maintain alignment with the true position of each device unit in the panel.
- the final under bump metallurgy (UBM) pad and BGA ball may be formed without aligning with respect to the measured position of the device unit.
- the UBM pad and BGA ball may be aligned consistently with respect to the package outline for each device unit, maintaining conformance to the package outline.
- Adaptive patterning may also be utilized to create a plurality of module-specific patterns across the panel.
- a plurality of device units and optionally other components may be assembled and molded to create a panel, or reticulated wafer.
- the other components may be optical elements, connectors (e.g. to connect to the outside of the module) and other electronic components, which may also be pre-packaged.
- a module includes a plurality of device units.
- a module may also include at least one device unit and another component.
- a panel including a plurality of arrangements of a plurality of device units, or at least one device unit and at least one additional component is inspected to measure the true position for each device unit and optional other component in the panel.
- the measured position may include an x-y position and/or orientation of at least one feature from each device unit and optional other component within a module with respect to a global fiducial(s) on the panel.
- a module-specific pattern for each module is then created based upon the measured position for each respective individual device unit and optional other component within the respective module, and provided to a laser, direct write imaging system or other mask-less patterning system.
- the module-specific patterns are then formed over each of the plurality of device units and optional other components so that each module-specific pattern is aligned with the respective module device units and optional other components.
- Creating the module-specific pattern may relate to adjusting the position or design of a unit or component detail pattern in a CSP build-up structure to align with the measured position of each device unit or component in the panel as previously described with regard to the single device unit package embodiment.
- device interconnect traces which may or may not be associated with a RDL may exist.
- a multi-layer build-up structure can also be utilized for both modules as well as single device packages.
- the process begins with a panel 102 including a plurality of device units 104 overmolded with an encapsulating material 106 such as an epoxy resin. While FIG. 1A illustrates a circular panel 102 , alternative panel formats such as rectangular or square may be utilized. As illustrated in FIG.
- panel 102 may be what is known in the art as a reconstituted wafer formed in a WLP technique where the plurality of device units are placed face down on a temporary tape carrier, followed by overmolding with epoxy molding compound using a compression molding process, followed by removal of the temporary tape carrier leaving the active surfaces of the plurality of die units exposed.
- a build-up structure may be formed on top of the structure illustrated in FIG. 1A and the device units are singulated to form packages or modules.
- the panel may be singulated into a plurality of single-die packages 150 , each package including a single semiconductor die unit 152 .
- a plurality of die units 152 , 154 may be mounted within the molded panel and singulated to form multi-die packages or modules 150 .
- a single die unit 152 or a plurality of die units 152 , 154 may be mounted within the molded panel with the addition of a passive device(s) 156 (such as capacitor, inductor or resistor) and/or other component(s) 158 (such as an optical element, connector or other electronic component) and singluated to form a packages or modules 150 which include both an active device(s) and a passive device(s) and/or other component 158 .
- a passive device(s) 156 such as capacitor, inductor or resistor
- other component(s) 158 such as an optical element, connector or other electronic component
- Embodiments of the present disclosure may be used in any panelized packaging application including single-die applications, multi-die modules, some combination of a die(s) and a passive component(s) within a module, or some combination of a device unit(s) and another component(s) within a module.
- embodiments of the present disclosure may eliminate or reduce package or module assembly yield loss caused by misalignment of the device unit or other component during panelization.
- embodiments of the present disclosure may maintain compliance to the package or module outline and not require changes to the position of UBM pads or BGA balls. Maintaining compliance with the package or module outline can be consistently achieved in the final product, e.g. as end-product package, test socket, etc.
- embodiments of the present disclosure may allow for a smaller bond pad opening on the device units.
- the CSP build-up structure 110 may be formed over the active surface of each individual die unit before singulation. While build-up structure 110 in FIG. 2B is illustrated as including a single dielectric layer 115 , it is understood that multiple layers may be used to form build-up structure 110 .
- Build-up structure 110 may be formed from a dielectric material 115 within which is included a first via 112 which is in electrical contact with a bond pad 105 of the die unit 152 .
- a redistribution layer (RDL) 114 is formed which may span under the bond pad 105 , first via 112 , and over an underbump metallurgy (UBM) via 116 , UBM pad 119 , and BGA ball 108 .
- BGA ball 108 is illustrated in FIG. 2B as a solder ball, though is not limited to such.
- multiple dielectric layers and device interconnect traces which may or may not be associated with the RDL, are formed in accordance with the principles described herein.
- Such multi-layer build-up structures can be utilized in both single-die package applications as well as multi-device modules.
- die unit placement and overmolding may cause displacement and/or rotation of the orientation of any of the plurality of die units 152 on the temporary tape carrier. This may be attributed to the die units not being rigidly attached to the temporary tape carrier as well as shrinkage of the molding compound during curing of the molding compound. As a result, the plurality of die units 152 on panel 102 may not lie in their nominal, reference positions after compression molding. As illustrated in FIG. 3A , the actual position of a die unit 152 may have a different x-y position than that of the nominal, reference position 152 ′ of the die unit. As illustrated in FIG.
- the actual position of the die unit 152 may be rotated such that it has a different orientation 0 than that of the nominal, reference orientation 0 ′ of the nominal, reference position 152 ′. While the difference in x-y position and orientation is illustrated in FIGS. 3A-3B with respect to the nominal, reference positions of the die unit within an individual singulated package outline, it is understood that the difference in x-y position and orientation may be actually measured with regard to a global fiducial(s) within the panel or reticulated wafer.
- Misalignment of the individual die units may cause some of the packages which are subsequently singulated from the panel to be defective.
- Conventional methods for forming a CSP build-up structure on a panel utilize mask-based patterning technologies to expose a pattern on multiple die units of the panel at the same time.
- the masks include fixed patterns for die pad to UBM interconnect and, therefore, lack the ability to adjust for the movement of each die within a panelized format.
- the impact of the conventional methods is either yield loss due to misalignment of first vias to the bond pads or the addition of some intermediate form of die pad re-routing in native wafer form (prior to panelization) to make larger die pads as targets to ensure the first vias make connection despite die movement.
- conventional processing technology requires that bond pads on the die units be larger than necessary to avoid yield loss from the panel, thereby reducing the application space for WLP technology.
- misalignment of the individual die units is adjusted for by utilizing an adaptive patterning technique which additionally implements mask-less lithography to pattern features of the build-up structure 110 .
- Laser ablation and direct write exposure are examples of suitable mask-less patterning techniques in accordance with embodiments of the present disclosure.
- a panel including a plurality of die units is provided as illustrated in FIG. 1A .
- a true position is measured for each of the plurality of die units 152 of the panel.
- the measurement may be of a specific feature formed on each of the die units of the panel.
- the specific position can be a variety of positions, such as a corner of the bond pad 105 , a center of the bond pad, an outline of the bond pad, etc.
- Included in the position measurement may be the x-y position and/or orientation with respect to a global fiducial(s) on the panel.
- Any suitable inspection tool may be utilized to measure the true first position, such as an optical inspection tool.
- a single feature is measured to obtain an x-y position of a die unit.
- a plurality of features are measured to obtain an orientation of a die unit.
- a build-up structure 110 is formed over the panel including the plurality of die units. Referring again to FIG. 2B , a singulated package is illustrated with a completed build-up structure 110 . While the build-up structure 110 is illustrated as being formed over a single package in FIG. 2B , it is understood that build-up structure 110 is formed prior to singulation, and that a plurality of build-up structures 110 are formed across the panel 102 and over each of the respective plurality of die units 152 on the panel 102 illustrated in FIG. 1A .
- the build-up structure 110 is formed from a dielectric material 115 , from which features are patterned.
- Build-up structure 110 may include a plurality of layers. For example, a separate dielectric layer may be formed in which the first via 112 , RDL pattern 114 , and UBM via 116 , and/or UBM pad 119 are separately formed. In an embodiment, there may be multiple via and RDL patterned layers.
- Dielectric material 115 may be opaque or translucent, and different materials can be utilized for the separate dielectric layers. Where the dielectric material 115 is opaque, optical measurements of a feature may be measured prior to forming the dielectric material 115 over the underlying feature. Where the dielectric material 115 is translucent it is possible to measure the position of a feature below the dielectric material 115 before or after forming the dielectric material over the panel.
- a specific pattern is created for each of the plurality of die units.
- the pattern is unit-specific for each of the respective die units, and therefore the unit-specific patterns may be different (e.g. x-y position, orientation, design) for each respective die unit so that each unit-specific pattern is aligned with each respective die unit, thereby compensating for misalignment of the individual die units.
- Each unit-specific pattern may be a common pattern aligned with the respective die unit.
- Each unit-specific pattern may also be uniquely created for each die unit in accordance with embodiments of the present disclosure.
- the pattern is then formed over each of the plurality of die units.
- the pattern is a unit detail pattern formed in a build-up structure 110 such as the first via 112 which connects the bond pad 105 to the RDL pattern 114 , the RDL pattern 114 , or the UBM pad pattern 119 .
- the RDL pattern 114 of FIG. 2B may include a first via capture pad 118 aligned with the first via 112 , a UBM via capture pad 120 aligned with the UBM via 116 , and a trace portion 122 connecting the capture pads 121 , 120 .
- the patterned features in the build-up structure 110 may be formed utilizing a mask-less patterning system.
- a first via 112 or RDL pattern 114 may be created through exposure of a photo imagable polymer or photoresist through a direct writing.
- First via 112 or RDL pattern 114 may also be created through laser ablation of dielectric material 115 .
- a number of methods are envisioned for creating a pattern for each of the plurality of die units based upon the measured position for each of the respective die units. In an embodiment, this may be accomplished by comparing the measured position of each of the plurality of die units to a number of defined nominal, reference positions.
- a nominal, reference position of at least one feature on each of the plurality of die units can be defined with respect to a global fiducial(s) on the panel 102 .
- the specific nominal, reference position can be a variety of positions, such as a corner of the bond pad 105 , a center of the bond pad, an outline of the bond pad, an alignment feature, etc.
- the specific nominal, reference position can also be the package outline, within which the die units will be packaged.
- defining a nominal, reference position includes generating an electronic panel map.
- the nominal, reference position (x-y position and/or orientation) of each die unit in the panel can be defined in an electronic panel map. Though embodiments do not require a panel map, and the nominal, reference positions can be provided elsewhere.
- the position or design of the pattern is adjusted for each die unit to align with the measured position of the respective die unit in the panel.
- Design software can create a pattern design for each of the plurality of die units based upon the measured position of each of the die units in the panel.
- This pattern design may then be stored in a panel design file, in which the x-y position and/or orientation of the pattern is adjusted.
- the pattern may also be changed to optimize the pattern design for each die unit.
- a panel design file may be transferred to a mask-less patterning system to form at least the unit-specific pattern.
- FIG. 5A illustrates a portion of a panel design in accordance with an embodiment of the present disclosure.
- the illustration provided in FIG. 5A is meant to be exemplary of a panel design in accordance with an embodiment of the present disclosure and is not meant to be limiting.
- an upper left-hand corner of an individual package outline is shown, however it is understood that the panel design may include additional or less information for the individual die package, and that the panel design may include similar information for each of the plurality of die units of the panel.
- the panel design may define nominal, reference positions for each die within the panel, as well as nominal, reference positions for yet to be formed features.
- the nominal, reference positions for the die 152 ′ and bond pad 105 ′ are defined.
- Features which have not yet been formed over the panel may include nominal, reference positions for the first via 112 ′, die via capture pad 118 ′, UBM via 116 ′, UBM via capture pad 120 ′, RDL pattern trace 122 ′, UBM pad 119 ′, and package outline 130 ′ of a package to be singulated from the panel.
- FIG. 5B illustrates a misaligned die unit in accordance with an embodiment of the present disclosure.
- die unit 152 is illustrated as being misaligned with respect to the nominal, reference die unit position 152 ′ or global fiducial(s) on the panel (not illustrated).
- the already formed die pad 105 is illustrated as being misaligned with respect to the nominal, reference die unit position 105 ′ or global fiducial(s) on the panel (not illustrated).
- a nominal, reference position of at least one feature on each of the plurality of die units is defined.
- the nominal, reference position may be die pad 105 ′.
- the true position of the die bond pad 105 is measured for each of the plurality of die units on the panel.
- misalignment of the individual die units is determined when the measured position of the die bond pad 105 has a different x-y position or orientation than that of the reference position of the die bond pad 105 ′.
- the position of the patterned feature (e.g. first via 112 , die via capture pad 118 , UBM via 116 , UBM via capture pad 120 , RDL pattern trace 122 ) formed in the CSP build-up structure 110 has a different x-y position or orientation than the nominal, reference position of the feature for at least one of the plurality of die units.
- the formed first via 112 has a different x-y position as compared to the reference position of the first via 112 ′ for at least one of the plurality of die units.
- the formed RDL pattern 114 has a different x-y position as compared to the reference position of the RDL pattern 114 ′ for at least one of the plurality of die units.
- the formed RDL pattern 114 has a different x-y position and orientation as compared to the reference position of the RDL pattern 114 ′ for at least one of the plurality of die units.
- the amount of misalignment of the die unit in the x-y direction and/or orientation is measured by the inspection tool, and a delta-value between the nominal, reference position and measured position of the die unit is calculated for at least one of the plurality of die units. Based upon the delta-value, the pattern to be formed is created by adjusting the pattern from its reference position by the same delta-value. It is contemplated, however, that the patterned feature may not necessarily have to be formed with the same delta-value in accordance with embodiments of the disclosure.
- FIG. 5B it is shown that the relative alignment between the first via 112 , and the bond pad 105 and die unit 152 is the same as the relative alignment illustrated in FIG. 5A between the nominal, reference positions 112 ′, 105 ′, 152 ′.
- any of the portions 118 , 122 , 120 of the RDL pattern 114 , or the entire RDL pattern 114 may be shifted in FIG. 5B by the same delta-value between the true first position of the bond pad 105 and the reference bond pad position 105 ′.
- an additional feature may be formed over each of the plurality of die units without regard to the measured position of each of the respective plurality of die units.
- UBM pad 119 is formed at the nominal, reference position 119 ′ without regard to the measured position of each of the respective plurality of die units.
- position of the actual positions of the UBM pad 119 and package outline 130 are the same as the corresponding nominal, reference positions 108 ′, 130 ′.
- the actual position UBM via 116 may also be in the position as the nominal, reference position 116 ′.
- Adjusting the position of a unit detail pattern formed in the CSP build-up structure to align with the measured position of each die in the panel may also include changing the RDL pattern design.
- changing the RDL pattern design includes selecting a best-fit RDL pattern design from a discrete plurality of different design options. An illustration of a discrete plurality of different design options is provided in FIG. 6 .
- each quadrant I-IX represents a range of delta-values between the measured position of the bond pad 105 and the reference bond pad position 105 ′.
- the delta-value corresponds to point 140 in FIG. 6
- the RDL pattern design for quadrant VI is selected. If the delta-value corresponds to point 142 in FIG.
- the RDL pattern for quadrant IX is selected.
- the design tool can automatically generate a given best-fit pattern for each individual die based upon the corresponding delta-value for that specific die.
- each of the different design patterns associated with the quadrants can have different sizes, shapes, and/or orientations for the RDL pattern. While FIG. 6 illustrates a nine different design options, it is to be understood that any discrete number of different design options may be used.
- adjusting the position of a unit detail pattern formed in the CSP build-up structure to align with the measured position of each die in the panel includes changing the RDL pattern design with a dynamic design approach. For example, a customized RDL pattern may be dynamically generated for each specific die unit based upon the corresponding delta-values for each specific die unit.
- the manner of adjusting a unit detail pattern formed in the CSP build-up structure may depend upon the amount of adjustment required to align the unit detail pattern with the respective die in the panel.
- adjustment of the first via 112 position may be sufficient to compensate for misalignment of the die 152 .
- all or a portion of the RDL pattern 114 position may need to be adjusted by the same delta-value by which the first via 112 position was adjusted.
- the design of the RDL pattern 114 may be changed so that the first via capture pad 118 is aligned to the first via 112 , and the UBM via capture pad 120 is aligned with the UBM via 116 . This may be accomplished by selecting a best-fit design of the RDL pattern 114 for each of the respective die units based upon the position of the delta-value in the quadrants illustrated in FIG. 6 , or dynamically designing a customized RDL pattern 114 for each die unit.
- an adaptive patterning technique in accordance with embodiments of the present disclosure may be utilized to pattern features within a build-up structure 100 , such as a first via 112 and RDL pattern 114 .
- an adaptive patterning technique may be utilized for any structure within the build-up structure.
- build-up structure may contain multiple layers, vias, and RDL patterns.
- an adaptive patterning technique may include measurement of a first true position followed by adaptive patterning of a first via and RDL- 1 , then measurement of a second true position followed by adaptive patterning of a via- 2 and RDL- 2 , then measurement of true position ‘n’ followed by adaptive patterning of a via-n and RDL-n.
- a lot of die packages may be singulated from a panel or reticulated wafer.
- the lot may be characterized by a unique statistical range of relative orientations.
- the statistical average across the lot for the misalignment of the first via 112 relative to the respective die 152 outline for the lot is directly proportional to the statistical average of the misalignment of the die 152 relative to the package outline 130 .
- the first via 112 may be adjusted for each individual die to compensate for misalignment of the respective die 152 . Therefore, the statistical average across the lot for the misalignment of the first via 112 relative to the respective die 152 outline is considerably less than the statistical average of the misalignment of the die 152 relative to the package outline 130 .
- the statistical average across the lot for the misalignment of the first via 112 relative to the respective die 152 outline is nill.
- Certain embodiments may be implemented as a computer program product that may include instructions stored on a non-transitory machine-readable medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations.
- a machine-readable medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer).
- the machine-readable medium may include, but is not limited to, magnetic storage medium (e.g., floppy diskette); optical storage medium (e.g., CD-ROM); magneto-optical storage medium; read-only memory (ROM); random-access memory (RAM); erasable programmable memory (e.g., EPROM and EEPROM); flash memory; or another type of medium suitable for storing electronic instructions.
- magnetic storage medium e.g., floppy diskette
- optical storage medium e.g., CD-ROM
- magneto-optical storage medium e.g., magneto-optical storage medium
- ROM read-only memory
- RAM random-access memory
- EPROM and EEPROM erasable programmable memory
- flash memory or another type of medium suitable for storing electronic instructions.
- some embodiments may be practiced in distributed computing environments where the machine-readable medium is stored on and/or executed by more than one computer system.
- the information transferred between computer systems may either be pulled or pushed across the communication medium connecting the computer systems.
- the digital processing devices described herein may include one or more general-purpose processing devices such as a microprocessor or central processing unit, a controller, or the like.
- the digital processing device may include one or more special-purpose processing devices such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like.
- DSP digital signal processor
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- the digital processing device may be a network processor having multiple processors including a core unit and multiple microengines.
- the digital processing device may include any combination of general-purpose processing devices and special-purpose processing devices.
- Embodiments of the present disclosure may be performed with an adaptive patterning system 700 as illustrated in FIG. 7 .
- Operations may be performed by hardware components, software, firmware, or a combination thereof. Any of the signals provided over various buses 701 described herein may be time multiplexed with other signals and provided over one or more common buses.
- a panel or reticulated wafer 702 may be supplied to an inspection tool 704 which measures a position of a plurality of device units on the panel and creates a file 706 containing the measured position of each of the plurality of device units.
- Design software stored on server 708 then creates a pattern design file 710 for each of the plurality of device units based upon the measured position of each of the plurality of device units.
- a patterning machine 712 imports the pattern design and forms a patterned feature over each of the plurality of device units.
- the panel or reticulated wafer 702 is provided to a patterning machine 712 from the inspection tool 704 .
- a patterned panel 714 may be output from the patterning machine 712 .
- the design software further creates a new drawing for at least one layer of design, which is adjusted such that the first via and/or RDL pattern is aligned to the measured position of each of the plurality of device units.
- the software includes an algorithm for adaptive patterning. For example, the algorithm may adjust the x-y position or orientation of a feature based upon a delta-value. In an embodiment, the algorithm may select a feature pattern from a discrete number of design options based upon a delta-value. In an embodiment, the algorithm may dynamically design a feature based upon a delta-value.
- the schematic illustration provided in FIG. 7 is indicative of the order of a process in accordance with embodiments of the disclosure, however, it is not necessary that the actual equipment be arranged as illustrated.
- the design software is stored on a separate server 708 , which can also store a panel map which includes nominal, reference positions of the plurality of device units on the panel. It is not required that the design software be stored on a separate server 708 .
- design software could be stored on the inspection tool 704 or patterning machine 712 . It is possible to have all components integrated into a single system.
- Server 708 can be utilized to control any part of or the entire adaptive patterning system 700 .
- server 708 includes memory 711 having instructions stored thereon, which when executed by a processor 709 , cause the processor to instruct the inspection tool 704 to measure a position of each of a plurality of device units of a panel, create a unit-specific pattern for each of the respective plurality of device units based upon the measured position for each of the respective device units, and instruct the patterning tool 712 to form the unit-specific patterns over each of the plurality of device units, wherein each unit-specific pattern is aligned with the respective device unit.
- creating a unit-specific pattern for each of the respective plurality of device units based upon the measured position for each of the respective device units may include adjusting an x-y position and/or orientation of at least one unit-specific pattern, selecting from a discrete number of design options, or dynamically generating the unit-specific pattern.
Abstract
Description
- This application is a continuation application of U.S. Pat. No. 12/876,915, titled “Adaptive Patterning for Panelized Packaging,” filed Sep. 7, 2010, which claims the benefit of U.S. Provisional Application No. 61/305,125, filed Feb. 16, 2010, the disclosures of which are hereby incorporated herein by this reference.
- Embodiments of the present disclosure relate to the field of panelized packaging.
- A common implementation of panelized packaging gaining acceptance in industry is fan-out wafer level packaging (WLP) in which multiple die units are placed face down on a temporary tape carrier. The carrier is overmolded with epoxy molding compound using a compression molding process. After molding the carrier tape is removed, leaving the active surface of the multiple die exposed in a structure commonly referred to as a reconstituted wafer. Subsequently, a wafer level chip scale package (WLCSP) build-up structure is formed on top of the reconstituted wafer. Ball grid array (BGA) balls are attached to the reconstituted wafer and then the reconstituted wafer is saw singulated to form individual packages. It has been observed that the die placement and overmolding processes may cause displacement and/or rotation of the die, resulting in defective packages and yield loss.
- An aspect of the disclosure relates to an adaptive patterning method that may comprise measuring a position of each of a plurality of device units of a panel, creating a unique unit-specific pattern for each of the respective plurality of device units based upon the measured position for each of the respective device units, and forming the unique unit-specific patterns over each of the plurality of device units, wherein each unit-specific pattern is aligned with the respective device unit.
- Particular embodiments may comprise one or more of the following. The unique unit-specific pattern may be selected from the group consisting of a first via pattern, a capture pad, a conductive interconnect, and an interconnecting trace pattern. The interconnecting trace pattern may be a redistribution layer (RDL) pattern comprising a die interconnect capture pad, a via capture pad, and a RDL pattern trace. The unique unit-specific pattern may be a redistribution layer (RDL) pattern comprising at least one of a RDL pattern trace and a capture pad. The unique unit-specific pattern may be formed over each of the plurality of device units with a mask-less patterning system. Defining a reference position of at least one feature on each of the plurality of device units, wherein the measured position has a different x-y position or orientation as compared to the reference position for the at least one of the plurality of device units. Defining a reference position of the unique unit-specific pattern over each the plurality of device units, wherein the unique unit-specific pattern formed has a different x-y position or orientation as compared to the reference position of the unique unit-specific pattern for the at least one of the plurality of device units. Creating the unique unit-specific pattern for each of the plurality of device units based upon the measured position for each of the respective device units may comprise calculating a delta-value between the measured position and the reference position for each of the respective plurality of device units, and adjusting a position of the unique unit-specific pattern by the same delta-value from reference position of the unique unit-specific pattern for at least one of the plurality of device units. The unique unit-specific pattern may be a via, and the position of the formed via may have a different x-y position as compared to the reference position of the via for the at least one of the plurality of device units. The unique unit-specific pattern may comprise an RDL pattern, and the position of the formed RDL pattern may have a different x-y position or orientation as compared to the reference position of the RDL pattern for the at least one of the plurality of device units. The unique unit-specific pattern may be an RDL pattern, and the position of the formed RDL pattern may have a different design than a reference RDL pattern. The plurality of device units of the panel may be arranged in a plurality of modules such that each module includes at least two device units, creating the unique unit-specific pattern for each of the respective device units may comprise creating a module-specific pattern for each of the respective plurality of device units based upon the measured position for each of the respective device units, and forming the unique unit-specific patterns over each of the plurality of device units may comprise forming the module-specific patterns over each of the plurality of device units, wherein each module-specific pattern is aligned with the respective at least two device units within the respective module. Measuring a position of each of a plurality of other components of the panel, the other components selected from the group consisting of optical elements, connectors and electronic components, wherein the plurality of device units of the panel may be arranged in a plurality of modules such that each module includes at least one device unit and at least one other component, wherein creating the unique unit-specific pattern for each of the respective device units may comprise creating a module-specific pattern for each of the respective plurality of device units and other components based upon the measured position for each of the respective device units and other components, and wherein forming the unique unit-specific patterns over each of the plurality of device units may comprise forming the module-specific patterns over each of the plurality of device units and other components, wherein each module-specific pattern is uniquely adapted to align with the respective at least one device unit and at least one other component within the respective module. Measuring a misalignment of each of the plurality of device units relative to a package outline and calculating a statistical average for the misalignment between the plurality of device units and the respective package outlines, and measuring a misalignment of each of the plurality of device units relative to a build-up layer and calculating a statistical average for the misalignment between the plurality of device units and the build-up layer. The statistical average of the misalignment between the plurality of device units and the respective package outlines may be greater than the statistical average of the misalignment between the plurality of device units and the build-up layer. The statistical averages of the misalignment of the plurality of device units may be measured with respect to at least one of a first via pattern, a capture pad, a conductive interconnect, and an interconnecting trace pattern, of each device unit and a point on an edge of the package outline.
- An aspect of the disclosure relates to an adaptive patterning system that may comprise an inspection tool to measure a position of a plurality of device units on a panel, and create a file containing the measured position of each of the plurality of device units, design software that creates a unit-specific pattern design for each of the plurality of device units based upon the measured position of each of the plurality of device units, and a patterning machine to import the unit-specific pattern design and form a patterned feature over each of the plurality of device units.
- Particular embodiments may comprise one or more of the following. The design software may adjust an x-y position or rotation of the patterned feature. The design software may create the unit-specific pattern design by selecting from a discrete number of design options or dynamically generating the unit-specific pattern.
-
FIG. 1A illustrates a top view of a reconstituted wafer in accordance with embodiments. -
FIGS. 1B-1D illustrate a top view of a plurality of packages or modules arranged in a reconstituted wafer in accordance with embodiments. -
FIG. 2A illustrates a top view of a fan-out WLP in accordance with embodiments. -
FIG. 2B illustrates a cross-sectional side view of a fan-out WLP in accordance with embodiments. -
FIG. 3A illustrates a top view of the actual position of a package die having a different x-y position than that of the nominal, reference position in accordance with embodiments. -
FIG. 3B illustrates a top view of the actual position of a package die having a different orientation than that of the nominal, reference orientation in accordance with embodiments. -
FIG. 4 illustrates an RDL pattern in accordance with embodiments. -
FIG. 5A illustrates a portion of panel design in accordance with embodiments. -
FIG. 5B illustrates a misaligned die unit in accordance with embodiments. -
FIG. 6 illustrates a discrete plurality of different design options in accordance with embodiments. -
FIG. 7 illustrates an adaptive patterning system in accordance with embodiments. - Embodiments of the present disclosure disclose methods and systems to improve panelized packaging. In accordance with embodiments of the present disclosure, misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the misalignment for each individual device unit and adjusting the position or design of a feature in the build-up layer for each respective device unit utilizing a mask-less patterning technique.
- In the following description, numerous specific details are set forth, such as specific configurations, compositions, and processes, etc., in order to provide a thorough understanding of the present disclosure. In other instances, well-known processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the FIGs. are illustrative representations and are not necessarily drawn to scale.
- The terms “over,” “between,” and “on” as used herein refer to a relative position of one layer with respect to other layers. One layer deposited or disposed above or under another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with that second layer.
- In accordance with embodiments of the present disclosure, a plurality of device units may be assembled and molded to create a panel, or reticulated wafer. Device units may be active device units such as dies, and may also be passive device units such as an integrated passive network, or a discrete passive device unit such as a capacitor, resistor, or inductor. The device units may be pre-packaged, though pre-packaging is not required. In accordance with embodiments of the present disclosure, the pre-packages may contain single or a plurality of device units and other components. The panel is inspected to measure the true position for each device unit in the panel. For example, the measured position may include an x-y position and/or orientation of at least one feature from each device unit with respect to a global fiducial(s) on the panel. A unit-specific pattern for each individual device unit is then created based upon the measured position for each respective individual device unit, and provided to a laser, direct write imaging system or other mask-less patterning system. The unit-specific patterns are then formed over each of the plurality of device units so that each unit-specific pattern is aligned with the respective device unit.
- In an embodiment, creating the pattern relates to adjusting the position or design of a unit detail pattern in a chip scale package (CSP) build-up structure to align with the measured position of each device unit in the panel. In an embodiment, the unit detail pattern is a first via pattern, a capture pad, or an interconnecting trace pattern that may or may not be associated with a redistribution layer (RDL). For example, the position of a first via pattern can be adjusted so that it is formed in alignment with the measured position of each device unit in the panel. Also, an RDL layer, including at least a capture pad for the first via may be adjusted or designed to maintain alignment with the true position of each device unit in the panel. The final under bump metallurgy (UBM) pad and BGA ball may be formed without aligning with respect to the measured position of the device unit. As such, the UBM pad and BGA ball may be aligned consistently with respect to the package outline for each device unit, maintaining conformance to the package outline.
- Adaptive patterning may also be utilized to create a plurality of module-specific patterns across the panel. In accordance with embodiments of the present disclosure, a plurality of device units and optionally other components may be assembled and molded to create a panel, or reticulated wafer. The other components may be optical elements, connectors (e.g. to connect to the outside of the module) and other electronic components, which may also be pre-packaged. In an embodiment, a module includes a plurality of device units. A module may also include at least one device unit and another component. A panel including a plurality of arrangements of a plurality of device units, or at least one device unit and at least one additional component is inspected to measure the true position for each device unit and optional other component in the panel. For example, the measured position may include an x-y position and/or orientation of at least one feature from each device unit and optional other component within a module with respect to a global fiducial(s) on the panel. A module-specific pattern for each module is then created based upon the measured position for each respective individual device unit and optional other component within the respective module, and provided to a laser, direct write imaging system or other mask-less patterning system. The module-specific patterns are then formed over each of the plurality of device units and optional other components so that each module-specific pattern is aligned with the respective module device units and optional other components.
- Creating the module-specific pattern may relate to adjusting the position or design of a unit or component detail pattern in a CSP build-up structure to align with the measured position of each device unit or component in the panel as previously described with regard to the single device unit package embodiment. Where multiple devices and optional other components exist, device interconnect traces which may or may not be associated with a RDL may exist. A multi-layer build-up structure can also be utilized for both modules as well as single device packages.
- Referring to
FIG. 1A , in an embodiment, the process begins with a panel 102 including a plurality of device units 104 overmolded with an encapsulatingmaterial 106 such as an epoxy resin. WhileFIG. 1A illustrates a circular panel 102, alternative panel formats such as rectangular or square may be utilized. As illustrated inFIG. 1A , the active surfaces of the plurality of device units 104 are substantially flush with the encapsulating material 106.In an embodiment, panel 102 may be what is known in the art as a reconstituted wafer formed in a WLP technique where the plurality of device units are placed face down on a temporary tape carrier, followed by overmolding with epoxy molding compound using a compression molding process, followed by removal of the temporary tape carrier leaving the active surfaces of the plurality of die units exposed. - Subsequently, a build-up structure may be formed on top of the structure illustrated in
FIG. 1A and the device units are singulated to form packages or modules. For example, as illustrated inFIG. 1B , the panel may be singulated into a plurality of single-die packages 150, each package including a singlesemiconductor die unit 152. Referring toFIG. 1C , a plurality ofdie units modules 150. Referring toFIG. 1D , asingle die unit 152 or a plurality ofdie units modules 150 which include both an active device(s) and a passive device(s) and/orother component 158. A variety of combinations of active and passive devices and optionally other components within packages or modules are envisioned in accordance with embodiments of the present disclosure. Accordingly, the particular configurations illustrated inFIGS. 1B-1D are meant to be illustrated rather than limiting. - In the following discussion, certain embodiments are described with regard to the formation of a single die fan-out WLCSP, though embodiments of the disclosure are not limited to such. Embodiments of the present disclosure may be used in any panelized packaging application including single-die applications, multi-die modules, some combination of a die(s) and a passive component(s) within a module, or some combination of a device unit(s) and another component(s) within a module. In one aspect, embodiments of the present disclosure may eliminate or reduce package or module assembly yield loss caused by misalignment of the device unit or other component during panelization. In another aspect, embodiments of the present disclosure may maintain compliance to the package or module outline and not require changes to the position of UBM pads or BGA balls. Maintaining compliance with the package or module outline can be consistently achieved in the final product, e.g. as end-product package, test socket, etc. In another aspect, embodiments of the present disclosure may allow for a smaller bond pad opening on the device units.
- Referring now to
FIGS. 2A-2B , ball grid array (BGA)balls 108 are attached and the panel is saw singulated to form individual packages. The CSP build-upstructure 110 may be formed over the active surface of each individual die unit before singulation. While build-upstructure 110 inFIG. 2B is illustrated as including asingle dielectric layer 115, it is understood that multiple layers may be used to form build-upstructure 110. Build-upstructure 110 may be formed from adielectric material 115 within which is included a first via 112 which is in electrical contact with abond pad 105 of thedie unit 152. A redistribution layer (RDL) 114 is formed which may span under thebond pad 105, first via 112, and over an underbump metallurgy (UBM) via 116,UBM pad 119, andBGA ball 108.BGA ball 108 is illustrated inFIG. 2B as a solder ball, though is not limited to such. In other embodiments, multiple dielectric layers and device interconnect traces, which may or may not be associated with the RDL, are formed in accordance with the principles described herein. Such multi-layer build-up structures can be utilized in both single-die package applications as well as multi-device modules. - It has been observed that die unit placement and overmolding may cause displacement and/or rotation of the orientation of any of the plurality of
die units 152 on the temporary tape carrier. This may be attributed to the die units not being rigidly attached to the temporary tape carrier as well as shrinkage of the molding compound during curing of the molding compound. As a result, the plurality ofdie units 152 on panel 102 may not lie in their nominal, reference positions after compression molding. As illustrated inFIG. 3A , the actual position of adie unit 152 may have a different x-y position than that of the nominal,reference position 152′ of the die unit. As illustrated inFIG. 3B , the actual position of thedie unit 152 may be rotated such that it has adifferent orientation 0 than that of the nominal,reference orientation 0′ of the nominal,reference position 152′. While the difference in x-y position and orientation is illustrated inFIGS. 3A-3B with respect to the nominal, reference positions of the die unit within an individual singulated package outline, it is understood that the difference in x-y position and orientation may be actually measured with regard to a global fiducial(s) within the panel or reticulated wafer. - Misalignment of the individual die units may cause some of the packages which are subsequently singulated from the panel to be defective. Conventional methods for forming a CSP build-up structure on a panel utilize mask-based patterning technologies to expose a pattern on multiple die units of the panel at the same time. The masks include fixed patterns for die pad to UBM interconnect and, therefore, lack the ability to adjust for the movement of each die within a panelized format. The impact of the conventional methods is either yield loss due to misalignment of first vias to the bond pads or the addition of some intermediate form of die pad re-routing in native wafer form (prior to panelization) to make larger die pads as targets to ensure the first vias make connection despite die movement. As a result, conventional processing technology requires that bond pads on the die units be larger than necessary to avoid yield loss from the panel, thereby reducing the application space for WLP technology.
- In accordance with embodiments of the present disclosure, misalignment of the individual die units is adjusted for by utilizing an adaptive patterning technique which additionally implements mask-less lithography to pattern features of the build-up
structure 110. Laser ablation and direct write exposure are examples of suitable mask-less patterning techniques in accordance with embodiments of the present disclosure. - In an embodiment, a panel including a plurality of die units is provided as illustrated in
FIG. 1A . A true position is measured for each of the plurality ofdie units 152 of the panel. The measurement may be of a specific feature formed on each of the die units of the panel. For example, the position of at least onebond pad 105 on each of the plurality of die units on the panel can be measured. The specific position can be a variety of positions, such as a corner of thebond pad 105, a center of the bond pad, an outline of the bond pad, etc. Included in the position measurement may be the x-y position and/or orientation with respect to a global fiducial(s) on the panel. Any suitable inspection tool may be utilized to measure the true first position, such as an optical inspection tool. In an embodiment, a single feature is measured to obtain an x-y position of a die unit. In an embodiment, a plurality of features are measured to obtain an orientation of a die unit. - A build-up
structure 110 is formed over the panel including the plurality of die units. Referring again toFIG. 2B , a singulated package is illustrated with a completed build-upstructure 110. While the build-upstructure 110 is illustrated as being formed over a single package inFIG. 2B , it is understood that build-upstructure 110 is formed prior to singulation, and that a plurality of build-upstructures 110 are formed across the panel 102 and over each of the respective plurality ofdie units 152 on the panel 102 illustrated inFIG. 1A . - In an embodiment, the build-up
structure 110 is formed from adielectric material 115, from which features are patterned. Build-upstructure 110 may include a plurality of layers. For example, a separate dielectric layer may be formed in which the first via 112, RDL pattern 114, and UBM via 116, and/orUBM pad 119 are separately formed. In an embodiment, there may be multiple via and RDL patterned layers.Dielectric material 115 may be opaque or translucent, and different materials can be utilized for the separate dielectric layers. Where thedielectric material 115 is opaque, optical measurements of a feature may be measured prior to forming thedielectric material 115 over the underlying feature. Where thedielectric material 115 is translucent it is possible to measure the position of a feature below thedielectric material 115 before or after forming the dielectric material over the panel. - Based upon the true measured position for each of the respective die units, a specific pattern is created for each of the plurality of die units. The pattern is unit-specific for each of the respective die units, and therefore the unit-specific patterns may be different (e.g. x-y position, orientation, design) for each respective die unit so that each unit-specific pattern is aligned with each respective die unit, thereby compensating for misalignment of the individual die units. Each unit-specific pattern may be a common pattern aligned with the respective die unit. Each unit-specific pattern may also be uniquely created for each die unit in accordance with embodiments of the present disclosure.
- The pattern is then formed over each of the plurality of die units. In an embodiment, the pattern is a unit detail pattern formed in a build-up
structure 110 such as the first via 112 which connects thebond pad 105 to the RDL pattern 114, the RDL pattern 114, or the UBM pad pattern 119.As illustrated inFIG. 4 , the RDL pattern 114 ofFIG. 2B may include a first viacapture pad 118 aligned with the first via 112, a UBM viacapture pad 120 aligned with the UBM via 116, and atrace portion 122 connecting thecapture pads 121, 120. The patterned features in the build-upstructure 110 may be formed utilizing a mask-less patterning system. For example, a first via 112 or RDL pattern 114 may be created through exposure of a photo imagable polymer or photoresist through a direct writing. First via 112 or RDL pattern 114 may also be created through laser ablation ofdielectric material 115. - A number of methods are envisioned for creating a pattern for each of the plurality of die units based upon the measured position for each of the respective die units. In an embodiment, this may be accomplished by comparing the measured position of each of the plurality of die units to a number of defined nominal, reference positions. For example, a nominal, reference position of at least one feature on each of the plurality of die units can be defined with respect to a global fiducial(s) on the panel 102. The specific nominal, reference position can be a variety of positions, such as a corner of the
bond pad 105, a center of the bond pad, an outline of the bond pad, an alignment feature, etc. The specific nominal, reference position can also be the package outline, within which the die units will be packaged. Multiple features for each unit may be used in order to determine the orientation of the die within the unit. Included in the nominal, reference position may be the x-y position and/or orientation with respect to a global fiducial(s) on the panel. In an embodiment, defining a nominal, reference position includes generating an electronic panel map. For example, the nominal, reference position (x-y position and/or orientation) of each die unit in the panel can be defined in an electronic panel map. Though embodiments do not require a panel map, and the nominal, reference positions can be provided elsewhere. - In an embodiment, the position or design of the pattern is adjusted for each die unit to align with the measured position of the respective die unit in the panel. Design software can create a pattern design for each of the plurality of die units based upon the measured position of each of the die units in the panel. This pattern design may then be stored in a panel design file, in which the x-y position and/or orientation of the pattern is adjusted. The pattern may also be changed to optimize the pattern design for each die unit. A panel design file may be transferred to a mask-less patterning system to form at least the unit-specific pattern.
-
FIG. 5A illustrates a portion of a panel design in accordance with an embodiment of the present disclosure. The illustration provided inFIG. 5A is meant to be exemplary of a panel design in accordance with an embodiment of the present disclosure and is not meant to be limiting. As illustrated, an upper left-hand corner of an individual package outline is shown, however it is understood that the panel design may include additional or less information for the individual die package, and that the panel design may include similar information for each of the plurality of die units of the panel. - As illustrated in
FIG. 5A , the panel design may define nominal, reference positions for each die within the panel, as well as nominal, reference positions for yet to be formed features. In an embodiment, the nominal, reference positions for the die 152′ andbond pad 105′ are defined. Features which have not yet been formed over the panel may include nominal, reference positions for the first via 112′, die viacapture pad 118′, UBM via 116′, UBM viacapture pad 120′,RDL pattern trace 122′,UBM pad 119′, andpackage outline 130′ of a package to be singulated from the panel. -
FIG. 5B illustrates a misaligned die unit in accordance with an embodiment of the present disclosure. As illustrated, dieunit 152 is illustrated as being misaligned with respect to the nominal, reference dieunit position 152′ or global fiducial(s) on the panel (not illustrated). Likewise, the already formeddie pad 105 is illustrated as being misaligned with respect to the nominal, reference dieunit position 105′ or global fiducial(s) on the panel (not illustrated). - In an embodiment, a nominal, reference position of at least one feature on each of the plurality of die units is defined. For example, the nominal, reference position may be
die pad 105′. The true position of thedie bond pad 105 is measured for each of the plurality of die units on the panel. In accordance with embodiments of the disclosure, misalignment of the individual die units is determined when the measured position of thedie bond pad 105 has a different x-y position or orientation than that of the reference position of thedie bond pad 105′. - In an embodiment, the position of the patterned feature (e.g. first via 112, die via
capture pad 118, UBM via 116, UBM viacapture pad 120, RDL pattern trace 122) formed in the CSP build-upstructure 110 has a different x-y position or orientation than the nominal, reference position of the feature for at least one of the plurality of die units. In an embodiment, the formed first via 112 has a different x-y position as compared to the reference position of the first via 112′ for at least one of the plurality of die units. In an embodiment, the formed RDL pattern 114 has a different x-y position as compared to the reference position of the RDL pattern 114′ for at least one of the plurality of die units. In an embodiment, the formed RDL pattern 114 has a different x-y position and orientation as compared to the reference position of the RDL pattern 114′ for at least one of the plurality of die units. - In an embodiment, the amount of misalignment of the die unit in the x-y direction and/or orientation is measured by the inspection tool, and a delta-value between the nominal, reference position and measured position of the die unit is calculated for at least one of the plurality of die units. Based upon the delta-value, the pattern to be formed is created by adjusting the pattern from its reference position by the same delta-value. It is contemplated, however, that the patterned feature may not necessarily have to be formed with the same delta-value in accordance with embodiments of the disclosure.
- Other embodiments of the present disclosure may maintain the relative alignment of certain features within the end package. In the embodiment illustrated in
FIG. 5B , it is shown that the relative alignment between the first via 112, and thebond pad 105 and dieunit 152 is the same as the relative alignment illustrated inFIG. 5A between the nominal,reference positions 112′, 105′, 152′. In an embodiment, any of theportions FIG. 5B by the same delta-value between the true first position of thebond pad 105 and the referencebond pad position 105′. - In an embodiment, an additional feature may be formed over each of the plurality of die units without regard to the measured position of each of the respective plurality of die units. In accordance with embodiments of the present
disclosure UBM pad 119 is formed at the nominal,reference position 119′ without regard to the measured position of each of the respective plurality of die units. In the embodiment illustrated inFIG. 5B , position of the actual positions of theUBM pad 119 andpackage outline 130 are the same as the corresponding nominal,reference positions 108′, 130′. As illustrated, the actual position UBM via 116 may also be in the position as the nominal,reference position 116′. - Adjusting the position of a unit detail pattern formed in the CSP build-up structure to align with the measured position of each die in the panel may also include changing the RDL pattern design. In an embodiment, changing the RDL pattern design includes selecting a best-fit RDL pattern design from a discrete plurality of different design options. An illustration of a discrete plurality of different design options is provided in
FIG. 6 . For example, each quadrant I-IX represents a range of delta-values between the measured position of thebond pad 105 and the referencebond pad position 105′. By way of example, if the delta-value corresponds to point 140 inFIG. 6 , then the RDL pattern design for quadrant VI is selected. If the delta-value corresponds to point 142 inFIG. 6 , then the RDL pattern for quadrant IX is selected. In this manner the design tool can automatically generate a given best-fit pattern for each individual die based upon the corresponding delta-value for that specific die. For example each of the different design patterns associated with the quadrants can have different sizes, shapes, and/or orientations for the RDL pattern. WhileFIG. 6 illustrates a nine different design options, it is to be understood that any discrete number of different design options may be used. - In an embodiment, adjusting the position of a unit detail pattern formed in the CSP build-up structure to align with the measured position of each die in the panel includes changing the RDL pattern design with a dynamic design approach. For example, a customized RDL pattern may be dynamically generated for each specific die unit based upon the corresponding delta-values for each specific die unit.
- In application, several variations are envisioned in accordance with embodiments of the present disclosure. For example, the manner of adjusting a unit detail pattern formed in the CSP build-up structure may depend upon the amount of adjustment required to align the unit detail pattern with the respective die in the panel. In a first level operation, where the delta-value is minimal, it is contemplated that adjustment of the first via 112 position may be sufficient to compensate for misalignment of the
die 152. In a first variation, if the reference first viacapture pad 118′ no longer sufficiently overlaps the adjusted first via 112 position, then all or a portion of the RDL pattern 114 position may need to be adjusted by the same delta-value by which the first via 112 position was adjusted. In a second variation, where adjustment of the RDL pattern 114 position is not adequate, the design of the RDL pattern 114 may be changed so that the first viacapture pad 118 is aligned to the first via 112, and the UBM viacapture pad 120 is aligned with the UBM via 116. This may be accomplished by selecting a best-fit design of the RDL pattern 114 for each of the respective die units based upon the position of the delta-value in the quadrants illustrated inFIG. 6 , or dynamically designing a customized RDL pattern 114 for each die unit. - As described above, an adaptive patterning technique in accordance with embodiments of the present disclosure may be utilized to pattern features within a build-up
structure 100, such as a first via 112 and RDL pattern 114. In an embodiment, an adaptive patterning technique may be utilized for any structure within the build-up structure. For example, build-up structure may contain multiple layers, vias, and RDL patterns. In an embodiment, an adaptive patterning technique may include measurement of a first true position followed by adaptive patterning of a first via and RDL-1, then measurement of a second true position followed by adaptive patterning of a via-2 and RDL-2, then measurement of true position ‘n’ followed by adaptive patterning of a via-n and RDL-n. - In accordance with embodiments of the present disclosure, a lot of die packages may be singulated from a panel or reticulated wafer. The lot may be characterized by a unique statistical range of relative orientations. In conventional processes, where a plurality of die are misaligned across the panel, the statistical average across the lot for the misalignment of the first via 112 relative to the
respective die 152 outline for the lot is directly proportional to the statistical average of the misalignment of thedie 152 relative to thepackage outline 130. These relationships can be represented as follows: -
Δ(avg, lot)(112, 152)≈Δ(avg, lot)(152, 130) - In accordance with embodiments of the present disclosure, the first via 112 may be adjusted for each individual die to compensate for misalignment of the
respective die 152. Therefore, the statistical average across the lot for the misalignment of the first via 112 relative to therespective die 152 outline is considerably less than the statistical average of the misalignment of thedie 152 relative to thepackage outline 130. These relationships can be represented as follows: -
Δ(avg, lot)(112, 152)<<Δ(avg, lot)(152, 130) - In an embodiment, the statistical average across the lot for the misalignment of the first via 112 relative to the
respective die 152 outline is nill. -
Δ(avg, lot)(112, 152)=0 - Certain embodiments may be implemented as a computer program product that may include instructions stored on a non-transitory machine-readable medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations. A machine-readable medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). The machine-readable medium may include, but is not limited to, magnetic storage medium (e.g., floppy diskette); optical storage medium (e.g., CD-ROM); magneto-optical storage medium; read-only memory (ROM); random-access memory (RAM); erasable programmable memory (e.g., EPROM and EEPROM); flash memory; or another type of medium suitable for storing electronic instructions.
- Additionally, some embodiments may be practiced in distributed computing environments where the machine-readable medium is stored on and/or executed by more than one computer system. In addition, the information transferred between computer systems may either be pulled or pushed across the communication medium connecting the computer systems.
- The digital processing devices described herein may include one or more general-purpose processing devices such as a microprocessor or central processing unit, a controller, or the like. Alternatively, the digital processing device may include one or more special-purpose processing devices such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. In an alternative embodiment, for example, the digital processing device may be a network processor having multiple processors including a core unit and multiple microengines. Additionally, the digital processing device may include any combination of general-purpose processing devices and special-purpose processing devices.
- Embodiments of the present disclosure may be performed with an adaptive patterning system 700 as illustrated in
FIG. 7 . Operations may be performed by hardware components, software, firmware, or a combination thereof. Any of the signals provided over various buses 701 described herein may be time multiplexed with other signals and provided over one or more common buses. As illustrated, a panel or reticulated wafer 702 may be supplied to an inspection tool 704 which measures a position of a plurality of device units on the panel and creates a file 706 containing the measured position of each of the plurality of device units. Design software stored on server 708 then creates a pattern design file 710 for each of the plurality of device units based upon the measured position of each of the plurality of device units. A patterning machine 712 imports the pattern design and forms a patterned feature over each of the plurality of device units. The panel or reticulated wafer 702 is provided to a patterning machine 712 from the inspection tool 704. A patterned panel 714 may be output from the patterning machine 712. - In an embodiment, the design software further creates a new drawing for at least one layer of design, which is adjusted such that the first via and/or RDL pattern is aligned to the measured position of each of the plurality of device units. In an embodiment, the software includes an algorithm for adaptive patterning. For example, the algorithm may adjust the x-y position or orientation of a feature based upon a delta-value. In an embodiment, the algorithm may select a feature pattern from a discrete number of design options based upon a delta-value. In an embodiment, the algorithm may dynamically design a feature based upon a delta-value.
- The schematic illustration provided in
FIG. 7 is indicative of the order of a process in accordance with embodiments of the disclosure, however, it is not necessary that the actual equipment be arranged as illustrated. As illustrated, the design software is stored on a separate server 708, which can also store a panel map which includes nominal, reference positions of the plurality of device units on the panel. It is not required that the design software be stored on a separate server 708. For example, design software could be stored on the inspection tool 704 or patterning machine 712. It is possible to have all components integrated into a single system. - Server 708 can be utilized to control any part of or the entire adaptive patterning system 700. In an embodiment, server 708 includes memory 711 having instructions stored thereon, which when executed by a processor 709, cause the processor to instruct the inspection tool 704 to measure a position of each of a plurality of device units of a panel, create a unit-specific pattern for each of the respective plurality of device units based upon the measured position for each of the respective device units, and instruct the patterning tool 712 to form the unit-specific patterns over each of the plurality of device units, wherein each unit-specific pattern is aligned with the respective device unit. In an embodiment, creating a unit-specific pattern for each of the respective plurality of device units based upon the measured position for each of the respective device units may include adjusting an x-y position and/or orientation of at least one unit-specific pattern, selecting from a discrete number of design options, or dynamically generating the unit-specific pattern.
- In the foregoing specification, various embodiments have been described. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the inventions as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/775,425 US9418905B2 (en) | 2010-02-16 | 2013-02-25 | Adaptive patterning for panelized packaging |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US30512510P | 2010-02-16 | 2010-02-16 | |
US12/876,915 US8799845B2 (en) | 2010-02-16 | 2010-09-07 | Adaptive patterning for panelized packaging |
US13/775,425 US9418905B2 (en) | 2010-02-16 | 2013-02-25 | Adaptive patterning for panelized packaging |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/876,915 Continuation US8799845B2 (en) | 2010-02-16 | 2010-09-07 | Adaptive patterning for panelized packaging |
Publications (2)
Publication Number | Publication Date |
---|---|
US20130167102A1 true US20130167102A1 (en) | 2013-06-27 |
US9418905B2 US9418905B2 (en) | 2016-08-16 |
Family
ID=44370520
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/876,915 Active 2030-09-08 US8799845B2 (en) | 2010-02-16 | 2010-09-07 | Adaptive patterning for panelized packaging |
US13/775,425 Active 2031-10-13 US9418905B2 (en) | 2010-02-16 | 2013-02-25 | Adaptive patterning for panelized packaging |
US13/891,663 Active US9520331B2 (en) | 2010-02-16 | 2013-05-10 | Adaptive patterning for panelized packaging |
US13/893,117 Active US8826221B2 (en) | 2010-02-16 | 2013-05-13 | Adaptive patterning for panelized packaging |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/876,915 Active 2030-09-08 US8799845B2 (en) | 2010-02-16 | 2010-09-07 | Adaptive patterning for panelized packaging |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/891,663 Active US9520331B2 (en) | 2010-02-16 | 2013-05-10 | Adaptive patterning for panelized packaging |
US13/893,117 Active US8826221B2 (en) | 2010-02-16 | 2013-05-13 | Adaptive patterning for panelized packaging |
Country Status (4)
Country | Link |
---|---|
US (4) | US8799845B2 (en) |
CN (1) | CN102549732B (en) |
SG (1) | SG182715A1 (en) |
WO (1) | WO2011103216A2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100013082A1 (en) * | 2006-08-11 | 2010-01-21 | Megica Corporation | Chip package and method for fabricating the same |
US20110198762A1 (en) * | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9177926B2 (en) | 2011-12-30 | 2015-11-03 | Deca Technologies Inc | Semiconductor device and method comprising thickened redistribution layers |
US9576919B2 (en) | 2011-12-30 | 2017-02-21 | Deca Technologies Inc. | Semiconductor device and method comprising redistribution layers |
US8799845B2 (en) | 2010-02-16 | 2014-08-05 | Deca Technologies Inc. | Adaptive patterning for panelized packaging |
US8922021B2 (en) | 2011-12-30 | 2014-12-30 | Deca Technologies Inc. | Die up fully molded fan-out wafer level packaging |
US8604600B2 (en) * | 2011-12-30 | 2013-12-10 | Deca Technologies Inc. | Fully molded fan-out |
US10373870B2 (en) | 2010-02-16 | 2019-08-06 | Deca Technologies Inc. | Semiconductor device and method of packaging |
US9196509B2 (en) * | 2010-02-16 | 2015-11-24 | Deca Technologies Inc | Semiconductor device and method of adaptive patterning for panelized packaging |
US8269348B2 (en) * | 2010-02-22 | 2012-09-18 | Texas Instruments Incorporated | IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch |
CN102971674B (en) * | 2010-02-26 | 2015-07-15 | 密克罗尼克麦达塔公司 | Method and apparatus for performing pattern alignment |
WO2013102146A1 (en) | 2011-12-30 | 2013-07-04 | Deca Technologies, Inc. | Die up fully molded fan-out wafer level packaging |
US10050004B2 (en) | 2015-11-20 | 2018-08-14 | Deca Technologies Inc. | Fully molded peripheral package on package device |
US9831170B2 (en) | 2011-12-30 | 2017-11-28 | Deca Technologies, Inc. | Fully molded miniaturized semiconductor module |
US9613830B2 (en) | 2011-12-30 | 2017-04-04 | Deca Technologies Inc. | Fully molded peripheral package on package device |
US10672624B2 (en) | 2011-12-30 | 2020-06-02 | Deca Technologies Inc. | Method of making fully molded peripheral package on package device |
US8698323B2 (en) * | 2012-06-18 | 2014-04-15 | Invensas Corporation | Microelectronic assembly tolerant to misplacement of microelectronic elements therein |
WO2014071312A1 (en) * | 2012-11-05 | 2014-05-08 | Deca Technologies Inc. | Semiconductor device and method of adaptive patterning for panelized packaging |
KR102029645B1 (en) * | 2013-01-14 | 2019-11-18 | 삼성전자 주식회사 | Fabricating method for customized mask and fabricating method for semiconductor device using customized mask |
US9269622B2 (en) * | 2013-05-09 | 2016-02-23 | Deca Technologies Inc. | Semiconductor device and method of land grid array packaging with bussing lines |
KR101488608B1 (en) * | 2013-07-19 | 2015-02-02 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
NL2011575C2 (en) | 2013-10-08 | 2015-04-09 | Besi Netherlands B V | Method for positioning a carrier with electronic components and electronic component produced with such method. |
US9040316B1 (en) * | 2014-06-12 | 2015-05-26 | Deca Technologies Inc. | Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping |
US20160172243A1 (en) * | 2014-12-11 | 2016-06-16 | Nxp B.V. | Wafer material removal |
WO2016100560A1 (en) * | 2014-12-16 | 2016-06-23 | Deca Technologies Inc. | Method of marking a semiconductor package |
US9818659B2 (en) | 2015-10-12 | 2017-11-14 | Deca Technologies Inc. | Multi-die package comprising unit specific alignment and unit specific routing |
WO2017069738A1 (en) | 2015-10-20 | 2017-04-27 | Hewlett-Packard Development Company, L.P. | Patterned layer deposition |
KR102513427B1 (en) * | 2016-04-26 | 2023-03-24 | 삼성전자주식회사 | fan-out panel level package and fabrication method of the same |
US10157803B2 (en) | 2016-09-19 | 2018-12-18 | Deca Technologies Inc. | Semiconductor device and method of unit specific progressive alignment |
US10573601B2 (en) * | 2016-09-19 | 2020-02-25 | Deca Technologies Inc. | Semiconductor device and method of unit specific progressive alignment |
CN107887324B (en) | 2016-09-30 | 2019-09-13 | 上海微电子装备(集团)股份有限公司 | A kind of semiconductor rewiring method |
KR102582382B1 (en) | 2017-06-09 | 2023-09-25 | 나가세케무텍쿠스가부시키가이샤 | Epoxy resin composition, electronic component mounting structure, and method for manufacturing the same |
JP2019149507A (en) * | 2018-02-28 | 2019-09-05 | 東芝メモリ株式会社 | Semiconductor device and manufacturing method thereof |
JP2019178949A (en) * | 2018-03-30 | 2019-10-17 | 株式会社 Ngr | Image generation method |
KR102528016B1 (en) | 2018-10-05 | 2023-05-02 | 삼성전자주식회사 | Solder member mounting method and system |
TWI809201B (en) | 2018-10-23 | 2023-07-21 | 以色列商奧寶科技有限公司 | Adaptive routing for correcting die placement errors |
US10678150B1 (en) | 2018-11-15 | 2020-06-09 | Applied Materials, Inc. | Dynamic generation of layout adaptive packaging |
US11056453B2 (en) | 2019-06-18 | 2021-07-06 | Deca Technologies Usa, Inc. | Stackable fully molded semiconductor structure with vertical interconnects |
US11183482B2 (en) * | 2019-09-17 | 2021-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shift control method in manufacture of semiconductor device |
US11424167B2 (en) * | 2020-10-09 | 2022-08-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
EP4060410A1 (en) | 2021-03-17 | 2022-09-21 | Visitech Lithography AS | Digital direct recording device comprising real time analysis and correction of recorded artwork by dividing the artwork into submodules |
JP2022162313A (en) | 2021-04-12 | 2022-10-24 | 株式会社ニコン | Exposure device, exposure method, device manufacturing method and device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090278263A1 (en) * | 2008-05-09 | 2009-11-12 | Texas Instruments Incorporated | Reliability wcsp layouts |
Family Cites Families (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4722060A (en) * | 1984-03-22 | 1988-01-26 | Thomson Components-Mostek Corporation | Integrated-circuit leadframe adapted for a simultaneous bonding operation |
US4627151A (en) * | 1984-03-22 | 1986-12-09 | Thomson Components-Mostek Corporation | Automatic assembly of integrated circuits |
JPH03211757A (en) * | 1989-12-21 | 1991-09-17 | General Electric Co <Ge> | Hermetically sealed object |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5465217A (en) | 1993-08-16 | 1995-11-07 | Motorola, Inc. | Method for automatic tab artwork building |
US6335571B1 (en) * | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
EP1051745B1 (en) | 1998-01-28 | 2007-11-07 | Thin Film Electronics ASA | A method for generating electrical conducting or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating |
US6188301B1 (en) * | 1998-11-13 | 2001-02-13 | General Electric Company | Switching structure and method of fabrication |
US6249047B1 (en) | 1999-09-02 | 2001-06-19 | Micron Technology, Inc. | Ball array layout |
US6392301B1 (en) | 1999-10-22 | 2002-05-21 | Intel Corporation | Chip package and method |
JP2001257307A (en) | 2000-03-09 | 2001-09-21 | Sharp Corp | Semiconductor device |
US6537482B1 (en) | 2000-08-08 | 2003-03-25 | Micron Technology, Inc. | Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography |
DE10125029B4 (en) * | 2001-05-22 | 2008-08-21 | Qimonda Ag | Use of a Kerf-type subcircuit semiconductor device and method |
US6555400B2 (en) * | 2001-08-22 | 2003-04-29 | Micron Technology, Inc. | Method for substrate mapping |
JP2003186173A (en) | 2001-12-18 | 2003-07-03 | Fujitsu Ltd | Pattern forming method |
KR100442697B1 (en) * | 2002-03-11 | 2004-08-02 | 삼성전자주식회사 | Integrated Management System for automated wire bonding processes |
US6836023B2 (en) * | 2002-04-17 | 2004-12-28 | Fairchild Semiconductor Corporation | Structure of integrated trace of chip package |
JP4190269B2 (en) | 2002-07-09 | 2008-12-03 | 新光電気工業株式会社 | Device-embedded substrate manufacturing method and apparatus |
US6965160B2 (en) | 2002-08-15 | 2005-11-15 | Micron Technology, Inc. | Semiconductor dice packages employing at least one redistribution layer |
DE10334577B3 (en) | 2003-07-28 | 2005-02-10 | Infineon Technologies Ag | A method of applying a rewiring to a benefit by compensating for positional errors and semiconductor chips in component positions of the benefit |
US20050248022A1 (en) | 2004-05-10 | 2005-11-10 | Northern Microdesign, Inc. | High data rate chip mounting |
US7078272B2 (en) * | 2004-09-20 | 2006-07-18 | Aptos Corporation | Wafer scale integration packaging and method of making and using the same |
US7253528B2 (en) | 2005-02-01 | 2007-08-07 | Avago Technologies General Ip Pte. Ltd. | Trace design to minimize electromigration damage to solder bumps |
US7391107B2 (en) * | 2005-08-18 | 2008-06-24 | Infineon Technologies Ag | Signal routing on redistribution layer |
US7932615B2 (en) * | 2006-02-08 | 2011-04-26 | Amkor Technology, Inc. | Electronic devices including solder bumps on compliant dielectric layers |
US20080136004A1 (en) * | 2006-12-08 | 2008-06-12 | Advanced Chip Engineering Technology Inc. | Multi-chip package structure and method of forming the same |
US20080178127A1 (en) * | 2007-01-19 | 2008-07-24 | Thomas J Dewkett | Silicon Multiple Core or Redundant Unit Optimization Tool |
US20080197474A1 (en) * | 2007-02-16 | 2008-08-21 | Advanced Chip Engineering Technology Inc. | Semiconductor device package with multi-chips and method of the same |
US8786072B2 (en) | 2007-02-27 | 2014-07-22 | International Rectifier Corporation | Semiconductor package |
US20080237828A1 (en) * | 2007-03-30 | 2008-10-02 | Advanced Chip Engineering Technology Inc. | Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same |
US20080288908A1 (en) * | 2007-05-15 | 2008-11-20 | Mirror Semiconductor, Inc. | Simultaneous design of integrated circuit and printed circuit board |
US8053279B2 (en) | 2007-06-19 | 2011-11-08 | Micron Technology, Inc. | Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces |
US7772696B2 (en) | 2007-08-30 | 2010-08-10 | Nvidia Corporation | IC package having IC-to-PCB interconnects on the top and bottom of the package substrate |
US7767496B2 (en) | 2007-12-14 | 2010-08-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer |
US7928563B2 (en) | 2008-05-28 | 2011-04-19 | Georgia Tech Research Corporation | 3-D ICs with microfluidic interconnects and methods of constructing same |
US8350377B2 (en) * | 2008-09-25 | 2013-01-08 | Wen-Kun Yang | Semiconductor device package structure and method for the same |
US7979813B2 (en) * | 2009-01-15 | 2011-07-12 | Micrel, Inc. | Chip-scale package conversion technique for dies |
US8580612B2 (en) * | 2009-02-12 | 2013-11-12 | Infineon Technologies Ag | Chip assembly |
US8466542B2 (en) * | 2009-03-13 | 2013-06-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
US8445329B2 (en) | 2009-09-30 | 2013-05-21 | Ati Technologies Ulc | Circuit board with oval micro via |
US8084871B2 (en) | 2009-11-10 | 2011-12-27 | Maxim Integrated Products, Inc. | Redistribution layer enhancement to improve reliability of wafer level packaging |
US20110154277A1 (en) | 2009-12-18 | 2011-06-23 | Ankenbauer Christopher J | Method and apparatus for generating substrate layout |
US20110156240A1 (en) * | 2009-12-31 | 2011-06-30 | Stmicroelectronics Asia Pacific Pte. Ltd. | Reliable large die fan-out wafer level package and method of manufacture |
US8535978B2 (en) * | 2011-12-30 | 2013-09-17 | Deca Technologies Inc. | Die up fully molded fan-out wafer level packaging |
US8799845B2 (en) | 2010-02-16 | 2014-08-05 | Deca Technologies Inc. | Adaptive patterning for panelized packaging |
US8617935B2 (en) * | 2011-08-30 | 2013-12-31 | Freescale Semiconductor, Inc. | Back side alignment structure and manufacturing method for three-dimensional semiconductor device packages |
-
2010
- 2010-09-07 US US12/876,915 patent/US8799845B2/en active Active
-
2011
- 2011-02-16 WO PCT/US2011/025129 patent/WO2011103216A2/en active Application Filing
- 2011-02-16 SG SG2012054995A patent/SG182715A1/en unknown
- 2011-02-16 CN CN201180001658.9A patent/CN102549732B/en active Active
-
2013
- 2013-02-25 US US13/775,425 patent/US9418905B2/en active Active
- 2013-05-10 US US13/891,663 patent/US9520331B2/en active Active
- 2013-05-13 US US13/893,117 patent/US8826221B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090278263A1 (en) * | 2008-05-09 | 2009-11-12 | Texas Instruments Incorporated | Reliability wcsp layouts |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100013082A1 (en) * | 2006-08-11 | 2010-01-21 | Megica Corporation | Chip package and method for fabricating the same |
US9391021B2 (en) | 2006-08-11 | 2016-07-12 | Qualcomm Incorporated | Chip package and method for fabricating the same |
US9899284B2 (en) | 2006-08-11 | 2018-02-20 | Qualcomm Incorporated | Chip package and method for fabricating the same |
US11031310B2 (en) | 2006-08-11 | 2021-06-08 | Qualcomm Incorporated | Chip package |
US20110198762A1 (en) * | 2010-02-16 | 2011-08-18 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
US20140225271A1 (en) * | 2010-02-16 | 2014-08-14 | Deca Technologies Inc. | Panelized packaging with transferred dielectric |
Also Published As
Publication number | Publication date |
---|---|
US9418905B2 (en) | 2016-08-16 |
US20130249088A1 (en) | 2013-09-26 |
WO2011103216A2 (en) | 2011-08-25 |
CN102549732B (en) | 2016-03-23 |
US8826221B2 (en) | 2014-09-02 |
SG182715A1 (en) | 2012-09-27 |
US8799845B2 (en) | 2014-08-05 |
WO2011103216A3 (en) | 2012-01-05 |
US20130241074A1 (en) | 2013-09-19 |
US9520331B2 (en) | 2016-12-13 |
US20110202896A1 (en) | 2011-08-18 |
CN102549732A (en) | 2012-07-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9418905B2 (en) | Adaptive patterning for panelized packaging | |
US9887103B2 (en) | Semiconductor device and method of adaptive patterning for panelized packaging | |
US9978655B2 (en) | Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping | |
KR20180030391A (en) | Semiconductor packages having dummy connectors and methods of forming same | |
US20110285030A1 (en) | Method for producing chip packages, and chip package produced in this way | |
US8656333B1 (en) | Integrated circuit package auto-routing | |
US8835193B2 (en) | Non-uniform alignment of wafer bumps with substrate solders | |
US10573601B2 (en) | Semiconductor device and method of unit specific progressive alignment | |
KR102311442B1 (en) | Lithography process for semiconductor packaging and structures resulting therefrom | |
US20220077108A1 (en) | Shift control method in manufacture of semiconductor device | |
Sandstrom et al. | Scaling M-series™ for chiplets | |
KR102197228B1 (en) | Semiconductor device and method of unit-specific progressive alignment | |
US11972966B2 (en) | Method of manufacturing a semiconductor package including correcting alignment error while forming redistribution wiring struture | |
TWI757639B (en) | Semiconductor device and method of forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: DECA TECHNOLOGIES INC, ARIZONA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OLSON, TIMOTHY L.;SCANLAN, CHRISTOPHER M.;REEL/FRAME:029866/0131 Effective date: 20130131 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FEPP | Fee payment procedure |
Free format text: SURCHARGE FOR LATE PAYMENT, LARGE ENTITY (ORIGINAL EVENT CODE: M1554); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
AS | Assignment |
Owner name: DECA TECHNOLOGIES USA, INC., ARIZONA Free format text: CHANGE OF NAME;ASSIGNOR:DECA TECHNOLOGIES INC.;REEL/FRAME:055017/0342 Effective date: 20201222 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |