TWI757639B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device includes a molding compound encapsulating a first integrated circuit die and a second integrated circuit die; a dielectric layer over the molding compound, the first integrated circuit die, and the second integrated circuit die; and a metallization pattern over the dielectric layer and electrically connecting the first integrated circuit die to the second integrated circuit die. The metallization pattern comprises a plurality of conductive lines. Each of the plurality of conductive lines extends continuously from a first region of the metallization pattern through a second region of the metallization pattern to a third region of the metallization pattern; and has a same type of manufacturing anomaly in the second region of the metallization pattern.

Description

Semiconductor element and method of forming the same

Embodiments of the present invention relate to a semiconductor device and a method for forming the same.

The semiconductor industry has undergone rapid growth due to ongoing improvements in the bulk density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). Primarily, improvements in bulk density, which allow more components to be integrated into a given area, result from iterative reductions in minimum feature size. As the demand for shrinking electronic components has grown, the need for smaller and more inventive packaging techniques for semiconductor dies has arisen. An example of such packaging systems is Package-on-Package (PoP) technology. In PoP devices, the top semiconductor package is stacked on top of the bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor components with enhanced functionality and a small footprint on a printed circuit board (PCB).

According to an embodiment of the present invention, a semiconductor device includes a mold compound, a dielectric layer, and a metallization pattern. The molding compound encapsulates the first integrated circuit die and the second integrated circuit die. A dielectric layer is located on the mold compound, the first product the bulk circuit die and above the second integrated circuit die. a metallization pattern is on the dielectric layer and electrically connects the first integrated circuit die to the second integrated circuit die, wherein the metallization pattern includes a plurality of wires, and wherein the each of a plurality of conductive lines: extending continuously from a first region of the metallization pattern through a second region of the metallization pattern to a third region of the metallization pattern; and at the metallization pattern The second zone has the same type of manufacturing anomaly.

According to an embodiment of the present invention, a method of forming a semiconductor device includes: encapsulating a first integrated circuit die and a second integrated circuit die in a molding compound; depositing a seed layer over the second integrated circuit die and the mold compound; depositing a photoresist over the seed layer; performing a first exposure process on the first patterned region of the photoresist to defining a first exposure area; after performing the first exposure process, a second exposure process is performed on the second patterned area of the photoresist to define a second exposure area, wherein the first patterned area and the the second patterned regions overlap in the tiling region; developing the photoresist to define a first opening extending from the first patterned region through the tiling region to the second pattern plating a conductive material in the first opening, wherein the conductive material electrically connects the first integrated circuit die and the second integrated circuit die; and removing the photoresist.

According to an embodiment of the present invention, a method of forming a semiconductor device includes depositing a photoresist over a first die, a second die, and a molding compound, wherein the molding compound is disposed to surround the first die and the second die; perform a first exposure process on the first patterned area of the photoresist using a first reticle; after performing the first exposure process, use a second reticle A second exposure process is performed on the second patterned region of the photoresist, wherein the first patterned region and all The second patterned area overlaps in a splicing area, wherein performing the first exposure process includes placing the first triangular opening of the first reticle directly above the splicing area, and wherein performing the first exposure process The second exposure process includes placing the second triangular opening of the second reticle directly above the splicing area; developing the photoresist to define a third opening in the photoresist, wherein the a third opening extends from the first patterned region through the spliced region to the second patterned region; and a conductive material is plated in the third opening, wherein the conductive material connects the first A die is electrically connected to the second die.

100: carrier substrate

100A: The first package area

100B: Second packaging area

100C: District

102: Release Layer

104, 108, 132, 140, 148, 156: Dielectric layer

106, 138, 138A, 138B, 138C, 146, 154: Metallization pattern

110: Back-side wiring structure

112, 506: perforation

114: integrated circuit die

116: Adhesive

118: Semiconductor substrate

120: Interconnect structure

122, 162: padding

124: Passivation film

126: Die connector

128: Dielectric Materials

130: Sealing body

132A, 132B, 204A, 204B, 204D, 204F: Exposure area

133: seed layer

160: Front-focused wiring structure

166, 514: Conductive connectors

184: Sawing

190: Tape

200: Integrated fan-out package

200A: First patterned area

200B: Second patterned area

200C, 200E, 200G, 200H: Splicing area

200D, 200F: Patterned area

202A, 202B, 206A, 206B, 206D, 206F: Reduction mask

204: Photoresist

208: Overlap

209A, 209C, 209D, 306, 308: Arrow

210A, 210B: Curve

212: Opening

302: Alignment Mark

503, 504, 552: Bond pads

304, 304A, 304B, 304C: Overlapping markers

510: Wire Bonding

400, 500: package body

502, 550: base

508, 508A, 508B: stacked die

512: Molding Materials

570: Package Structure

Aspects of the present disclosure are best understood from the following description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1-3, 4A, 4B, 5-10, 11A, 11B, 11C, 12A, 12B, and 12C illustrate differences in intermediate steps of fabricating a semiconductor package according to various embodiments view.

12D shows exposure intensity curves for a lithography process in accordance with various embodiments.

13A, 13B, 13C, 13D, 14A, 14B, 15, 16A, 16B, 16C, 16D, 16E, 16F, and 17-27 illustrate diagrams according to various embodiments Different views of the intermediate steps in the manufacture of semiconductor packages.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature over or over a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include additional features that may be formed between the first feature and the second feature. Embodiments are formed between the second features such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description herein, spatially relative terms such as "below," "below," "lower," "above," "upper," and similar terms may be used to describe a component or the relationship of a feature to another member or feature as shown in the drawings. In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments for integrated fan-out (InFO) lithography processes are described below. It should be understood, however, that the various embodiment methods and resulting structures described herein may be applied to any type of semiconductor package, including, for example, chip on wafer on substrate (CoWoS) packaging, fan-in (fan-in) -in) package or similar.

Various embodiments provide a stitching lithography process for large integrated chip packages to achieve a multifunctional system. Embodiment The splicing lithography process is not limited by the exposure field size of the lithography stepper. self-viewing The viewing angle, the field size of the lithography stepper depends on the size of the optical lens. For example, the resulting pattern of photoresist masks obtainable using a single exposure step is limited by the diameter of the optical lens, and is often further limited by placement on the optical axis to reduce optical aberration. In addition, the pattern edge of the mask is typically spaced from the physical edge of the optical lens to avoid image distortion. This further limits the size of the pattern that can be obtained using a single exposure step.

For the integration of large field sizes, the desired pattern size of the layers is typically large, and increasing the optical lens size to accommodate the desired pattern size is expensive and may be impractical. Example stitching lithography processes use multiple exposure steps with multiple reticle masks to define large field size integrated patterns without increasing the optical lens size. For example, the layer is exposed to the first pattern in the first patterned region of the layer using a first reticle, and the layer is exposed to the first pattern in the second patterned region of the layer using a second reticle Two patterns. The first patterned region of the layer overlaps the second patterned region, the overlap allowing the first and second patterns to interconnect and to define a stitching together and extending through the first and second patterned regions the entire desired pattern. A region where the first patterned region and the second patterned region overlap can be referred to as a stitching region. During each exposure step within a tile (eg, referred to as a grey tone pattern), the shape of the pattern (eg, triangles) may be adapted to reduce the effects of exposure steps, eg, performed on the tile patterning defects caused by overexposure.

Additionally, the depth of field (DoF) associated with low NA steppers is relatively large compared to high numerical aperture (NA) steppers, so embodiments may use low NA steppers to reduce Small stitching error. Low NA steppers can be used for large critical dimension (CD) applications with the added benefit of cost reduction compared to high NA steppers.

By using stitching lithography, the field volume size is no longer limited by the size of the exposure field (eg, the size of each optical lens). For example, the size of a pattern in a layer can be enlarged by splicing patterns of different masks in different splice regions. Further use of gray-tone patterns and low NA steppers can increase tolerance at the splices and reduce manufacturing defects at the splices.

Various embodiments may realize one or more of the following non-limiting advantages/features: large field sizes of semiconductor packages are achieved by splicing different mask patterns at the splices when the interconnects span the splices; if If the alignment marks of the previous process are placed outside the field, the package size will be expanded in one direction; if the alignment marks are placed in the field, the package size will be expanded without borders; gray-tone patterns and low NA steppers have Higher tolerance to control the critical dimension (CD) of interconnects at the splice region; lower cost; and high yield.

1-27 illustrate cross-sectional views of intermediate steps during a process for forming a first package structure, such as forming an InFO packaged component, in accordance with some embodiments. FIG. 1 shows a carrier substrate 100 and a release layer 102 formed on the carrier substrate 100 . A first package area 100A and a second package area 100B are shown for forming the first package body and the second package body, respectively.

The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 100 may be a wafer such that a plurality of packages may be simultaneously formed on the carrier substrate 100 . The release layer 102 may be formed of a polymer-based material, which, along with the carrier substrate 100, may be removed from an overlying structure to be formed in a subsequent step. In some embodiments, the release layer 102 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 102 may be damaged upon exposure to UV light Ultra-violet (UV) adhesives that lose their adhesive properties. The release layer 102 may be formulated as a liquid and cured, may be a laminated film laminated to the carrier substrate 100, or may be the like. The top surface of the release layer 102 can be leveled and can be highly planar.

In FIG. 2, a dielectric layer 104 and a metallization pattern 106 are formed. As shown in FIG. 2 , a dielectric layer 104 is formed on the release layer 102 . The bottom surface of the dielectric layer 104 may be in contact with the top surface of the release layer 102 . In some embodiments, the dielectric layer 104 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 104 is formed of: nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (borosilicate glass) glass; BSG), boron-doped phosphosilicate glass (BPSG) or the like; or the like. The dielectric layer 104 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or combinations thereof.

A metallization pattern 106 is formed on the dielectric layer 104 . As an example of forming the metallization pattern 106 , a seed layer (not shown) is formed over the dielectric layer 104 . In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed on the seed layer and patterned. Photoresist can be formed by spin coating or similar methods and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 106 . One or more exposure steps can be applied to the photoresist to define the metallization Pattern 106 . After one or more exposures, the photoresist is developed to form openings through the photoresist to expose the seed layer. An embodiment stitching lithography process (eg, as discussed with reference to FIGS. 10-16F ) may be employed to define the metallization pattern 106 . Alternatively, multiple exposure steps may be used to define the metallization pattern 106, with each exposure step (eg, at any splice) defining a separate pattern that is not interconnected.

A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. Subsequently, the photoresist and the portion of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by acceptable ashing or lift-off processes, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern 106 .

In FIG. 3 , an optional dielectric layer 108 is formed on the metallization pattern 106 and the dielectric layer 104 . In some embodiments, dielectric layer 108 is formed of similar materials and using similar methods as dielectric layer 106 . Subsequently, the dielectric layer 108 is patterned to form openings to expose portions of the metallization pattern 106 . Patterning may be performed by acceptable processes, such as by exposing the dielectric layer 108 to light when the dielectric layer is a photosensitive material or by etching using, for example, anisotropic etching.

Dielectric layer 104 and dielectric layer 108 and metallization pattern 106 may be referred to as backside wiring structure 110 . As shown, the backside wiring structure 110 includes two dielectric layers 104 and 108 and a metallization pattern 106 . In other embodiments, the backside wiring structure 110 may include any number of dielectric layers, metallization patterns, and vias. can be used to form the metallization pattern 106 and the dielectric layer 108 by repeating the process to form one or more additional metallization patterns and dielectric layers in the backside wiring structure 110 . Vias may be formed by forming a seed layer and conductive material of the metallization pattern in the openings under the dielectric layer during formation of the metallization pattern. The vias can thus interconnect and electrically couple the various metallization patterns. In other embodiments, the backside wiring structure 110 may be omitted entirely, such that the features described later are formed directly on the release layer 102 .

In addition, in FIG. 3, a plurality of through holes 112 are formed. As an example of forming the via 112 , an optional seed layer is formed over the backside wiring structure 110 , such as exposed portions of the dielectric layer 108 and the metallization pattern 106 . In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed on the seed layer and patterned. Photoresist can be formed by spin coating or similar methods and can be exposed to light for patterning. The pattern of the photoresist corresponds to the through hole 112 . One or more exposure steps may be applied to the photoresist to define the vias 112 . After one or more exposures, the photoresist is developed to form openings through the photoresist to expose the seed layer.

A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. The photoresist and the portion of the seed layer where no conductive material is formed are removed. The photoresist can be removed by acceptable ashing or lift-off processes, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The seed layer and the remainder of the conductive material form through holes 112 . Alternatively, in embodiments where the dielectric layer 108 is omitted (see, eg, FIG. 4B ), the seed layer may also be omitted and the metallization pattern 106 may be used as a seed for plated vias 112 layer. For example, in such embodiments, the vias 112 may be plated directly on the metallization pattern 106 .

In FIG. 4A , a plurality of integrated circuit dies 114 are adhered to the dielectric layer 108 by an adhesive 116 . As shown in FIG. 4A, two integrated circuit dies 114 are attached in each of the first package area 100A and the second package area 100B, and in other embodiments, more or less area A bulk circuit die 114 may be attached in each region. For example, in one embodiment, only one type of IC die 114 may be attached in each region, or three or more IC dies 114 may be attached in each region. The integrated circuit die 114 may be a logic die (eg, central processing unit, microcontroller, etc.), a memory die (eg, dynamic random access memory (DRAM) die, static random access memory (DRAM) die, etc. memory (static random access memory; SRAM) die, etc.), power management die (such as power management integrated circuit (PMIC) die), radio frequency (radio frequency; RF) die, sensing device die, micro-electro-mechanical-system (MEMS) die, signal processing die (such as digital signal processing (DSP) die), front-end die (such as analog front-end (analog) die front-end; AFE) die), the like, or a combination thereof. Furthermore, in some embodiments, the integrated circuit dies 114 can be of different sizes (eg, different heights and/or surface areas), and in other embodiments, the integrated circuit dies 114 can be of the same size (eg, the same height and / or surface area).

The integrated circuit die 114 may be processed to form integrated circuits in the integrated circuit die 114 according to a suitable manufacturing process prior to being attached to the carrier 100 . For example, the integrated circuit dies 114 each include a semiconductor substrate 118 such as doped or undoped silicon, or a semiconductor-on-insulator (SOI) Active layer of the substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates can also be used, such as multilayer substrates or gradient substrates. Elements such as transistors, diodes, capacitors, resistors, etc. may be formed in and/or on the semiconductor substrate 118 and may be formed by, for example, in one or more dielectric layers on the semiconductor substrate 118 The interconnect structure 120 formed by the metallization pattern is interconnected to form an integrated circuit.

The plurality of integrated circuit dies 114 further include a plurality of pads 122, such as aluminum pads, to which the pads are connected externally. A plurality of pads 122 are located on respective active sides of what may be referred to as the integrated circuit die 114 . Passivation film 124 is on integrated circuit die 114 and on portions of pad 122 . The opening penetrates the passivation film 124 to the pad 122 . A plurality of die connectors 126 such as conductive pillars (eg, including metal such as copper) extend through passivation film 124 and are mechanically and electrically coupled to corresponding pads 122 . Die connectors 126 may be formed by, for example, plating or the like. The die connectors 126 are electrically coupled to the respective integrated circuits of the integrated circuit die 114 .

Dielectric material 128 is on the active side of integrated circuit die 114 , such as on passivation film 124 and die connectors 126 . The dielectric material 128 encapsulates the die connectors 126 laterally, and the dielectric material 128 is laterally coterminous with the corresponding integrated circuit die 114 . The dielectric material 128 can be a polymer such as PBO, polyimide, BCB or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG or the like; or a combination thereof, and may be formed, for example, by spin coating, lamination, CVD, or the like.

The adhesive 116 is on the backside of the IC die 114 and attaches the IC The die 114 is attached to the backside wiring structure 110, such as the dielectric layer 108 in FIG. 4A. Alternatively, in embodiments when dielectric layer 108 is omitted, adhesive 116 may adhere the integrated circuit die to metallization pattern 106 and dielectric layer 104, such as shown in FIG. 4B. In such embodiments, the adhesive 116 may extend along the top surface and sidewalls of the metallization pattern 106 . The adhesive 116 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 116 may be applied to the backside of the integrated circuit die 114 , such as the backside of the corresponding semiconductor wafer, or may be applied to the surface of the carrier substrate 100 . The integrated circuit die 114 may be singulated, such as by sawing or dicing, and attached to the backside wiring structure 110 by the adhesive 116 using, for example, a pick-and-place method.

In FIG. 5, a sealing body 130 is formed on various components. The encapsulant 130 may be molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. After curing, the encapsulant 130 may undergo a grinding process to expose the through holes 112 and the die connectors 126 . After the grinding process, the top surfaces of the vias 112 , the die connectors 126 and the encapsulant 130 are coplanar. In some embodiments, grinding may be omitted, eg, if the vias 112 and die connectors 126 have been exposed.

In FIGS. 6 to 21 , the front side wiring structure 160 is formed. As will be shown in FIG. 21, the front side wiring structure 160 includes a dielectric layer 132, a dielectric layer 140, a dielectric layer 148, and a dielectric layer 156, and a metallization pattern 138, a metallization pattern 146, and a metallization pattern 154.

In FIG. 6 , a dielectric layer 132 is deposited on the encapsulant 130 , the vias 112 and the die connectors 126 . In some embodiments, the dielectric layer 132 is formed of a polymer, which may be a photosensitive material that can be patterned using a lithographic mask, such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric layer 132 is composed of the following or form: nitrides, such as silicon nitride; oxides, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 132 may be formed by spin coating, lamination, CVD, the like, or a combination thereof.

In FIGS. 7-9, the dielectric layer 132 is subsequently patterned. Openings are patterned to expose portions of vias 112 and die connectors 126 . When the dielectric layer 132 is a photosensitive material, a lithography process can be used to achieve patterning.

An embodiment lithography process for patterning the dielectric layer 132 may include performing multiple exposure steps in each encapsulation area (eg, the first encapsulation area 100A and the second encapsulation area 100B) on the carrier substrate 100 . For example, in FIG. 7 , the first package area 100A is divided into a first patterned area 200A and a second patterned area 200B. The first patterned area 200A and the second patterned area 200B overlap in the splicing area 200C.

In FIG. 7, a first exposure is performed on the dielectric layer 132 in the first patterned region 200A using the first reticle 202A. Thus, a plurality of exposed regions 132A of the dielectric layer 132 are formed. The size of the reticle 202A may correspond to the size (eg, diameter) of the lens used by the NA stepper to expose the dielectric layer 132 in the first patterned region 200A. For example, in a top view (not shown), the reticle 202A may have a length of about 52 millimeters and a width of about 34 millimeters to correspond to an optical lens for exposing the dielectric layer 132 . Other sizes of reticle 202A are also possible. Additionally, a low NA stepper (eg, with an NA of less than 0.2) can be used to increase the DoF of the patterning process and reduce cost. As a result of the increased DoF, patterning defects caused by warpage of various features can be advantageously reduced. Because the package wafer is relatively large, it may be particularly susceptible to warpage, which increases the top surface topography of the dielectric layer 132 . By providing an increased DoF, patterning defects caused by warpage and increased topography can be reduced. Due to the patterned features in the redistribution structure 160 (see FIG. 21 ) For relatively large feature sizes (eg, critical dimensions), a low NA stepper may be used in various embodiments.

Next, in FIG. 8, a second exposure is performed on the dielectric layer 132 in the second patterned region 200B using the second reticle 202B. Thus, a plurality of exposed regions 132B of the dielectric layer 132 are formed. The size of the reticle 202B may correspond to the size (eg, diameter) of the lens used by the NA stepper to expose the dielectric layer 132 in the patterned region 200B. For example, in a top view (not shown), the reticle 202B may have a length of about 52 millimeters and a width of about 34 millimeters to correspond to an optical lens for exposing the dielectric layer 132 . Other sizes of reticle 202B are also possible. Additionally, a low NA stepper (eg, with an NA of less than 0.2) can be used to increase the DoF of the patterning process and reduce cost. As a result of the increased DoF, patterning defects caused by warpage and increased topography of the dielectric layer 132 may be reduced. Due to the relatively large feature size (eg, critical dimension) of the patterned features in the redistribution structure 160 (see FIG. 21 ), a low NA stepper may be used in various embodiments.

In this way, opening patterns through the dielectric layer 132 are defined in the first encapsulation region 100A. The total size of the opening pattern in the first encapsulation area 100A does not need to be limited by the physical size of the optical lens for exposing the dielectric layer 132, because multiple exposure steps and photomasks can be enlarged and formed in each encapsulation area 100A and the size of the package body in the package area 100B.

Similar exposure steps may be performed in other encapsulation areas on the carrier substrate 100 (eg, in the second encapsulation area 100B) to define the desired pattern in the dielectric layer 132 . The exposing of the second encapsulation area 100B may be performed after all exposure steps in the first encapsulation area 100A are completed. Alternatively, each reticle (eg, the first reticle) is used to expose the dielectric layer 132 before subsequent reticles (eg, the second reticle 202B) A photomask 202A) can be used to expose each package area on the carrier substrate 100 .

In FIG. 9 , after exposing various patterned and encapsulated regions of dielectric layer 132 , dielectric layer 132 is developed to form openings extending through dielectric layer 132 . The openings may expose portions of the vias 112 and die connectors 126 . FIG. 9 shows the dielectric layer 132 as a positive photoresist material, wherein the exposed areas 132A/132B are removed due to the development of the dielectric layer 132 . In other embodiments, the dielectric layer 132 may be a negative photoresist, wherein the exposed areas 132A/132B of the dielectric layer 132 remain, while the unexposed areas of the dielectric layer 132 are removed as a result of development remove.

In FIGS. 10-16F , a metallization pattern 138 having a plurality of vias is formed on the dielectric layer 132 . As an example of forming the metallization pattern 138 , a seed layer 133 is formed over the dielectric layer 132 and in openings through the dielectric layer 132 . In some embodiments, the seed layer 133 is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer 133 includes a titanium layer and a copper layer over the titanium layer. The seed layer 133 may be formed using, for example, PVD or the like.

Photoresist 204 is then formed and patterned on seed layer 133 . Photoresist 204 can be formed by spin coating or similar methods and can be exposed to light for patterning. Multiple exposure processes (eg, tile lithography) as described below will be used to expose multiple areas of the photoresist. After multiple exposure processes, a single development process is performed to remove exposed or unexposed portions, depending on whether negative photoresist or positive photoresist is used.

In FIG. 11A, a first exposure is performed on the photoresist 204 in the first patterned area 200A using the first photomask 206A. A plurality of exposed regions 204A of the photoresist 204 are thus formed. The size of the reticle 202A may correspond to the size (eg, diameter) of the lens, The lens is used by the NA stepper to expose the photoresist 204 in the first patterned region 200A. For example, in a top view (not shown), the reticle 206A may have a length of about 52 millimeters and a width of about 34 millimeters to correspond to an optical lens for exposing the photoresist 204 . Other sizes of reticle 206A are also possible. Additionally, a low NA stepper (eg, with an NA of less than 0.2) can be used to increase the DoF of the patterning process and reduce cost. As a result of the increased DoF, patterning defects caused by warpage and increased topography of the dielectric layer 132 may be reduced. Due to the relatively large feature size (eg, critical dimension) of the patterned features in the redistribution structure 160 (see FIG. 21 ), a low NA stepper may be used in various embodiments.

The exposure area 204A extends to the splicing area 200C (eg, where the first patterned area 200A and the second patterned area 200B overlap). The reticle 206A may be designed to reduce the exposure dose applied to the photoresist 204 in the tiling region 200C compared to the area of the first patterned region 200A outside the tiling region 200C. For example, during the exposure step, light (eg, ultraviolet (UV) light) is projected onto the photoresist 204 through the reticle 206A. The openings in the reticle 206A allow light to impinge on the photoresist 204 , while the solid regions of the reticle 206A block light from impinging on the photoresist 204 . The shape and size of the openings in the reticle 206A can reduce the light transmittance in the tiling region 200C compared to the area of the first patterned region 200A outside the tiling region 200C. For example, the reticle 206A may allow the light transmittance in the first patterned area 200A outside the splicing area 200C to be 100%, while the reticle 206A may allow the transmittance of light in the splicing area 200C to be 100% The direction toward the second patterned region 200B gradually decreases from 100% to about 0%. This can be achieved by selecting an appropriate shape for the opening of the reticle 206A on the tile 200C and reducing the area of the opening in the reticle 206A on the tile 200C.

11B and 11C illustrate top views of exposed regions 204A in first patterned region 200A, both outside and within tiling region 200C, according to various embodiments. The shape of the exposure area 204A corresponds to the shape of the opening in the reticle 206A. As shown in FIGS. 11B and 11C , as the exposed area 204A extends to the tiling area 200C, the width of the exposed area 204A decreases, so that the exposed area 204A has a triangular shape in the tiling area 200C. The triangular shape of the exposure region 204A may span the entire tiled region 200C. For example, a triangular shape may start at a first edge of tile 200C and narrow to an apex at a second edge of tile 200C, opposite the first edge. In the tiling region 200C, the width of the exposure region 204A may decrease all the time (eg, as shown in FIG. 11B ) or discretely decrease at set intervals (eg, as shown in FIG. 11C ).

As a result of the embodiment shapes and varying widths of the exposure areas 204A, the exposure intensity of the exposure areas 204A decreases as the exposure areas 204A extend into the tiling area 200C. By configuring the exposure area 204A to have the shape shown in the splicing area 200C (eg, by configuring corresponding openings in the reticle 206A on the splicing area 200C), the exposure intensity in the splicing area 200C can also be changed. Gradually decreasing, this reduces overexposure defects and increases overlap tolerance, as will be described in detail below.

Next, in FIG. 12A, a second exposure is performed on the photoresist 204 in the second patterned region 200B using the second reticle 206B. A plurality of exposed regions 204B of the photoresist 204 are thus formed. The size of the reticle 202B may correspond to the size (eg, diameter) of the lens used by the NA stepper to expose the photoresist 204 in the first patterned area 200A. For example, in a top view (not shown), the reticle 206B may have a length of about 52 millimeters and a width of about 34 millimeters to correspond to the optical lens used to expose the photoresist 204 . Other sizes of reticle 206B are also possible. Additionally, a low NA stepper (eg, with an NA less than 0.2) can be used to increase the patterning capability Process DoF and reduce costs. As a result of the increased DoF, patterning defects caused by warpage and increased topography of the dielectric layer 132 may be reduced. Due to the relatively large feature size (eg, critical dimension) of the patterned features in the redistribution structure 160 (see FIG. 21 ), a low NA stepper may be used in various embodiments.

The exposure area 204B extends to the splicing area 200C (eg, where the first patterned area 200A and the second patterned area 200B overlap). The exposure area 204B may overlap the exposure area 204A in the tiling area 200C, so that the photoresist 204 is included from the first patterned area 200A (specifically, the area of the first patterned area 200A outside the tiling area 200C) passing through The splicing area 200C extends continuously to the splicing exposure area of the second patterning area 200B (specifically, the area of the second patterning area 200B outside the splicing area 200C).

Similar to the reticle 206A, the reticle 206B may be designed to reduce the exposure dose applied to the photoresist 204 in the tiling 200C compared to the area of the second patterned region 200B outside the tiling 200C. The shape and size of the openings in the reticle 206B can reduce the light transmittance in the tiling region 200C compared to the area of the second patterned region 200B outside the tiling region 200C. For example, the reticle 206B may allow the light transmittance in the second patterned area 200B outside the splicing area 200C to be 100%, while the slashing mask 206B may allow the transmittance of light in the splicing area 200C to be 100%. It gradually decreases from 100% to about 0% in the direction toward the first patterned region 200A. This can be achieved by choosing an appropriate shape for the opening of the reticle 206B on the tile 200C and reducing the area of the opening in the reticle 206B on the tile 200C.

12B and 12C illustrate top views of exposed areas 204A and 204B in the first and second patterned areas 200A and 200B, according to various embodiments. The shape of the exposure area 204B corresponds to the shape of the opening in the reticle 206B. As shown in FIGS. 12B and 12C, as the exposure area 204B extends to the splicing area 200C, The reduced width of the exposure area 204B causes the exposure area 204B to have a triangular shape in the tiling area 200C. The triangular shape of the exposure region 204B may span the entire tiled region 200C. For example, a triangular shape may start at the second edge of the tiling region 200C and narrow to an apex at the first edge of the tiling edge 200C. In the tiling region 200C, the width of the exposure region 204B may decrease all the time (eg, as shown in FIG. 12B ) or discretely decrease at set intervals (eg, as shown in FIG. 12C ).

As a result of the embodiment shapes and varying widths of the exposed regions 204B, the exposure intensity of the exposed regions 204B decreases as the exposed regions 204B extend into the tiling region 200C. By configuring the exposure area 204B to have the shape shown in the splicing area 200C (eg, by configuring corresponding openings in the reticle 206B on the splicing area 200C), the exposure area 204B within the splicing area 200C is The exposure intensity can also be gradually reduced, which reduces overexposure defects and increases overlap tolerance.

Exposure area 204A and exposure area 204B overlap at overlapping area 208 . When the exposure intensity in tiled region 200C is not reduced, overlapping region 208 may be overexposed (eg, with an exposure intensity of about 200%). By gradually reducing the exposure intensity of exposed areas 204A and 204B in stitched area 200C, the risk of overexposing overlapping areas 208 is reduced, as the exposure from the first exposure (eg, defining exposed area 204A) and the second exposure (eg, defining exposed area 204A) is reduced. The cumulative exposure intensity of overlapping regions 208 resulting from exposure region 204B) is reduced. For example, FIG. 12D shows the exposure intensity of the exposure area 204A and the exposure area 204B at each of the first patterned area 200A and the second patterned area 200B. In Figure 12D, the x-axis represents position and the y-axis represents exposure intensity. Curve 210A corresponds to the exposure intensity of exposure area 204A, and curve 210B corresponds to the exposure intensity of exposure area 204B. The slope of curve 210A and curve 210B in tile 200C may correspond to and depend on the distance across tile 200C that determines each exposure 204A/exposure The length of the triangular shape of 204B. The cumulative exposure intensity for any given location of photoresist 204 can be obtained by adding the corresponding intensities of curve 210A and curve 210B. As can be seen in Figure 12D, the cumulative exposure intensity at any given location in the first patterned region 200A and the second patterned region 200B is in the range of about 1 (eg, 100%) and about 1.2 (eg, 120%) . In particular, the cumulative exposure intensities in tiled region 200C (when two exposure steps are performed) are substantially the same as the cumulative exposure intensities outside tiled region 200C (when only one exposure step is performed). By reducing overexposure, defects caused by overexposure (eg, defining oversized features) are also reduced.

In addition, the triangular shape of the exposure area 204A and the exposure area 204B in the tiling area 200C can also improve the overlap tolerance. 13A, 13B, 13C, and 13D illustrate example overlap errors that may result from alignment errors between reticle 206A and reticle 206B. 13A shows an embodiment in which the reticle 206B is translated laterally in the direction indicated by arrow 209A toward the first patterned region 200A. Therefore, the exposure area 204B may extend to the area of the first patterned area 200A outside the tiling area 200C. Figure 13B shows an embodiment in which the reticle 206B is translated laterally in the direction indicated by arrow 209A toward the second patterned region 200B. Therefore, the exposure region 204B does not extend completely through the tiling region 200C. Figures 13C and 13D illustrate an embodiment where the vertical translation of the reticle 206B as indicated by arrows 209C and 209D causes the edges of the exposure areas 204A and 204B to be out of alignment. Although each of Figures 13A, 13B, 13C, and 13D shows a single overlap error, it should be understood that such errors may also be combined. It has been observed that by providing exposure regions 204A and 204B having a triangular shape, overlay errors in any direction as high as 10% are allowed, while still being within manufacturing tolerances.

Triangle of exposure area 204A and exposure area 204B in splicing area 200C The shape allows a linear change in exposure intensity such that any translation does not significantly affect the cumulative exposure intensity. For example, in FIG. 13A, the portion of the exposed area 204B in the first patterned area 200A outside the tiling area 200C may have a relatively low exposure intensity (eg, less than about 20%). Therefore, although the exposure area 204A in the first patterned area 200A outside the overlap area 200C is fully exposed (eg, having an exposure intensity of about 100%), the cumulative exposure intensity of the exposure area 204A and the exposure area 204B remains at about 120%, even though the overlap error shown in Figure 13A is within manufacturing tolerances. As another example, in FIG. 13B, the exposure area 204B does not extend to the area 200D of the spliced area 200C. For example, in region 200D, only one exposure is performed (ie, the exposure corresponds to exposure region 204A). However, because exposed area 204A has nearly sufficient exposure intensity (eg, at least 80%) in area 200D, the underexposure of the second exposure step does not result in unacceptably underexposed areas. For example, even with the overlap error shown in FIG. 13B , in region 200D, the cumulative exposure intensity of exposure region 204A and exposure region 204B remains at about 80%, which is still within manufacturing tolerances.

Therefore, the photoresist 204 is exposed using a plurality of reticle 206A/206B to extend the size of the pattern in the splice area. Although only two exposure steps are described above, it should be understood that any number of exposure steps may be applied to photoresist 204 . For example, if even larger areas are required, additional exposure steps may be applied. Each of the additional exposure steps may overlap the previous exposure steps in additional tiling regions. For example, Figures 14A and 14B illustrate multiple tiling regions. Different reticle 206A, reticle 206B, reticle 206D, and reticle 206F are used for patterning in different patterned areas 200A, 200B, 200D, and 200D of the wafer, respectively. A pattern is defined in area 200F. The patterned area 200A and the patterned area 200B overlap in the splicing area 200C; the patterned area 200A and the patterned area 200D are in the splicing area 200E patterned region 200B and patterned region 200F overlap in tiled region 200G; and patterned region 200D and patterned region 200F overlap in tiled region 200H. Exposed areas 204A and 204B extend through splicing area 200C; exposed areas 204A and 204D extend through splicing area 200E; exposed areas 204B and 204F extend through splicing area 200G; and exposed areas 204D and 204F extend through the splice region 200H. Alignment marks 302 are used to align reticle 206A, reticle 206B, reticle 206D, and reticle 206F with the pattern of the underlying layer (eg, the pattern of dielectric layer 132, see FIG. 10). Overlapping marks 304 are used to match the pattern of the reticle 206A, 206B, 206D, and 206F with the other reticle 206A, 206B, 206D and the reticle 206F alignment. For example, overlapping marks 304A can be used to align reticle 206A and reticle 206B; overlapping marks 304B can be used to align reticle 206B and 206D; and overlapping marks 304C can be used to align Reduced light cover 206A and reduced light cover 206F. The alignment marks (alignment mark 302 and overlapping mark 304) may overlap to reduce the area required for the alignment marks. When alignment marks 302 and overlapping marks 304 are placed outside of a patterned area (eg, patterned area 200A, patterned area 200B, etc.), the size of the pattern may be in one direction (eg, as indicated by arrow 306 in FIG. 14A ) indication) extension. When alignment marks 302 and overlapping marks 304 are placed inside a patterned area (eg, patterned area 200A, patterned area 200B, etc.), the size of the pattern can be in multiple directions (eg, as indicated by arrow 308 in FIG. 14B ) extension in the instruction). Furthermore, since multiple photomasks are used to stitch the pattern of layers together, the alignment marks 302 and overlapping marks 304 may surround the pattern (eg, as shown in FIG. 14A ) or through the pattern (eg, as shown in FIG. 14B ) Set at regular intervals. The spacing between adjacent alignment marks 302/overlapping marks 304 may correspond to the size of the reticle.

Thus, by providing multiple exposure steps, larger wafers can be patterned by using multiple photomasks to define overlapping patterns in the splices. A low NA lithography tool with a higher DoF can be used to apply multiple exposure steps to achieve a defined pattern even with warpage. The shape of the overlapping pattern may be triangular to reduce exposure intensity in the tiled regions. By reducing the exposure intensity, manufacturing tolerances can be improved and defects reduced. Alternatively, other shapes that reduce the exposure intensity in the tiling region may be employed to accommodate multiple exposure steps.

Similar exposure steps may be performed in other encapsulation areas on the carrier substrate 100 (eg, in the second encapsulation area 100B) to define the desired pattern in the photoresist 204 . The exposing of the second encapsulation area 100B may be performed after all exposure steps in the first encapsulation area 100A are completed. Alternatively, each reticle (eg, first reticle 206A) may be used to expose the carrier substrate 100B before a subsequent reticle (eg, second reticle 206B) is used to expose photoresist 204 of each package area.

In FIG. 15 , after the various patterned and encapsulated areas of photoresist 204 have been exposed, photoresist 204 is developed to form a plurality of openings 212 extending through photoresist 204 . Figure 15 shows the photoresist 204 as a positive photoresist material with the exposed areas 204A/204B removed as the photoresist 204 is developed. In other embodiments, the photoresist 204 may be a negative photoresist, wherein the exposed areas 204A/204B of the photoresist 204 remain, while the unexposed areas of the photoresist 204 are removed due to development.

Subsequently, in FIG. 16A, a conductive material is formed in the openings 212 by plating, such as electroplating or electroless plating or the like. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. Subsequently, portions of the photoresist 204 and the seed layer 133 where no conductive material is formed are removed. Photoresist 204 may be removed by acceptable ashing or lift-off processes, such as using oxygen plasma or the like. Once the photoresist 204 is removed, such as by Exposed portions of seed layer 133 are removed using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form metallization patterns 138 and vias. Vias are formed in openings through dielectric layer 132 to, for example, vias 112 and/or die connectors 126 .

FIG. 16A shows a cross-sectional view of the metallization pattern 138 . Figures 16B, 16C, 16D, 16E, and 16F show top views of the metallization patterns 138 in the region 100C (see Figure 16A). The region 100C includes a first patterned region 200A, a second patterned region 200B, and a portion of the tiling region 200C. The location of the metallization pattern 138 may further correspond to the exposure area 204A/exposure area 204B/exposure area 204D/exposure area 204F shown in FIGS. 14A and 14B . For example, the metallization pattern 138 may include wires disposed between adjacent alignment marks 302/overlapping marks 304.

In FIG. 16B , metallization patterns 138A, metallization patterns 138B, and metallization patterns 138C are formed without fabrication anomaly to define a continuous extension from patterned region 200A through splicing region 200C to patterned region 200B Conductive rewiring. In FIGS. 16C, 16D, 16E, and 16F, metallization pattern 138A, metallization pattern 138B, and metallization pattern 138C are formed with fabrication anomalies to define an extension from patterned region 200A through splicing region 200C to patterned region 200B of conductive rewiring. Because the manufacturing anomaly is due to overlay errors between the reticle (eg, reticle 206A and 206B), each of metallization pattern 138A, metallization pattern 138B, and metallization pattern 138C is The same type of manufacturing anomalies may be present within the splice region 200C. In FIG. 16C, a translation error occurs in the splice region 200C, which defines a manufacturing anomaly when the sidewalls of the metallization pattern 138A/metallization pattern 138B/metallization pattern 138C are no longer aligned. In FIG. 16D, metallization pattern 138A, metallization pattern 138B, and metallization pattern in splice region 200C There are gaps in each of 138C. This gap is acceptable, for example, when metallization patterns 138A, metallization patterns 138B, and metallization patterns 138C define dummy patterns. The gap size in each of metallization patterns 138A, metallization patterns 138B, and metallization patterns 138C may be the same. In FIG. 16E, each of metallization pattern 138A, metallization pattern 138B, and metallization pattern 138C in splice region 200C has a narrower region (eg, referred to as a neck). The amount by which each of metallization pattern 138A, metallization pattern 138B, and metallization pattern 138C narrows in tiling region 200C may be the same. The fabrication anomalies illustrated by Figures 16D and 16E may result from underexposure in the spliced region 200C (eg, as described above with respect to Figure 13B). In Figure 16F, each of metallization pattern 138A, metallization pattern 138B, and metallization pattern 138C in splice region 200C has a wider area (eg, referred to as dilation). Each of metallization pattern 138A, metallization pattern 138B, and metallization pattern 138C may widen by the same amount in tiling region 200C. The fabrication anomalies illustrated by FIG. 16F may result from overexposure in tiling region 200C (eg, as described above with respect to FIG. 13A ). Other manufacturing anomalies are also possible, but generally within manufacturing tolerances due to the embodiment patterning methods described above. In various embodiments, each metallization pattern in a spliced region (eg, spliced region 200C) may have the same type of fabrication anomalies, since these anomalies are the result of overlapping errors caused by multiple exposure steps, and the same Overlap errors will apply to the entire tiled region 200C. Typically, fabrication anomalies can be detected as shape differences between the desired pattern of conductive features defined in a reticle or layout file and the physical pattern of conductive features fabricated. In various embodiments, manufacturing anomalies within a single splice area may include non-uniform wires, wires with non-linear edges within each wire, wires with varying widths within each wire, or the like.

In FIG. 17 , a dielectric layer 140 is deposited over the metallization pattern 138 and the dielectric layer 132 . Dielectric layer 140 may be made of similar materials and deposited using similar processes as dielectric layer 132 . After the dielectric layer 140 is deposited, it may be patterned to form openings that expose portions of the metallization patterns 138 . The patterning of the dielectric layer 140 may be performed by an acceptable process, such as a process similar to the multiple exposure patterning process described above for patterning the dielectric layer 132 .

In FIG. 18 , a metallization pattern 146 with vias is formed on the dielectric layer 140 . Metallization pattern 146 may be made of similar materials and formed using similar processes as metallization pattern 138 . For example, a seed layer can be deposited, a photoresist can be deposited on the seed layer, multiple exposure lithography processes as described above can be applied to the photoresist to define openings for exposing the seed layer, a plating process can be performed A conductive material is plated on the exposed portions of the seed layer, and portions of the photoresist and the unformed conductive material on the seed layer are removed. The remaining portions of the seed layer and conductive material form metallization patterns 146 and vias. Vias are formed in openings through dielectric layer 140 to portions such as metallization patterns 138 .

In FIG. 19 , a dielectric layer 148 is deposited on the metallization pattern 146 and the dielectric layer 140 . Dielectric layer 148 may be made of similar materials and deposited using similar processes as dielectric layer 132 . After the dielectric layer 148 is deposited, it may be patterned to form openings that expose portions of the metallization patterns 146 . The patterning of the dielectric layer 148 may be performed by an acceptable process, such as a process similar to the multiple exposure patterning process described above for patterning the dielectric layer 132 .

In FIG. 20 , a metallization pattern 154 with vias is formed on the dielectric layer 148 . Metallization pattern 154 may be made of similar materials and formed using similar processes as metallization pattern 138 . For example, a seed layer can be deposited, a photoresist can be deposited on the seed layer, and multiple exposure lithography processes as described above can be applied to the photoresist to define the exposure Exposing the opening of the seed layer, a plating process can be performed to plate the conductive material on the exposed portion of the seed layer, and to remove the photoresist and the portion of the unformed conductive material on the seed layer. The remaining portions of the seed layer and conductive material form metallization patterns 154 and vias. Vias are formed in openings through portions of dielectric layer 148 to, for example, metallization pattern 146 .

In FIG. 21 , a dielectric layer 156 is deposited over the metallization pattern 154 and the dielectric layer 148 . Dielectric layer 156 may be made of similar materials and deposited using similar processes as dielectric layer 132 . After the dielectric layer 156 is deposited, it may be patterned to form openings that expose portions of the metallization patterns 154 . The patterning of the dielectric layer 156 may be performed by an acceptable process, such as a process similar to the multiple exposure patterning process described above for patterning the dielectric layer 132 .

Front side routing structure 160 is shown as an example. More or less dielectric layers and metallization patterns may be formed in the front side wiring structure 160 . The steps and processes discussed above may be omitted if fewer dielectric layers and metallization patterns are to be formed. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed above may be repeated. Those skilled in the art will readily understand which steps and processes will be omitted or repeated.

Although the RDL routing design described herein is discussed with respect to the front-side routing structure 160 , the teachings of the RDL routing process can also be applied to the back-side routing structure 110 .

In FIG. 22 , a plurality of pads 162 are formed on the outer side of the front side wiring structure 160 . Pads 162 are used to couple to conductive connections 166 (see FIG. 23 ) and may be referred to as under bump metallurgy (UBM) 162 . In the embodiment shown, the liner 162 is formed via openings through the dielectric layer 156 to the metallization pattern 154 . Pad 162 can be made of similar materials and used with the metallization pattern Case 138 is formed by a similar process. For example, a seed layer can be deposited, a photoresist can be deposited on the seed layer, multiple exposure lithography processes as described above can be applied to the photoresist to define openings for exposing the seed layer, a plating process can be performed A conductive material is plated on the exposed portions of the seed layer, and portions of the photoresist and the unformed conductive material on the seed layer are removed. The seed layer and the remainder of the conductive material form pads 162 .

In FIG. 23 , a plurality of conductive connections 166 are formed on pads 162 . The conductive connectors 166 may be BGA connectors, solder balls, metal posts, controlled collapse chip connections (C4) bumps, micro bumps, electroless nickel-electroless palladium- immersion gold technique; ENEPIG) technology formed bumps or the like. The conductive connections 166 may comprise conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, similar conductive materials, or combinations thereof. In some embodiments, a layer of solder is initially formed to form conductive connections 166 by such common methods as evaporation, electroplating, printing, solder transfer, bumping, or the like. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connections 166 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the metal post connectors 166 . The metal capping layer can include nickel, tin, tin lead, gold, silver, palladium, indium, nickel palladium gold, nickel gold, the like, or a combination thereof, and can be formed by a plating process.

In FIG. 24, a carrier substrate lift-off is performed to detach (peel off) the carrier substrate 100 from the rear side wiring structure (eg, the dielectric layer 104). According to some embodiments, lift-off includes projecting light, such as laser light or UV light, on release layer 102 to allow The release layer 102 is decomposed under light and heat and the carrier substrate 100 can be removed. The structure is then turned over and placed on tape 190 .

As further shown in FIG. 25 , openings are formed through dielectric layer 104 to expose portions of metallization pattern 106 . For example, the openings may be formed using laser drilling, etching, or the like.

In FIG. 26, the singulation process is performed by sawing along the scribe line area (eg, between adjacent first encapsulation area 100A and second encapsulation area 100B). The sawing singulates the first encapsulation area 100A from the second encapsulation area 100B.

Figure 26 shows the resulting singulated package 400, which can be from one of the first encapsulation area 100A or the second encapsulation area 100B. The package 400 may also be referred to as an integrated fan-out (InFO) package 200 .

FIG. 27 shows a package structure 570 including a package body 400 (which may be referred to as a first package body 400 ), a second package body 500 , and a substrate 550 . The second package 500 includes a base 502 and one or more stacked dies 508 (stacked die 508A and stacked die 508B) coupled to the base 502 . The substrate 502 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, indium gallium phosphide, and the like may also be used Combinations and the like. In addition, the substrate 502 may be a silicon-on-insulator (SOI) substrate. Typically, SOI substrates include layers of semiconductor materials such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In an alternative embodiment, the substrate 502 is an insulating core based on, for example, a fiberglass reinforced resin core. An example core material is fiberglass resin such as FR4. Alternatives to core materials include bismaleimide-triazine (BT) resins, Or alternatively contain other printed circuit board (PCB) materials or films. A build-up film such as an Ajinomoto build-up film (ABF) or other laminate can be used for substrate 502 .

The substrate 502 may include active elements and passive elements. As those skilled in the art will recognize, a wide variety of elements such as transistors, capacitors, resistors, combinations of these, and the like can be used to create the structural and functional requirements for the design of semiconductor package 500 . The elements may be formed using any suitable method.

The substrate 502 may also include a metallization layer (not shown) and through holes 506 . Metallization layers can be formed over active and passive elements, and are designed to connect the various elements to form functional circuits. The metallization layers may be formed from alternating layers of dielectric (eg, low-k dielectric materials) and conductive materials (eg, copper), with vias interconnecting the layers of conductive material and may be formed by any suitable process such as deposition, damascene, dual mosaic or the like). In some embodiments, the substrate 502 is substantially free of active and passive elements.

The substrate 502 may have bond pads 503 on a first side of the substrate 502 for coupling to the stacked die 508 and bond pads 504 on a second side of the substrate 502 for coupling to the conductive connections 514, the The second side is opposite the first side. In some embodiments, bond pads 503 and 504 are formed by forming recesses (not shown) into a dielectric layer (not shown) on the first and second sides of substrate 502 . Recesses can be formed to allow bond pads 503 and bond pads 504 to be embedded in the dielectric layer. In other embodiments, the recesses are omitted because bond pads 503 and bond pads 504 may be formed on the dielectric layer. In some embodiments, bond pads 503 and 504 comprise thin seed layers (not shown) made of copper, titanium, nickel, gold, palladium, the like, or combinations thereof. The conductive material of bond pad 503 and bond pad 504 may be deposited over a thin seed layer. electrochemically Plating processes, electroless plating processes, CVD, ALD, PVD, the like, or combinations thereof form the conductive material. In one embodiment, the conductive materials of the bonding pads 503 and 504 are copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In one embodiment, bond pads 503 and 504 are UBMs that include three layers of conductive material, such as titanium, copper, and nickel. However, those skilled in the art will recognize that there are many suitable configurations of materials and layers suitable for forming UBM 503 and UBM 504, such as a chromium/chromium copper alloy/copper/gold configuration, a titanium/titanium tungsten/copper configuration , or a copper/nickel/gold configuration. Any suitable materials or layers of materials that may be used in UBM 503 and UBM 504 are all intended to be included within the scope of the current application. In some embodiments, perforations 506 extend through substrate 502 and couple at least one bond pad 503 to at least one bond pad 504 .

In the embodiment shown, the stacked die 508 is coupled to the substrate 502 by wire bonds 510, but other connections, such as conductive bumps, may be used. In one embodiment, the stacked die 508 is a stacked memory die. For example, the stacked memory die 508 may include low-power (LP) double data rate (DDR) memory modules such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules Group.

In some embodiments, the stacked die 508 and wire bonds 510 may be encapsulated by the molding material 512 . The molding material 512 may be molded over the stacked die 508 and the wire bonds 510, eg, using compression molding. In some embodiments, the molding material 512 is a molding compound, a polymer, an epoxy, a silicon oxide fill material, the like, or a combination thereof. A curing step may be performed to cure the molding material 512, wherein the curing may be thermal curing, UV curing, the like, or a combination thereof.

In some embodiments, the stacked die 508 and wire bonds 510 are buried in In the molding material 512, and after curing the molding material 512, a planarization step such as grinding is performed to remove excess portions of the molding material 512 and provide the second package 500 with a substantially planar surface.

After the second package body 500 is formed, the package body 500 is bonded to the first package body 400 by means of the conductive connections 514 , the bonding pads 504 , and the metallization pattern 106 . In some embodiments, the stacked memory die (stacked die 508 ) may be coupled to the integrated circuit die by wire bonds 510 , bond pads 503 and 504 , vias 506 , conductive connections 514 , and vias 112 Granules 114.

The conductive connections 514 may be similar to the conductive connections 166 described above, and the description is not repeated herein, although the conductive connections 514 and 166 need not be the same. In some embodiments, the conductive connectors 514 are coated with a flux (not shown), such as no-clean flux, prior to bonding the conductive connectors 514 . The conductive connectors 514 can be dipped in flux or the flux can be sprayed onto the conductive connectors 514 . In another embodiment, the flux may be applied to the surface of the metallization pattern 106 .

In some embodiments, the conductive connector 514 may have an epoxy flux (not shown) that remains of the epoxy flux after it is attached with the second package 500 to the first package 400 . At least some of the epoxy portions are formed thereon prior to reflow. This remaining epoxy portion can act as a primer to reduce stress and protect the joints created by reflowing the conductive connections 514 . In some embodiments, an underfill (not shown) may be formed between the second package body 500 and the first package body 400 and surround the conductive connections 514 . The primer may be formed by a capillary flow process after the second package body 500 is attached, or a primer may be formed by a suitable deposition method before the second package body 500 is attached.

The bonding between the second package body 500 and the first package body 400 may be solder Bonding or direct metal-to-metal (such as copper-to-copper or tin-to-tin) bonding. In one embodiment, the second package body 500 is bonded to the first package body 400 by a reflow process. During this reflow process, the conductive connections 514 are in contact with the bonding pads 504 and the metallization pattern 106 to physically and electrically couple the second package 500 to the first package 400 . After the bonding process, an intermetallic compound (IMC) (not shown) may be formed at the interface of the metallization pattern 106 and the conductive connections 514 , and also at the interface between the conductive connections 514 and the bond pads 504 .

Although the second package 500 is shown attached to the first package 400 after the first package 400 is singulated from other packages in the wafer, in other embodiments, the second package 500 may be Attached to the first package body 400 before singulation. For example, the second package body 500 may be attached to the first package body 400, and then the first package body 400 may be singulated (eg, as described in FIG. 26).

The semiconductor package 570 includes the package 400 and the package 500 mounted to the package substrate 550 . Package body 400 is mounted to package substrate 550 using conductive connectors 166 .

The package substrate 550 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, indium gallium phosphide, combinations of these, and the like can also be used . In addition, the package substrate 550 may be an SOI substrate. Generally, SOI substrates include layers of semiconductor materials, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the encapsulation substrate 550 is an insulating core based on, for example, a fiberglass reinforced resin core. An example core material is fiberglass resin such as FR4. Alternatives to core materials include bismaleimide-triazine (BT) resins, or alternatively include other PCB materials or membrane. A build-up film such as ABF or other laminate may be used to encapsulate substrate 550 .

The package substrate 550 may include active elements and passive elements. As those skilled in the art will recognize, a wide variety of elements such as transistors, capacitors, resistors, combinations of these, and the like can be used to create the structural and functional requirements for the design of semiconductor package 500 . The elements may be formed using any suitable method.

Package substrate 550 may include metallization layers and vias (not shown) and bond pads 552 over the metallization layers and vias. Metallization layers can be formed over active and passive elements, and are designed to connect the various elements to form functional circuits. The metallization layers may be formed from alternating layers of dielectric (eg, low-k dielectric materials) and conductive materials (eg, copper), with vias interconnecting the layers of conductive material and may be formed by any suitable process such as deposition, damascene, dual mosaic or the like). In some embodiments, the package substrate 550 is substantially free of active and passive components.

In some embodiments, the conductive connections 166 may be reflowed to attach the package body 400 to the bond pads 552 . The conductive connections 166 electrically and/or physically couple the package substrate 550 (including the metallization layers in the package substrate 550 ) to the first package body 400 .

The conductive connector 166 may have an epoxy flux (not shown) that reflows at least some of the epoxy portion of the epoxy flux remaining after it is attached to the package substrate 550 with the package body 400 formed on it before. This remaining epoxy portion can act as a primer to reduce stress and protect the joints created by reflowing the conductive connections 166 . In some embodiments, an underfill (not shown) may be formed between the first package body 400 and the package substrate 550 and surround the conductive connections 166 . The primer may be formed by a capillary flow process after the package body 400 is attached or may be formed by a suitable deposition method before the package body 400 is attached.

Other features and processes may also be included. For example, a test structure can be included To help with verification testing of 3D packages or 3DIC components. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, allowing for testing of 3D packages or 3DICs, use of probes and/or probe cards, and the like. Verification tests can be performed on intermediate and final structures. Additionally, the structures and methods disclosed herein can be used in conjunction with test methods with intermediate validation of known good dies to increase yield and reduce cost.

Various embodiments use a stitching lithography process to stitch together different patterns defined by different photomasks on different patterned areas. By using stitching lithography, the field volume size is no longer limited by the exposure field size (eg, the size of each optical lens). For example, the size of a pattern in a layer can be enlarged by splicing patterns of different masks in different splice regions. Further use of gray-tone patterns and low NA steppers can increase tolerance at the splices and reduce manufacturing defects at the splices.

In one embodiment, the device includes: a mold compound encapsulating the first integrated circuit die and the second integrated circuit die; a dielectric layer over the mold compound, the first integrated circuit die, and the second integrated circuit die over the bulk circuit die; and a metallization pattern over the dielectric layer and electrically connecting the first integrated circuit die to the second integrated circuit die, wherein the metallization pattern includes a plurality of wires, and wherein the plurality of each of the wires: extending continuously from the first region of the metallization pattern through the second region of the metallization pattern to the third region of the metallization pattern; and having the same type of fabrication in the second region of the metallization pattern abnormal. In one embodiment, the width of each of the plurality of wires is increased in the second region of the metallization pattern compared to the first region of the metallization pattern and the third region of the metallization pattern. In one embodiment, the width of each of the plurality of conductive lines is reduced in the second region of the metallization pattern compared to the first region of the metallization pattern and the third region of the metallization pattern. In one embodiment, the plurality of sidewalls of each of the plurality of wires are in the metal misalignment in the second region of the pattern. In one embodiment, the second region of the metallization pattern is disposed between the first alignment mark and the second alignment mark. In one embodiment, the device further includes a third alignment mark and a fourth alignment mark, wherein the metallization pattern includes a plurality of second wires between the third alignment mark and the fourth alignment mark, and wherein the The distance between the first alignment mark and the third alignment mark is equal to the distance between the second alignment mark and the fourth alignment mark. In one embodiment, the metallization pattern includes a plurality of third conductive lines between the first alignment mark and the third alignment mark.

In one embodiment, the method includes encapsulating a first integrated circuit die and a second integrated circuit die in a molding compound; molding the first integrated circuit die, the second integrated circuit die, and molding depositing a seed layer over the compound; depositing a photoresist over the seed layer; performing a first exposure process on the first patterned area of the photoresist to define the first exposure area; A second exposure process is performed on the second patterned area to define a second exposure area, wherein the first patterned area and the second patterned area overlap in the splicing area; the photoresist is developed to define the first opening, the first The opening extends from the first patterned area through the splicing area to the second patterned area; conductive material is plated in the first opening, wherein the conductive material is electrically connected to the first integrated circuit die and the second integrated circuit die; and removing the photoresist. In one embodiment, the shape of the first exposure area is triangular in the tiling area. In one embodiment, the shape of the second exposure area is triangular in the tiling area. In one embodiment, performing the first exposure process includes reducing the exposure intensity applied by the first exposure process in the spliced region, wherein the exposure intensity applied by the first exposure process is reduced in a direction toward the second patterned region. In one embodiment, the exposure intensity applied by the first exposure process decreases continuously in the direction toward the second patterned region. In one embodiment, the exposure intensity applied by the first exposure process decreases at discrete intervals in the direction toward the second patterned region. In one embodiment, the first exposure The cumulative exposure intensity generated by the second exposure process and the second exposure process does not exceed 120% in the entire splicing area. In one embodiment, the size of the first patterned region corresponds to the size of the reticle used during the first exposure process. In one embodiment, performing the first exposure process includes using a lithography stepper tool having a numerical aperture (NA) of less than 0.2.

In one embodiment, the method includes depositing a photoresist over the first die, the second die, and a mold compound, wherein the mold compound is disposed to surround the first die and the second die; using a first photomultiplier performing a first exposure process on the first patterned area of the photoresist; after performing the first exposure process, a second photoresist is used to perform a second exposure process on the second patterned area of the photoresist, wherein the first A patterned area and a second patterned area overlap in the splicing area, wherein performing the first exposure process includes placing the first triangular opening of the first reticle directly above the splicing area, and wherein performing the second exposure The process includes placing the second triangular opening of the second photomask directly above the splicing area; developing the photoresist to define a third opening in the photoresist, wherein the third opening extends from the first patterned area through the splicing area to the second patterned region; and plating a conductive material in the third opening, wherein the conductive material electrically connects the first die to the second die. In one embodiment, performing the first exposure process includes: placing one side of the first triangular opening at the first edge of the splicing area; placing the vertex of the first triangular opening at the second edge of the splicing area; placing one side of the second triangular opening at the second edge of the splice area; and placing the apex of the second triangular opening at the first edge of the splice area. In one embodiment, the method further includes using first alignment marks to align the first reticle with the layer under the photoresist; and using overlapping marks to align the second reticle with the layer formed by the first reticle. Reticle-defined pattern alignment. In one embodiment, the first alignment marks overlap the overlapping marks.

The foregoing outlines the features of several embodiments in order that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other methods and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art could make them herein without departing from the spirit and scope of the present disclosure Alterations, Substitutions and Alterations.

100: carrier substrate

100A: The first package area

100B: Second packaging area

100C: District

102: Release Layer

104, 108, 132: Dielectric layer

106, 138: Metallization pattern

110: Back-side wiring structure

112: perforation

114: integrated circuit die

116: Adhesive

126: Die connector

128: Dielectric Materials

130: Sealing body

200A: First patterned area

200B: Second patterned area

200C: Splicing area

Claims (7)

A semiconductor device comprising: a molding compound encapsulating a first integrated circuit die and a second integrated circuit die; a dielectric layer on the molding compound, the first integrated circuit die and the over a second integrated circuit die; and a metallization pattern on the dielectric layer and electrically connecting the first integrated circuit die to the second integrated circuit die, wherein the metal The metallization pattern includes a plurality of conductive lines, and wherein each of the plurality of conductive lines: extends continuously from a first region of the metallization pattern through a second region of the metallization pattern to the end of the metallization pattern a third region; and having the same type of fabrication anomaly in the second region of the metallization pattern as the first region of the metallization pattern and the third region of the metallization pattern In contrast, the width of each of the plurality of wires is reduced in the second region of the metallization pattern. The semiconductor device of claim 1, wherein a plurality of sidewalls of each of the plurality of wires are misaligned in the second region of the metallization pattern. The semiconductor device of claim 1, wherein the second region of the metallization pattern is disposed between the first alignment mark and the second alignment mark. A method of forming a semiconductor device, comprising: encapsulating a first integrated circuit die and a second integrated circuit die in a molding compound; grains and the depositing a seed layer over the molding compound; depositing a photoresist over the seed layer; performing a first exposure process on a first patterned area of the photoresist to define a first exposure area, wherein the first exposure is performed The exposure process includes reducing the exposure intensity applied by the first exposure process in the spliced area, wherein the exposure intensity applied by the first exposure process is reduced in a direction toward the second patterned area; performing the first exposure process After the exposure process, a second exposure process is performed on the second patterned area of the photoresist to define a second exposure area, wherein the first patterned area and the second patterned area are in the splicing overlapping in the area; developing the photoresist to define a first opening extending from the first patterned area through the splicing area to the second patterned area; in the first patterned area A conductive material is plated in the opening, wherein the conductive material electrically connects the first integrated circuit die and the second integrated circuit die; and the photoresist is removed. The method of claim 4, wherein the shape of the first exposure area or the shape of the second exposure area is triangular in the tiling area. The method of claim 4, wherein the size of the first patterned region corresponds to the size of a reticle used during the first exposure process. A method of forming a semiconductor device comprising: depositing photoresist over a first die, a second die, and a molding compound, wherein the molding compound is disposed to surround the first die and the second die ; performing a first exposure process on the first patterned area of the photoresist using a first reticle; After performing the first exposure process, a second exposure process is performed on the second patterned area of the photoresist using a second reticle, wherein the first patterned area and the second patterned area are The regions overlap in the splicing region, wherein performing the first exposure process includes placing the first triangular opening of the first reticle directly above the splicing region, and placing a first triangular opening of the first triangular opening the side is placed at a first edge of the spliced area, and the apex of the first triangular opening is placed at a second edge of the spliced area; and wherein performing the second exposure process includes placing the The second triangular opening of the second reticle is placed just above the splicing area, one side of the second triangular opening is placed at the second edge of the splicing area, and the The apex of a second triangular opening is placed at the first edge of the tiling area; the photoresist is developed to define a third opening in the photoresist, wherein the third opening is from the first pattern a patterned region extending through the splicing region to the second patterned region; and plating a conductive material in the third opening, wherein the conductive material electrically connects the first die to the second grains.

Images