TW202029283A - Semiconductor device and method of forming the same - Google Patents

Abstract

A device includes a molding compound encapsulating a first integrated circuit die and a second integrated circuit die; a dielectric layer over the molding compound, the first integrated circuit die, and the second integrated circuit die; and a metallization pattern over the dielectric layer and electrically connecting the first integrated circuit die to the second integrated circuit die. The metallization pattern comprises a plurality of conductive lines. Each of the plurality of conductive lines extends continuously from a first region of the metallization pattern through a second region of the metallization pattern to a third region of the metallization pattern; and has a same type of manufacturing anomaly in the second region of the metallization pattern.

Description

The lithography process for semiconductor packaging and the resulting structure

The semiconductor industry has experienced rapid development due to ongoing improvements in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). Mainly, the improvement in integrated density comes from repeated reductions in the minimum feature size, which allows more components to be integrated into a given area. As the demand for smaller electronic components has grown, the need for smaller and more creative semiconductor die packaging technology has emerged. Examples of such packaging systems are package-on-package (PoP) technology. In PoP devices, the top semiconductor package is stacked on top of the bottom semiconductor package to provide high-level integration and component density. PoP technology can generally produce semiconductor components with enhanced functionality and a small footprint on a printed circuit board (PCB).

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features. An embodiment is formed between the second features such that the first feature and the second feature may not directly contact each other. In addition, the content of the present disclosure may be repeated with icons and/or letters in various examples. This repetition is for simplicity and clarity, and does not indicate the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description in this article, spatially relative terms such as "below", "below", "lower", "above", "upper" and similar terms can be used to describe a component Or the relationship between the feature and another component or feature as shown in the drawing. In addition to the orientations depicted in the drawings, spatially relative terms are intended to cover different orientations of elements in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations) and the spatial relative descriptors used in this article can be interpreted accordingly.

The following describes various embodiments for the integrated fan-out (InFO) lithography process. However, it should be understood that the various embodiments described herein and the resulting structures can be applied to any type of semiconductor package, including, for example, chip on wafer on substrate (CoWoS) package, fan-in (fan-in) package. -in) package or similar.

Various embodiments provide a stitching lithography process for large integrated chip packages to realize a multifunctional system. The splicing lithography process of the embodiment is not limited by the size of the exposure field of the lithography stepper. From the top view, the field size of the lithography stepper depends on the size of the optical lens. For example, the resulting pattern of the photoresist mask that can be obtained using a single exposure step is limited by the diameter of the optical lens, and is generally further limited by placing it on the optical axis in order to reduce optical aberration. In addition, the pattern edge of the mask is usually spaced from the physical edge of the optical lens to avoid image distortion. This further limits the size of the pattern that can be obtained using a single exposure step.

For the integration of large field sizes, the desired pattern size of the layer is usually large, and increasing the optical lens size to accommodate the desired pattern size is expensive and may be impractical. The stitching lithography process of the embodiment uses multiple exposure steps with multiple reduction masks to define a large field size integrated pattern without increasing the size of the optical lens. For example, a first reduction mask is used to expose the layer to the first pattern in the first patterned area of the layer, and a second reduction mask is used to expose the layer to the first pattern in the second patterned area of the layer. Two patterns. The first patterned area and the second patterned area of the layer overlap, and the overlap allows the first pattern and the second pattern to be interconnected and define stitching together and extend through the first patterned area and the second patterned area. The entire desired pattern. The area where the first patterned region and the second patterned region overlap can be referred to as a stitching region. During each exposure step within the stitching area (for example, referred to as a grey tone pattern), the shape of the pattern (for example a triangle) can be adapted to reduce the result of, for example, multiple exposure steps performed on the stitching area Patterning defects caused by overexposure.

In addition, compared with a high numerical aperture (numerical aperture; NA) stepper, the depth of field (DoF) associated with a low NA stepper is relatively large, so embodiments may use a low NA stepper to reduce Small splicing error. The low NA stepper can be used for large critical dimension (CD) applications and has the additional benefit of cost reduction compared to the high NA stepper.

By using stitching lithography, the field-integrated body size is no longer limited by the exposure field size (for example, the size of each optical lens). For example, the size of the pattern in the layer can be enlarged by splicing patterns of different masks in different splicing areas. Further use of gray-tone patterns and low NA steppers can increase tolerance at the splicing area and reduce manufacturing defects at the splicing area.

Various embodiments can achieve one or more of the following non-limiting advantages/features: when the interconnection crosses the splicing area, the large field size of the semiconductor package is realized by splicing different mask patterns at the splicing area; if If the alignment marks of the previous process are placed outside the field, the package size will be enlarged in one direction; if the alignment marks are placed in the field, the package size will be expanded without boundaries; the gray-scale pattern and low NA stepper can have Higher tolerance to control the critical dimension (CD) of interconnects at the splicing area; lower cost; and high yield.

FIGS. 1-27 illustrate cross-sectional views of intermediate steps during a process for forming a first package structure according to some embodiments (for example, forming a component of an InFO package). FIG. 1 shows a carrier substrate 100 and a release layer 102 formed on the carrier substrate 100. The first package area 100A and the second package area 100B respectively used to form the first package body and the second package body are shown.

The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 100 may be a wafer, so that multiple packages may be formed on the carrier substrate 100 at the same time. The release layer 102 may be formed of a polymer-based material, which together with the carrier substrate 100 may be removed from the overlying structure to be formed in a subsequent step. In some embodiments, the release layer 102 is an epoxy-based heat release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 102 may be an ultra-violet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release layer 102 may be formulated as a liquid and cured, may be a laminated film laminated on the carrier substrate 100, or may be similar. The top surface of the release layer 102 may be leveled and may have a high degree of planarity.

In FIG. 2, a dielectric layer 104 and a metallization pattern 106 are formed. As shown in FIG. 2, the dielectric layer 104 is formed on the release layer 102. The bottom surface of the dielectric layer 104 may be in contact with the top surface of the release layer 102. In some embodiments, the dielectric layer 104 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 104 is formed of: nitride, such as silicon nitride; oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (borosilicate glass; glass; BSG), boron-doped phosphosilicate glass (BPSG) or similar; or similar. The dielectric layer 104 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof.

The metallization pattern 106 is formed on the dielectric layer 104. As an example of forming the metallization pattern 106, a seed layer (not shown) is formed on the dielectric layer 104. In some embodiments, the seed layer is a metal layer, and the metal layer may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. For example, PVD or the like can be used to form the seed layer. The photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 106. One or more exposure steps can be applied to the photoresist to define the metallization pattern 106. After one or more exposures, the photoresist is developed to form openings through the photoresist to expose the seed layer. Embodiment stitching lithography processes (for example, as discussed with reference to FIGS. 10 to 16F) can be used to define the metallization pattern 106. Alternatively, multiple exposure steps may be used to define the metallization pattern 106, each exposure step (eg, at any stitching area) defining a separate pattern that is not interconnected.

The conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. Subsequently, the photoresist and the part of the seed layer where no conductive material is formed are removed. The photoresist can be removed by an acceptable ashing or stripping process (such as using oxygen plasma or the like). Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process (such as by wet or dry etching). The remaining part of the seed layer and the conductive material forms the metallization pattern 106.

In FIG. 3, a dielectric layer 108 optionally selected is formed on the metallization pattern 106 and the dielectric layer 104. In some embodiments, the dielectric layer 108 is formed of a material similar to the dielectric layer 106 and similar methods are used. Subsequently, the dielectric layer 108 is patterned to form openings to expose portions of the metallization pattern 106. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 108 to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching.

The dielectric layer 104 and the dielectric layer 108 and the metallization pattern 106 can be referred to as the backside redistribution structure 110. As shown, the back-side heavy wiring structure 110 includes two dielectric layers 104 and 108 and one metallization pattern 106. In other embodiments, the back-side heavy wiring structure 110 may include any number of dielectric layers, metallization patterns, and vias. One or more additional metallization patterns and dielectric layers can be formed in the backside redistribution wiring structure 110 by repeating the process used to form the metallization pattern 106 and the dielectric layer 108. The through hole can be formed by forming the seed layer of the metallization pattern and the conductive material in the opening under the dielectric layer during the formation of the metallization pattern. The vias can therefore be interconnected and electrically coupled to various metallization patterns. In other embodiments, the back-side heavy wiring structure 110 can be omitted entirely, so that the features described later are directly formed on the release layer 102.

In addition, in FIG. 3, a plurality of through holes 112 are formed. As an example of forming the through hole 112, an optional seed layer is formed on the backside redistribution structure 110, such as the dielectric layer 108 and the exposed portion of the metallization pattern 106. In some embodiments, the seed layer is a metal layer, and the metal layer may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD or the like. The photoresist is formed on the seed layer and is patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the perforation 112. One or more exposure steps can be applied to the photoresist to define the perforations 112. After one or more exposures, the photoresist is developed to form openings through the photoresist to expose the seed layer.

The conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. Remove the photoresist and the part of the seed layer where no conductive material is formed. The photoresist can be removed by an acceptable ashing or stripping process (such as using oxygen plasma or the like). Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process (such as by wet or dry etching). The seed layer and the remaining part of the conductive material form the through hole 112. Alternatively, in an embodiment where the dielectric layer 108 is omitted (see, for example, FIG. 4B), the seed layer can also be omitted and the metallization pattern 106 can be used as the seed layer for plating the through holes 112. For example, in such an embodiment, the through hole 112 can be directly plated on the metallization pattern 106.

In FIG. 4A, a plurality of integrated circuit dies 114 are adhered to the dielectric layer 108 by an adhesive 116. As shown in FIG. 4A, two integrated circuit dies 114 are adhered to each of the first package area 100A and the second package area 100B, and in other embodiments, more or less product The bulk circuit die 114 can be attached to each region. For example, in one embodiment, only one type of integrated circuit die 114 may be attached in each region, or three or more integrated circuit die 114 may be attached in each region. The integrated circuit die 114 can be a logic die (such as a central processing unit, a microcontroller, etc.), a memory die (such as a dynamic random access memory (DRAM) die, and a static random access memory). Memory (static random access memory; SRAM) die, etc.), power management die (for example, power management integrated circuit (PMIC) die), radio frequency (RF) die, sensing Dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (such as digital signal processing (DSP) dies), front-end dies (such as analog front-end (analog) front-end; AFE) die), similar or a combination thereof. In addition, in some embodiments, the integrated circuit die 114 may be of different sizes (such as different heights and/or surface areas), and in other embodiments, the integrated circuit die 114 may be of the same size (such as the same height and / Or surface area).

Before being adhered to the carrier 100, the integrated circuit die 114 may be processed according to an applicable manufacturing process to form an integrated circuit in the integrated circuit die 114. For example, the integrated circuit die 114 each includes a semiconductor substrate 118 such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination thereof. Other substrates can also be used, such as multilayer substrates or gradient substrates. Components such as transistors, diodes, capacitors, resistors, etc. can be formed in and/or on the semiconductor substrate 118, and can be formed by, for example, one or more dielectric layers on the semiconductor substrate 118 The interconnect structure 120 formed by the metallization pattern is interconnected to form an integrated circuit.

The plurality of integrated circuit dies 114 further include a plurality of pads 122 (such as aluminum pads) to externally connect the pads. A plurality of pads 122 are located on respective active sides which may be referred to as integrated circuit die 114. The passivation film 124 is on the integrated circuit die 114 and on the part of the pad 122. The opening penetrates through the passivation film 124 to the liner 122. A plurality of die connectors 126 such as conductive pillars (for example, including a metal such as copper) extend through the passivation film 124 and are mechanically and electrically coupled to the corresponding pad 122. The die connecting member 126 may be formed by, for example, plating or the like. The die connector 126 is electrically coupled to the individual integrated circuits of the integrated circuit die 114.

The dielectric material 128 is on the active side of the integrated circuit die 114, such as on the passivation film 124 and the die connector 126. The dielectric material 128 seals the die connector 126 laterally, and the dielectric material 128 is coterminous laterally with the corresponding integrated circuit die 114. The dielectric material 128 may be a polymer, such as PBO, polyimide, BCB, or the like; nitride, such as silicon nitride or the like; oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; similar Or a combination thereof, and can be formed, for example, by spin coating, lamination, CVD, or the like.

The adhesive 116 is on the back side of the integrated circuit die 114 and adheres the integrated circuit die 114 to the backside redistribution structure 110, such as the dielectric layer 108 in FIG. 4A. Alternatively, in an embodiment when the dielectric layer 108 is omitted, the adhesive 116 may adhere the integrated circuit die to the metallization pattern 106 and the dielectric layer 104, such as shown in FIG. 4B. In such embodiments, the adhesive 116 may extend along the top surface and sidewalls of the metallization pattern 106. The adhesive 116 can be any suitable adhesive, epoxy resin, die attach film (DAF) or the like. The adhesive 116 may be coated on the back side of the integrated circuit die 114, such as on the back side of the corresponding semiconductor wafer, or may be coated on the surface of the carrier substrate 100. The integrated circuit die 114 can be singulated, such as by sawing or dicing, and adhered to the back-side heavy wiring structure 110 by the adhesive 116 using, for example, a pick-and-place method.

In FIG. 5, the sealing body 130 is formed on various components. The sealing body 130 may be a molding compound, epoxy resin, or the like, and may be coated by compression molding, transfer molding, or the like. After curing, the sealing body 130 may undergo a grinding process to expose the through hole 112 and the die connecting member 126. After the grinding process, the top surface of the through hole 112, the die connector 126, and the sealing body 130 are coplanar. In some embodiments, for example, if the through hole 112 and the die connecting member 126 are exposed, the grinding may be omitted.

In FIGS. 6 to 21, a front-focused wiring structure 160 is formed. As will be shown in FIG. 21, the front-focused wiring structure 160 includes a dielectric layer 132, a dielectric layer 140, a dielectric layer 148, and a dielectric layer 156, and a metallization pattern 138, a metallization pattern 146, and a metallization pattern 154.

In FIG. 6, the dielectric layer 132 is deposited on the sealing body 130, the through hole 112 and the die connecting member 126. In some embodiments, the dielectric layer 132 is formed of a polymer, and the polymer may be a photosensitive material that can be patterned using a lithography mask, such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric layer 132 is formed of: nitride, such as silicon nitride; oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 132 may be formed by spin coating, lamination, CVD, the like, or a combination thereof.

In FIGS. 7-9, the dielectric layer 132 is subsequently patterned. An opening is patterned to expose a portion of the through hole 112 and the die connecting member 126. When the dielectric layer 132 is a photosensitive material, a photolithography process can be used to achieve patterning.

Embodiments of the lithography process for patterning the dielectric layer 132 may include performing multiple exposure steps in each packaging area (for example, the first packaging area 100A and the second packaging area 100B) on the carrier substrate 100. For example, in FIG. 7, the first packaging area 100A is divided into a first patterned area 200A and a second patterned area 200B. The first patterned area 200A and the second patterned area 200B overlap in the stitching area 200C.

In FIG. 7, the first exposure is performed on the dielectric layer 132 in the first patterned area 200A using the first reduction mask 202A. As a result, multiple exposure regions 132A of the dielectric layer 132 are formed. The size of the reduction mask 202A may correspond to the size (eg, diameter) of the lens used by the NA stepper to expose the dielectric layer 132 in the first patterned area 200A. For example, in a top view (not shown), the reduction mask 202A may have a length of about 52 mm and a width of about 34 mm to correspond to the optical lens for exposing the dielectric layer 132. Other sizes of the zoom mask 202A are also possible. In addition, a low NA stepper (for example, with a NA less than 0.2) can be used to increase the DoF of the patterning process and reduce the cost. As a result of the increased DoF, patterning defects caused by warpage of various features can be advantageously reduced. Because the package wafer is relatively large, it may be particularly susceptible to warpage, which increases the topography of the top surface of the dielectric layer 132. By providing increased DoF, patterning defects caused by warpage and increased topography can be reduced. Due to the relatively large feature size (eg, critical size) of the patterned features in the rewiring structure 160 (see FIG. 21), a low NA stepper may be used in various embodiments.

Next, in FIG. 8, a second exposure is performed on the dielectric layer 132 in the second patterned area 200B using the second reduction mask 202B. Therefore, a plurality of exposure regions 132B of the dielectric layer 132 are formed. The size of the reduction mask 202B may correspond to the size (eg, diameter) of the lens used by the NA stepper to expose the dielectric layer 132 in the patterned area 200B. For example, in a top view (not shown), the reduction mask 202B may have a length of about 52 mm and a width of about 34 mm to correspond to the optical lens for exposing the dielectric layer 132. Other sizes of the reduction mask 202B are also possible. In addition, a low NA stepper (for example, with a NA less than 0.2) can be used to increase the DoF of the patterning process and reduce the cost. As a result of the increased DoF, patterning defects caused by the warpage and increased topography of the dielectric layer 132 can be reduced. Due to the relatively large feature size (eg, critical size) of the patterned features in the rewiring structure 160 (see FIG. 21), a low NA stepper may be used in various embodiments.

In this way, an opening pattern penetrating the dielectric layer 132 is defined in the first packaging area 100A. The total size of the opening pattern in the first encapsulation area 100A does not need to be limited by the physical size of the optical lens used to expose the dielectric layer 132, because multiple exposure steps and reduction masks can be enlarged and formed in each encapsulation area 100A And the size of the package body in the package area 100B.

A similar exposure step can be performed in other packaging areas on the carrier substrate 100 (for example, in the second packaging area 100B) in order to define a desired pattern in the dielectric layer 132. Exposing the second packaging area 100B may be performed after all the exposure steps in the first packaging area 100A are completed. Alternatively, before the subsequent reduction mask (for example, the second reduction mask 202B) is used to expose the dielectric layer 132, each reduction mask (for example, the first reduction mask 202A) may be used to expose the carrier substrate 100 Each package area on the

In FIG. 9, after exposing various patterned areas and encapsulation areas of the dielectric layer 132, the dielectric layer 132 is developed to form an opening extending through the dielectric layer 132. The opening may expose part of the through hole 112 and the die connecting member 126. FIG. 9 shows the dielectric layer 132 as a positive photo resist material, in which the exposed area 132A/exposed area 132B is removed due to the development of the dielectric layer 132. In other embodiments, the dielectric layer 132 may be a negative photo resist, wherein the exposed area 132A/exposed area 132B of the dielectric layer 132 remains, and the unexposed area of the dielectric layer 132 is used as a result of development. Remove.

In FIGS. 10 to 16F, a metallization pattern 138 with a plurality of through holes is formed on the dielectric layer 132. As an example of forming the metallization pattern 138, the seed layer 133 is formed on the dielectric layer 132 and in the opening through the dielectric layer 132. In some embodiments, the seed layer 133 is a metal layer, and the metal layer may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer 133 includes a titanium layer and a copper layer above the titanium layer. The seed layer 133 can be formed using, for example, PVD or the like.

Then a photoresist 204 is formed and patterned on the seed layer 133. The photoresist 204 can be formed by spin coating or the like and can be exposed to light for patterning. Multiple exposure processes (such as stitching lithography) as described below will be used to expose multiple areas of the photoresist. After multiple exposure processes, a single development process will be performed to remove exposed or unexposed parts depending on whether negative photoresist or positive photoresist is used.

In FIG. 11A, the first exposure is performed on the photoresist 204 in the first patterned area 200A by using the first reduction mask 206A. Therefore, a plurality of exposure regions 204A of the photoresist 204 are formed. The size of the reduction mask 202A may correspond to the size (eg, diameter) of the lens used by the NA stepper to expose the photoresist 204 in the first patterned area 200A. For example, in a top view (not shown), the zoom mask 206A may have a length of about 52 mm and a width of about 34 mm to correspond to the optical lens used to expose the photoresist 204. Other sizes of the reduction mask 206A are also possible. In addition, a low NA stepper (for example, with a NA less than 0.2) can be used to increase the DoF of the patterning process and reduce the cost. As a result of the increased DoF, patterning defects caused by the warpage and increased topography of the dielectric layer 132 can be reduced. Due to the relatively large feature size (eg, critical size) of the patterned features in the rewiring structure 160 (see FIG. 21), a low NA stepper may be used in various embodiments.

The exposure area 204A extends to the stitching area 200C (for example, where the first patterned area 200A and the second patterned area 200B overlap). Compared with the area of the first patterned area 200A outside the splicing area 200C, the shrinking mask 206A can be designed to reduce the exposure dose applied to the photoresist 204 in the splicing area 200C. For example, during the exposure step, light (for example, ultraviolet (UV) light) is projected onto the photoresist 204 through the reduction mask 206A. The opening in the magnifying mask 206A allows light to shine on the photoresist 204, and the solid area of the magnifying mask 206A blocks light from radiating to the photoresist 204. Compared with the area of the first patterned area 200A outside the splicing area 200C, the shape and size of the opening in the shrinking mask 206A can reduce the light transmittance in the splicing area 200C. For example, the reduction mask 206A may allow the light transmittance in the first patterned area 200A outside the splicing area 200C to be 100%, and the reduction mask 206A may allow the light transmittance in the splicing area 200C to be lower than The direction toward the second patterned area 200B gradually decreases from 100% to about 0%. This can be achieved by selecting an appropriate shape of the opening of the reduction mask 206A on the splicing area 200C and reducing the area of the opening in the reduction mask 206A on the splicing area 200C.

11B and 11C show top views of the exposure area 204A in the first patterned area 200A both outside and inside the stitching area 200C according to various embodiments. The shape of the exposure area 204A corresponds to the shape of the opening in the reduction mask 206A. As shown in FIGS. 11B and 11C, as the exposure area 204A extends to the splicing area 200C, the width of the exposure area 204A decreases, so that the exposure area 204A has a triangular shape in the splicing area 200C. The triangular shape of the exposure area 204A can span the entire stitching area 200C. For example, the triangular shape may start at the first edge of the splicing area 200C and narrow to the apex at the second edge of the splicing area 200C, the second edge being opposite to the first edge. In the splicing area 200C, the width of the exposure area 204A may be reduced all the time (for example, as shown in FIG. 11B) or discretely reduced at a set interval (for example, as shown in FIG. 11C).

As a result of the embodiment shape and varying width of the exposure area 204A, as the exposure area 204A extends into the splicing area 200C, the exposure intensity of the exposure area 204A decreases. By configuring the exposure area 204A to have the shape shown in the splicing area 200C (for example, by arranging the corresponding opening in the reduction mask 206A on the splicing area 200C), the exposure intensity in the splicing area 200C can also be Gradually decreasing, this reduces overexposure defects and increases overlap tolerance, as will be described in detail below.

Next, in FIG. 12A, a second exposure is performed on the photoresist 204 in the second patterned area 200B using the second reduction mask 206B. Therefore, a plurality of exposure regions 204B of the photoresist 204 are formed. The size of the reduction mask 202B may correspond to the size (eg, diameter) of the lens used by the NA stepper to expose the photoresist 204 in the first patterned area 200A. For example, in a top view (not shown), the reduction mask 206B may have a length of about 52 mm and a width of about 34 mm to correspond to the optical lens used for the exposure photoresist 204. Other sizes of the reduction mask 206B are also possible. In addition, a low NA stepper (for example, with a NA less than 0.2) can be used to increase the DoF of the patterning process and reduce the cost. As a result of the increased DoF, patterning defects caused by the warpage and increased topography of the dielectric layer 132 can be reduced. Due to the relatively large feature size (eg, critical size) of the patterned features in the rewiring structure 160 (see FIG. 21), a low NA stepper may be used in various embodiments.

The exposure area 204B extends to the stitching area 200C (for example, where the first patterned area 200A and the second patterned area 200B overlap). The exposure area 204B may overlap the exposure area 204A in the splicing area 200C, so that the photoresist 204 includes the first patterned area 200A (specifically, the area of the first patterned area 200A outside the splicing area 200C). The stitching area 200C continuously extends to the stitching exposure area of the second patterned area 200B (specifically, the area of the second patterned area 200B outside the stitching area 200C).

Similar to the shrinking mask 200A, the shrinking mask 206B can be designed to reduce the exposure dose applied to the photoresist 204 in the splicing area 200C compared with the area of the second patterned area 200B outside the splicing area 200C. Compared with the area of the second patterned area 200B outside the splicing area 200C, the shape and size of the opening in the shrinking mask 206B can reduce the light transmittance in the splicing area 200C. For example, the reduction mask 206B may allow the light transmittance in the second patterned area 200B outside the splicing area 200C to be 100%, and the reduction mask 206B may allow the light transmittance in the splicing area 200C to be lower than The direction toward the first patterned area 200A gradually decreases from 100% to about 0%. This can be achieved by selecting an appropriate shape of the opening of the reduction mask 206B on the splicing area 200C and reducing the area of the opening in the reduction mask 206B on the splicing area 200C.

12B and 12C show top views of the exposure area 204A and the exposure area 204B in the first patterned area 200A and the second patterned area 200B according to various embodiments. The shape of the exposure area 204B corresponds to the shape of the opening in the reduction mask 206B. As shown in FIGS. 12B and 12C, as the exposure area 204B extends to the splicing area 200C, the width of the exposure area 204B decreases so that the exposure area 204B has a triangular shape in the splicing area 200C. The triangular shape of the exposure area 204B can span the entire stitching area 200C. For example, the triangular shape may start at the second edge of the splicing area 200C and narrow to the vertex at the first edge of the splicing edge 200C. In the splicing area 200C, the width of the exposure area 204B may be reduced all the time (for example as shown in FIG. 12B) or discretely reduced at a set interval (for example, as shown in FIG. 12C).

As a result of the embodiment shape and varying width of the exposure area 204B, as the exposure area 204B extends into the splicing area 200C, the exposure intensity of the exposure area 204B decreases. By configuring the exposure area 204B to have the shape shown in the splicing area 200C (for example, by arranging a corresponding opening in the reduction mask 206B on the splicing area 200C), the exposure area 204B in the splicing area 200C The exposure intensity can also be gradually reduced, which reduces overexposure defects and increases overlap tolerance.

The exposure area 204A and the exposure area 204B overlap at the overlap area 208. When the exposure intensity in the stitching area 200C is not reduced, the overlap area 208 may be overexposed (for example, having an exposure intensity of about 200%). By gradually reducing the exposure intensity of the exposure area 204A and the exposure area 204B in the splicing area 200C, the risk of overexposing the overlapping area 208 is reduced because the first exposure (for example, the defined exposure area 204A) and the second exposure (for example, the definition The cumulative exposure intensity of the overlapping area 208 caused by the exposure area 204B) is reduced. For example, FIG. 12D shows the exposure intensity of the exposure area 204A and the exposure area 204B in each of the first patterned area 200A and the second patterned area 200B. In FIG. 12D, the x-axis represents position and the y-axis represents exposure intensity. The curve 210A corresponds to the exposure intensity of the exposure area 204A, and the curve 210B corresponds to the exposure intensity of the exposure area 204B. The slopes of the curves 210A and 210B in the splicing area 200C can correspond to and depend on the distance across the splicing area 200C, which determines the length of the triangular shape of each exposure area 204A/exposure area 204B. The cumulative exposure intensity of any given position of the photoresist 204 can be obtained by adding the corresponding intensities of the curve 210A and the curve 210B. As can be seen in FIG. 12D, the cumulative exposure intensity at any given position in the first patterned area 200A and the second patterned area 200B is in the range of about 1 (for example, 100%) and about 1.2 (for example, 120%) . In particular, the cumulative exposure intensity in the splicing area 200C (when two exposure steps are performed) is substantially the same as the cumulative exposure intensity outside the splicing area 200C (when only one exposure step is performed). By reducing overexposure, defects caused by overexposure can also be reduced (for example, over-exposure is defined).

In addition, the triangular shape of the exposure area 204A and the exposure area 204B in the splicing area 200C can also increase the overlap tolerance. FIGS. 13A, 13B, 13C, and 13D show the overlap error of the embodiment, which may be caused by the alignment error between the reduction mask 206A and the reduction mask 206B. FIG. 13A shows an embodiment in which the reduction mask 206B is translated laterally in the direction indicated by the arrow 209A toward the first patterned area 200A. Therefore, the exposure area 204B may extend to the area of the first patterned area 200A outside the stitching area 200C. FIG. 13B shows an embodiment in which the reduction mask 206B is translated laterally in the direction indicated by the arrow 209A toward the second patterned area 200B. Therefore, the exposure area 204B does not completely extend through the splicing area 200C. 13C and 13D show an embodiment in which the vertical translation of the zoom mask 206B as indicated by the arrow 209C and the arrow 209D makes the edges of the exposure area 204A and the exposure area 204B no longer aligned. Although each of FIGS. 13A, 13B, 13C, and 13D show a single overlap error, it should be understood that these errors can also be combined. It has been observed that by providing the exposure area 204A and the exposure area 204B having a triangular shape, the overlap error in any direction is allowed to be as high as 10%, while still being within manufacturing tolerance.

The triangular shape of the exposure area 204A and the exposure area 204B in the splicing area 200C allows linear changes in the exposure intensity, so that any translation does not significantly affect the cumulative exposure intensity. For example, in FIG. 13A, the part of the exposure area 204B in the first patterned area 200A outside the stitching area 200C may have a relatively low exposure intensity (for example, less than about 20%). Therefore, although the exposed area 204A in the first patterned area 200A outside the overlap area 200C is fully exposed (for example, has an exposure intensity of about 100%), the cumulative exposure intensity of the exposed area 204A and the exposed area 204B remains at about 120%, even if the overlap error shown in Figure 13A is within manufacturing tolerance. As another example, in FIG. 13B, the exposure area 204B does not extend to the area 200D of the splicing area 200C. For example, in the area 200D, only one exposure is performed (that is, the exposure corresponds to the exposure area 204A). However, because the exposed area 204A has almost sufficient exposure intensity (eg, at least 80%) in the area 200D, the underexposure of the second exposure step does not result in an unacceptable underexposed area. For example, even with the overlap error shown in FIG. 13B, in the area 200D, the cumulative exposure intensity of the exposure area 204A and the exposure area 204B remains at about 80%, which is still within the manufacturing tolerance.

Therefore, multiple reduction masks 206A/reduction masks 206B are used to expose the photoresist 204 to extend the size of the pattern in the splicing area. Although only two exposure steps are described above, it should be understood that any number of exposure steps can be applied to the photoresist 204. For example, if even a larger area is needed, additional exposure steps can be applied. Each of the additional exposure steps may overlap the previous exposure steps in the additional stitching area. For example, FIGS. 14A and 14B show multiple splicing regions. Different reduction masks 206A, reduction masks 206B, reduction masks 206D, and reduction masks 206F are used for different patterning areas 200A, 200B, 200D and 200D of the wafer. The pattern is defined in the area 200F. The patterned area 200A and the patterned area 200B overlap in the splicing area 200C; the patterned area 200A and the patterned area 200D overlap in the splicing area 200E; the patterned area 200B and the patterned area 200F overlap in the splicing area 200G And the patterned area 200D and the patterned area 200F overlap in the stitching area 200H. Exposure area 204A and exposure area 204B extend through splicing area 200C; exposure area 204A and exposure area 204D extend through splicing area 200E; exposure area 204B and exposure area 204F extend through splicing area 200G; and exposure area 204D and exposure area 204F extend Pass through the splicing area 200H. The alignment mark 302 is used to align the reduction mask 206A, the reduction mask 206B, the reduction mask 206D, and the reduction mask 206F with the pattern of the bottom layer (for example, the pattern of the dielectric layer 132, see FIG. 10). The overlap mark 304 is used to combine the patterns of the reduction mask 206A, reduction mask 206B, reduction mask 206D, and reduction mask 206F with other reduction masks 206A, reduction mask 206B, and reduction mask 206D And the zoom mask 206F is aligned. For example, the overlap mark 304A can be used to align the reduction mask 206A and the reduction mask 206B; the overlap mark 304B can be used to align the reduction mask 206B and the reduction mask 206D; and the overlap mark 304C can be used for alignment Shrinking mask 206A and shrinking mask 206F. The alignment marks (alignment mark 302 and overlap mark 304) may overlap to reduce the area required for the alignment mark. When the alignment mark 302 and the overlap mark 304 are placed outside the patterned area (for example, the patterned area 200A, the patterned area 200B, etc.), the size of the pattern can be in one direction (for example, as shown by the arrow 306 in FIG. 14A). Instructions) extension. When the alignment mark 302 and the overlap mark 304 are placed inside the patterned area (such as the patterned area 200A, the patterned area 200B, etc.), the size of the pattern can be in multiple directions (for example, as shown by the arrow 308 in FIG. 14B). Instructions). In addition, since multiple reduction masks are used to splice the patterns of the layers together, the alignment mark 302 and the overlap mark 304 can surround the pattern (for example as shown in FIG. 14A) or penetrate the pattern (for example, as shown in FIG. 14B) Set at regular intervals. The interval between adjacent alignment marks 302/overlapping marks 304 may correspond to the size of the reduction mask.

Therefore, by providing multiple exposure steps, it is possible to pattern a larger wafer by defining an overlap pattern in the splicing area by using multiple reduction masks. A low NA lithography tool with a higher DoF can be used to apply multiple exposure steps even in the case of warpage to achieve a defined pattern. The shape of the overlapping pattern may be a triangle to reduce the exposure intensity in the splicing area. By reducing the exposure intensity, manufacturing tolerance can be improved and defects can be reduced. Alternatively, other shapes that reduce the exposure intensity in the stitching area can be adopted to accommodate multiple exposure steps.

A similar exposure step can be performed in other packaging areas on the carrier substrate 100 (for example, in the second packaging area 100B) in order to define the desired pattern in the photoresist 204. Exposing the second packaging area 100B may be performed after all the exposure steps in the first packaging area 100A are completed. Alternatively, before the subsequent reduction mask (for example, the second reduction mask 206B) is used to expose the photoresist 204, each reduction mask (for example, the first reduction mask 206A) can be used for the exposure carrier substrate 100B Of each package area.

In FIG. 15, after various patterned areas and encapsulation areas of the photoresist 204 are exposed, the photoresist 204 is developed to form a plurality of openings 212 extending through the photoresist 204. 15 shows the photoresist 204 as a positive photoresist material, in which the exposed area 204A/exposed area 204B is removed due to the photoresist 204 being developed. In other embodiments, the photoresist 204 may be a negative photoresist, wherein the exposed area 204A/exposed area 204B of the photoresist 204 remains, and the unexposed area of the photoresist 204 is removed due to development.

Subsequently, in FIG. 16A, a conductive material is formed in the opening 212 by plating (such as electroplating or electroless plating or the like). The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. Subsequently, the photoresist 204 and the portions of the seed layer 133 where no conductive material is formed are removed. The photoresist 204 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist 204 is removed, the exposed portion of the seed layer 133 is removed, such as by using an acceptable etching process (such as by wet or dry etching). The remaining part of the seed layer and the conductive material forms a metallization pattern 138 and through holes. The through hole is formed in an opening that passes through the dielectric layer 132 to, for example, the through hole 112 and/or the die connector 126.

FIG. 16A shows a cross-sectional view of the metallization pattern 138. 16B, 16C, 16D, 16E, and 16F show top views of the metallization pattern 138 in the region 100C (see FIG. 16A). The area 100C includes a portion of the first patterned area 200A, the second patterned area 200B, and the stitching area 200C. The position of the metallization pattern 138 may further correspond to the exposure area 204A/exposure area 204B/exposure area 204D/exposure area 204F shown in FIGS. 14A and 14B. For example, the metallization pattern 138 may include wires disposed between adjacent alignment marks 302/overlapping marks 304.

In FIG. 16B, the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C are formed without anomaly to define the self-patterned area 200A through the stitching area 200C and continuously extend to the patterned area 200B. Conductive rewiring. In FIG. 16C, FIG. 16D, FIG. 16E, and FIG. 16F, the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C are formed with manufacturing abnormalities to define the self-patterned region 200A extends through the stitching region 200C to the patterned region 200B The conductive rewiring line. Because the manufacturing abnormality is due to the overlap error between the reduction mask (for example, the reduction mask 206A and the reduction mask 206B), each of the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C is The splicing area 200C may have the same type of manufacturing abnormalities. In FIG. 16C, a translation error occurs in the splicing area 200C, which defines a manufacturing abnormality when the sidewalls of the metallization pattern 138A/metallization pattern 138B/metallization pattern 138C are no longer aligned. In FIG. 16D, there is a gap in each of the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C in the stitching area 200C. For example, when the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C define dummy patterns, this gap is acceptable. The gap size in each of the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C may be the same. In FIG. 16E, each of the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C in the splicing area 200C has a narrower area (for example, referred to as a neck portion). The amount of narrowing of each of the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C in the splicing area 200C may be the same. The manufacturing abnormalities shown in FIGS. 16D and 16E can be caused by underexposure in the splicing area 200C (for example, as described above with respect to FIG. 13B). In FIG. 16F, each of the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C in the splicing area 200C has a wider area (for example, referred to as expansion). The amount of widening of each of the metallization pattern 138A, the metallization pattern 138B, and the metallization pattern 138C in the splicing area 200C may be the same. The manufacturing abnormality shown by FIG. 16F can be caused by overexposure in the splicing area 200C (eg, as described above with respect to FIG. 13A). Other manufacturing abnormalities are also possible, but due to the patterning method of the embodiment described above, the abnormalities are usually within manufacturing tolerance. In various embodiments, each metallization pattern in the splicing area (for example, splicing area 200C) may have the same type of manufacturing anomaly, because these anomalies are the result of overlap errors caused by multiple exposure steps, and the same The overlap error will act on the entire splicing area 200C. Generally, manufacturing anomalies can be detected as the shape difference between the required pattern of conductive features defined in the mask or layout file and the physical pattern of the manufactured conductive features. In various embodiments, manufacturing anomalies in a single splicing area may include uneven wires, wires with non-linear edges in each wire, wires with varying widths in each wire, or the like.

In FIG. 17, the dielectric layer 140 is deposited on the metallization pattern 138 and the dielectric layer 132. The dielectric layer 140 may be made of similar materials and deposited using a similar process as the dielectric layer 132. After the dielectric layer 140 is deposited, it may be patterned to form an opening exposing a portion of the metallization pattern 138. The patterning of the dielectric layer 140 may be performed by an acceptable process, such as a process similar to the multiple exposure patterning process described above for the patterned dielectric layer 132.

In FIG. 18, the metallization pattern 146 with through holes is formed on the dielectric layer 140. The metallization pattern 146 may be made of similar materials, and is formed using a process similar to that of the metallization pattern 138. For example, a seed layer can be deposited, and a photoresist can be deposited on the seed layer. Multiple exposure lithography processes as described above can be applied to the photoresist to define an opening for exposing the seed layer, and a plating process can be performed The conductive material is plated on the exposed part of the seed layer, and the photoresist and the part of the conductive material not formed on the seed layer are removed. The remaining part of the seed layer and the conductive material forms the metallization pattern 146 and the through hole. Vias are formed in the openings passing through the dielectric layer 140 to, for example, the metallization pattern 138.

In FIG. 19, the dielectric layer 148 is deposited on the metallization pattern 146 and the dielectric layer 140. The dielectric layer 148 may be made of similar materials and deposited using a similar process as the dielectric layer 132. After the dielectric layer 148 is deposited, it may be patterned to form an opening exposing a portion of the metallization pattern 146. The patterning of the dielectric layer 148 may be performed by an acceptable process, such as a process similar to the multiple exposure patterning process described above for the patterned dielectric layer 132.

In FIG. 20, a metallization pattern 154 with through holes is formed on the dielectric layer 148. The metallization pattern 154 may be made of similar materials, and is formed using a process similar to that of the metallization pattern 138. For example, a seed layer can be deposited, and a photoresist can be deposited on the seed layer. Multiple exposure lithography processes as described above can be applied to the photoresist to define an opening for exposing the seed layer, and a plating process can be performed The conductive material is plated on the exposed part of the seed layer, and the photoresist and the part of the conductive material not formed on the seed layer are removed. The remaining part of the seed layer and the conductive material forms the metallization pattern 154 and through holes. Vias are formed in openings passing through the dielectric layer 148 to, for example, portions of the metallization pattern 146.

In FIG. 21, the dielectric layer 156 is deposited on the metallization pattern 154 and the dielectric layer 148. The dielectric layer 156 may be made of similar materials and deposited using a similar process as the dielectric layer 132. After the dielectric layer 156 is deposited, it may be patterned to form openings that expose portions of the metallization pattern 154. The patterning of the dielectric layer 156 may be performed by an acceptable process, such as a process similar to the multiple exposure patterning process described above for the patterned dielectric layer 132.

The front focused wiring structure 160 is shown as an example. More or fewer dielectric layers and metallization patterns can be formed in the front-focused wiring structure 160. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed above can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed above can be repeated. Those skilled in the art will easily understand which steps and processes will be omitted or repeated.

Although the RDL wiring design described herein is discussed with respect to the front-focused wiring structure 160, the teaching of the RDL wiring process can also be applied to the back-focused wiring structure 110.

In FIG. 22, a plurality of pads 162 are formed on the outer side of the front-side heavy wiring structure 160. The pad 162 is used to couple to the conductive connector 166 (see FIG. 23 ), and may be referred to as an under bump metallurgy (UBM) 162. In the illustrated embodiment, the liner 162 is formed through the opening through the dielectric layer 156 to the metallization pattern 154. The liner 162 may be made of similar materials and formed using a process similar to that of the metallization pattern 138. For example, a seed layer can be deposited, and a photoresist can be deposited on the seed layer. Multiple exposure lithography processes as described above can be applied to the photoresist to define an opening for exposing the seed layer, and a plating process can be performed The conductive material is plated on the exposed part of the seed layer, and the photoresist and the part of the conductive material not formed on the seed layer are removed. The remaining part of the seed layer and the conductive material forms a liner 162.

In FIG. 23, a plurality of conductive connections 166 are formed on the pad 162. The conductive connectors 166 can be BGA connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-plated gold (electroless nickel-electroless palladium- immersion gold technique; ENEPIG) technology to form bumps or similar. The conductive connector 166 may include conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, similar conductive materials, or a combination thereof. In some embodiments, the solder layer is initially formed to form the conductive connection member 166 by common methods such as evaporation, electroplating, printing, solder transfer, bumping, or the like. Once the solder layer has been formed on the structure, reflow can be performed to mold the material into the desired bump shape. In another embodiment, the conductive connection member 166 is a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the metal pillar connector 166. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

In FIG. 24, the carrier substrate peeling is performed to detach (peel) the carrier substrate 100 from the backside rewiring structure (for example, the dielectric layer 104). According to some embodiments, peeling includes projecting light such as laser light or UV light onto the release layer 102 so that the release layer 102 decomposes under light and heat and the carrier substrate 100 can be removed. The structure is then turned over and placed on the tape 190.

As further shown in FIG. 25, an opening is formed through the dielectric layer 104 to expose a portion of the metallization pattern 106. For example, laser drilling, etching, or the like can be used to form the opening.

In FIG. 26, the singulation process is performed by sawing along the scribe track area (for example, between adjacent first packaging area 100A and second packaging area 100B). The sawing separates the first packaging area 100A from the second packaging area 100B.

FIG. 26 shows the resulting singulated package 400, which may be from one of the first package area 100A or the second package area 100B. The package 400 may also be referred to as an integrated fan-out (InFO) package 200.

FIG. 27 shows a package structure 570 including a package body 400 (may be referred to as a first package body 400 ), a second package body 500 and a substrate 550. The second package 500 includes a substrate 502 and one or more stacked die 508 (stacked die 508A and stacked die 508B) coupled to the substrate 502. The substrate 502 may be made of a semiconductor material, such as silicon, germanium, diamond, or the like. In some embodiments, compound materials can also be used, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, etc. Combinations and similar ones. In addition, the substrate 502 may be a silicon-on-insulator (SOI) substrate. Generally, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. In an alternative embodiment, the substrate 502 is an insulating core based on, for example, a glass fiber reinforced resin core. An example core material is glass fiber resin such as FR4. The replacement of the core material includes bismaleimide-triazine (BT) resin, or alternatively includes other printed circuit board (PCB) materials or films. A build-up film such as Ajinomoto build-up film (ABF) or other laminates can be used for the substrate 502.

The substrate 502 may include active devices and passive devices. As those skilled in the art will recognize, a wide variety of components such as transistors, capacitors, resistors, combinations of these, and the like can be used to generate the structural and functional requirements of the semiconductor package 500 design. Any suitable method can be used to form the element.

The substrate 502 may also include a metallization layer (not shown) and perforations 506. The metallization layer can be formed on the active device and the passive device, and is designed to connect various devices to form a functional circuit. The metallization layer can be formed by alternating layers of dielectric (such as low-k dielectric materials) and conductive materials (such as copper), where vias interconnect the conductive material layers and can be formed by any suitable process (such as deposition, damascene, double Mosaic or similar). In some embodiments, the substrate 502 contains substantially no active devices and passive devices.

The substrate 502 may have a bonding pad 503 on the first side of the substrate 502 for coupling to the stacked die 508, and a bonding pad 504 on the second side of the substrate 502 for coupling to the conductive connectors 514, The second side is opposite to the first side. In some embodiments, the bonding pads 503 and 504 are formed by forming recesses (not shown) into the dielectric layer (not shown) on the first side and the second side of the substrate 502. A recess may be formed to allow the bonding pad 503 and the bonding pad 504 to be embedded in the dielectric layer. In other embodiments, the recess is omitted because the bonding pad 503 and the bonding pad 504 can be formed on the dielectric layer. In some embodiments, the bonding pad 503 and the bonding pad 504 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bonding pad 503 and the bonding pad 504 may be deposited over the thin seed layer. The conductive material can be formed by an electrochemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. In one embodiment, the conductive material of the bonding pad 303 and the bonding pad 304 is copper, tungsten, aluminum, silver, gold, the like or a combination thereof.

In an embodiment, the bonding pad 503 and the bonding pad 504 are UBM including three conductive material layers (such as a titanium layer, a copper layer, and a nickel layer). However, those skilled in the art will recognize that there are many suitable material and layer configurations suitable for forming UBM 503 and UBM 504, such as chromium/chromium copper alloy/copper/gold configuration, titanium/titanium tungsten/copper configuration , Or copper/nickel/gold configuration. Any suitable materials or material layers that can be used for UBM 503 and UBM 504 are all intended to be included in the scope of the current application. In some embodiments, the through hole 506 extends through the substrate 502 and couples the at least one bonding pad 503 to the at least one bonding pad 504.

In the illustrated embodiment, the stacked die 508 is coupled to the substrate 502 by wire bonding 510, but other connections, such as conductive bumps, may be used. In one embodiment, the stacked die 508 is a stacked memory die. For example, the stacked memory die 508 may include low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4 or similar memory modules. group.

In some embodiments, the stacked die 508 and the wire bond 510 can be sealed by a molding material 512. The molding material 512 may be molded on the stacked die 508 and the wire bond 510 using compression molding, for example. In some embodiments, the molding material 512 is a molding compound, polymer, epoxy, silica filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material 512, where the curing may be thermal curing, UV curing, the like, or a combination thereof.

In some embodiments, the stacked die 508 and the wire bond 510 are embedded in the molding material 512, and after curing the molding material 512, a planarization step such as grinding is performed to remove the excess portion of the molding material 512 and A substantially flat surface is provided for the second package body 500.

After the second package body 500 is formed, the package body 500 is bonded to the first package body 400 via the conductive connection member 514, the bonding pad 504, and the metallization pattern 106. In some embodiments, the stacked memory die (stacked die 508) can be coupled to the integrated circuit die by wire bonding 510, bonding pads 503 and bonding pads 504, through holes 506, conductive connectors 514, and through holes 112.粒114.

The conductive connector 514 may be similar to the conductive connector 166 described above, and the description is not repeated herein, but the conductive connector 514 and the conductive connector 166 need not be the same. In some embodiments, before the conductive connection member 514 is joined, the conductive connection member 514 is coated with a flux (not shown), such as a non-clean flux. The conductive connecting member 514 may be dipped in flux or the flux may be sprayed onto the conductive connecting member 514. In another embodiment, the flux may be applied to the surface of the metallization pattern 106.

In some embodiments, the conductive connection member 514 may have epoxy resin flux (not shown), which is composed of epoxy resin flux remaining after it is attached to the second package 500 to the first package 400 At least some of the epoxy resin portion is formed on it before reflow. This remaining epoxy resin part can act as a primer to reduce stress and protect the joints created by reflowing the conductive connector 514. In some embodiments, a primer (not shown) may be formed between the second package 500 and the first package 400 and surround the conductive connection member 514. It can be formed by a capillary flow process after the second package 500 is attached, or the primer can be formed by a suitable deposition method before the second package 500 is attached.

The bonding between the second package 500 and the first package 400 may be solder bonding or direct metal-to-metal (such as copper to copper or tin to tin) bonding. In one embodiment, the second package 500 is joined to the first package 400 by a reflow process. During this reflow process, the conductive connection member 514 contacts the bonding pad 504 and the metallization pattern 106 to physically and electrically couple the second package 500 to the first package 400. After the bonding process, an intermetallic compound (IMC) (not shown) can be formed at the interface between the metallization pattern 106 and the conductive connector 514, and also at the interface between the conductive connector 514 and the bonding pad 504.

Although the second package 500 is shown as being attached to the first package 400 after the first package 400 is singulated from other packages in the wafer, in other embodiments, the second package 500 may be It is attached to the first package body 400 before singulation. For example, the second package 500 may be attached to the first package 400, and then the first package 400 may be singulated (for example, as described in FIG. 26).

The semiconductor package 570 includes a package 400 and a package 500 mounted to the package substrate 550. The package body 400 is mounted to the package substrate 550 using the conductive connection member 166.

The package substrate 550 may be made of semiconductor materials, such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, and the like can also be used . In addition, the package substrate 550 may be an SOI substrate. Generally speaking, the SOI substrate includes a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an alternative embodiment, the packaging substrate 550 is an insulating core based on, for example, a glass fiber reinforced resin core. An example core material is glass fiber resin such as FR4. The replacement of the core material includes bismaleimide-triazine (BT) resin, or alternatively includes other PCB materials or films. A cumulative film such as ABF or other laminates may be used for the encapsulation substrate 550.

The packaging substrate 550 may include active devices and passive devices. As those skilled in the art will recognize, a wide variety of components such as transistors, capacitors, resistors, combinations of these, and the like can be used to generate the structural and functional requirements of the semiconductor package 500 design. Any suitable method can be used to form the element.

The package substrate 550 may include a metallization layer and through holes (not shown), and a bonding pad 552 above the metallization layer and the through holes. The metallization layer can be formed on the active device and the passive device, and is designed to connect various devices to form a functional circuit. The metallization layer can be formed by alternating layers of dielectric (such as low-k dielectric materials) and conductive materials (such as copper), where vias interconnect the conductive material layers and can be formed by any suitable process (such as deposition, damascene, double Mosaic or similar). In some embodiments, the package substrate 550 contains substantially no active devices and passive devices.

In some embodiments, the conductive connector 166 may be reflowed to attach the package 400 to the bonding pad 552. The conductive connector 166 electrically and/or physically couples the package substrate 550 (including the metallization layer in the package substrate 550) to the first package body 400.

The conductive connector 166 may have an epoxy resin flux (not shown), and at least some of the epoxy resin part of the epoxy flux remaining after the flux is attached to the package base 550 with the package body 400 is reflowed Formed on it before. The remaining epoxy resin part can serve as a primer to reduce stress and protect the joints created by the reflow conductive connector 166. In some embodiments, a primer (not shown) may be formed between the first package body 400 and the package substrate 550 and surround the conductive connector 166. The primer may be formed by a capillary flow process after the package 400 is attached or may be formed by a suitable deposition method before the package 400 is attached.

It may also include other features and processes. For example, a test structure may be included to facilitate verification testing of 3D packages or 3DIC components. The test structure may include, for example, test pads formed in the redistribution layer or on the substrate to allow testing of 3D packages or 3DIC, use of probes and/or probe cards, and the like. The verification test can be performed on the intermediate structure and the final structure. In addition, the structure and method disclosed in this article can be used in combination with a test method for intermediate verification of known good crystal grains to improve yield and reduce cost.

Various embodiments use a stitching lithography process to stitch together different patterns defined by different magnification masks on different patterned areas. By using stitching lithography, the field-integrated body size is no longer limited by the exposure field size (such as the size of each optical lens). For example, the size of the pattern in the layer can be enlarged by splicing patterns of different masks in different splicing areas. Further use of gray-tone patterns and low NA steppers can increase tolerance at the splicing area and reduce manufacturing defects at the splicing area.

In one embodiment, the component includes: a molding compound to seal the first integrated circuit die and the second integrated circuit die; the dielectric layer is located in the molding compound, the first integrated circuit die, and the second integrated circuit die. Above the bulk circuit die; and a metallization pattern located above the dielectric layer and electrically connecting the first integrated circuit die to the second integrated circuit die, wherein the metallization pattern includes a plurality of wires, and a plurality of Each of the wires: extends continuously from the first area of the metallization pattern through the second area of the metallization pattern to the third area of the metallization pattern; and has the same type of manufacturing in the second area of the metallization pattern abnormal. In one embodiment, compared with the first area of the metallization pattern and the third area of the metallization pattern, the width of each of the plurality of conductive lines increases in the second area of the metallization pattern. In an embodiment, compared with the first area of the metallization pattern and the third area of the metallization pattern, the width of each of the plurality of conductive lines is reduced in the second area of the metallization pattern. In an embodiment, the sidewalls of each of the plurality of conductive lines are not aligned in the second region of the metallization pattern. In an embodiment, the second area of the metallization pattern is disposed between the first alignment mark and the second alignment mark. In an embodiment, the device further includes a third alignment mark and a fourth alignment mark, wherein the metallization pattern includes a plurality of second conductive lines between the third alignment mark and the fourth alignment mark, and among them The distance between the first alignment mark and the third alignment mark is equal to the distance between the second alignment mark and the fourth alignment mark. In an embodiment, the metallization pattern includes a plurality of third conductive lines between the first alignment mark and the third alignment mark.

In one embodiment, the method includes sealing the first integrated circuit die and the second integrated circuit die in a molding compound; in the first integrated circuit die, the second integrated circuit die, and molding Deposit a seed layer over the compound; deposit a photoresist over the seed layer; perform a first exposure process on the first patterned area of the photoresist to define the first exposure area; after performing the first exposure process, in the photoresist A second exposure process is performed on the second patterned area to define a second exposure area, wherein the first patterned area and the second patterned area overlap in the splicing area; the photoresist is developed to define the first opening, the first The opening extends from the first patterned area through the splicing area to the second patterned area; a conductive material is plated in the first opening, wherein the conductive material is electrically connected to the first integrated circuit die and the second integrated circuit die; And remove the photoresist. In an embodiment, the shape of the first exposure area is a triangle in the splicing area. In an embodiment, the shape of the second exposure area is a triangle in the splicing area. In an embodiment, performing the first exposure process includes reducing the exposure intensity applied by the first exposure process in the splicing area, wherein the exposure intensity applied by the first exposure process decreases in a direction toward the second patterned area. In one embodiment, the exposure intensity applied by the first exposure process continuously decreases in the direction toward the second patterned area. In one embodiment, the exposure intensity applied by the first exposure process decreases at discrete intervals in the direction toward the second patterned region. In one embodiment, the cumulative exposure intensity generated by the first exposure process and the second exposure process does not exceed 120% of the entire stitching area. In one embodiment, the size of the first patterned area corresponds to the size of the shrinking mask used during the first exposure process. In one embodiment, performing the first exposure process includes using a lithographic stepper tool with a numerical aperture (NA) less than 0.2.

In one embodiment, the method includes depositing a photoresist on the first die, the second die, and the molding compound, wherein the molding compound is arranged to surround the first die and the second die; using the first zoom The mask performs a first exposure process on the first patterned area of the photoresist; after performing the first exposure process, a second zoom mask is used to perform a second exposure process on the second patterned area of the photoresist. A patterned area and a second patterned area overlap in the splicing area, where performing the first exposure process includes placing the first triangular opening of the first zoom mask directly above the splicing area, and performing the second exposure therein The manufacturing process includes placing the second triangular opening of the second reduction mask directly above the splicing area; developing the photoresist to define a third opening in the photoresist, wherein the third opening extends from the first patterned area through the splicing area To the second patterned area; and plating a conductive material in the third opening, wherein the conductive material electrically connects the first die to the second die. In one embodiment, performing the first exposure process includes: placing one side of the first triangular opening at the first edge of the splicing area; placing the vertex of the first triangular opening at the second edge of the splicing area; Place one side of the second triangular opening at the second edge of the splicing area; and place the vertex of the second triangular opening at the first edge of the splicing area. In one embodiment, the method further includes using a first alignment mark to align the first reduction mask with a layer under the photoresist; and using an overlap mark to make the second reduction mask and the first The pattern defined by the zoom mask is aligned. In an embodiment, the first alignment mark overlaps with the overlap mark.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspect of the disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other methods and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and those skilled in the art can make in this article without departing from the spirit and scope of the disclosure. Changes, substitutions and changes.

100: carrier substrate 100A: The first package area 100B: second packaging area 100C: District 102: release layer 104, 108, 132, 140, 148, 156: Dielectric layer 106, 138, 138A, 138B, 138C, 146, 154: metallization pattern 110: Back-side wiring structure 112, 506: Perforation 114: Integrated Circuit Die 116: Adhesive 118: Semiconductor substrate 120: Interconnect structure 122, 162: liner 124: Passivation film 126: Die connector 128: Dielectric material 130: Seal body 132A, 132B, 204A, 204B, 204D, 204F: exposure area 133: Seed Layer 160: Front focus on wiring structure 166, 514: Conductive connector 184: Sawing 190: Tape 200: Integrated fan-out package 200A: the first patterned area 200B: second patterned area 200C, 200E, 200G, 200H: splicing area 200D, 200F: patterned area 202A, 202B, 206A, 206B, 206D, 206F: Shrink mask 204: photoresist 208: Overlap Zone 209A, 209C, 209D, 306, 308: Arrow 210A, 210B: Curve 212: open 302: Alignment mark 303, 304, 503, 504, 552: bonding pad 304, 304A, 304B, 304C: overlapping marks 510: Wire Bonding 400, 500: package body 502, 550: Base 508, 508A, 508B: stacked die 512: molding material 570: Package structure

When reading in conjunction with the accompanying drawings, the aspect of the present disclosure can be best understood from the following embodiments. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or decreased for clarity of discussion. FIGS. 1 to 3, 4A, 4B, 5 to 10, 11A, 11B, 11C, 12A, 12B, and 12C show differences in intermediate steps of manufacturing semiconductor packages according to various embodiments view. FIG. 12D shows an exposure intensity curve of a lithography process according to various embodiments. Figure 13A, Figure 13B, Figure 13C, Figure 13D, Figure 14A, Figure 14B, Figure 15, Figure 16A, Figure 16B, Figure 16C, Figure 16D, Figure 16E, Figure 16F and Figure 17 to Figure 27 show according to various embodiments Different views of the intermediate steps of manufacturing a semiconductor package.

100: carrier substrate

100A: The first package area

100B: second packaging area

100C: District

102: release layer

104, 108, 132: Dielectric layer

106, 138: Metallized pattern

110: Back-side wiring structure

112: Piercing

114: Integrated Circuit Die

116: Adhesive

126: Die connector

128: Dielectric material 130: Seal body

200A: the first patterned area

200B: second patterned area

200C: splicing area

Claims (20)

A component including: Molding compound to seal the first integrated circuit die and the second integrated circuit die; A dielectric layer above the molding compound, the first integrated circuit die and the second integrated circuit die; and A metallization pattern is located on the dielectric layer and electrically connects the first integrated circuit die to the second integrated circuit die, wherein the metallization pattern includes a plurality of wires, and Each of the multiple wires: Extend continuously from the first region of the metallization pattern through the second region of the metallization pattern to the third region of the metallization pattern; and There are the same type of manufacturing abnormalities in the second region of the metallization pattern. The device according to claim 1, wherein each of the plurality of conductive lines is compared with the first region of the metallization pattern and the third region of the metallization pattern The width of is increased in the second region of the metallization pattern. The device according to claim 1, wherein each of the plurality of conductive lines is compared with the first region of the metallization pattern and the third region of the metallization pattern The width of is reduced in the second region of the metallization pattern. The device according to claim 1, wherein the sidewalls of each of the plurality of conductive lines are not aligned in the second region of the metallization pattern. The device according to item 1 of the scope of patent application, wherein the second area of the metallization pattern is disposed between the first alignment mark and the second alignment mark. The device described in item 5 of the scope of the patent application further includes a third alignment mark and a fourth alignment mark, wherein the metallization pattern is included between the third alignment mark and the fourth alignment mark And the distance between the first alignment mark and the third alignment mark is equal to the distance between the second alignment mark and the fourth alignment mark distance. The element according to the sixth item of the scope of patent application, wherein the metallization pattern includes a plurality of third conductive lines between the first alignment mark and the third alignment mark. One method includes: Sealing the first integrated circuit die and the second integrated circuit die in a molding compound; Depositing a seed layer on the first integrated circuit die, the second integrated circuit die and the molding compound; Depositing a photoresist on the seed layer; Performing a first exposure process on the first patterned area of the photoresist to define a first exposure area; After the first exposure process is performed, a second exposure process is performed on the second patterned area of the photoresist to define a second exposure area, wherein the first patterned area and the second patterned area Overlap in the splicing area; Developing the photoresist to define a first opening, the first opening extending from the first patterned area through the splicing area to the second patterned area; Plating a conductive material in the first opening, wherein the conductive material is electrically connected to the first integrated circuit die and the second integrated circuit die; and Remove the photoresist. The method according to item 8 of the scope of patent application, wherein the shape of the first exposure area is a triangle in the splicing area. The method according to item 8 of the scope of patent application, wherein the shape of the second exposure area is a triangle in the splicing area. The method according to item 8 of the scope of patent application, wherein performing the first exposure process includes reducing the exposure intensity applied by the first exposure process in the splicing area, wherein the first exposure process applies The exposure intensity decreases in the direction toward the second patterned area. The method according to claim 11, wherein the exposure intensity applied by the first exposure process continuously decreases in the direction toward the second patterned area. The method according to claim 11, wherein the exposure intensity applied by the first exposure process decreases at discrete intervals in a direction toward the second patterned region. The method according to claim 11, wherein the cumulative exposure intensity generated by the first exposure process and the second exposure process does not exceed 120% in the entire splicing area. The method according to claim 11, wherein the size of the first patterned area corresponds to the size of the reduction mask used during the first exposure process. The method according to claim 11, wherein performing the first exposure process includes using a lithography stepper tool with a numerical aperture (NA) less than 0.2. One method includes: Depositing a photoresist on the first die, the second die, and the molding compound, wherein the molding compound is arranged to surround the first die and the second die; Performing a first exposure process on the first patterned area of the photoresist by using a first zoom mask; After the first exposure process is performed, a second exposure process is performed on the second patterned area of the photoresist using a second reduction mask, wherein the first patterned area and the second patterned area The areas overlap in the splicing area, wherein performing the first exposure process includes placing the first triangular opening of the first reduction mask directly above the splicing area, and performing the second exposure process therein Including placing the second triangular opening of the second zoom mask directly above the splicing area; Developing the photoresist to define a third opening in the photoresist, wherein the third opening extends from the first patterned area through the splicing area to the second patterned area; and A conductive material is plated in the third opening, wherein the conductive material electrically connects the first die to the second die. The method according to item 17 of the scope of patent application, wherein performing the first exposure process includes: Place one side of the first triangular opening on the first edge of the splicing area: Placing the vertex of the first triangular opening on the second edge of the splicing area; Placing one side of the second triangular opening at the second edge of the splicing area; and The apex of the second triangular opening is placed at the first edge of the splicing area. The method described in item 17 of the scope of patent application further includes: Using a first alignment mark to align the first reduction mask with the layer under the photoresist; and An overlap mark is used to align the second reduction mask with the pattern defined by the first reduction mask. The method according to item 19 of the scope of patent application, wherein the first alignment mark overlaps the overlap mark.

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