US20130155556A1 - Electrostatic discharge protection circuit and method for radio frequency semiconductor device - Google Patents
Electrostatic discharge protection circuit and method for radio frequency semiconductor device Download PDFInfo
- Publication number
- US20130155556A1 US20130155556A1 US13/332,095 US201113332095A US2013155556A1 US 20130155556 A1 US20130155556 A1 US 20130155556A1 US 201113332095 A US201113332095 A US 201113332095A US 2013155556 A1 US2013155556 A1 US 2013155556A1
- Authority
- US
- United States
- Prior art keywords
- esd
- coupled
- voltage terminal
- intermediate node
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Definitions
- ESD electrostatic discharge
- FIG. 1 is a schematic block diagram of an ESD protection circuit in accordance with some embodiments.
- FIG. 4 is a flow chart of an ESD protection method in accordance with some embodiments.
- the ESD protection circuit 100 is arranged to protect an internal radio frequency (RF) circuit 180 from ESD events.
- the ESD protection circuit 100 and the RF circuit 180 together define an RF semiconductor device.
- the ESD protection circuit 100 and RF circuit 180 are incorporated in a single IC, or on a single substrate.
- the RF circuit 180 includes one or more semiconductor components.
- the RF circuit 180 includes one or more complementary metal-oxide-semiconductor (CMOS) components.
- CMOS complementary metal-oxide-semiconductor
- the RF circuit 180 is configured to receive, process and/or output RF signals.
- the RF operating frequency at which the RF circuit 180 is configured to operate is in the GHz spectrum and higher.
- the RF operating frequency of the RF circuit 180 is 60 GHz and up to the THz spectrum.
- the RF circuit 180 includes an RF millimeter-wave front-end circuit.
- the RF circuit 180 is coupled to the first power supply voltage terminal 110 and second power supply voltage terminal 120 , and includes an RF input pad RF in . In some embodiments, the RF circuit 180 further includes an RF output pad RF out .
- the RF input pad RF in is arranged to receive an RF input signal having an RF operating frequency at which the RF circuit 180 is configured to operate.
- ESD events ESD pulses of different polarities are applied to the RF input pad RF in . Without the ESD protection circuit 100 , such ESD events cause excessive and potentially damaging voltages or currents in the RF circuit 180 .
- the first power supply voltage terminal 110 is configured to receive a first power supply voltage for the RF circuit 180
- the second power supply voltage terminal is configured to receive a second power supply voltage for the RF circuit 180
- the first power supply voltage is a positive power supply voltage VDD
- the second power supply voltage is a ground voltage.
- Other power supply arrangements are within the scope of this disclosure.
- the power clamp 140 is coupled between the first and second power supply voltage terminals 110 , 120 .
- the power clamp 140 is a normally closed device which is closed during normal operation of the RF circuit 180 . Specifically, the power clamp 140 is closed if the voltage difference between the first power supply voltage terminal 110 and the second power supply voltage terminal 120 is within a predetermined range, e.g., around (VDD ⁇ VSS). When the voltage difference across the power clamp 140 is greater than a threshold voltage of the power clamp 140 , the power clamp 140 is opened to conduct the current from the first power supply voltage terminal 110 to the second power supply voltage terminal 120 .
- the first ESD block 150 is coupled between the intermediate node 130 and the first power supply voltage terminal 110 .
- the first ESD block 150 is configured to direct an ESD pulse of a first polarity toward the first power supply voltage terminal 110 during an ESD event.
- the second ESD block 160 is coupled between the intermediate node 130 and the second power supply voltage terminal 120 .
- the second ESD block 160 is configured to direct an ESD pulse of a second, opposite polarity toward the second power supply voltage terminal 120 .
- the power clamp 140 conducts the ESD current from the first power supply voltage terminal 110 to the second power supply voltage terminal 120 , thereby preventing the voltage surge on the first power supply voltage terminal 110 from damaging circuitry of the RF circuit 180 .
- ESD events occurring at the RF input pad RF in are unlikely to cause excess voltages to be applied to the circuitry of the RF circuit 180 , thereby avoiding dielectric breakdown in various semiconductor devices of the RF circuit 180 .
- the first ESD block 150 and/or second ESD block 160 include one or more elements, such as diodes, which have parasitic capacitance. At certain RF operating frequencies, such parasitic capacitance, if not isolated from the RF input pad begins to affect RF performance of the RF circuit 180 .
- the first ESD block 150 and second ESD block 160 are isolated from the RF input pad RF in by the large impedance of the resonance circuit 170 during normal operation of the RF circuit 180 .
- the resonance circuit 170 exhibits a much lower impedance to an ESD pulse at the RF input pad RF in , and permits the ESD pulse to be conducted through to the intermediate node 130 and then to either the first power supply voltage terminal 110 or the second power supply voltage terminal 120 depending on the ESD pulse polarity. Functionality of both the ESD protection circuit 100 and the RF circuit 180 during ESD events and normal RF operation is therefore ensured.
- the resonance circuit 170 then exhibits a very large, theoretically infinite, impedance to the RF input signal at the RF input pad RF in and effectively isolates the RF input pad RF in from parasitic capacitance of the first ESD block 150 and/or second ESD block 160 behind the resonance circuit 170 .
- the impedance of the resonance circuit 170 is very low, and ESD currents are permitted to flow through the resonance circuit 170 to other components of the ESD protection circuit 100 .
- the voltage difference across the NMOS transistor MN exceeds a threshold value and the NMOS transistor MN undergoes snapback where the source, drain, and substrate of the NMOS transistor MN form a forward biased N-P-N bipolar junction transistor which conducts current from power supply voltage terminal VDD to ground voltage terminal VSS, thereby preventing the voltage surge from affecting the LNA.
- a similar snapback operation takes place when an excess voltage drop occurs on the ground voltage terminal VSS.
- other power clamp configurations are usable instead of the NMOS transistor MN.
- the LC resonance circuit 270 includes an inductor L T and an element that exhibits a capacitive characteristic at the RF operating frequency.
- the element is a capacitor C T .
- the inductor L r and capacitor C T are coupled in parallel between the RF input pad RF in and the intermediate node 130 .
- the LC resonance circuit 270 includes a resistor and functions as an RLC resonance circuit.
- any connections among the inductor L T , the capacitor C T , any resistor included in the LC resonance circuit 270 , the RF input pad RF in and the intermediate node 130 are usable, provided that the LC resonance circuit 270 has a resonance frequency that matches the RF operating frequency of the LNA.
- RF input signals at the RF input pad RF in are isolated from the diode D T and diode D B (and also from the diodes' parasitic capacitance) by the LC resonance circuit 270 as described with respect to the resonance circuit 170 .
- the ESD current which has a much lower frequency than the RF operating frequency is transmitted through the inductor L T in the LC resonance circuit 270 , to the intermediate node 130 , and then either though the diode D T or the diode D B depending on the polarity of the ESD event.
- the inductor L T is the only inductor in the whole ESD protection circuit 200 . In some embodiments, the inductor L T is the only inductor in both a first ESD current path from the RF input pad RF in to the intermediate node 130 and then to the power supply voltage terminal VDD, and a second ESD current path from the RF input pad RF in to the intermediate node 130 and then to the ground voltage terminal VSS.
- FIGS. 3A-3G are schematic circuit diagrams of various ESD protection circuits in accordance with some embodiments.
- An ESD protection circuit 300 A in FIG. 3A is similar to the ESD protection circuit 200 , except that the capacitor C T of the ESD protection circuit 200 is replaced by an ESD block 310 which is coupled in parallel with the inductor L T .
- an ESD block such as the ESD block 310 , has parasitic capacitance which, under certain circumstances, becomes significant at the RF operating frequency of the LNA.
- the parasitic capacitance of the ESD block 310 is used, in combination with the inductor L T , to isolate parasitic capacitance of the diode D T and diode D B from RF input signals during normal operation of the LNA.
- the ESD block 310 performs the ESD protection function and conducts, in addition to the inductor L T , the ESD current toward the diode D T and/or the diode D B .
- multiple ESD current paths are provided which improves the ESD performance.
- ESD protection circuits 300 B, 300 C, 300 D in FIGS. 3B , 3 C, 3 D realize the ESD block 310 of the ESD protection circuit 300 A by at least one diode.
- the ESD protection circuit 300 B in FIG. 3B realizes the ESD block 310 of the ESD protection circuit 300 A by a pair of diode D 1 and diode D 2 both of which are coupled in parallel with the inductor L T .
- the diode D 1 has an anode coupled to the intermediate node 130 and a cathode coupled to the RF input pad RF in .
- the diode D 2 has an anode coupled to the RF input pad RF in and a cathode coupled to the intermediate node 130 .
- the parasitic capacitance of the diode D 1 and diode D 2 is used, in combination with the inductor L T , to isolate parasitic capacitance of the diode D T and diode D B from RF input signals during normal operation of the LNA.
- the diode D 2 conducts, in addition to the inductor L T , the ESD current toward the diode D T and then to the power supply voltage terminal VDD.
- the diode D 1 conducts, in addition to the inductor L T , the ESD current toward the diode D B and then to the ground voltage terminal VSS.
- the diode D 1 conducts, in addition to the inductor L T , the ESD current toward the diode D B and then to the ground voltage terminal VSS.
- the ESD protection circuit 300 C in FIG. 3C realizes the ESD block 310 of the ESD protection circuit 300 A by one diode D 2 coupled in parallel with the inductor L r .
- the inductor L T By tuning the inductor L T based on the parasitic capacitance of the diode D 2 , a resonance frequency that matches the RF operating frequency of the LNA is achieved.
- the parasitic capacitance of the diode D 2 is used, in combination with the inductor L T , to isolate parasitic capacitance of the diode D T and diode D B from RF input signals during normal operation of the LNA.
- the diode D 2 conducts, in addition to the inductor L T , the ESD current toward the diode D T and then to the power supply voltage terminal VDD.
- the ESD current is conducted by the inductor L T toward the diode D B and then to the ground voltage terminal VSS.
- the ESD protection circuit 300 D in FIG. 3D realizes the ESD block 310 of the ESD protection circuit 300 A by one diode D 1 coupled in parallel with the inductor L T .
- a resonance frequency that matches the RF operating frequency of the LNA is achieved.
- the parasitic capacitance of the diode D 1 is used, in combination with the inductor L T , to isolate parasitic capacitance of the diode D T and diode D B from RF input signals during normal operation of the LNA.
- the ESD current is conducted by the inductor L T toward the diode D T and then to the power supply voltage terminal VDD.
- the ESD current is conducted by the diode D 1 , in addition to the inductor L T , toward the diode D B and then to the ground voltage terminal VSS.
- An ESD protection circuit 300 E in FIG. 3E realizes the ESD block 310 of the ESD protection circuit 300 A by an NMOS transistor 320 .
- the NMOS transistor 320 has a source and a gate commonly coupled to the intermediate node 130 , and a drain coupled to the RF input pad RF in .
- the NMOS transistor 320 is configured and operates similarly to the gate-grounded NMOS transistor MN described with respect to FIG. 2 . Specifically, the NMOS transistor 320 is normally closed, and becomes conductive during an ESD event. By tuning the inductor L T based on the parasitic capacitance of the NMOS transistor 320 , a resonance frequency that matches the RF operating frequency of the LNA is achieved.
- the parasitic capacitance of the NMOS transistor 320 is used, in combination with the inductor L T , to isolate parasitic capacitance of the diode D T and diode D B from RF input signals during normal operation of the LNA.
- the NMOS transistor 320 becomes conductive and conducts, in addition to the inductor L T , the ESD current toward the diode D B and/or diode D T .
- multiple ESD current paths are provided which improves the ESD performance.
- An ESD protection circuit 300 F in FIG. 3F realizes the ESD block 310 of the ESD protection circuit 300 A by a silicon-controlled rectifier (SCR) 330 .
- the SCR 330 has an anode A coupled to the intermediate node 130 , and a cathode C coupled to the RF input pad RF in .
- a control gate G of the SCR 330 is floating.
- the SCR 330 operates similarly to the gate-grounded NMOS transistor MN described with respect to FIG. 2 . Specifically, the SCR 330 is normally closed, and snapbacks to become conductive during an ESD event.
- the parasitic capacitance of the SCR 330 is used, in combination with the inductor L T , to isolate parasitic capacitance of the diode D T and diode D B from RF input signals during normal operation of the LNA.
- the SCR 330 becomes conductive and conducts, in addition to the inductor L T , the ESD current toward the diode D B and/or diode D T .
- multiple ESD current paths are provided which improves the ESD performance.
- An ESD protection circuit 300 G in FIG. 3G is similar to the ESD protection circuit 300 A, except that a resistor R is coupled in parallel to the ESD block 310 and the inductor L T . Specifically, the resistor R has a first end coupled to the RF input pad RF in and a second, opposite end coupled to the intermediate node 130 . In some embodiments, a resistance value of the resistor R is in a range from a few ohms to a few megaohms. By tuning the inductor L T and/or the resistance value of the resistor R based on the parasitic capacitance of the ESD block 310 , a resonance frequency that matches the RF operating frequency of the LNA is achieved.
- the presence of the resistor R permits easy tuning of the resonance frequency of the LC resonance circuit 270 .
- the ESD protection circuit 300 G operates similarly to the ESD protection circuit 300 A, except that during an ESD event, the ESD current is conducted by not only the inductor L T but also the resistor R. Thus, multiple ESD current paths are provided which improves the ESD performance.
- FIG. 4 is a flow chart of an ESD protection method 400 in accordance with some embodiments.
- a first ESD pulse e.g., 191
- the first ESD pulse is transmitted along a first ESD current path from the RF input pad RF in , through a resonance circuit (e.g., 270 ), to an intermediate node 130 , then through a first diode (e.g., diode D T ) to a power supply voltage terminal VDD of the RF semiconductor device.
- the second ESD pulse upon occurrence of a second ESD pulse (e.g., 192 ) of a negative polarity at the RF input pad RF in , the second ESD pulse is transmitted along a second ESD current path from the RF input pad RF in , through the resonance circuit 270 , to the intermediate node 130 , then through a second diode (e.g., diode D B ) to a ground voltage terminal VSS of the RF semiconductor device.
- the resonance circuit 270 is common to both the first and second ESD current paths.
- the resonance circuit 270 upon application of an RF input signal, which has an RF operating frequency matching a resonance frequency of the resonance circuit 270 , to the RF input pad RF in , the resonance circuit 270 exhibits very large impedance to the RF input signal and shields the RF input signal and the RF input pad from parasitic capacitances of the first and second diodes.
- an electrostatic discharge (ESD) protection circuit for a radio frequency (RF) semiconductor device comprises a first power supply voltage terminal configured to receive a first power supply voltage, and a second power supply voltage terminal configured to receive a second power supply voltage.
- a power clamp is coupled between the first and second power supply voltage terminals.
- An RF input pad is configured to receive an RF input signal having an RF operating frequency for the RF semiconductor device.
- a first ESD block is coupled between an intermediate node and the first power supply voltage terminal, to direct an ESD pulse of a first polarity toward the first power supply voltage terminal.
- a second ESD block is coupled between the intermediate node and the second power supply voltage terminal, to direct an ESD pulse of a second, opposite polarity toward the second power supply voltage terminal.
- a resonance circuit is coupled between the RF input pad and the intermediate node. The resonance circuit is configured to present a greater impedance to the RF input signal having the RF operating frequency than to the ESD pulses.
- a radio frequency (RF) semiconductor device comprises: a power supply voltage terminal, a ground voltage terminal and an intermediate node.
- An internal RF circuit to be protected from ESD pulses is coupled to the power supply voltage terminal and ground voltage terminal.
- a power clamp is coupled between the power supply voltage terminal and the ground voltage terminal.
- An RF input pad is coupled to the internal RF circuit and configured to receive an RF input signal having an RF operating frequency for the internal RF circuit.
- a first diode has an anode coupled to the intermediate node and a cathode coupled to the power supply voltage terminal.
- a second diode has a cathode coupled to the intermediate node and an anode coupled to the ground voltage terminal.
- An LC resonance circuit is coupled between the RF input pad and the intermediate node.
- the LC resonance circuit includes an inductor which is the only inductor in an ESD current path from the RF input pad to the intermediate node and then to the power supply voltage terminal and the ground voltage terminal.
- the first ESD pulse upon occurrence of a first ESD pulse of a positive polarity at an RF input pad of the RF semiconductor device, the first ESD pulse is transmitted from the RF input pad, through an LC resonance circuit, to an intermediate node, through a first diode to a power supply voltage terminal of the RF semiconductor device.
- the second ESD pulse is transmitted from the RF input pad, through the LC resonance circuit, to the intermediate node, through to a second diode to a ground voltage terminal of the RF semiconductor device.
Abstract
Description
- The recent trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices which consume less power, yet provide more functionally at higher speeds than before. The miniaturization process has also increased the devices' susceptibility to electrostatic discharge (ESD) events due to various factors, such as thinner dielectric thicknesses and associated lowered dielectric breakdown voltages. ESD is one of the causes of electronic circuit damage and is also one of the considerations in semiconductor advanced technology.
- One or more embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout. The drawings are not to scale, unless otherwise disclosed.
-
FIG. 1 is a schematic block diagram of an ESD protection circuit in accordance with some embodiments. -
FIG. 2 is a schematic circuit diagram of an ESD protection circuit in accordance with some embodiments. -
FIGS. 3A-3G are schematic circuit diagrams of various ESD protection circuits in accordance with some embodiments. -
FIG. 4 is a flow chart of an ESD protection method in accordance with some embodiments. - It is to be understood that the following disclosure provides many different embodiments or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this description will be thorough and complete, and will fully convey the inventive concept to those of ordinary skill in the art. It will be apparent, however, that one or more embodiments may be practiced without these specific details.
- The drawings are not drawn to scale, and include certain features that are exaggerated for clarity. Like reference numerals in the drawings denote like elements. The elements and regions illustrated in the figures are schematic in nature, and thus relative sizes or intervals illustrated in the figures are not intended to limit the scope of the inventive concept.
-
FIG. 1 is a schematic block diagram of anESD protection circuit 100 in accordance with some embodiments. TheESD protection circuit 100 includes a first powersupply voltage terminal 110, a second powersupply voltage terminal 120, and anintermediate node 130. TheESD protection circuit 100 further includes apower clamp 140, first andsecond ESD blocks resonance circuit 170. - The
ESD protection circuit 100 is arranged to protect an internal radio frequency (RF)circuit 180 from ESD events. TheESD protection circuit 100 and theRF circuit 180 together define an RF semiconductor device. In some embodiments, theESD protection circuit 100 andRF circuit 180 are incorporated in a single IC, or on a single substrate. In some embodiments, theRF circuit 180 includes one or more semiconductor components. In some embodiments, theRF circuit 180 includes one or more complementary metal-oxide-semiconductor (CMOS) components. TheRF circuit 180 is configured to receive, process and/or output RF signals. In some embodiments, the RF operating frequency at which theRF circuit 180 is configured to operate is in the GHz spectrum and higher. In some embodiments, the RF operating frequency of theRF circuit 180 is 60 GHz and up to the THz spectrum. In some embodiments, theRF circuit 180 includes an RF millimeter-wave front-end circuit. - The
RF circuit 180 is coupled to the first powersupply voltage terminal 110 and second powersupply voltage terminal 120, and includes an RF input pad RFin. In some embodiments, theRF circuit 180 further includes an RF output pad RFout. The RF input pad RFin is arranged to receive an RF input signal having an RF operating frequency at which theRF circuit 180 is configured to operate. During ESD events, ESD pulses of different polarities are applied to the RF input pad RFin. Without theESD protection circuit 100, such ESD events cause excessive and potentially damaging voltages or currents in theRF circuit 180. - The first power
supply voltage terminal 110 is configured to receive a first power supply voltage for theRF circuit 180, and the second power supply voltage terminal is configured to receive a second power supply voltage for theRF circuit 180. In some embodiments, the first power supply voltage is a positive power supply voltage VDD, and the second power supply voltage is a ground voltage. Other power supply arrangements are within the scope of this disclosure. - The
power clamp 140 is coupled between the first and second powersupply voltage terminals power clamp 140 is a normally closed device which is closed during normal operation of theRF circuit 180. Specifically, thepower clamp 140 is closed if the voltage difference between the first powersupply voltage terminal 110 and the second powersupply voltage terminal 120 is within a predetermined range, e.g., around (VDD−VSS). When the voltage difference across thepower clamp 140 is greater than a threshold voltage of thepower clamp 140, thepower clamp 140 is opened to conduct the current from the first powersupply voltage terminal 110 to the second powersupply voltage terminal 120. - The
first ESD block 150 is coupled between theintermediate node 130 and the first powersupply voltage terminal 110. Thefirst ESD block 150 is configured to direct an ESD pulse of a first polarity toward the first powersupply voltage terminal 110 during an ESD event. Thesecond ESD block 160 is coupled between theintermediate node 130 and the second powersupply voltage terminal 120. Thesecond ESD block 160 is configured to direct an ESD pulse of a second, opposite polarity toward the second powersupply voltage terminal 120. - For example, when a
positive ESD pulse 191 occurs at the RF input pad RFin and has a voltage higher than VDD, thefirst ESD block 150 conducts to thereby divert an ESD current caused by thepositive ESD pulse 191 away from theRF circuit 180. Specifically, the ESD current flows from the RF input pad RFin, via theintermediate node 130, to the first powersupply voltage terminal 110. The ESD current causes a voltage surge on the first powersupply voltage terminal 110 and, as a result, an excess voltage difference occurs across thepower clamp 140. If the excess voltage difference is greater than the threshold voltage of thepower clamp 140, thepower clamp 140 conducts the ESD current from the first powersupply voltage terminal 110 to the second powersupply voltage terminal 120, thereby preventing the voltage surge on the first powersupply voltage terminal 110 from damaging circuitry of theRF circuit 180. - If a
negative ESD pulse 192 occurs at the RF input pad RFin and has a lower voltage than VSS, thesecond ESD block 160 conducts to divert an ESD current caused by thenegative ESD pulse 192 away from theRF circuit 180. Specifically, the ESD current flows from the RF input pad RFin, via theintermediate node 130, to the second powersupply voltage terminal 120. The ESD current causes a voltage drop on the second powersupply voltage terminal 120 and, as a result, an excess voltage difference occurs across thepower clamp 140. If the excess voltage difference is greater than the threshold voltage of thepower clamp 140, thepower clamp 140 conducts current from the first powersupply voltage terminal 110 to the second powersupply voltage terminal 120, thereby preventing the voltage drop on the second powersupply voltage terminal 120 from damaging circuitry of theRF circuit 180. - As a result of the protection action of the
ESD protection circuit 100, ESD events occurring at the RF input pad RFin are unlikely to cause excess voltages to be applied to the circuitry of theRF circuit 180, thereby avoiding dielectric breakdown in various semiconductor devices of theRF circuit 180. - Several components of the
ESD protection circuit 100, while useful for ESD protection purposes, are isolated from RF input signals at the RF input pad RFin during normal operation of theRF circuit 180. For example, thefirst ESD block 150 and/orsecond ESD block 160 include one or more elements, such as diodes, which have parasitic capacitance. At certain RF operating frequencies, such parasitic capacitance, if not isolated from the RF input pad begins to affect RF performance of theRF circuit 180. - The
resonance circuit 170 is included in theESD protection circuit 100 for isolating the parasitic capacitance from the RF input pad RFin during normal operation of theRF circuit 180. Theresonance circuit 170 is coupled between the RF input pad RFin and theintermediate node 130 and is common to both thefirst ESD block 150 and thesecond ESD block 160. Theresonance circuit 170 is configured to present various impedances to signals of various frequencies. Specifically, theresonance circuit 170 presents a greater impedance to signals of RF frequencies than to ESD pulses of much lower frequencies. Thus, during normal operation of theRF circuit 180, theresonance circuit 170 presents a large impedance to the RF input signal applied to the RF input pad RFin. As a result, thefirst ESD block 150 andsecond ESD block 160, as well as their parasitic capacitance, are isolated from the RF input pad RFin by the large impedance of theresonance circuit 170 during normal operation of theRF circuit 180. During an ESD event, theresonance circuit 170 exhibits a much lower impedance to an ESD pulse at the RF input pad RFin, and permits the ESD pulse to be conducted through to theintermediate node 130 and then to either the first powersupply voltage terminal 110 or the second powersupply voltage terminal 120 depending on the ESD pulse polarity. Functionality of both theESD protection circuit 100 and theRF circuit 180 during ESD events and normal RF operation is therefore ensured. - In some embodiments, the
resonance circuit 170 has a resonance frequency that matches an RF operating frequency of theRF circuit 180, or an RF operating frequency of the RF input signal applied to theRF circuit 180. The resonance frequency is considered to match the RF operating frequency if the resonance frequency is in a range from 80% to 120% of the RF operating frequency. In some embodiments, the resonance frequency is in a range from 90% to 110% of the RF operating frequency. In some embodiments, the resonance frequency is in a range from 95% to 105% of the RF operating frequency. With a resonance frequency that matches the RF operating frequency, theresonance circuit 170 is at or near resonance when an RF input signal of the RF operating frequency is applied to the RF input pad RFin. Theresonance circuit 170 then exhibits a very large, theoretically infinite, impedance to the RF input signal at the RF input pad RFin and effectively isolates the RF input pad RFin from parasitic capacitance of thefirst ESD block 150 and/or second ESD block 160 behind theresonance circuit 170. At a much lower frequency of an ESD event, the impedance of theresonance circuit 170 is very low, and ESD currents are permitted to flow through theresonance circuit 170 to other components of theESD protection circuit 100. By including acommon resonance circuit 170 for shielding both thefirst ESD block 150 and the second ESD block 160 from RF input signals, the circuit complexity and manufacture costs are reduced. -
FIG. 2 is a schematic circuit diagram of anESD protection circuit 200 in accordance with some embodiments. TheESD protection circuit 200 includes a diode DT which functions as thefirst ESD block 150, a diode DB which functions as thesecond ESD block 160, a gate-grounded n-channel metal-oxide semiconductor (NMOS) transistor MN which functions as thepower clamp 140, and an LC resonance circuit 270 which functions as theresonance circuit 170. - The
RF circuit 180 to be protected by theESD protection circuit 200 is a low noise amplifier (LNA). In some embodiments, the LNA is coupled to the outside (e.g., via the RF output pad RFout) by an antenna and is often exposed to ESD events. Other RF circuits are usable in some embodiments. - The diode DT has an anode coupled to the
intermediate node 130 and a cathode coupled to the power supply voltage terminal VDD. The diode DB has an anode coupled to the ground voltage terminal VSS and a cathode coupled to theintermediate node 130. In some embodiments, other ESD block configurations are usable for thefirst ESD block 150 and/or the second ESD block 160 instead of one or both of the diode DT and diode DB. - The NMOS transistor MN has a drain coupled to a power supply voltage terminal VDD, and a source and a gate commonly coupled to a ground voltage terminal VSS. During normal operation of the LNA without a voltage surge or drop on the power supply voltage terminal VDD or ground voltage terminal VSS, the NMOS transistor MN remains in the OFF state, because its gate-to-source voltage (zero) is less than a threshold voltage of the NMOS transistor MN. During an ESD event with a voltage surge on the power supply voltage terminal VDD, the voltage difference across the NMOS transistor MN exceeds a threshold value and the NMOS transistor MN undergoes snapback where the source, drain, and substrate of the NMOS transistor MN form a forward biased N-P-N bipolar junction transistor which conducts current from power supply voltage terminal VDD to ground voltage terminal VSS, thereby preventing the voltage surge from affecting the LNA. A similar snapback operation takes place when an excess voltage drop occurs on the ground voltage terminal VSS. In some embodiments, other power clamp configurations are usable instead of the NMOS transistor MN.
- The LC resonance circuit 270 includes an inductor LT and an element that exhibits a capacitive characteristic at the RF operating frequency. In the particular embodiment of the
ESD protection circuit 200, the element is a capacitor CT. The inductor Lr and capacitor CT are coupled in parallel between the RF input pad RFin and theintermediate node 130. In some embodiments, the LC resonance circuit 270 includes a resistor and functions as an RLC resonance circuit. In some embodiments, any connections among the inductor LT, the capacitor CT, any resistor included in the LC resonance circuit 270, the RF input pad RFin and theintermediate node 130 are usable, provided that the LC resonance circuit 270 has a resonance frequency that matches the RF operating frequency of the LNA. - During normal operation of the LNA, RF input signals at the RF input pad RFin are isolated from the diode DT and diode DB (and also from the diodes' parasitic capacitance) by the LC resonance circuit 270 as described with respect to the
resonance circuit 170. When an ESD event occurs, the ESD current which has a much lower frequency than the RF operating frequency is transmitted through the inductor LT in the LC resonance circuit 270, to theintermediate node 130, and then either though the diode DT or the diode DB depending on the polarity of the ESD event. - In some embodiments, the inductor LT is the only inductor in the whole
ESD protection circuit 200. In some embodiments, the inductor LT is the only inductor in both a first ESD current path from the RF input pad RFin to theintermediate node 130 and then to the power supply voltage terminal VDD, and a second ESD current path from the RF input pad RFin to theintermediate node 130 and then to the ground voltage terminal VSS. By including a single inductor, which often occupies a die area comparable to hundreds of other semiconductor components, the manufacturing and area costs of theESD protection circuit 200 are reduced. -
FIGS. 3A-3G are schematic circuit diagrams of various ESD protection circuits in accordance with some embodiments. - An
ESD protection circuit 300A inFIG. 3A is similar to theESD protection circuit 200, except that the capacitor CT of theESD protection circuit 200 is replaced by anESD block 310 which is coupled in parallel with the inductor LT. As discussed with respect to thefirst ESD block 150 and thesecond ESD block 160, an ESD block, such as theESD block 310, has parasitic capacitance which, under certain circumstances, becomes significant at the RF operating frequency of the LNA. By tuning the inductor LT based on the parasitic capacitance of theESD block 310, a resonance frequency that matches the RF operating frequency of the LNA is achieved. As a result, the parasitic capacitance of theESD block 310 is used, in combination with the inductor LT, to isolate parasitic capacitance of the diode DT and diode DB from RF input signals during normal operation of the LNA. During an ESD event, theESD block 310 performs the ESD protection function and conducts, in addition to the inductor LT, the ESD current toward the diode DT and/or the diode DB. Thus, multiple ESD current paths are provided which improves the ESD performance. -
ESD protection circuits 300B, 300C, 300D inFIGS. 3B , 3C, 3D realize the ESD block 310 of theESD protection circuit 300A by at least one diode. Specifically, theESD protection circuit 300B inFIG. 3B realizes the ESD block 310 of theESD protection circuit 300A by a pair of diode D1 and diode D2 both of which are coupled in parallel with the inductor LT. The diode D1 has an anode coupled to theintermediate node 130 and a cathode coupled to the RF input pad RFin. The diode D2 has an anode coupled to the RF input pad RFin and a cathode coupled to theintermediate node 130. By tuning the inductor LT based on the parasitic capacitance of both the diode D1 and diode D2, a resonance frequency that matches the RF operating frequency of the LNA is achieved. As a result, the parasitic capacitance of the diode D1 and diode D2 is used, in combination with the inductor LT, to isolate parasitic capacitance of the diode DT and diode DB from RF input signals during normal operation of the LNA. During a positive ESD event, the diode D2 conducts, in addition to the inductor LT, the ESD current toward the diode DT and then to the power supply voltage terminal VDD. During a negative ESD event, the diode D1 conducts, in addition to the inductor LT, the ESD current toward the diode DB and then to the ground voltage terminal VSS. Thus, multiple ESD current paths are provided which improves the ESD performance. - The ESD protection circuit 300C in
FIG. 3C realizes the ESD block 310 of theESD protection circuit 300A by one diode D2 coupled in parallel with the inductor Lr. By tuning the inductor LT based on the parasitic capacitance of the diode D2, a resonance frequency that matches the RF operating frequency of the LNA is achieved. As a result, the parasitic capacitance of the diode D2 is used, in combination with the inductor LT, to isolate parasitic capacitance of the diode DT and diode DB from RF input signals during normal operation of the LNA. During a positive ESD event, the diode D2 conducts, in addition to the inductor LT, the ESD current toward the diode DT and then to the power supply voltage terminal VDD. During a negative ESD event, the ESD current is conducted by the inductor LT toward the diode DB and then to the ground voltage terminal VSS. Thus, multiple ESD current paths are provided which improves the ESD performance. - The ESD protection circuit 300D in
FIG. 3D realizes the ESD block 310 of theESD protection circuit 300A by one diode D1 coupled in parallel with the inductor LT. By tuning the inductor LT based on the parasitic capacitance of the diode D1, a resonance frequency that matches the RF operating frequency of the LNA is achieved. As a result, the parasitic capacitance of the diode D1 is used, in combination with the inductor LT, to isolate parasitic capacitance of the diode DT and diode DB from RF input signals during normal operation of the LNA. During a positive ESD event, the ESD current is conducted by the inductor LT toward the diode DT and then to the power supply voltage terminal VDD. During a negative ESD event, the ESD current is conducted by the diode D1, in addition to the inductor LT, toward the diode DB and then to the ground voltage terminal VSS. Thus, multiple ESD current paths are provided which improves the ESD performance. - An
ESD protection circuit 300E inFIG. 3E realizes the ESD block 310 of theESD protection circuit 300A by anNMOS transistor 320. TheNMOS transistor 320 has a source and a gate commonly coupled to theintermediate node 130, and a drain coupled to the RF input pad RFin. TheNMOS transistor 320 is configured and operates similarly to the gate-grounded NMOS transistor MN described with respect toFIG. 2 . Specifically, theNMOS transistor 320 is normally closed, and becomes conductive during an ESD event. By tuning the inductor LT based on the parasitic capacitance of theNMOS transistor 320, a resonance frequency that matches the RF operating frequency of the LNA is achieved. As a result, the parasitic capacitance of theNMOS transistor 320 is used, in combination with the inductor LT, to isolate parasitic capacitance of the diode DT and diode DB from RF input signals during normal operation of the LNA. During an ESD event, theNMOS transistor 320 becomes conductive and conducts, in addition to the inductor LT, the ESD current toward the diode DB and/or diode DT. Thus, multiple ESD current paths are provided which improves the ESD performance. - An
ESD protection circuit 300F inFIG. 3F realizes the ESD block 310 of theESD protection circuit 300A by a silicon-controlled rectifier (SCR) 330. TheSCR 330 has an anode A coupled to theintermediate node 130, and a cathode C coupled to the RF input pad RFin. A control gate G of theSCR 330 is floating. TheSCR 330 operates similarly to the gate-grounded NMOS transistor MN described with respect toFIG. 2 . Specifically, theSCR 330 is normally closed, and snapbacks to become conductive during an ESD event. By tuning the inductor LT based on the parasitic capacitance of theSCR 330, a resonance frequency that matches the RF operating frequency of the LNA is achieved. As a result, the parasitic capacitance of theSCR 330 is used, in combination with the inductor LT, to isolate parasitic capacitance of the diode DT and diode DB from RF input signals during normal operation of the LNA. During an ESD event, theSCR 330 becomes conductive and conducts, in addition to the inductor LT, the ESD current toward the diode DB and/or diode DT. Thus, multiple ESD current paths are provided which improves the ESD performance. - An
ESD protection circuit 300G inFIG. 3G is similar to theESD protection circuit 300A, except that a resistor R is coupled in parallel to theESD block 310 and the inductor LT. Specifically, the resistor R has a first end coupled to the RF input pad RFin and a second, opposite end coupled to theintermediate node 130. In some embodiments, a resistance value of the resistor R is in a range from a few ohms to a few megaohms. By tuning the inductor LT and/or the resistance value of the resistor R based on the parasitic capacitance of theESD block 310, a resonance frequency that matches the RF operating frequency of the LNA is achieved. The presence of the resistor R permits easy tuning of the resonance frequency of the LC resonance circuit 270. TheESD protection circuit 300G operates similarly to theESD protection circuit 300A, except that during an ESD event, the ESD current is conducted by not only the inductor LT but also the resistor R. Thus, multiple ESD current paths are provided which improves the ESD performance. -
FIG. 4 is a flow chart of anESD protection method 400 in accordance with some embodiments. Atstep 405, upon occurrence of a first ESD pulse (e.g., 191) of a positive polarity at an RF input pad RFin of the RF semiconductor device, the first ESD pulse is transmitted along a first ESD current path from the RF input pad RFin, through a resonance circuit (e.g., 270), to anintermediate node 130, then through a first diode (e.g., diode DT) to a power supply voltage terminal VDD of the RF semiconductor device. - At
step 410, upon occurrence of a second ESD pulse (e.g., 192) of a negative polarity at the RF input pad RFin, the second ESD pulse is transmitted along a second ESD current path from the RF input pad RFin, through the resonance circuit 270, to theintermediate node 130, then through a second diode (e.g., diode DB) to a ground voltage terminal VSS of the RF semiconductor device. Thus, the resonance circuit 270 is common to both the first and second ESD current paths. - At
step 415, upon application of an RF input signal, which has an RF operating frequency matching a resonance frequency of the resonance circuit 270, to the RF input pad RFin, the resonance circuit 270 exhibits very large impedance to the RF input signal and shields the RF input signal and the RF input pad from parasitic capacitances of the first and second diodes. By using a common resonance circuit for isolating both first and second diodes from RF input signals, manufacture and area costs are reduced. - The above method embodiment shows exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure.
- According to some embodiments, an electrostatic discharge (ESD) protection circuit for a radio frequency (RF) semiconductor device comprises a first power supply voltage terminal configured to receive a first power supply voltage, and a second power supply voltage terminal configured to receive a second power supply voltage. A power clamp is coupled between the first and second power supply voltage terminals. An RF input pad is configured to receive an RF input signal having an RF operating frequency for the RF semiconductor device. A first ESD block is coupled between an intermediate node and the first power supply voltage terminal, to direct an ESD pulse of a first polarity toward the first power supply voltage terminal. A second ESD block is coupled between the intermediate node and the second power supply voltage terminal, to direct an ESD pulse of a second, opposite polarity toward the second power supply voltage terminal. A resonance circuit is coupled between the RF input pad and the intermediate node. The resonance circuit is configured to present a greater impedance to the RF input signal having the RF operating frequency than to the ESD pulses.
- According to some embodiments, a radio frequency (RF) semiconductor device comprises: a power supply voltage terminal, a ground voltage terminal and an intermediate node. An internal RF circuit to be protected from ESD pulses is coupled to the power supply voltage terminal and ground voltage terminal. A power clamp is coupled between the power supply voltage terminal and the ground voltage terminal. An RF input pad is coupled to the internal RF circuit and configured to receive an RF input signal having an RF operating frequency for the internal RF circuit. A first diode has an anode coupled to the intermediate node and a cathode coupled to the power supply voltage terminal. A second diode has a cathode coupled to the intermediate node and an anode coupled to the ground voltage terminal. An LC resonance circuit is coupled between the RF input pad and the intermediate node. The LC resonance circuit includes an inductor which is the only inductor in an ESD current path from the RF input pad to the intermediate node and then to the power supply voltage terminal and the ground voltage terminal.
- According to some embodiments, in a method of protecting a radio frequency (RF) semiconductor device from ESD events, upon occurrence of a first ESD pulse of a positive polarity at an RF input pad of the RF semiconductor device, the first ESD pulse is transmitted from the RF input pad, through an LC resonance circuit, to an intermediate node, through a first diode to a power supply voltage terminal of the RF semiconductor device. Upon occurrence of a second ESD pulse of a negative polarity at the RF input pad, the second ESD pulse is transmitted from the RF input pad, through the LC resonance circuit, to the intermediate node, through to a second diode to a ground voltage terminal of the RF semiconductor device.
- It will be readily seen by one of ordinary skill in the art that one or more of the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/332,095 US8792218B2 (en) | 2011-12-20 | 2011-12-20 | Electrostatic discharge protection circuit and method for radio frequency semiconductor device |
US14/315,424 US9917079B2 (en) | 2011-12-20 | 2014-06-26 | Electrostatic discharge protection circuit and method for radio frequency circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/332,095 US8792218B2 (en) | 2011-12-20 | 2011-12-20 | Electrostatic discharge protection circuit and method for radio frequency semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/315,424 Continuation-In-Part US9917079B2 (en) | 2011-12-20 | 2014-06-26 | Electrostatic discharge protection circuit and method for radio frequency circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20130155556A1 true US20130155556A1 (en) | 2013-06-20 |
US8792218B2 US8792218B2 (en) | 2014-07-29 |
Family
ID=48609897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/332,095 Active 2032-07-09 US8792218B2 (en) | 2011-12-20 | 2011-12-20 | Electrostatic discharge protection circuit and method for radio frequency semiconductor device |
Country Status (1)
Country | Link |
---|---|
US (1) | US8792218B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140321008A1 (en) * | 2013-04-26 | 2014-10-30 | Ferfics Limited | An rf switch with inter-domain esd protection |
US9665113B2 (en) | 2014-05-21 | 2017-05-30 | Analog Devices, Inc. | High-speed multiphase precision clamping circuit |
TWI595628B (en) * | 2016-10-19 | 2017-08-11 | 國立臺灣師範大學 | Esd protection circuit and integrated circuit |
US11411396B2 (en) * | 2018-09-25 | 2022-08-09 | Huawei Technologies Co., Ltd. | ESD protection circuit |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9887188B2 (en) | 2015-01-20 | 2018-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electro-static discharge structure, circuit including the same and method of using the same |
US9602071B2 (en) * | 2015-04-16 | 2017-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Filter with electrostatic discharge protection |
US9685604B2 (en) | 2015-08-31 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Magnetoresistive random access memory cell and fabricating the same |
US9666661B2 (en) | 2015-09-08 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Coplanar metal-insulator-metal capacitive structure |
US9882553B2 (en) | 2015-12-18 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and circuit protecting method |
US9608616B1 (en) | 2016-05-27 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power clamp circuits and methods |
US10290714B2 (en) | 2016-05-31 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Transistor structure with field plate for reducing area thereof |
US10109621B2 (en) | 2016-08-08 | 2018-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-capacitance electrostatic damage protection device and method of designing and making same |
US10325906B2 (en) | 2016-09-23 | 2019-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | ESD testing structure, method of using same and method of forming same |
US10777546B2 (en) | 2016-11-30 | 2020-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planar and non-planar FET-based electrostatic discharge protection devices |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6885534B2 (en) * | 2002-10-21 | 2005-04-26 | Silicon Integrated Systems Corporation | Electrostatic discharge protection device for giga-hertz radio frequency integrated circuits with varactor-LC tanks |
US6894567B2 (en) * | 2001-12-04 | 2005-05-17 | Koninklijke Philips Electronics N.V. | ESD protection circuit for use in RF CMOS IC design |
US7224949B2 (en) * | 2002-03-28 | 2007-05-29 | Advanced Micro Devices, Inc. | ESD protection circuit for radio frequency input/output terminals in an integrated circuit |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7023677B2 (en) | 2004-02-25 | 2006-04-04 | United Microelectronics Corp. | ESD protection designs with parallel LC tank for Giga-Hertz RF integrated circuits |
-
2011
- 2011-12-20 US US13/332,095 patent/US8792218B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6894567B2 (en) * | 2001-12-04 | 2005-05-17 | Koninklijke Philips Electronics N.V. | ESD protection circuit for use in RF CMOS IC design |
US7224949B2 (en) * | 2002-03-28 | 2007-05-29 | Advanced Micro Devices, Inc. | ESD protection circuit for radio frequency input/output terminals in an integrated circuit |
US6885534B2 (en) * | 2002-10-21 | 2005-04-26 | Silicon Integrated Systems Corporation | Electrostatic discharge protection device for giga-hertz radio frequency integrated circuits with varactor-LC tanks |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140321008A1 (en) * | 2013-04-26 | 2014-10-30 | Ferfics Limited | An rf switch with inter-domain esd protection |
US9520251B2 (en) * | 2013-04-26 | 2016-12-13 | Ferfics Limited | RF switch with inter-domain ESD protection |
US9665113B2 (en) | 2014-05-21 | 2017-05-30 | Analog Devices, Inc. | High-speed multiphase precision clamping circuit |
TWI595628B (en) * | 2016-10-19 | 2017-08-11 | 國立臺灣師範大學 | Esd protection circuit and integrated circuit |
US11411396B2 (en) * | 2018-09-25 | 2022-08-09 | Huawei Technologies Co., Ltd. | ESD protection circuit |
US20230006440A1 (en) * | 2018-09-25 | 2023-01-05 | Huawei Technologies Co., Ltd. | Esd protection circuit |
US11791627B2 (en) * | 2018-09-25 | 2023-10-17 | Huawei Technologies Co., Ltd. | ESD protection circuit |
Also Published As
Publication number | Publication date |
---|---|
US8792218B2 (en) | 2014-07-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8792218B2 (en) | Electrostatic discharge protection circuit and method for radio frequency semiconductor device | |
US9917079B2 (en) | Electrostatic discharge protection circuit and method for radio frequency circuit | |
US8564065B2 (en) | Circuit architecture for metal oxide semiconductor (MOS) output driver electrical overstress self-protection | |
KR101422974B1 (en) | HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs | |
TWI326157B (en) | ||
US7518841B2 (en) | Electrostatic discharge protection for power amplifier in radio frequency integrated circuit | |
US20090195946A1 (en) | Electrostatic Discharge Protection Using an Intrinsic Inductive Shunt | |
US7974053B2 (en) | ESD protection circuit for differential I/O pair | |
US10587114B2 (en) | Bi-directional electrostatic discharge protection device for radio frequency circuits | |
US8208233B2 (en) | ESD protection circuit and method thereof | |
US20200321923A1 (en) | Concurrent electrostatic discharge and surge protection clamps in power amplifiers | |
US20190287960A1 (en) | Semiconductor ESD Protection Device and Method | |
EP2329526B1 (en) | Esd protection | |
US8493705B2 (en) | Electrostatic discharge circuit for radio frequency transmitters | |
US20170229446A1 (en) | Protection element, protection circuit, and semiconductor integrated circuit | |
EP3447800B1 (en) | Mos field effect transistor-based filter circuit and chip | |
CN112542453A (en) | Radio frequency chip and ESD protection circuit design method thereof | |
US9548609B2 (en) | Driver circuit and impedance adjustment circuit | |
US10833064B2 (en) | ESD protection circuit and integrated circuit for broadband circuit | |
Muthukrishnan et al. | A novel on-chip protection circuit for RFICs implemented in D-mode pHEMT technology | |
US20230361110A1 (en) | Electrostatic Discharge Protection For Wireless Device | |
US9099862B1 (en) | Self ESD protected device and method thereof | |
CN109216341B (en) | Electrostatic discharge protection circuit | |
US20230154919A1 (en) | Protection of a domain of an integrated circuit against overvoltages | |
US11901353B2 (en) | Integrated circuits including coil circuit and SCR |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TSAI, MING HSIEN;REEL/FRAME:027421/0803 Effective date: 20111219 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |