CN112542453A - Radio frequency chip and ESD protection circuit design method thereof - Google Patents

Radio frequency chip and ESD protection circuit design method thereof Download PDF

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Publication number
CN112542453A
CN112542453A CN202011457463.2A CN202011457463A CN112542453A CN 112542453 A CN112542453 A CN 112542453A CN 202011457463 A CN202011457463 A CN 202011457463A CN 112542453 A CN112542453 A CN 112542453A
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radio frequency
esd protection
port
chip
module
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Chinese (zh)
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赵奂
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Kangxi Communication Technology Shanghai Co ltd
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Kangxi Communication Technology Shanghai Co ltd
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Priority to CN202011457463.2A priority Critical patent/CN112542453A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields

Abstract

The application discloses radio frequency chip and ESD protection circuit design method thereof, the radio frequency chip includes: a radio frequency module; a charge bleed terminal electrically coupled to the radio frequency module; the radio frequency port is electrically coupled to the radio frequency module, and a DC blocking capacitor is connected in series in an electric signal transmission path between the radio frequency port and the charge discharging end; and the ESD protection module is connected with the blocking capacitor in parallel, and when the ESD protection module is conducted, a charge discharging passage is formed between the radio frequency port and the charge discharging end. The radio frequency chip has an ESD protection effect on the radio frequency port.

Description

Radio frequency chip and ESD protection circuit design method thereof
Technical Field
The application relates to the technical field of radio frequency chips, in particular to a radio frequency chip and an ESD protection circuit design method thereof.
Background
Electrostatic discharge (ESD) has been a critical design issue for integrated circuits. ESD has become a major threat to product reliability because it exists in all IC manufacturing processes from mainstream silicon-based complementary metal oxide semiconductors to compound semiconductor processes. Traditional analog circuit and digital circuit, peripheral ESD protection circuit is not obvious with the interact between the protected core circuit, when the static high voltage and the heavy current entering chip of port are inside, ESD protection circuit work, discharge the heavy current at low-impedance discharge channel, simultaneously clamp discharge voltage at the safety level, the core circuit of avoiding the chip suffers from thermal breakdown and electrical failure, under normal operating condition, ESD protection circuit's existence can be ignored to the influence of core circuit normal work.
However, as Integrated Circuit (IC) processes enter deep sub-micron levels and Radio-Frequency (RF) IC operating frequencies move toward the multi-gigahertz band, the design of on-chip ESD protection becomes increasingly challenging for RF IC design. Since the performance index of the rf integrated circuit is easily affected by external parasitic parameters, and the influence of the parasitic capacitance effect of the ESD protection circuit on the protected rf core circuit is unavoidable, adding the ESD protection circuit between the rf core circuit and the port may impose more strict requirements and challenges on the ESD protection circuit and the design of the rf core circuit. On one hand, the influence of the ESD protection circuit on the radio frequency core circuit to be protected is avoided, so that the working conditions of the radio frequency core circuit, such as normal amplification or receiving of radio frequency power, cannot be influenced by the existence of the ESD protection circuit, and the original radio frequency impedance matching condition of the radio frequency core circuit cannot be influenced; on the other hand, false triggering due to the influence of the core circuit is avoided. High-frequency signals inside the radio frequency chip change, and small signal noise caused by the change often causes large voltage fluctuation on a port, so that the ESD protection circuit is triggered by mistake, and the ESD protection circuit fails.
How to reduce the design difficulty of the port ESD protection circuit in the rf chip without affecting the normal operation of the rf chip is a problem to be solved.
Disclosure of Invention
In view of this, the present application provides a radio frequency chip and a method for designing an ESD protection circuit thereof, so as to solve the problem of high design difficulty of the existing ESD protection circuit.
The application provides a radio frequency chip, includes: a radio frequency module; a charge bleed terminal electrically coupled to the radio frequency module; the radio frequency port is electrically coupled to the radio frequency module, and a DC blocking capacitor is connected in series in an electric signal transmission path between the radio frequency port and the charge discharging end; and the ESD protection module is connected with the blocking capacitor in parallel, and when the ESD protection module is conducted, a charge discharging passage is formed between the radio frequency port and the charge discharging end.
Optionally, a parallel capacitance value of the turn-off capacitor of the ESD protection module and the blocking capacitor meets a requirement of the radio frequency chip for normal operation.
Optionally, a sum of a turn-off capacitance value of the ESD protection module and a capacitance value of the blocking capacitor forms a value condition of a required capacitor device within a working frequency band of the radio frequency chip.
Optionally, the capacitor device includes: at least one of a matching capacitance required by the radio frequency chip port, a capacitance required by the series resonant network, and a capacitance required by the parallel resonant network.
Optionally, the ESD protection module can bear a voltage swing required by a working condition of the radio frequency chip when a large signal works.
Optionally, the dc blocking capacitor on the shortest electrical signal transmission path between the radio frequency port and the charge discharging end is connected in parallel with the ESD protection module.
Optionally, the charge draining end includes: at least one of a power ground, a signal ground, an ESD protection circuit, and a potential reference point.
Optionally, the ESD protection module includes a plurality of ESD protection units connected in parallel.
Optionally, the ESD protection units connected in parallel have different turn-on thresholds respectively.
The application also provides a design method of the ESD protection circuit of the radio frequency chip, which comprises the following steps: providing a main circuit of a radio frequency chip, wherein the main circuit comprises a radio frequency module and a radio frequency port coupled to the radio frequency module; determining a radio frequency port needing ESD protection, wherein a blocking capacitor is connected in series in an electric signal transmission path between the radio frequency port and a charge discharging end; and adding an ESD protection module in the main circuit, wherein the ESD protection module is connected with the DC blocking capacitor in parallel, so that a charge discharge path is formed between the port and the charge discharge end when the ESD protection module is conducted.
Optionally, the ESD protection module is connected in parallel with a dc blocking capacitor on the shortest electrical signal transmission path between the radio frequency port and the charge discharging terminal.
Optionally, a sum of a turn-off capacitance value of the ESD protection module and a capacitance value of the blocking capacitor forms a value condition of a required capacitance device within a working frequency band of the radio frequency chip, where the capacitance device includes: at least one of a matching capacitor required by a radio frequency chip port, a capacitor required by a series resonant network and a capacitor required by a parallel resonant network; the ESD protection module can bear the voltage swing amplitude required by the working condition of the radio frequency chip when a large signal works.
Optionally, the charge draining end includes: at least one of a power ground, a signal ground, an ESD protection circuit, and a potential reference point.
According to the radio frequency chip, the blocking capacitor on the path between the radio frequency port and the charge discharging end is connected with the ESD protection module in parallel, when the ESD voltage of the radio frequency port exceeds the threshold value, the ESD protection module is conducted to discharge the charges, and the ESD protection effect is achieved. The ESD protection module does not change the topological structure of the circuit and the working condition of the circuit, has little influence on the radio frequency module, does not influence the performance of the radio frequency chip, and has low design difficulty.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1a is a schematic circuit diagram of a radio frequency chip according to an embodiment of the present application;
fig. 1b is an equivalent schematic diagram of an ESD protection module in a circuit structure of a radio frequency chip according to an embodiment of the present application in an off state;
fig. 2a is a schematic circuit structure diagram of an ESD protection module of an rf chip according to an embodiment of the present application;
fig. 2b is a schematic circuit structure diagram of an ESD protection module of an rf chip according to an embodiment of the present application;
fig. 2c is a schematic circuit structure diagram of an ESD protection module of an rf chip according to an embodiment of the present application;
fig. 3 is a schematic circuit diagram of a radio frequency chip according to an embodiment of the present application;
fig. 4 is a schematic circuit diagram of an rf chip according to an embodiment of the present application;
fig. 5 is a schematic circuit diagram of an rf chip according to an embodiment of the present application;
fig. 6 is a schematic flowchart of a method for designing an ESD protection circuit of an rf chip according to an embodiment of the present application.
Detailed Description
As described in the background art, the design difficulty of the ESD protection circuit is large due to the complex interaction relationship between the rf circuit and the ESD protection circuit.
The technical solution in the embodiments of the present application is described clearly and completely below with reference to the accompanying drawings. It is to be understood that the embodiments described are only some of the embodiments of the present application and not all of them. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Fig. 1a is a schematic circuit diagram of a radio frequency chip according to an embodiment of the invention.
In this embodiment, the rf chip includes: a radio frequency module 110, a radio frequency port PAD1, the radio frequency port PAD1 coupled to the radio frequency module 110.
The rf module 110 is a core function module of the rf chip, and may include a power amplifier circuit, a radio frequency low noise amplifier circuit, a radio frequency switch circuit, and the like.
The radio frequency port PAD1 is used as an input or output port of a radio frequency signal and is used for being directly connected with an external circuit. In this embodiment, the rf port PAD1 is coupled to the antenna E1. In other embodiments, the rf port PAD1 may also be connected to an external signal processing circuit.
Peripheral circuits such as a filter circuit, a dc blocking circuit, etc. may be disposed between the rf port PAD1 and the rf module 110 as required.
The rf chip further includes a charge bleed terminal capable of bleeding current, and may generally include: power ground, signal ground, potential reference points, and the like. In the embodiments of the present invention, the signal ground GND is taken as an example of the charge draining terminal. Usually, a plurality of signal grounds are disposed in the rf chip to realize multi-point grounding, so that an electrical signal transmission path can be easily found between the rf port and the charge draining port. However, due to the wide use of the capacitor in the rf circuit, a dc blocking capacitor often exists on an electrical signal transmission path between the rf port and the charge discharging port, so that a dc signal cannot pass through the dc blocking capacitor, and thus the ESD discharging path is blocked. When the ESD high voltage occurs at the rf port, the charge cannot be discharged in time, and the rf module 110 is damaged.
In this embodiment, a series resonant circuit is disposed between the rf port PAD1 and the ground GND to function as a notch filter, and includes an inductor L1 and a capacitor C1 connected in series. Due to the existence of the capacitor C1, the electrical signal transmission path between the rf port PAD1 and the ground GND cannot be discharged with charges, and an ESD problem is easily caused.
In this embodiment, to solve this problem, the rf chip further includes an ESD protection module 120, where the ESD protection module has a turn-on threshold, and the turn-on threshold may be a positive voltage value or a negative voltage value. The ESD protection module is connected in parallel with the capacitor C1, and when the ESD voltage generated at the end of the rf port PAD1 reaches the conduction threshold of the ESD protection module 120, the ESD protection module 120 is turned on, and a charge discharging path is formed between the rf port PAD1 and the ground GND, so as to achieve the ESD protection effect. When the ESD voltage does not exist at the rf port PAD1, or the ESD voltage does not reach the turn-on threshold, the ESD protection module 120 is in an off state, which is equivalent to an off-capacitor Coff (see fig. 1 b). In this embodiment, the off capacitor Coff is connected in parallel with the capacitor C1, and the parallel capacitance value is equal to the design value C0 when the rf chip operates normally, i.e., C1+ Coff — C0. Originally, the capacitance of the radio frequency circuit is designed to be C0, C0 is realized by connecting C1 and Coff in parallel, and C0 and L1 form a series resonance condition of a required frequency.
In this embodiment, when the ESD protection module 120 needs to trigger ESD protection, a charge discharging path between the rf port PAD1 and the ground GND is turned on; when the rf chip circuit normally works, the ESD protection module 120 provides a turn-off capacitor Coff, which is connected in parallel with the original capacitor C1 of the rf chip circuit, so that the topology structure of the circuit is not changed, and the original working conditions of the rf chip circuit can be maintained by reasonably setting the sizes of C1 and Coff.
The ESD protection module 120 may adopt a commonly used ESD protection circuit structure.
Referring to fig. 2a, which is a circuit structure diagram of an ESD protection module 120 according to an embodiment of the present invention, the ESD protection module 120 includes a ggNMOS structure as an example. In this embodiment, the ESD protection module 120 includes: and the drain electrode of the NMOS tube M1 is connected to the A end of the capacitor C1, the source electrode of the NMOS tube is connected to the B end of the capacitor C1, and the grid electrode and the source electrode are connected through a resistor R, so that the M1 is ensured to be in an off state when the radio frequency port 110 does not reach an ESD triggering condition or the radio frequency circuit works normally.
Fig. 2b is a circuit diagram of an ESD protection module 120 according to another embodiment of the invention. In this embodiment, the ESD protection module 120 includes two series-connected diodes, which respectively include diodes D11-D1 m and diodes D21-D2 n, the two series-connected diodes are connected in opposite directions, and are connected to the a terminal and the B terminal of the capacitor C1, respectively. The increased number of diodes connected in series can improve the voltage swing capability of the ESD protection module 120, thereby improving the rf power to be borne, and avoiding the voltage swing of the output signal generated by the rf module 110 from being triggered by mistake, but at the same time, the impedance is increased, and the charge discharging capability is weakened.
Fig. 2c is a circuit diagram of an ESD protection module 120 according to another embodiment of the invention.
In this embodiment, the ESD protection module 120 includes a back-to-back diode (back-to-back diode) pair connected in parallel with the ends A, B of the capacitor C1. The back-to-back diode pair is formed by serially connecting diodes D1 and D2 back to back.
In other embodiments, the ESD protection module 120 may also include multiple sets of back-to-back diode pairs connected in series to improve the ability to withstand voltage swings.
The back-to-back diode pairs are used as internal circuits of the ESD protection module, ESD protection can be achieved with less diode quantity, and reduction of chip area is facilitated.
In other embodiments, a person skilled in the art may also adjust the specific circuit of the ESD protection module 120 as needed or adopt other circuit structures, which is not limited herein.
In the embodiment of the present invention, the ESD protection module 120 is connected in parallel with the capacitor C1, and the capacitance value of the capacitor C1 is usually large, so the ac complex impedance value is low, and the voltage swing at both ends is small in the normal operating state, so the requirement for the voltage swing of the ESD protection module 120 is low, the design difficulty of the ESD protection module 120 can be reduced, and more selection spaces are provided for the specific circuits and devices used.
In other embodiments, the ESD protection module may further include a plurality of ESD protection cells connected in parallel. Each ESD protection unit has the same conduction threshold, ESD charges are shunted and discharged through the plurality of ESD protection units, conduction impedance can be reduced, and charge discharge effect is improved.
In other embodiments, the ESD protection units in the ESD protection module may further have different turn-on thresholds respectively. When the ESD voltage of the rf port PAD1 reaches different turn-on thresholds, the corresponding ESD protection unit is turned on, and the higher the ESD voltage is, the more ESD units are turned on, the smaller the turn-on impedance is, and the higher the charge discharging efficiency is. Certainly, when the ESD voltage takes two different positive and negative signs, the ESD protection units with different positive and negative conduction voltages can be designed according to the requirement, so that the positive and negative ESD conduction thresholds are different.
Fig. 3 is a schematic circuit diagram of a radio frequency chip according to another embodiment of the invention.
In this embodiment, an LC circuit is coupled between the rf port PAD1 of the rf chip and the rf module 110, and includes a capacitor C2 and an inductor L2, one end of the capacitor C2 is connected to the rf port PAD1, the other end is connected to the rf module 110, one end of the capacitor L2 is grounded to GND, and the other end is connected to the coupling end of the capacitor C2 and the rf module 110. The charge leakage path of the electrical signal transmission path between the radio frequency port PAD1 and the ground terminal GND is blocked by the capacitor C2.
The ESD protection module 320 is connected in parallel to the capacitor C2, and when the electrostatic voltage at the rf port PAD1 is large, so that the voltage across the capacitor C2 exceeds the conduction threshold of the ESD protection module 320, the ESD protection module 320 is turned on to turn on the charge discharging path between the rf port PAD1 and GND, and the ESD charge on the PAD1 is discharged to the ground GND through the ESD protection module 320 and the inductor L2.
In fig. 3, the connection between the inductor L2 and the capacitor C2 is only an example, and in other embodiments, other circuit elements may be connected to the paths of C2 and L2.
Fig. 4 is a schematic circuit diagram of a radio frequency chip according to another embodiment of the invention.
In this embodiment, the rf port PAD1 of the rf chip and the rf module 110 are directly connected in series with a capacitor C3, and no other branch is directly connected to ground GND.
Also in this embodiment, there is a port PAD2, the port PAD2 is typically a power port for applying a power signal, such as the operating voltage VDD. The ESD protection circuit 410 is designed at the port PAD 2. Due to the port parameters at the port PAD2, which has less impact on the circuit performance of the rf module 110, the ESD protection circuit 410, which is grounded, can be designed generally directly at the port PAD 2. Since the ESD protection circuit 410 is conductive to the ground GND in the on state to form a charge discharging path, the ESD protection circuit 410 may be used as a charge discharging terminal. The charge leakage path between the rf port PAD1 and the ESD protection circuit 410 is blocked by a capacitor C3.
The ESD protection module 420 for ESD protection of the rf port PAD1 is connected in parallel with the capacitor C3. When the ESD voltage at the rf port PAD1 is so large that the voltage across the capacitor C3 exceeds the turn-on threshold of the ESD protection module 420, the ESD protection module 420 turns on to form a charge discharging path between the rf port PAD1 and the ESD protection circuit 410, so that the electrostatic charge at the rf port PAD1 is discharged to the ground GND through the ESD protection circuit 410 and the ESD protection circuit 420.
Fig. 5 is a schematic circuit diagram of a radio frequency chip according to an embodiment of the invention.
In this embodiment, a T-shaped network structure formed by capacitors C51, C52 to C53 is connected between the rf port PAD1 and the rf module 110, one end of the capacitor C51 is connected to the rf port PAD1, the other end of the capacitor C51 is connected to the capacitor C52, the other end of the capacitor C52 is connected to the rf module 110, one end of the capacitor C53 is grounded, and the other end of the capacitor C53 is connected to the connection end of C51 and C52.
The inductor L5 has one end connected to ground and the other end connected to the connection path between the capacitor C52 and the rf module 110.
Two signal transmission path paths are arranged between the radio frequency port PAD1 and the ground, namely a first signal path where the radio frequency port PAD1, the capacitor C51 and the capacitor C53 are located, and a second signal path where the radio frequency port PAD1, the capacitor C51 and the capacitor C52 are located.
In this embodiment, the ESD protection module 521 is connected in parallel across the capacitor C51, and the ESD protection module 522 is connected in parallel across the capacitor C53. When the ESD voltage at the rf port PAD1 is large, so that the voltages at two ends of the capacitors C51 and C52 exceed the threshold voltage, the ESD protection module 521 and the ESD protection module 522 are turned on, and the rf port PAD1 forms a charge discharging path with the ground GND through the ESD protection module 521 and the ESD protection module 522, thereby implementing ESD protection. Under normal operating conditions, ESD protection module 521 provides off-capacitance Coff1, in parallel with capacitance C51; ESD protection module 522 provides off capacitance Coff2 in parallel with capacitance C53; the ESD protection module 521 and the ESD protection module 522 do not change the original circuit topology structure of the rf chip, and do not affect the performance and function of the rf module.
In other embodiments, the ESD protection modules may be respectively connected in parallel across the capacitor C51 and the capacitor C52 to form an ESD charge discharging path from the rf port PAD1 to the inductor L5.
Preferably, the ESD protection module is connected in parallel to two ends of the blocking capacitor on the shortest electrical signal transmission path to form the shortest charge discharging path, so as to improve the charge discharging efficiency during ESD protection.
The radio frequency chip in the embodiment of the invention reduces the influence of the addition of the ESD protection module on the topological structure and the working condition of the radio frequency circuit to the maximum extent, keeps all parameters at the radio frequency port PAD1 consistent with the original circuit design in the normal working state, and does not need to change the design of the core circuit of the radio frequency chip because of the addition of the ESD protection module, so that the design of the circuit of the radio frequency module and the ESD protection module is simpler. The sum of the turn-off capacitance value of the ESD protection module and the capacitance value of the blocking capacitor forms a value condition of a required capacitance device in a working frequency band of the radio frequency chip, and the capacitance device comprises: at least one of a matching capacitor required by a radio frequency chip port, a capacitor required by a series resonant network and a capacitor required by a parallel resonant network; the ESD protection module can bear the voltage swing amplitude required by the working condition of the radio frequency chip when a large signal works.
The embodiment of the invention also provides a design method of the ESD protection circuit of the radio frequency circuit.
Fig. 6 is a schematic flow chart illustrating a method for designing an ESD protection circuit according to an embodiment of the invention.
In this embodiment, the method for designing the ESD protection circuit of the rf chip includes the following steps:
step S101: a main circuit of a radio frequency chip is provided, which comprises a radio frequency module and a radio frequency port coupled to the radio frequency module.
The main circuit of the radio frequency chip is designed according to target parameters and functions of the radio frequency chip, and influences of an EDS protection circuit of a radio frequency port on a circuit topological structure and circuit working conditions are not required to be considered.
Step S102: and determining a radio frequency port needing ESD protection, wherein a blocking capacitor is connected in series in an electric signal transmission path between the radio frequency port and the charge discharging end.
Due to the existence of the blocking capacitor, a direct current discharge path cannot be directly formed between the radio frequency port and the charge discharge end, and when the ESD voltage generated by the radio frequency port exceeds a safety threshold, the charge discharge cannot be performed, which damages an internal circuit of the radio frequency module, so that an additional ESD protection design is required.
If no blocking capacitor exists in an electric signal transmission path between the radio frequency port and the charge discharging end, current can reach the charge discharging end through elements such as a resistor and/or an inductor and be led out, and an ESD protection design is not needed to be additionally carried out.
The charge bleed terminal includes: at least one of a power ground, a signal ground, an ESD protection circuit, and a potential reference point.
Step S103, adding an ESD protection module in the main circuit, wherein the ESD protection module is connected with the blocking capacitor in parallel, so that when the ESD protection module is conducted, a charge discharging path between the radio frequency port and the charge discharging end is conducted.
And connecting the ESD protection module with a blocking capacitor on the shortest electric signal transmission path between the radio frequency port and the charge discharging end in parallel to form a shortest charge discharging path and improve the ESD protection efficiency.
The parallel capacitance value of the parasitic capacitance and the blocking capacitance of the ESD protection module in the non-conducting state is equal to the design value required by the radio frequency chip when the radio frequency chip works normally, so that the influence on the normal working condition of the radio frequency chip is avoided, and the topological structure of the circuit cannot be changed. Specifically, the sum of the off capacitance value and the capacitance value of the blocking capacitor forms a value condition of a capacitance device required in a working frequency band of the radio frequency chip, and the capacitance device includes: at least one of a matching capacitor required by a radio frequency chip port, a capacitor required by a series resonant network and a capacitor required by a parallel resonant network; the ESD protection module can bear the voltage swing amplitude required by the working condition of the radio frequency chip when a large signal works.
According to the design method of the ESD protection circuit of the radio frequency chip, after the main circuit of the radio frequency chip is designed as required, the ESD protection module is added in the circuit as required, and the protection module is connected with the blocking capacitor in parallel, so that the topological structure of the circuit is not changed. Furthermore, the parallel value of the turn-off capacitance and the blocking capacitance of the ESD protection module in a non-conduction state is equal to a target design value on a circuit, the working parameters of the radio frequency chip are not changed, and the normal working performance and the function of the radio frequency module to be protected are not affected. In the main circuit design process of the radio frequency chip, the influence of the ESD protection module is not required to be considered, the ESD protection is realized, meanwhile, the circuit design difficulty is reduced, and the realization is easier.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.

Claims (14)

1. A radio frequency chip, comprising:
a radio frequency module;
a charge bleed terminal electrically coupled to the radio frequency module;
the radio frequency port is electrically coupled to the radio frequency module, and a DC blocking capacitor is connected in series in an electric signal transmission path between the radio frequency port and the charge discharging end;
and the ESD protection module is connected with the blocking capacitor in parallel, and when the ESD protection module is conducted, a charge discharging passage is formed between the radio frequency port and the charge discharging end.
2. The radio frequency chip according to claim 1, wherein a parallel capacitance value of the turn-off capacitor and the blocking capacitor of the ESD protection module satisfies a requirement of normal operation of the radio frequency chip.
3. The RF chip according to claim 2, wherein a sum of a turn-off capacitance value of the ESD protection module and a capacitance value of the blocking capacitor constitutes a value condition of a required capacitive device within an operating frequency band of the RF chip.
4. The radio frequency chip of claim 3, wherein the capacitance device comprises: at least one of a matching capacitance required by the radio frequency chip port, a capacitance required by the series resonant network, and a capacitance required by the parallel resonant network.
5. The RF chip of claim 1, wherein the ESD protection module is capable of withstanding a voltage swing required by an operating condition of the RF chip when operating with a large signal.
6. The RF chip according to claim 1, wherein a DC blocking capacitor on a shortest electrical signal transmission path between the RF port and the charge draining terminal is connected in parallel with the ESD protection module.
7. The RF chip of claim 1, wherein the RF port is an RF signal output port or an RF signal input port.
8. The RF chip of claim 1, wherein the charge bleed terminal comprises: at least one of a power ground, a signal ground, an ESD protection circuit, and a potential reference point.
9. The RF chip of claim 1, wherein the ESD protection module comprises a plurality of ESD protection units connected in parallel.
10. The RF chip of claim 9, wherein the ESD protection units connected in parallel have different turn-on thresholds respectively.
11. A method for designing an ESD protection circuit of a radio frequency chip is characterized by comprising the following steps:
providing a main circuit of a radio frequency chip, wherein the main circuit comprises a radio frequency module and a radio frequency port coupled to the radio frequency module;
determining a radio frequency port needing ESD protection, wherein a blocking capacitor is connected in series in an electric signal transmission path between the radio frequency port and a charge discharging end;
and adding an ESD protection module in the main circuit, wherein the ESD protection module is connected with the blocking capacitor in parallel, so that a charge discharge path is formed between the radio frequency port and the charge discharge end when the ESD protection module is conducted.
12. The method of claim 11, wherein the ESD protection module is connected in parallel with a dc blocking capacitor on a shortest electrical signal transmission path between the rf port and the charge draining port.
13. The ESD protection circuit design method of claim 11, wherein a sum of a turn-off capacitance value of the ESD protection module and a capacitance value of the dc blocking capacitor constitutes a value condition of a required capacitance device within an operating frequency band of a radio frequency chip, and the capacitance device comprises: at least one of a matching capacitor required by a radio frequency chip port, a capacitor required by a series resonant network and a capacitor required by a parallel resonant network; the ESD protection module can bear the voltage swing amplitude required by the working condition of the radio frequency chip when a large signal works.
14. The ESD protection circuit design method of claim 11, wherein the charge draining terminal comprises: at least one of a power ground, a signal ground, an ESD protection circuit, and a potential reference point.
CN202011457463.2A 2020-12-11 2020-12-11 Radio frequency chip and ESD protection circuit design method thereof Pending CN112542453A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113595542A (en) * 2021-09-30 2021-11-02 成都明夷电子科技有限公司 Single-pole double-throw radio frequency switch
CN117318633A (en) * 2023-11-28 2023-12-29 厦门科塔电子有限公司 Circuit structure of low noise amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113595542A (en) * 2021-09-30 2021-11-02 成都明夷电子科技有限公司 Single-pole double-throw radio frequency switch
CN117318633A (en) * 2023-11-28 2023-12-29 厦门科塔电子有限公司 Circuit structure of low noise amplifier

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