CN109216341B - Electrostatic discharge protection circuit - Google Patents

Electrostatic discharge protection circuit Download PDF

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CN109216341B
CN109216341B CN201710521236.3A CN201710521236A CN109216341B CN 109216341 B CN109216341 B CN 109216341B CN 201710521236 A CN201710521236 A CN 201710521236A CN 109216341 B CN109216341 B CN 109216341B
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bus
trigger
input
output interface
coupling unit
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CN109216341A (en
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黄亚平
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

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  • Semiconductor Integrated Circuits (AREA)
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Abstract

Disclosed herein is an electrostatic discharge protection circuit including: the ESD protection circuit comprises a trigger bus group, a detection bus, a power bus, a grounding bus, a plurality of input/output interfaces, an ESD detection and trigger unit, a controlled coupling unit group and a coupling unit of each input/output interface; the ESD detection and trigger unit judges whether an electrostatic event occurs or not by detecting signals on the detection bus, and if so, outputs a first control signal to the trigger bus group; the coupling unit is used for coupling the signals of the input/output interface to the detection bus; the controlled coupling unit group includes: the first controlled coupling unit and the second controlled coupling unit are arranged between the input/output interface and the power bus and the grounding bus, and the third controlled coupling unit is arranged between the power bus and the grounding bus; and the controlled coupling unit group is used for conducting each controlled coupling unit controlled by the trigger bus group under the control of the first control signal. The technical scheme can realize the electrostatic discharge protection of the high-frequency input/output interface.

Description

Electrostatic discharge protection circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an electrostatic discharge protection circuit.
Background
In recent years, with the reduction of the line width of a CMOS (Complementary Metal Oxide Semiconductor) process, the gate of a MOS device becomes thinner and the gate breakdown voltage becomes lower. In advanced semiconductor processes with line widths smaller than 100nm, ESD (Electro-Static Discharge) has become an important factor affecting the performance of analog and rf chips.
The existing ESD protection technologies such as gate-grounded NMOS (gate-grounded NMOS), SCR (Silicon Controlled Rectifier), etc. are not suitable for integrated circuits in advanced CMOS process due to the over-high Trigger voltage. The R-C Clamp ESD protection circuit can reduce ESD Trigger Voltage (Trigger Voltage) and Clamp Voltage (Clamp Voltage) on input/output pins (I/O pads), an RC frequency selection loop is formed through a resistor-capacitor network (RC network), ESD signals are judged and identified through input signal frequency and amplitude characteristics, and the Clamp Voltage on the input/output pins is controlled through diodes between the input/output pins and power and ground by combining a Clamp (Clamp) circuit between a power supply (VDD) and ground (VSS), and ESD protection is finally achieved. The diode size can be increased if further reduction of the clamping voltage is required. However, the parasitic capacitance effect caused by the large-sized diode limits the frequency of the signal on the input/output interface, so that the ESD design of the high-frequency signal I/O becomes very difficult.
Therefore, how to realize ESD protection of high frequency input/output interface under advanced semiconductor process (line width is less than 100nm) has become a problem to be solved.
Disclosure of Invention
The invention aims to provide an electrostatic discharge protection circuit which can realize electrostatic discharge protection of a high-frequency input/output interface.
An embodiment of the present invention provides an electrostatic discharge protection circuit, including: the ESD protection circuit comprises a trigger bus group, a detection bus, a power bus, a grounding bus, a plurality of input/output interfaces, an electrostatic discharge (ESD) detection and trigger unit, a controlled coupling unit group and a coupling unit of each input/output interface;
the ESD detection and trigger unit is connected with the detection bus, the grounding bus, the power supply bus and the trigger bus group, judges whether an electrostatic event occurs or not by detecting signals on the detection bus, and outputs a first control signal to the trigger bus group if the electrostatic event occurs;
the coupling unit of each input/output interface is used for coupling the signals of the input/output interface to the detection bus;
the controlled coupling unit group includes: the first controlled coupling unit is arranged between each input/output interface and the power bus, the second controlled coupling unit is arranged between each input/output interface and the ground bus, and the third controlled coupling unit is arranged between the power bus and the ground bus;
the trigger bus group is connected with a third controlled coupling unit in the controlled coupling unit group and is also connected with each first controlled coupling unit and/or each second controlled coupling unit;
and the controlled coupling unit group is used for conducting each controlled coupling unit controlled by the trigger bus group under the control of the first control signal.
Compared with the prior art, in the electrostatic discharge protection circuit provided by the embodiment of the invention, the ESD detection and trigger unit judges whether an electrostatic event occurs or not by detecting a signal coupled to the detection bus by the input/output interface, outputs a control signal to the trigger bus group when the electrostatic occurs, the trigger bus group is connected with the control end of the controlled coupling unit group, and conducts an electrostatic current leakage path between the input/output interface and the power bus and the ground bus and an electrostatic current leakage path between the power bus and the ground bus when the electrostatic occurs. The electrostatic protection circuit can realize electrostatic discharge protection of the high-frequency input/output interface.
Drawings
Fig. 1 is a schematic diagram of an esd protection circuit according to embodiment 1 of the present invention;
fig. 2(a) is a schematic diagram of an esd protection circuit (dual triggered bus) in embodiment 1 of the present invention;
fig. 2(b) is a schematic diagram of an esd protection circuit (one-shot bus) in embodiment 1 of the present invention;
fig. 3 is a schematic diagram of an esd protection circuit (dual trigger bus, three controlled coupling units) in example 1 of the present invention;
FIG. 4(a) is a schematic diagram of an electrostatic discharge path between two I/O interfaces in example 1 of the present invention (dual triggered bus, three controlled coupling units);
fig. 4(b) is a schematic diagram of an electrostatic discharge path two between two input/output interfaces in example 1 of the present invention (dual trigger bus, three controlled coupling units);
fig. 4(c) is a schematic diagram of an electrostatic discharge path between two input/output interfaces (dual trigger bus, three controlled coupling units) in example 1 of the present invention;
FIG. 5(a) is a schematic diagram of a PMOS internal discharge path in example 1 of the present invention;
FIG. 5(b) is a schematic diagram of an NMOS internal discharge path in example 1 of the present invention;
fig. 6 is a schematic diagram of an electrostatic discharge path between an input/output interface and a ground bus in example 2 of the present invention (dual trigger bus, three controlled coupling units);
fig. 7 is a schematic diagram of an esd protection circuit (dual triggered bus, two controlled coupling units) in example 3 of the present invention;
fig. 8 is a schematic diagram of an esd protection circuit (one-shot bus, two controlled coupling units) in example 4 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
Example 1
As shown in fig. 1, an embodiment of the present invention provides an esd protection circuit, including: the ESD protection circuit comprises a trigger bus group 10, a detection bus 11, a power supply bus 12, a ground bus 13, a plurality of input/output interfaces 50, an ESD detection and trigger unit 20, a controlled coupling unit group 30 and a coupling unit 40 of each input/output interface;
the ESD detection and trigger unit is connected with the detection bus, the grounding bus, the power supply bus and the trigger bus group, judges whether an electrostatic event occurs or not by detecting signals on the detection bus, and outputs a first control signal to the trigger bus group if the electrostatic event occurs;
the coupling unit of each input/output interface is used for coupling the signals of the input/output interface to the detection bus;
the controlled coupling unit group includes: a first controlled coupling unit 301 between each input/output interface and the power bus, a second controlled coupling unit 302 between each input/output interface and the ground bus, and a third controlled coupling unit 303 between the power bus and the ground bus;
the trigger bus group is connected with a third controlled coupling unit in the controlled coupling unit group and is also connected with each first controlled coupling unit and/or each second controlled coupling unit;
the controlled coupling unit group is used for conducting each controlled coupling unit controlled by the trigger bus group under the control of the first control signal;
in one embodiment, the ESD detection and trigger unit is further configured to output a second control signal to the trigger bus group when it is determined that no electrostatic event occurs;
the controlled coupling unit group is also used for making each controlled coupling unit controlled by the trigger bus group not be conducted under the control of the second control signal;
in one embodiment, the ESD detection and trigger unit is configured to determine whether an electrostatic event occurs by detecting a signal on the detection bus in the following manner:
when the signal voltage value on the detection bus is greater than or equal to a threshold value, determining that an electrostatic event occurs; when the signal voltage value on the detection bus is smaller than a threshold value, judging that no electrostatic event occurs; or
When the amplitude-frequency characteristics of the signals on the detection bus meet the characteristics of the electrostatic signals, judging that an electrostatic event occurs; and when the amplitude-frequency characteristic of the signal on the detection bus does not meet the characteristic of the electrostatic signal, judging that no electrostatic event occurs.
Wherein the threshold is greater than a supply voltage on the power bus when no static electricity is occurring.
Wherein the amplitude-frequency characteristics of the electrostatic signal comprise: the electrostatic signal is a pulse signal and the amplitude variation exceeds a variation range threshold;
in one embodiment, the coupling unit of the input/output interface comprises a first diode, the anode of the first diode is connected with the input/output interface, and the cathode of the first diode is connected with the detection bus;
in one embodiment, the set of trigger buses includes a first trigger bus and a second trigger bus;
the first controlled coupling unit includes: a P-type metal-oxide-semiconductor field effect transistor PMOS tube; the control end of the PMOS tube is connected with the first trigger bus, the first end and the second end of the PMOS tube are respectively connected with the input/output interface and the power bus, and the substrate end is connected with the power bus; the first end is a source electrode of the PMOS tube, and the second end is a drain electrode of the PMOS tube; or the first end is the drain electrode of the PMOS tube, and the second end is the source electrode of the PMOS tube;
the second controlled coupling unit includes: an N-type metal-oxide-semiconductor field effect transistor (MOSFET); the control end of the NMOS tube is connected with the second trigger bus, the first end and the second end of the NMOS tube are respectively connected with the input/output interface and the grounding bus, and the substrate end is connected with the grounding bus; the first end is a source electrode of the NMOS tube, and the second end is a drain electrode of the NMOS tube; or the first end is the drain electrode of the NMOS tube, and the second end is the source electrode of the NMOS tube;
the third controlled coupling unit includes: the control end of the NMOS tube is connected with the second trigger bus, the first end and the second end of the NMOS tube are respectively connected with the power bus and the grounding bus, and the substrate end is connected with the grounding bus; the first end is a source electrode of the NMOS tube, and the second end is a drain electrode of the NMOS tube; or the first end is the drain electrode of the NMOS tube, and the second end is the source electrode of the NMOS tube;
the ESD detection and trigger unit is used for outputting a first control signal to the trigger bus group by adopting the following mode: outputting a first low level signal to the first trigger bus and outputting a first high level signal to the second trigger bus;
the ESD detection and trigger unit is further configured to output a second control signal to the trigger bus group in the following manner: outputting a second high level signal to the first trigger bus, and outputting a second low level signal to the second trigger bus;
in one embodiment, the set of trigger buses includes a first trigger bus and a second trigger bus;
the first controlled coupling unit includes: a P-type metal-oxide-semiconductor field effect transistor PMOS tube; the control end of the PMOS tube is connected with the first trigger bus, the first end and the second end of the PMOS tube are respectively connected with the input/output interface and the power bus, and the substrate end is connected with the power bus; the first end is a source electrode of the PMOS tube, and the second end is a drain electrode of the PMOS tube; or the first end is the drain electrode of the PMOS tube, and the second end is the source electrode of the PMOS tube;
the second controlled coupling unit includes: a second diode; the anode of the second diode is connected with the grounding bus, and the cathode of the second diode is connected with the input/output interface;
the third controlled coupling unit includes: the control end of the NMOS tube is connected with the second trigger bus, the first end and the second end of the NMOS tube are respectively connected with the power bus and the grounding bus, and the substrate end is connected with the grounding bus; the first end is a source electrode of the NMOS tube, and the second end is a drain electrode of the NMOS tube; or the first end is the drain electrode of the NMOS tube, and the second end is the source electrode of the NMOS tube;
the ESD detection and trigger unit is used for outputting a first control signal to the trigger bus group by adopting the following mode: outputting a first low level signal to the first trigger bus and outputting a first high level signal to the second trigger bus;
the ESD detection and trigger unit is further configured to output a second control signal to the trigger bus group in the following manner: outputting a second high level signal to the first trigger bus, and outputting a second low level signal to the second trigger bus;
in one embodiment, the set of trigger buses includes a third trigger bus;
the first controlled coupling unit comprises a third diode, the anode of the third diode is connected with the input/output interface, and the cathode of the third diode is connected with the power bus;
the second controlled coupling unit includes: an N-type metal-oxide-semiconductor field effect transistor (NMOS) tube; the control end of the NMOS tube is connected with the third trigger bus, the first end and the second end of the NMOS tube are respectively connected with the input/output interface and the grounding bus, and the substrate end is connected with the grounding bus; the first end is a source electrode of the NMOS tube, and the second end is a drain electrode of the NMOS tube; or the first end is the drain electrode of the NMOS tube, and the second end is the source electrode of the NMOS tube;
the third controlled coupling unit includes: the control end of the NMOS tube is connected with the third trigger bus, the first end and the second end of the NMOS tube are respectively connected with the power bus and the grounding bus, and the substrate end is connected with the grounding bus; the first end is a source electrode of the NMOS tube, and the second end is a drain electrode of the NMOS tube; or the first end is the drain electrode of the NMOS tube, and the second end is the source electrode of the NMOS tube;
the ESD detection and trigger unit is used for outputting a first control signal to the trigger bus group by adopting the following mode: outputting a first high level signal to a third trigger bus;
the ESD detection and trigger unit is further configured to output a second control signal to the trigger bus group in the following manner: and outputting a second low level signal to the third trigger bus.
Example 1
Taking the occurrence of static electricity between two I/O pads as an example, the working principle of the ESD protection circuit (dual trigger bus, three controlled coupling units) in the normal working state of the circuit (no static electricity occurring) and when static electricity occurs is described in detail with reference to fig. 3.
In this example, a Metal Oxide Semiconductor (MOS) FET (Field Effect Transistor) includes a PMOS or NMOS, and the MOS Transistor includes: a first end, a second end, a control end, and a substrate end; the first end of the MOS tube is a source electrode, and the second end of the MOS tube is a drain electrode, or the first end of the MOS tube is a drain electrode, and the second end of the MOS tube is a source electrode;
as shown in fig. 3, the electrostatic discharge protection circuit includes: the ESD protection circuit comprises a trigger bus group 10, a detection bus 11, a power supply bus 12, a ground bus 13, a plurality of input/output interfaces 50, an ESD detection and trigger unit 20, a controlled coupling unit group 30 and a coupling unit 40 of each input/output interface;
the trigger bus group 10 includes two trigger buses, namely a first trigger bus 101 and a second trigger bus 102; the first trigger bus is used for controlling the first controlled coupling unit 301, and the second trigger bus is used for controlling the second controlled coupling unit 302 and the third controlled coupling unit 303;
the third controlled coupling unit 303 between the power bus 12(VDD) and the ground bus 13(VSS) comprises an NMOS 3031;
the first controlled coupling unit 301 between the first input/output interface (I/O Pad _1)501 and the power bus comprises a PMOS3011, the second controlled coupling unit 302 between the first input/output interface and the ground bus comprises an NMOS3021, and the coupling unit 40 between the first input/output interface and the detection bus 11 comprises a diode 401;
the first controlled coupling unit 301 between the second input/output interface (I/O Pad _2)502 and the power bus comprises a PMOS3012, the second controlled coupling unit 302 between the second input/output interface and the ground bus comprises an NMOS3022, and the coupling unit 40 between the second input/output interface and the detection bus 11 comprises a diode 402;
the first end of the NMOS3031 is connected with a grounding bus, the second end of the NMOS3031 is connected with a power bus, the substrate end of the NMOS is connected with the grounding bus, and the control end of the NMOS is connected with a second trigger bus;
the PMOS3011 has a first end connected to the first input/output interface, a second end connected to the power bus, a substrate end connected to the power bus, and a control end connected to the first trigger bus; the first end of the PMOS3032 is connected with the second input/output interface, the second end is connected with the power bus, the substrate end is connected with the power bus, and the control end is connected with the first trigger bus;
the first end of the NMOS3021 is connected to the first input/output interface, the second end of the NMOS is connected to the ground bus, the substrate end of the NMOS is connected to the ground bus, and the control end of the NMOS is connected to the second trigger bus; the first end of the NMOS3022 is connected to the second input/output interface, the second end is connected to the ground bus, the substrate end is connected to the ground bus, and the control end is connected to the second trigger bus;
wherein, the positive pole of the diode 401 is connected with the first input/output interface, and the negative pole is connected with the detection bus; the anode of the diode 402 is connected with the second input/output interface, and the cathode is connected with the detection bus;
when static electricity occurs, as shown in fig. 3, when a forward static voltage difference occurs between the first input/output interface (I/O Pad _1) and the second input/output interface (I/O Pad _2), the voltage of the I/O Pad _1 rises, the diode 401 rapidly transmits a voltage signal on the I/O Pad _1 to the detection bus, and at this time, the voltage of the detection bus is greater than a threshold value, the ESD detection and trigger unit determines that a static electricity event occurs, outputs a first low level signal to the first trigger bus, and outputs a first high level signal to the second trigger bus. Under the control of a low level signal on the first trigger bus, the PMOS3011 and the PMOS3012 are conducted; under the control of a high level signal on the second trigger bus, the NMOS3031, the NMOS3021 and the NMOS3022 are conducted. The path between the first input/output interface and the power bus is conducted, the path between the first input/output interface and the ground bus is conducted, the path between the second input/output interface and the power bus is conducted, the path between the second input/output interface and the ground bus is conducted, and the path between the power bus and the ground bus is conducted.
The electrostatic current leakage paths between the first input/output interface 501 and the second input/output interface 502 are three in total, as shown in fig. 4(a), 4(b), and 4(c), respectively.
In fig. 4(a), the electrostatic current passes through the PMOS3011, the power supply bus, the NMOS3031, the ground bus, and the NMOS3021 in sequence from the first input/output interface to the second input/output interface, that is, the electrostatic current is discharged through a path between the first input/output interface and the power supply bus, a path between the power supply bus and the ground bus, and a path between the ground bus and the second input/output interface.
In fig. 4(b), the electrostatic current starts from the first input/output interface, passes through the NMOS3021, the ground bus, and the NMOS3022 in sequence, and reaches the second input/output interface, that is, discharges through a path between the first input/output interface and the ground bus and a path between the ground bus and the second input/output interface.
In fig. 4(c), the electrostatic current starts from the first input/output interface, sequentially passes through the PMOS3011, the power bus, and the PMOS3012, and reaches the second input/output interface, that is, discharges through a path between the first input/output interface and the power bus and a path between the power bus and the second input/output interface.
Also, as shown in fig. 5(a), when the PMOS device is turned on, two discharge paths are provided inside the PMOS device, and the PMOS carriers are holes that migrate along a first path from the source to the drain through the channel inversion layer, and a second path from the source to the parasitic diode of the N-Well (N _ Well). The arrows in fig. 5(a) indicate the direction of the discharge current.
As shown in fig. 5(b), when the NMOS device is turned on, two discharge paths are also provided inside the NMOS device, and NMOS carriers are electrons that migrate along a third path from the source to the drain through the channel inversion layer, and a fourth path from the source to the P-substrate (P _ Sub) or the P-Well (P _ Well). The arrows in fig. 5(b) indicate the direction of the discharge current.
In the ESD protection circuit shown in fig. 3, three discharge paths are simultaneously opened to discharge ESD current, so that the Voltage Clamp (Clamp Voltage) on the first input/output interface is within the safe Voltage.
After the ESD current is discharged, the voltage on the first input/output interface is reduced, the voltage on the detection bus is reduced, at the moment, the voltage of the detection bus is smaller than the threshold value, the ESD detection and trigger unit judges that the electrostatic event is ended, a second high-level signal is output to the first trigger bus, and a second low-level signal is output to the second trigger bus. Under the control of a high level signal on the first trigger bus, the PMOS3011 and the PMOS3012 are cut off; under the control of a low level signal on the second trigger bus, the NMOS3031, the NMOS3021, and the NMOS3022 are turned off. The path between the first input/output interface and the power bus is not conductive, the path between the first input/output interface and the ground bus is not conductive, the path between the second input/output interface and the power bus is not conductive, the path between the second input/output interface and the ground bus is not conductive, and the path between the power bus and the ground bus is not conductive.
Wherein, the voltage values of the first low-level signal and the second low-level signal can be the same or different; the voltage values of the first high-level signal and the second high-level signal can be the same or different;
in the ESD protection circuit in this example, MOS (PMOS or NMOS) in the controlled coupling unit may be turned on in two directions, there are many ESD discharge paths, and the ESD current on each path is relatively small, which reduces the requirement for ESD layout design. With the reduction of the line width of the CMOS process, the MOS device in the example can obtain higher width-length ratio and stronger ESD discharge capacity under the condition of not increasing the ESD area, and is more beneficial to working in an advanced small-line-width semiconductor CMOS process. The parasitic capacitance between the input/output interface and the power bus or the grounding bus is smaller, and the high-frequency input/output interface is more beneficial to work under the condition of high-frequency input/output interface.
Example 2
As shown in fig. 6, taking ESD discharge between the input/output interface and the ground bus as an example, the operation principle of the ESD protection circuit (dual trigger bus, three controlled coupling units) when ESD occurs is explained.
When a positive static voltage differential occurs between the first input/output interface (I/O Pad _1)501 and the ground bus, the voltage at the first input/output interface rises rapidly and is coupled to the sense bus through diode 401. At the moment, the voltage of the detection bus is greater than the threshold value, the ESD detection and trigger unit judges that the electrostatic event occurs, outputs a second low-level signal to the first trigger bus, and outputs a second high-level signal to the second trigger bus. Under the control of a second low-level signal on the first trigger bus, the PMOS3011 and the PMOS3012 are conducted; under the control of the second high level signal on the second trigger bus, the NMOS3031, the NMOS3021, and the NMOS3022 are turned on. The path between the first input/output interface and the power bus is conducted, the path between the first input/output interface and the ground bus is conducted, the path between the second input/output interface and the power bus is conducted, the path between the second input/output interface and the ground bus is conducted, and the path between the power bus and the ground bus is conducted.
The electrostatic current leakage paths between the first input/output interface and the ground bus are two in total. The first electrostatic current leakage path between the first input/output interface and the ground bus is: the electrostatic current starts from the first input/output interface, and reaches the ground bus through the PMOS3011, the power bus, and the NMOS3021 in sequence, that is, the electrostatic current is discharged through a path between the first input/output interface and the power bus and a path between the power bus and the ground bus. The second electrostatic current leakage path between the first input/output interface and the ground bus is: the electrostatic current starts from the first input/output interface, passes through the NMOS3021 to the ground bus, i.e., is discharged through the ESD path between the first input/output interface and the ground bus.
Example 3
Taking the occurrence of static electricity between two I/O pads as an example, the working principle of the ESD protection circuit (dual trigger bus, two controlled coupling units) in the normal working state of the circuit (no static electricity occurring) and when static electricity occurs is described in detail with reference to fig. 7.
As shown in fig. 7, the electrostatic discharge protection circuit includes: the ESD protection circuit comprises a trigger bus group 10, a detection bus 11, a power supply bus 12, a ground bus 13, a plurality of input/output interfaces 50, an ESD detection and trigger unit 20, a controlled coupling unit group 30 and a coupling unit 40 of each input/output interface;
the trigger bus group 10 includes two trigger buses, namely a first trigger bus 101 and a second trigger bus 102; the first trigger bus is used for controlling the first controlled coupling unit 301, and the second trigger bus is used for controlling the third controlled coupling unit 303;
the third controlled coupling unit 303 between the power bus 12(VDD) and the ground bus 13(VSS) comprises an NMOS 3031;
the first controlled coupling unit 301 between the first input/output interface (I/O Pad _1)501 and the power bus comprises a PMOS3011, a diode 3021 is connected between the first input/output interface and the ground bus, and the coupling unit 40 between the first input/output interface and the detection bus 11 comprises a diode 401;
the first controlled coupling unit 301 between the second input/output interface (I/O Pad _2)502 and the power bus comprises a PMOS3012, a diode 3022 is connected between the second input/output interface and the ground bus, and the coupling unit 40 between the second input/output interface and the detection bus 11 comprises a diode 402;
the first end of the NMOS3031 is connected with a grounding bus, the second end of the NMOS3031 is connected with a power bus, the substrate end of the NMOS is connected with the grounding bus, and the control end of the NMOS is connected with a second trigger bus;
the PMOS3011 has a first end connected to the first input/output interface, a second end connected to the power bus, a substrate end connected to the power bus, and a control end connected to the first trigger bus; the first end of the PMOS3032 is connected with the second input/output interface, the second end is connected with the power bus, the substrate end is connected with the power bus, and the control end is connected with the first trigger bus;
the anode of the diode 3021 is connected to the ground bus, and the cathode is connected to the first input/output interface; the anode of the diode 3022 is connected to the ground bus, and the cathode is connected to the second input/output interface;
wherein, the positive pole of the diode 401 is connected with the first input/output interface, and the negative pole is connected with the detection bus; the anode of the diode 402 is connected with the second input/output interface, and the cathode is connected with the detection bus;
when static electricity occurs, as shown in fig. 7, when a forward static voltage difference occurs between the first input/output interface (I/O Pad _1) and the second input/output interface (I/O Pad _2), the voltage of the I/O Pad _1 rises, the diode 401 rapidly transmits a voltage signal on the I/O Pad _1 to the detection bus, and at this time, the voltage of the detection bus is greater than a threshold value, the ESD detection and trigger unit determines that a static electricity event occurs, outputs a first low level signal to the first trigger bus, and outputs a first high level signal to the second trigger bus. Under the control of a low level signal on the first trigger bus, the PMOS3011 and the PMOS3012 are conducted; the NMOS3031 is turned on under the control of a high signal on the second trigger bus. Diode 3021 is turned off and diode 3022 is turned on. The path between the first input/output interface and the power bus is conducted, the path between the first input/output interface and the ground bus is not conducted, the path between the second input/output interface and the power bus is conducted, the path between the second input/output interface and the ground bus is conducted, and the path between the power bus and the ground bus is conducted.
As shown in fig. 7, there are two electrostatic current leakage paths between the first input/output interface 501 and the second input/output interface 502. The first electrostatic current leakage path between the first input/output interface and the second input/output interface is: the electrostatic current starts from the first input/output interface, sequentially passes through the PMOS3011, the power supply bus, the NMOS3031, the ground bus, and the diode 3022, and reaches the second input/output interface, that is, discharges through a path between the first input/output interface and the power supply bus, a path between the power supply bus and the ground bus, and a path between the ground bus and the second input/output interface. The second electrostatic current leakage path between the first input/output interface and the second input/output interface is: the electrostatic current starts from the first input/output interface, sequentially passes through the PMOS3011, the power bus, and the PMOS3012, and reaches the second input/output interface, that is, discharges through a path between the first input/output interface and the power bus and a path between the power bus and the second input/output interface.
In the ESD protection circuit shown in fig. 7, the two discharge paths are simultaneously opened to discharge ESD current, and the Voltage Clamp (Clamp Voltage) on the first input/output interface is within the safe Voltage.
After the ESD current is discharged, the voltage on the first input/output interface is reduced, the voltage on the detection bus is reduced, at the moment, the voltage of the detection bus is smaller than the threshold value, the ESD detection and trigger unit judges that the electrostatic event is ended, a second high-level signal is output to the first trigger bus, and a second low-level signal is output to the second trigger bus. Under the control of a first high level signal on the first trigger bus, the PMOS3011 and the PMOS3012 are cut off; the NMOS3031 is turned off under the control of the low level signal on the second trigger bus. The path between the first input/output interface and the power bus is non-conductive, the path between the second input/output interface and the power bus is non-conductive, and the path between the power bus and the ground bus is non-conductive. Whether the path between the first input/output interface and the ground bus is conductive is determined by the voltage difference between the level of the first input/output interface and the level of the ground bus: if the level of the ground bus is higher than that of the first input/output interface and the voltage difference is greater than or equal to the forward conduction voltage drop of the diode 3021, the path is conducted; if the level of the ground bus is lower than or equal to the level of the first input/output interface, or the level of the ground bus is higher than the level of the first input/output interface and the voltage difference is less than the forward conduction voltage drop of diode 3021, the path is non-conductive. Whether the path between the second input/output interface and the ground bus is conducted or not is determined by a voltage difference between the level of the second input/output interface and the level of the ground bus, and the principle is the same.
Example 4
Taking the occurrence of static electricity between two I/O pads as an example, the working principle of the ESD protection circuit (one-shot bus, two controlled coupling units) in the normal working state of the circuit (no static electricity occurring) and when static electricity occurs is described in detail with reference to fig. 8.
As shown in fig. 8, the electrostatic discharge protection circuit includes: the ESD protection circuit comprises a trigger bus group 10, a detection bus 11, a power supply bus 12, a ground bus 13, a plurality of input/output interfaces 50, an ESD detection and trigger unit 20, a controlled coupling unit group 30 and a coupling unit 40 of each input/output interface;
the trigger bus group 10 includes a trigger bus: a third trigger bus 103; the third trigger bus is used for controlling the second controlled coupling unit 302 and the third controlled coupling unit 303;
the third controlled coupling unit 303 between the power bus 12(VDD) and the ground bus 13(VSS) comprises an NMOS 3031;
a diode 3011 is connected between the first input/output interface (I/O Pad _1)501 and the power bus, the second controlled coupling unit 302 between the first input/output interface and the ground bus comprises an NMOS3021, and the coupling unit 40 between the first input/output interface and the detection bus 11 comprises a diode 401;
a diode 3012 is connected between the second input/output interface (I/O Pad _2)502 and the power bus, the second controlled coupling unit 302 between the second input/output interface and the ground bus comprises an NMOS3022, and the coupling unit 40 between the second input/output interface and the detection bus 11 comprises a diode 402;
the first end of the NMOS3031 is connected with a grounding bus, the second end of the NMOS3031 is connected with a power bus, the substrate end of the NMOS is connected with the grounding bus, and the control end of the NMOS is connected with a third trigger bus;
the first end of the NMOS3021 is connected to the first input/output interface, the second end of the NMOS is connected to the ground bus, the substrate end of the NMOS is connected to the ground bus, and the control end of the NMOS is connected to the third trigger bus; the first end of the NMOS3022 is connected to the second input/output interface, the second end is connected to the ground bus, the substrate end is connected to the ground bus, and the control end is connected to the third trigger bus;
wherein, the positive pole of the diode 3011 is connected with the first input/output interface, the negative pole is connected with power bus; the anode of the diode 3012 is connected to the second input/output interface, and the cathode is connected to the power bus;
wherein, the positive pole of the diode 401 is connected with the first input/output interface, and the negative pole is connected with the detection bus; the anode of the diode 402 is connected with the second input/output interface, and the cathode is connected with the detection bus;
when static electricity occurs, as shown in fig. 8, when a forward static voltage difference occurs between the first input/output interface (I/O Pad _1) and the second input/output interface (I/O Pad _2), the voltage of the I/O Pad _1 rises, the diode 401 rapidly transmits a voltage signal on the I/O Pad _1 to the detection bus, and at this time, the voltage of the detection bus is greater than a threshold value, the ESD detection and trigger unit determines that a static electricity event occurs, and outputs a first high level signal to the third trigger bus. Under the control of a high level signal on the third trigger bus, the NMOS3031, the NMOS3021 and the NMOS3022 are conducted. Diode 3011 is on and diode 3012 is off. The path between the first input/output interface and the power bus is conducted, the path between the first input/output interface and the ground bus is conducted, the path between the second input/output interface and the power bus is not conducted, the path between the second input/output interface and the ground bus is conducted, and the path between the power bus and the ground bus is conducted.
As shown in fig. 8, there are two electrostatic current leakage paths between the first input/output interface 501 and the second input/output interface 502. The first electrostatic current leakage path between the first input/output interface and the second input/output interface is: the electrostatic current starts from the first input/output interface, sequentially passes through the diode 3011, the power supply bus, the NMOS3031, the ground bus, and the NMOS3022, and reaches the second input/output interface, that is, discharges through a path between the first input/output interface and the power supply bus, a path between the power supply bus and the ground bus, and a path between the ground bus and the second input/output interface. The second electrostatic current leakage path between the first input/output interface and the second input/output interface is: the electrostatic current starts from the first input/output interface, sequentially passes through the NMOS3021, the ground bus, and the NMOS3022, and reaches the second input/output interface, that is, the electrostatic current is discharged through a path between the first input/output interface and the ground bus and a path between the ground bus and the second input/output interface.
In the ESD protection circuit shown in fig. 8, the two discharge paths are simultaneously opened to discharge the ESD current, and the Voltage Clamp (Clamp Voltage) on the first input/output interface is within the safe Voltage.
After the ESD current is discharged, the voltage on the first input/output interface is reduced, the voltage on the detection bus is reduced, at the moment, the voltage of the detection bus is smaller than the threshold value, the ESD detection and trigger unit judges that the electrostatic event is finished, and a second low-level signal is output to the third trigger bus. Under the control of a low level signal on the third trigger bus, the NMOS3031, the NMOS3021, and the NMOS3022 are turned off. Diode 3011 and diode 3012 are non-conducting. The path between the power bus and the ground bus is non-conductive, the path between the first input/output interface and the ground bus is non-conductive, the path between the second input/output interface and the ground bus is non-conductive, the path between the first input/output interface and the power bus is non-conductive, and the path between the second input/output interface and the power bus is non-conductive.
It should be noted that the present invention can be embodied in other specific forms, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims (7)

1. An electrostatic discharge protection circuit comprising: the ESD protection circuit comprises a trigger bus group, a detection bus, a power bus, a grounding bus, a plurality of input/output interfaces, an electrostatic discharge (ESD) detection and trigger unit, a controlled coupling unit group and a coupling unit of each input/output interface;
the ESD detection and trigger unit is connected with the detection bus, the grounding bus, the power supply bus and the trigger bus group, judges whether an electrostatic event occurs or not by detecting signals on the detection bus, and outputs a first control signal to the trigger bus group if the electrostatic event occurs;
the coupling unit of each input/output interface is used for coupling the signals of the input/output interface to the detection bus;
the controlled coupling unit group includes: the first controlled coupling unit is arranged between each input/output interface and the power bus, the second controlled coupling unit is arranged between each input/output interface and the ground bus, and the third controlled coupling unit is arranged between the power bus and the ground bus;
the trigger bus group is connected with a third controlled coupling unit in the controlled coupling unit group and is also connected with each first controlled coupling unit and/or each second controlled coupling unit;
the controlled coupling unit group is used for conducting each controlled coupling unit controlled by the trigger bus group under the control of the first control signal;
the ESD detection and trigger unit is also used for outputting a second control signal to the trigger bus group when the ESD detection and trigger unit judges that no electrostatic event occurs;
the controlled coupling unit group is also used for making each controlled coupling unit controlled by the trigger bus group not be conducted under the control of the second control signal;
the coupling unit of the input/output interface comprises a first diode, the anode of the first diode is connected with the input/output interface, and the cathode of the first diode is connected with the detection bus;
the trigger bus group comprises a first trigger bus and a second trigger bus;
the ESD detection and trigger unit is used for outputting a first control signal to the trigger bus group by adopting the following mode: outputting a first low level signal to the first trigger bus and outputting a first high level signal to the second trigger bus;
the ESD detection and trigger unit is further configured to output a second control signal to the trigger bus group in the following manner: outputting a second high level signal to the first trigger bus, and outputting a second low level signal to the second trigger bus;
the third controlled coupling unit includes: the control end of the NMOS tube is connected with the second trigger bus, the first end and the second end of the NMOS tube are respectively connected with the power bus and the grounding bus, and the substrate end is connected with the grounding bus;
the first controlled coupling unit includes: a P-type metal-oxide-semiconductor field effect transistor PMOS tube; the control end of the PMOS tube is connected with the first trigger bus, the first end and the second end of the PMOS tube are respectively connected with the input/output interface and the power bus, and the substrate end is connected with the power bus.
2. The circuit of claim 1, wherein:
the second controlled coupling unit includes: an N-type metal-oxide-semiconductor field effect transistor (NMOS) tube; the control end of the NMOS tube is connected with the second trigger bus, the first end and the second end of the NMOS tube are respectively connected with the input/output interface and the grounding bus, and the substrate end is connected with the grounding bus.
3. The circuit of claim 1, wherein:
the second controlled coupling unit includes: a second diode; and the anode of the second diode is connected with the grounding bus, and the cathode of the second diode is connected with the input/output interface.
4. The circuit of claim 1, wherein:
the trigger bus group comprises a third trigger bus;
the ESD detection and trigger unit is used for outputting a first control signal to the trigger bus group by adopting the following mode: outputting a first high level signal to a third trigger bus;
the ESD detection and trigger unit is further configured to output a second control signal to the trigger bus group in the following manner: outputting a second low level signal to a third trigger bus;
the third controlled coupling unit includes: and the control end of the NMOS tube is connected with the third trigger bus, the first end and the second end of the NMOS tube are respectively connected with the power bus and the grounding bus, and the substrate end is connected with the grounding bus.
5. The circuit of claim 4, wherein:
the first controlled coupling unit comprises a third diode, the anode of the third diode is connected with the input/output interface, and the cathode of the third diode is connected with the power bus;
the second controlled coupling unit includes: an N-type metal-oxide-semiconductor field effect transistor (NMOS) tube; the control end of the NMOS tube is connected with the third trigger bus, the first end and the second end of the NMOS tube are respectively connected with the input/output interface and the grounding bus, and the substrate end is connected with the grounding bus.
6. The circuit of any one of claims 1-5, wherein:
the ESD detection and trigger unit is used for judging whether an electrostatic event occurs by detecting signals on the detection bus in the following modes:
when the signal voltage value on the detection bus is greater than or equal to a threshold value, determining that an electrostatic event occurs; when the signal voltage value on the detection bus is smaller than a threshold value, judging that no electrostatic event occurs;
the threshold is greater than a supply voltage on the power bus when no static electricity is occurring.
7. The circuit of any one of claims 1-5, wherein:
the ESD detection and trigger unit is used for judging whether an electrostatic event occurs by detecting signals on the detection bus in the following modes:
when the amplitude-frequency characteristics of the signals on the detection bus meet the characteristics of the electrostatic signals, judging that an electrostatic event occurs; when the amplitude-frequency characteristics of the signals on the detection bus do not meet the characteristics of the electrostatic signals, judging that no electrostatic event occurs;
the amplitude-frequency characteristics of the electrostatic signal include: the electrostatic signal is a pulse signal and the amplitude variation exceeds a variation range threshold.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1628385A (en) * 2002-08-09 2005-06-15 自由度半导体公司 Electrostatic discharge protection circuit and working method
KR100849068B1 (en) * 2007-03-15 2008-07-30 주식회사 하이닉스반도체 Electrostatic discharge protection circuit

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KR20080090725A (en) * 2007-04-05 2008-10-09 주식회사 하이닉스반도체 Electrostatic discharge protection circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1628385A (en) * 2002-08-09 2005-06-15 自由度半导体公司 Electrostatic discharge protection circuit and working method
KR100849068B1 (en) * 2007-03-15 2008-07-30 주식회사 하이닉스반도체 Electrostatic discharge protection circuit

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