US20130140704A1 - Low Frequency CMUT with Thick Oxide - Google Patents
Low Frequency CMUT with Thick Oxide Download PDFInfo
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- US20130140704A1 US20130140704A1 US13/309,853 US201113309853A US2013140704A1 US 20130140704 A1 US20130140704 A1 US 20130140704A1 US 201113309853 A US201113309853 A US 201113309853A US 2013140704 A1 US2013140704 A1 US 2013140704A1
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- top surface
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- thick oxide
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
- B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
- B06B1/0292—Electrostatic transducers, e.g. electret-type
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/22—Details, e.g. general constructional or apparatus details
- G01N29/24—Probes
- G01N29/2406—Electrostatic or capacitive probes, e.g. electret or cMUT-probes
Definitions
- the present invention relates to CMUTS and, more particularly, to a low frequency CMUT with thick oxide.
- CMUT capacitive micromachined ultrasonic transducer
- FIGS. 1A-1B show views that illustrate an example of a prior-art CMUT 100 .
- FIG. 1A shows a plan view of CMUT 100
- FIG. 1B shows a cross-sectional view taken along line 1 B- 1 B of FIG. 1A .
- CMUT 100 includes a conventionally-formed semiconductor substrate 110 , and a post oxide structure 112 that touches the top surface of semiconductor substrate 110 .
- Post oxide structure 112 in turn, has substrate contact openings 114 that extend completely through post oxide structure 112 to expose semiconductor substrate 110 .
- CMUT 100 includes a non-conductive structure 116 that touches the top surface of semiconductor substrate 110 , and a conductive structure 120 that touches the top surface of post oxide structure 112 and lies over non-conductive structure 116 to form a vacuum-sealed cavity 122 .
- conductive structure 120 includes a semiconductor structure 124 such as, for example, single crystal silicon, and an overlying metal structure 126 , such as an aluminum copper plate.
- CMUT 100 includes substrate bond pads 130 that lie within the substrate contact openings 114 to make electrical connections to semiconductor substrate 110 , and a passivation layer 132 that touches and lies over post oxide structure 112 , conductive structure 120 , and the substrate bond pads 130 .
- Passivation layer 132 has substrate bond pad openings 134 that expose the substrate bond pads 130 , and a conductor opening 136 that exposes a region of conductive structure 120 which functions as a bond pad.
- CMUT 100 has an acoustic dampening structure 140 that touches the bottom surface of semiconductor substrate 110 .
- a first bias voltage V 1 is placed on semiconductor substrate 110 , which functions as a first capacitor plate
- a second bias voltage V 2 is placed on conductive structure 120 , which functions as second capacitor plate.
- the voltage across the capacitor plates lies across vacuum-sealed cavity 122 .
- an ultrasonic wave causes conductive structure 120 to vibrate. The vibration varies the capacitance across the first and second capacitor plates, thereby generating an electrical signal that varies as the capacitance varies.
- an alternating electrical signal applied across the biased first and second capacitor plates causes conductive structure 120 to vibrate which, in turn, transmits ultrasonic waves.
- the rate or frequency at which conductive structure 120 vibrates depends on the volume of vacuum-sealed cavity 122 , and the stiffness of conductive structure 120 .
- ultrasonic waves are also transmitted backward towards the bottom surface of semiconductor substrate 110 .
- These backward ultrasonic waves can resonate within semiconductor substrate 110 depending on the thickness of semiconductor substrate 110 and the frequency of operation, and can interfere with the quality of the resultant image.
- Acoustic dampening structure 140 absorbs and dampens the ultrasonic waves in semiconductor substrate 110 .
- FIGS. 2A-2B show views that illustrate an example of a prior-art CMUT array 200 .
- FIG. 2A shows a plan view of array 200
- FIG. 2B shows a cross-sectional view taken along line 2 B- 2 B of FIG. 2A .
- CMUT array 200 includes three CMUTS 100 in a single row.
- FIGS. 3A-3N show cross-sectional views that illustrate an example of a prior-art method of forming a CMUT.
- the method utilizes a conventionally-formed single-crystal silicon wafer 310 .
- Silicon wafer 310 has rows and columns of die-sized regions, and one or more CMUTS can be simultaneously formed in each die-sized region.
- FIGS. 3A-3N illustrate the formation of a single CMUT.
- the method begins by forming a post oxide structure 312 on the top surface of silicon wafer 310 using the well-known local oxidation of silicon (LOCOS) process.
- LOCOS local oxidation of silicon
- the LOCOS process also forms a backside oxide structure 314 that touches the bottom surface of silicon wafer 310 at the same time.
- a cell oxide layer 316 is grown on the exposed regions of the top surface of silicon wafer 310 .
- SOI wafer 320 is fusion bonded to the top surface of post oxide structure 312 to form a cavity 322 .
- SOI wafer 320 has a handle wafer 324 , an insulation layer 326 that touches handle wafer 324 , and a single-crystal silicon substrate structure 328 .
- Substrate structure 328 in turn, has a first surface that touches insulation layer 326 , and a second surface that touches post oxide structure 312 .
- Cavity 322 has a depth that is measured vertically from the top surface of cell oxide layer 316 to the second surface of substrate structure 328 .
- the thickness of cell oxide layer 316 defines the position of the top surface of cell oxide layer 316 .
- the height of post oxide structure 312 over the top surface of silicon wafer 310 defines the position of the second surface of substrate structure 328 .
- the thickness of cell oxide layer 316 is relatively small compared to the height of post oxide structure 312 over the top surface of silicon wafer 310 .
- the depth of cavity 322 is substantially defined by the height of post oxide structure 312 over the top surface of silicon wafer 310 .
- substrate structure 328 of SOI wafer 320 is fusion bonded to the top surface of post oxide structure 312 of silicon wafer 310 in a vacuum to vacuum seal cavity 322 .
- handle wafer 324 is removed in a conventional manner, followed by the conventional removal of insulation layer 326 .
- a patterned photoresist layer 330 is formed on the first surface of substrate structure 328 .
- the exposed region of substrate structure 328 is etched to form a CMUT membrane 332 .
- Patterned photoresist layer 330 is then removed in a conventional manner.
- a patterned photoresist layer 340 is formed on post oxide structure 312 and CMUT membrane 332 .
- patterned photoresist layer 340 has been formed, as shown in FIG. 3H , the exposed regions of post oxide structure 312 are etched until silicon wafer 310 has been exposed. Patterned photoresist layer 340 is then removed in a conventional manner.
- a metal layer 342 such as a layer of aluminum copper, is deposited to touch silicon wafer 310 , post oxide structure 312 , and CMUT membrane 332 . After this, a patterned photoresist layer 350 is formed on metal layer 342 .
- metal layer 342 is etched to form semiconductor bond pads 352 that extend through post oxide structure 312 to touch silicon wafer 310 , and a metal plate 354 that touches the top surface of CMUT membrane 332 .
- Patterned photoresist layer 350 is then removed in a conventional manner.
- a passivation layer 356 is formed to touch post oxide structure 312 , CMUT membrane 332 , the bond pads 352 , and metal plate 354 .
- a patterned photoresist layer 360 is formed on passivation layer 356 .
- the exposed regions of passivation layer 356 are etched to form openings that expose the semiconductor bond pads 352 , and an opening, like opening 136 in FIG. 1A , that exposes a bond pad region of metal plate 354 .
- patterned photoresist layer 360 is then removed in a conventional manner.
- backside oxide structure 314 is removed in a conventional manner.
- backside oxide structure 314 can be removed using chemical mechanical polishing.
- backside oxide structure 314 can be removed using a single-sided wet etch, such as a SEZ etch.
- an acoustic damping structure 362 such as a tungsten epoxy mixture, is deposited onto the bottom side of silicon wafer 310 to form, as shown in FIG. 3N , a CMUT 364 . Silicon wafer 310 is then diced to form a number of individual die that each has one or more CMUTS 364 .
- cavity 322 has a depth of approximately 0.2 ⁇ m and a diameter of approximately 36.0 ⁇ m.
- CMUT membrane 332 , metal plate 354 , and the overlying region of passivation layer 356 vibrate at frequencies of approximately 10-20 MHz. These frequencies are suitable for contact or near contact body imaging applications, like echo cardiograms, but are not suitable for airborne ultrasound applications where, for example, the object to be detected, such as the hand motions of a person playing a game, is one or more meters away.
- CMUT 364 would require a larger cell diameter (e.g. increasing from about 36 ⁇ m to about 1 mm-2 mm), a thicker CMUT membrane 332 (e.g. increasing from 2 ⁇ m to 5 ⁇ m-40 ⁇ m), and a deeper cell cavity 322 (e.g. increasing from 0.2 ⁇ m to 1 ⁇ m-12 ⁇ m).
- a deeper cell cavity is required to accommodate the atmospheric deflection of CMUT membrane 332 , which can be on the order of several microns.
- CMUT membrane 332 should not touch the bottom surface of cavity 322 , but rather be a fixed distance of one or more microns above the bottom surface of cavity 322 .
- post oxide structure 312 substantially determines the depth of cavity 322 . Since the height of post oxide structure 312 substantially determines the depth of cavity 322 , scaling up CMUT 364 requires that post oxide structure 312 have a height above the top surface of silicon wafer 310 of approximately 1 ⁇ m-12 ⁇ m, or a total thickness of 2 ⁇ m-24 ⁇ m. However, forming a post oxide structure with a thickness that exceeds approximately 5 ⁇ m (or heights that exceed 2.5 ⁇ m) is difficult to accomplish because the rate of oxide growth slows dramatically when the thickness of the post oxide structure approaches 5 ⁇ m.
- FIGS. 1A-1B are views illustrating an example of a prior-art CMUT 100 .
- FIG. 1A is a plan view of CMUT 100 .
- FIG. 1B is a cross-sectional view taken along line 1 B- 1 B of FIG. 1A .
- FIGS. 2A-2B are views illustrating an example of a prior-art CMUT array 200 .
- FIG. 2A is a plan view of array 200 .
- FIG. 2B is a cross-sectional view taken along line 2 B- 2 B of FIG. 2A .
- FIGS. 3A-3N are cross-sectional views illustrating an example of a prior-art method of forming a CMUT.
- FIGS. 4A-4B are views illustrating an example of a CMUT 400 in accordance with the present invention.
- FIG. 4A is a plan view of CMUT 400 .
- FIG. 4B is a cross-sectional view taken along line 4 B- 4 B of FIG. 4A .
- FIGS. 5A-5B are views illustrating an example of a CMUT array 500 in accordance with the present invention.
- FIG. 5A is a plan view of array 500 .
- FIG. 5B is a cross-sectional view taken along line 5 B- 5 B of FIG. 5A .
- FIGS. 6A-6R are cross-sectional views illustrating an example of a method of forming a CMUT in accordance with the present invention.
- FIGS. 7A-7B are views illustrating an example of a CMUT 700 in accordance with an alternate embodiment of the present invention.
- FIG. 7A is a plan view of CMUT 700 .
- FIG. 7B is a cross-sectional view taken along line 7 B- 7 B of FIG. 7A .
- FIGS. 8A-8D are cross-sectional views illustrating an example of a method of forming a CMUT in accordance with an alternate embodiment of the present invention.
- FIGS. 4A-4B show views that illustrate an example of a CMUT 400 in accordance with the present invention.
- FIG. 4A shows a plan view of CMUT 400
- FIG. 4B shows a cross-sectional view taken along line 4 B- 4 B of FIG. 4A .
- CMUT 400 utilizes thick oxide to increase the size of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves.
- CMUT 400 includes a semiconductor substrate 410 that has a bottom surface 412 and a top surface 414 , where the top surface 414 lies in a plane 415 .
- Semiconductor substrate 410 which is conductive, can be implemented with, for example, single-crystal silicon.
- CMUT 400 also includes a post structure 420 that touches the top surface 414 of semiconductor substrate 410 such that no portion of post structure 420 lies below plane 415 , and no non-conductive region lies below plane 415 and touches the bottom surface of post structure 420 .
- post structure 420 which is non-conductive, laterally surrounds a cell region 422 of the top surface 414 of semiconductor substrate 410 .
- no conductive structure extends through post structure 420 .
- CMUT 400 includes a non-conductive structure 424 that touches the cell region 422 of the top surface 414 of semiconductor substrate 410 .
- non-conductive structure 424 which can be implemented with a layer of oxide, is laterally surrounded and touched by post structure 420 .
- CMUT 400 also includes a conductive structure 430 that touches the top surface of post structure 420 , and lies directly vertically over non-conductive structure 424 to form a cavity 432 that lies vertically between non-conductive structure 424 and conductive structure 430 .
- conductive structure 430 includes a semiconductor structure 434 such as, for example, single-crystal silicon, and an overlying metal structure 436 , such as an aluminum copper plate.
- CMUT 400 includes a passivation layer 442 that touches and lies over post structure 420 and conductive structure 430 .
- Passivation layer 442 which is non-conductive, has a conductive opening 446 that exposes a region of metal structure 436 that functions as a bond pad.
- CMUT 400 includes a metal bond pad structure 450 that touches the bottom surface 412 of semiconductor substrate 410 .
- a first bias voltage V 1 is placed on semiconductor substrate 410 , which functions as a first capacitor plate
- a second bias voltage V 2 is placed on conductive structure 430 , which functions as second capacitor plate.
- the voltage across the capacitor plates lies vertically across cavity 432 .
- an ultrasonic wave causes conductive structure 430 to vibrate.
- the vibration varies the capacitance across the first and second capacitor plates, thereby generating an electrical signal that varies as the capacitance varies.
- an alternating electrical signal applied across the biased first and second capacitor plates causes conductive structure 430 to vibrate which, in turn, transmits ultrasonic waves.
- CMUT 400 One of the advantages of CMUT 400 is that the volume of cavity 432 is substantially greater than the volume of cavity 122 because post structure 420 has a height above the top surface of semiconductor substrate 410 that is significantly larger that the height of post oxide structure 112 above the top surface of semiconductor substrate 110 .
- the increased volume allows CMUT 400 to accommodate the low frequency signals required by ultrasonic airborne imaging applications.
- FIGS. 5A-5B show views that illustrate an example of a CMUT array 500 in accordance with the present invention.
- FIG. 5A shows a plan view of array 500
- FIG. 5B shows a cross-sectional view taken along line 5 B- 5 B of FIG. 5A .
- CMUT array 500 includes three CMUTS 400 in a single row.
- laterally adjacent CMUT membranes 434 are separated by 50 ⁇ m.
- FIGS. 6A-6R show cross-sectional views that illustrate an example of a method of forming a CMUT in accordance with the present invention.
- the method utilizes a conventionally-formed single-crystal silicon wafer 610 that has a bottom surface 612 and a top surface 614 , where the top surface 614 lies in a plane 615 .
- silicon wafer 610 has a low resistivity (e.g., 0.1 ⁇ -cm).
- Silicon wafer 610 has rows and columns of die-sized regions, and one or more CMUTS can be simultaneously formed in each die-sized region.
- FIGS. 6A-6R illustrate the formation of a single CMUT.
- the method begins by forming a patterned photoresist layer on the top surface 614 of silicon wafer 610 in a conventional manner. After the patterned photoresist layer has been formed, the top surface 614 of silicon wafer 610 is etched for a predefined time to form two or more front side alignment marks.
- the resulting structure is rinsed following the etch.
- the patterned photoresist layer is conventionally removed, such as with an ash plus a solvent clean.
- the resulting structure is cleaned to remove organics, such as with a Piranha etch (e.g., using a solution of 50H 2 SO 4 :1H 2 O 2 @ 120° C. removes approximately 240 nm/minute).
- the method continues by forming a post structure on the top surface 614 of silicon wafer 610 .
- the post structure which is non-conductive, is first formed by growing a thick oxide layer 616 on the top surface 614 of silicon wafer 610 using high-pressure oxidization (HIPOX).
- HIPOX high-pressure oxidization
- a thick oxide layer 617 is simultaneously grown on the bottom surface 612 of silicon wafer 610 .
- thick oxide layers 616 and 617 can be grown at a temperature in the range of 900° C. to 1200° C. with an operating pressure of 10 to 20 atm.
- thick oxide layers 616 and 617 are grown to each have a thickness of approximately 5.15 ⁇ m.
- a patterned photoresist layer 618 is formed on thick oxide layer 616 in a conventional manner.
- the exposed region of thick oxide layer 616 is etched to form an opening 620 approximately 1.12 mm wide that exposes a cell region 622 of the top surface 614 of silicon wafer 610 , and form a post structure 624 .
- a non-polymerizing plasma etch can be used to etch an opening through approximately 4.65 ⁇ m of the approximately 5.15 ⁇ m thick oxide layer 616 .
- the slope of the side wall at the end of the non-polymerizing etch is approximately 80° (i.e., the opening is slightly larger at the top than at the bottom), and results from the natural erosion of patterned photoresist layer 618 .
- the remaining approximately 0.5 ⁇ m of thick oxide layer 616 is removed without damaging the cell region 622 of the top surface 614 of silicon wafer 610 using, for example, a wet etchant that is highly or completely selective to silicon.
- the resulting structure is rinsed, and patterned photoresist layer 618 is conventionally removed, such as with an ash plus a solvent clean.
- the resulting structure is then subjected to a conventional pre-oxidization clean.
- the top surface of thick oxide layer 616 , and thereby the top surface of post structure 624 are substantially planar.
- the surface roughness of thick oxide layer 616 , and thereby the surface roughness of post structure 624 must be controlled to provide a good bonding surface. In the present example, the surface roughness is less than 3 ⁇ RMS.
- a cell oxide layer 634 is grown on the cell region 622 of the top surface 614 of silicon wafer 610 in a conventional manner to have a thickness of, for example, 0.3 ⁇ m.
- a silicon-on-oxide (SOI) wafer 640 is bonded to the top surface of post structure 624 to form a cavity 642 .
- SOI wafer 640 is vacuum fusion bonded to post structure 624 of silicon wafer 610 in a conventional manner so that cavity 624 has a vacuum, followed by an anneal to ensure reliable bonding strength.
- the anneal can be performed with a temperature in the range of 400° C. to 1050° C. In the present example, the anneal is performed at 1050° C. immediately after the bonding for approximately four hours. Alternately, other bonding approaches can also be used.
- SOI wafer 640 has a handle wafer 644 , an insulation layer 646 that touches handle wafer 644 , and a single-crystal silicon substrate structure 648 .
- Substrate structure 648 has a first substantially-planar surface that touches insulation layer 646 , and a second substantially-planar surface that touches post structure 624 .
- insulation layer 646 has a thickness of 1.1 ⁇ m
- substrate structure 648 has a thickness of 14 ⁇ m.
- handle wafer 644 is removed in a conventional manner.
- handle wafer 644 can be removed by first grinding handle wafer 644 down to a thickness of approximately 150 ⁇ m.
- a four hour anneal at 1050° C. is next performed, followed by a wet etch, such as with a solution of KOH or TMAH, to remove the remainder of handle wafer 644 .
- insulation layer 646 is removed in a conventional manner.
- insulation layer 646 can be removed using a wet HF etchant that is highly selective to silicon, or chemical mechanical polishing.
- the wet etch of insulation layer 646 could be performed using a single-sided wet etch, such as a SEZ etch by SEZ Austria GmbH, Draubodenweg 29, A-9500 Villach, Austria.
- the center region of substrate structure 648 is pulled towards the bottom surface of cavity 642 by approximately 4 ⁇ m due to the vacuum in cavity 642 and the effects of atmospheric pressure.
- the second four hour anneal is performed prior to the wet etch of the final 150 ⁇ m Si substrate remaining after the initial back grind process step, and the subsequent wet etch of insulation layer 646 .
- a patterned photoresist layer is formed on the first surface of substrate structure 648 in a conventional manner. Once the patterned photoresist layer has been formed, the exposed regions of substrate structure 648 are etched, such as with a plasma etch, to expose the alignment marks.
- a conventional Bosch etch can be used to expose the alignment marks. Since post structure 624 (which is approximately 5.15 ⁇ m thick and lies over the alignment marks) is transparent, only substrate structure 648 , which is approximately 14 ⁇ m thick, needs to be removed. After the etch, the patterned photoresist layer is conventionally removed, such as with an ash plus a solvent. Following the removal of the patterned photoresist layer, the resulting structure is cleaned to remove organics, such as with a Piranha etch.
- a patterned photoresist layer 660 is formed on the first surface of substrate structure 648 in a conventional manner.
- the exposed regions of substrate structure 648 are etched to form a CMUT membrane 662 that lies directly vertically over the cell region 622 of the top surface 414 of silicon wafer 610 .
- a conventional Bosch etch with a short Bosch cycle to minimize side wall scalloping can be used to pattern CMUT membrane 662 without damaging CMUT membrane 662 .
- patterned photoresist layer 660 is conventionally removed, such as with an ash plus a solvent clean.
- the resulting structure is cleaned to remove organics, such as with a Piranha etch.
- a metal layer 674 such as a layer of aluminum copper, is deposited to touch post structure 624 and CMUT membrane 662 .
- metal layer 674 is formed to have a thickness of 1 ⁇ m.
- a patterned photoresist layer 680 is formed on metal layer 674 in a conventional manner.
- metal plate 684 has a minimum width of approximately 50 ⁇ m.
- the resulting structure is rinsed.
- patterned photoresist layer 680 is conventionally removed, such as with an ash plus a solvent clean.
- a passivation layer 686 such as a layer of plasma oxide approximately 0.6 ⁇ m thick and an overlying layer of plasma nitride approximately 0.6 ⁇ m thick, is deposited on post structure 624 , CMUT membrane 662 , and metal plate 684 .
- a patterned photoresist layer 690 is formed on passivation layer 686 in a conventional manner.
- patterned photoresist layer 690 After patterned photoresist layer 690 has been formed, the exposed region of passivation layer 686 is wet etched to form an opening, like opening 446 shown in FIG. 4A , that exposes a bond pad region on metal plate 684 . Following the etch, the resulting structure is rinsed. After the rinse, patterned photoresist layer 690 is conventionally removed, such as with an ash plus a solvent clean. In the present example, after the removal of patterned photoresist layer 690 , the resulting structure is alloyed at, for example, 400° C. in an ambient of N 2 +H 2 .
- thick oxide layer 617 is removed in a conventional manner.
- thick oxide layer 617 can be removed using chemical mechanical polishing.
- thick oxide layer 617 can be removed using a single-sided wet etch, such as a SEZ etch.
- a metal layer 692 such as 100 ⁇ of titanium and 1 ⁇ m of aluminum copper, is deposited onto the bottom surface 612 of silicon wafer 610 to form a CMUT 694 .
- Metal layer 692 can also be implemented with other common back side metallization stacks, such as TiNiAg, TiNiAu, CRAu, or TiAu. Silicon wafer 610 is then diced to form a number of individual die that each has one or more CMUTS 694 .
- a metal layer 695 such as a layer of aluminum copper, is deposited to touch the top surface of substrate structure 648 .
- metal layer 695 is formed to have a thickness of 1 ⁇ m.
- a patterned photoresist layer 696 is formed on metal layer 695 in a conventional manner.
- metal plate 697 has a minimum width of approximately 50 ⁇ m. Following the etch, the resulting structure is rinsed.
- CMUT membrane 662 In a first variation, as shown in FIG. 6N , after the rinse, the exposed regions of substrate structure 648 are next etched to form CMUT membrane 662 . After the etch has been completed, patterned photoresist layer 696 is conventionally removed, such as with an ash plus a solvent clean.
- passivation layer 686 is formed on metal plate 697 rather than metal plate 684 .
- One advantage of the first variation is that the first variation eliminates one masking step. However, a dedicated silicon etch tool may be required to etch silicon with the exposed aluminum copper of metal plate 697 .
- patterned photoresist layer 696 is conventionally removed, such as with an ash plus a solvent clean.
- a patterned photoresist layer 698 is formed on substrate structure 648 and metal plate 697 in a conventional manner.
- CMUT membrane 662 As shown in FIG. 6Q , after patterned photoresist layer 698 has been formed, the exposed region of substrate structure 648 is etched to form CMUT membrane 662 . Following the etch, the resulting structure is rinsed. After the rinse, patterned photoresist layer 698 is conventionally removed, such as with an ash plus a solvent clean.
- passivation layer 686 is formed on metal plate 697 rather than metal plate 684 .
- One advantage of the second variation is that step coverage issues associated with depositing aluminum copper and a patterned photoresist layer over the 14 ⁇ m step of patterned CMUT membrane 662 are eliminated.
- FIGS. 7A-7B show views that illustrate an example of a CMUT 700 in accordance with an alternate embodiment of the present invention.
- FIG. 7A shows a plan view of CMUT 700 .
- FIG. 7B shows a cross-sectional view taken along line 7 B- 7 B of FIG. 7A .
- CMUT 700 is similar to CMUT 400 and, as a result, utilizes the same reference numerals to designate the elements which are common to both CMUTS.
- CMUT 700 differs from CMUT 400 in that post structure 420 of CMUT 700 includes substrate contact openings 710 that extend completely through post structure 420 to expose semiconductor substrate 410 .
- CMUT 700 includes substrate bond pads 712 that lie within the substrate contact openings 710 to make electrical connections to semiconductor substrate 410 .
- passivation layer 442 of CMUT 700 has openings 714 that expose the substrate bond pads 712 .
- CMUT 700 includes a backside structure 714 that touches the bottom side 412 of semiconductor substrate 410 .
- Backside oxide structure 710 which is non-conductive and can optionally be removed in the same manner that thick oxide layer 617 is removed, is formed automatically at the same time that post structure 420 is formed.
- FIGS. 8A-8D are cross-sectional views illustrating an example of a method of forming a CMUT in accordance with an alternate embodiment of the present invention.
- the present method is the same as the method illustrated in FIGS. 6A-6G , up through the removal of patterned photoresist layer 660 .
- a patterned photoresist layer 810 is formed on post structure 624 and CMUT membrate 662 in a conventional manner.
- the exposed regions of post structure 624 are etched to form substrate contact openings 812 that expose silicon wafer 610 .
- the substrate contact openings 812 each has a diameter of 50 ⁇ m.
- a wet etchant is used, the resulting structure is rinsed following the etch.
- patterned photoresist layer 810 is conventionally removed, such as with acetone.
- the resulting structure is cleaned to remove organics, such as with a Piranha etch.
- metal layer 674 is deposited as before to touch post structure 624 and CMUT membrane 662 , and now also lines the openings 812 to touch the top surface 614 of silicon wafer 610 .
- a patterned photoresist layer 814 is formed on metal layer 674 in lieu of patterned photoresist layer 680 .
- metal layer 674 is wet etched to form metal plate 684 as before, and also form substrate bond pads 816 that lie within the substrate contact openings 812 to make electrical connections to silicon substrate 610 .
- the resulting structure is rinsed.
- patterned photoresist layer 814 is conventionally removed, such as with acetone.
- the method continues as before with the formation of passivation layer 686 , except that openings are also formed in passivation layer 686 to expose the substrate bond pads 816 as the same time that the opening, like opening 446 in FIG. 4A , is formed to expose the bond pad region on metal plate 684 .
- the formation of bond pad structure 692 is omitted, and the removal of thick oxide layer 617 is optionally omitted.
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Abstract
A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer.
Description
- 1. Field of the Invention
- The present invention relates to CMUTS and, more particularly, to a low frequency CMUT with thick oxide.
- 2. Description of the Related Art
- A capacitive micromachined ultrasonic transducer (CMUT) is a semiconductor-based ultrasonic transducer that utilizes a change in capacitance to convert received ultrasonic waves into an electrical signal, and to convert an alternating electrical signal into transmitted ultrasonic waves.
-
FIGS. 1A-1B show views that illustrate an example of a prior-art CMUT 100.FIG. 1A shows a plan view ofCMUT 100, whileFIG. 1B shows a cross-sectional view taken alongline 1B-1B ofFIG. 1A . As shown inFIGS. 1A-1B , CMUT 100 includes a conventionally-formedsemiconductor substrate 110, and apost oxide structure 112 that touches the top surface ofsemiconductor substrate 110.Post oxide structure 112, in turn, hassubstrate contact openings 114 that extend completely throughpost oxide structure 112 to exposesemiconductor substrate 110. - As further shown in
FIGS. 1A-1B ,CMUT 100 includes anon-conductive structure 116 that touches the top surface ofsemiconductor substrate 110, and aconductive structure 120 that touches the top surface ofpost oxide structure 112 and lies overnon-conductive structure 116 to form a vacuum-sealedcavity 122. In the present example,conductive structure 120 includes asemiconductor structure 124 such as, for example, single crystal silicon, and anoverlying metal structure 126, such as an aluminum copper plate. - In addition,
CMUT 100 includessubstrate bond pads 130 that lie within thesubstrate contact openings 114 to make electrical connections tosemiconductor substrate 110, and apassivation layer 132 that touches and lies overpost oxide structure 112,conductive structure 120, and thesubstrate bond pads 130.Passivation layer 132 has substratebond pad openings 134 that expose thesubstrate bond pads 130, and aconductor opening 136 that exposes a region ofconductive structure 120 which functions as a bond pad. Further,CMUT 100 has anacoustic dampening structure 140 that touches the bottom surface ofsemiconductor substrate 110. - In operation, a first bias voltage V1 is placed on
semiconductor substrate 110, which functions as a first capacitor plate, and a second bias voltage V2 is placed onconductive structure 120, which functions as second capacitor plate. Thus, the voltage across the capacitor plates lies across vacuum-sealedcavity 122. When used as a receiver, an ultrasonic wave causesconductive structure 120 to vibrate. The vibration varies the capacitance across the first and second capacitor plates, thereby generating an electrical signal that varies as the capacitance varies. - When used as a transmitter, an alternating electrical signal applied across the biased first and second capacitor plates causes
conductive structure 120 to vibrate which, in turn, transmits ultrasonic waves. The rate or frequency at whichconductive structure 120 vibrates depends on the volume of vacuum-sealedcavity 122, and the stiffness ofconductive structure 120. - In addition to transmitting ultrasonic waves outward, ultrasonic waves are also transmitted backward towards the bottom surface of
semiconductor substrate 110. These backward ultrasonic waves can resonate withinsemiconductor substrate 110 depending on the thickness ofsemiconductor substrate 110 and the frequency of operation, and can interfere with the quality of the resultant image.Acoustic dampening structure 140 absorbs and dampens the ultrasonic waves insemiconductor substrate 110. -
FIGS. 2A-2B show views that illustrate an example of a prior-art CMUT array 200.FIG. 2A shows a plan view ofarray 200, whileFIG. 2B shows a cross-sectional view taken alongline 2B-2B ofFIG. 2A . As shown in theFIGS. 2A-2B example,CMUT array 200 includes threeCMUTS 100 in a single row. -
FIGS. 3A-3N show cross-sectional views that illustrate an example of a prior-art method of forming a CMUT. As shown inFIG. 3A , the method utilizes a conventionally-formed single-crystal silicon wafer 310.Silicon wafer 310 has rows and columns of die-sized regions, and one or more CMUTS can be simultaneously formed in each die-sized region. For simplicity,FIGS. 3A-3N illustrate the formation of a single CMUT. - As further shown in
FIG. 3A , the method begins by forming apost oxide structure 312 on the top surface ofsilicon wafer 310 using the well-known local oxidation of silicon (LOCOS) process. The LOCOS process also forms abackside oxide structure 314 that touches the bottom surface ofsilicon wafer 310 at the same time. Following this, as shown inFIG. 3B , acell oxide layer 316 is grown on the exposed regions of the top surface ofsilicon wafer 310. - After
cell oxide layer 316 has been formed, as shown inFIG. 3C , a silicon-on-oxide (SOI)wafer 320 is fusion bonded to the top surface ofpost oxide structure 312 to form acavity 322. SOIwafer 320 has ahandle wafer 324, aninsulation layer 326 that touches handle wafer 324, and a single-crystalsilicon substrate structure 328.Substrate structure 328, in turn, has a first surface that touchesinsulation layer 326, and a second surface that touchespost oxide structure 312. -
Cavity 322, in turn, has a depth that is measured vertically from the top surface ofcell oxide layer 316 to the second surface ofsubstrate structure 328. The thickness ofcell oxide layer 316 defines the position of the top surface ofcell oxide layer 316. In addition, the height ofpost oxide structure 312 over the top surface ofsilicon wafer 310 defines the position of the second surface ofsubstrate structure 328. - The thickness of
cell oxide layer 316 is relatively small compared to the height ofpost oxide structure 312 over the top surface ofsilicon wafer 310. As a result, the depth ofcavity 322 is substantially defined by the height ofpost oxide structure 312 over the top surface ofsilicon wafer 310. In addition,substrate structure 328 ofSOI wafer 320 is fusion bonded to the top surface ofpost oxide structure 312 ofsilicon wafer 310 in a vacuum tovacuum seal cavity 322. - After
substrate structure 328 has been fusion bonded to postoxide structure 312, as shown inFIG. 3D ,handle wafer 324 is removed in a conventional manner, followed by the conventional removal ofinsulation layer 326. Next, as shown inFIG. 3E , a patternedphotoresist layer 330 is formed on the first surface ofsubstrate structure 328. Once patternedphotoresist layer 330 has been formed, as shown inFIG. 3F , the exposed region ofsubstrate structure 328 is etched to form aCMUT membrane 332. Patternedphotoresist layer 330 is then removed in a conventional manner. - As shown in
FIG. 3G , after the removal ofphotoresist layer 330, a patternedphotoresist layer 340 is formed onpost oxide structure 312 andCMUT membrane 332. Once patternedphotoresist layer 340 has been formed, as shown inFIG. 3H , the exposed regions ofpost oxide structure 312 are etched untilsilicon wafer 310 has been exposed. Patternedphotoresist layer 340 is then removed in a conventional manner. - Following the removal of
photoresist layer 340, as shown inFIG. 3I , ametal layer 342, such as a layer of aluminum copper, is deposited to touchsilicon wafer 310, postoxide structure 312, andCMUT membrane 332. After this, a patternedphotoresist layer 350 is formed onmetal layer 342. - Next, as shown in
FIG. 3J , the exposed region ofmetal layer 342 is etched to formsemiconductor bond pads 352 that extend throughpost oxide structure 312 to touchsilicon wafer 310, and ametal plate 354 that touches the top surface ofCMUT membrane 332. Patternedphotoresist layer 350 is then removed in a conventional manner. - As shown in
FIG. 3K , after patternedphotoresist layer 350 has been removed, apassivation layer 356 is formed to touchpost oxide structure 312,CMUT membrane 332, thebond pads 352, andmetal plate 354. Oncepassivation layer 356 has been formed, a patternedphotoresist layer 360 is formed onpassivation layer 356. - After this, as shown in
FIG. 3L , the exposed regions ofpassivation layer 356 are etched to form openings that expose thesemiconductor bond pads 352, and an opening, like opening 136 inFIG. 1A , that exposes a bond pad region ofmetal plate 354. As shown inFIG. 3M , patternedphotoresist layer 360 is then removed in a conventional manner. - Next, the resulting structure is flipped over for processing, and
backside oxide structure 314 is removed in a conventional manner. For example,backside oxide structure 314 can be removed using chemical mechanical polishing. Alternately,backside oxide structure 314 can be removed using a single-sided wet etch, such as a SEZ etch. - Following the removal of
backside oxide structure 314, an acoustic dampingstructure 362, such as a tungsten epoxy mixture, is deposited onto the bottom side ofsilicon wafer 310 to form, as shown inFIG. 3N , aCMUT 364.Silicon wafer 310 is then diced to form a number of individual die that each has one ormore CMUTS 364. - In the present example,
cavity 322 has a depth of approximately 0.2 μm and a diameter of approximately 36.0 μm. In addition,CMUT membrane 332,metal plate 354, and the overlying region ofpassivation layer 356 vibrate at frequencies of approximately 10-20 MHz. These frequencies are suitable for contact or near contact body imaging applications, like echo cardiograms, but are not suitable for airborne ultrasound applications where, for example, the object to be detected, such as the hand motions of a person playing a game, is one or more meters away. - Instead, airborne ultrasound applications require much lower frequencies, such as 100-200 KHz. If
CMUT 364 were scaled up in size to operate at these lower frequencies, thenCMUT 364 would require a larger cell diameter (e.g. increasing from about 36 μm to about 1 mm-2 mm), a thicker CMUT membrane 332 (e.g. increasing from 2 μm to 5 μm-40 μm), and a deeper cell cavity 322 (e.g. increasing from 0.2 μm to 1 μm-12 μm). A deeper cell cavity is required to accommodate the atmospheric deflection ofCMUT membrane 332, which can be on the order of several microns. For proper CMUT operation,CMUT membrane 332 should not touch the bottom surface ofcavity 322, but rather be a fixed distance of one or more microns above the bottom surface ofcavity 322. - Since the height of
post oxide structure 312 substantially determines the depth ofcavity 322, scaling upCMUT 364 requires thatpost oxide structure 312 have a height above the top surface ofsilicon wafer 310 of approximately 1 μm-12 μm, or a total thickness of 2 μm-24 μm. However, forming a post oxide structure with a thickness that exceeds approximately 5 μm (or heights that exceed 2.5 μm) is difficult to accomplish because the rate of oxide growth slows dramatically when the thickness of the post oxide structure approaches 5 μm. - As a result, it is difficult to scale up
CMUT 364 to accommodate these lower frequencies. Thus, there is a need for an approach to forming low frequency CMUTS for airborne ultrasonic applications. -
FIGS. 1A-1B are views illustrating an example of a prior-art CMUT 100.FIG. 1A is a plan view ofCMUT 100.FIG. 1B is a cross-sectional view taken alongline 1B-1B ofFIG. 1A . -
FIGS. 2A-2B are views illustrating an example of a prior-art CMUT array 200.FIG. 2A is a plan view ofarray 200.FIG. 2B is a cross-sectional view taken alongline 2B-2B ofFIG. 2A . -
FIGS. 3A-3N are cross-sectional views illustrating an example of a prior-art method of forming a CMUT. -
FIGS. 4A-4B are views illustrating an example of aCMUT 400 in accordance with the present invention.FIG. 4A is a plan view ofCMUT 400.FIG. 4B is a cross-sectional view taken alongline 4B-4B ofFIG. 4A . -
FIGS. 5A-5B are views illustrating an example of aCMUT array 500 in accordance with the present invention.FIG. 5A is a plan view ofarray 500.FIG. 5B is a cross-sectional view taken alongline 5B-5B ofFIG. 5A . -
FIGS. 6A-6R are cross-sectional views illustrating an example of a method of forming a CMUT in accordance with the present invention. -
FIGS. 7A-7B are views illustrating an example of aCMUT 700 in accordance with an alternate embodiment of the present invention.FIG. 7A is a plan view ofCMUT 700.FIG. 7B is a cross-sectional view taken alongline 7B-7B ofFIG. 7A . -
FIGS. 8A-8D are cross-sectional views illustrating an example of a method of forming a CMUT in accordance with an alternate embodiment of the present invention. -
FIGS. 4A-4B show views that illustrate an example of aCMUT 400 in accordance with the present invention.FIG. 4A shows a plan view ofCMUT 400, whileFIG. 4B shows a cross-sectional view taken alongline 4B-4B ofFIG. 4A . As described in greater detail below,CMUT 400 utilizes thick oxide to increase the size of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. - As shown in
FIGS. 4A-4B ,CMUT 400 includes asemiconductor substrate 410 that has abottom surface 412 and atop surface 414, where thetop surface 414 lies in aplane 415.Semiconductor substrate 410, which is conductive, can be implemented with, for example, single-crystal silicon. - In addition,
CMUT 400 also includes apost structure 420 that touches thetop surface 414 ofsemiconductor substrate 410 such that no portion ofpost structure 420 lies belowplane 415, and no non-conductive region lies belowplane 415 and touches the bottom surface ofpost structure 420. Further,post structure 420, which is non-conductive, laterally surrounds acell region 422 of thetop surface 414 ofsemiconductor substrate 410. In addition, no conductive structure extends throughpost structure 420. - As further shown in
FIGS. 4A-4B ,CMUT 400 includes anon-conductive structure 424 that touches thecell region 422 of thetop surface 414 ofsemiconductor substrate 410. In addition,non-conductive structure 424, which can be implemented with a layer of oxide, is laterally surrounded and touched bypost structure 420. -
CMUT 400 also includes aconductive structure 430 that touches the top surface ofpost structure 420, and lies directly vertically overnon-conductive structure 424 to form acavity 432 that lies vertically betweennon-conductive structure 424 andconductive structure 430. In the present example,conductive structure 430 includes asemiconductor structure 434 such as, for example, single-crystal silicon, and anoverlying metal structure 436, such as an aluminum copper plate. - As further shown in
FIGS. 4A-4B ,CMUT 400 includes apassivation layer 442 that touches and lies overpost structure 420 andconductive structure 430.Passivation layer 442, which is non-conductive, has aconductive opening 446 that exposes a region ofmetal structure 436 that functions as a bond pad. In addition,CMUT 400 includes a metalbond pad structure 450 that touches thebottom surface 412 ofsemiconductor substrate 410. - In operation, a first bias voltage V1 is placed on
semiconductor substrate 410, which functions as a first capacitor plate, and a second bias voltage V2 is placed onconductive structure 430, which functions as second capacitor plate. Thus, the voltage across the capacitor plates lies vertically acrosscavity 432. - When used as a receiver, an ultrasonic wave causes
conductive structure 430 to vibrate. The vibration varies the capacitance across the first and second capacitor plates, thereby generating an electrical signal that varies as the capacitance varies. When used as a transmitter, an alternating electrical signal applied across the biased first and second capacitor plates causesconductive structure 430 to vibrate which, in turn, transmits ultrasonic waves. - One of the advantages of
CMUT 400 is that the volume ofcavity 432 is substantially greater than the volume ofcavity 122 becausepost structure 420 has a height above the top surface ofsemiconductor substrate 410 that is significantly larger that the height ofpost oxide structure 112 above the top surface ofsemiconductor substrate 110. The increased volume allowsCMUT 400 to accommodate the low frequency signals required by ultrasonic airborne imaging applications. -
FIGS. 5A-5B show views that illustrate an example of aCMUT array 500 in accordance with the present invention.FIG. 5A shows a plan view ofarray 500, whileFIG. 5B shows a cross-sectional view taken alongline 5B-5B ofFIG. 5A . As shown in theFIGS. 5A-5B example,CMUT array 500 includes three CMUTS 400 in a single row. In addition, in the present example, laterallyadjacent CMUT membranes 434 are separated by 50 μm. -
FIGS. 6A-6R show cross-sectional views that illustrate an example of a method of forming a CMUT in accordance with the present invention. As shown inFIG. 6A , the method utilizes a conventionally-formed single-crystal silicon wafer 610 that has abottom surface 612 and atop surface 614, where thetop surface 614 lies in aplane 615. In the present example,silicon wafer 610 has a low resistivity (e.g., 0.1 Ω-cm).Silicon wafer 610 has rows and columns of die-sized regions, and one or more CMUTS can be simultaneously formed in each die-sized region. For simplicity,FIGS. 6A-6R illustrate the formation of a single CMUT. - The method begins by forming a patterned photoresist layer on the
top surface 614 ofsilicon wafer 610 in a conventional manner. After the patterned photoresist layer has been formed, thetop surface 614 ofsilicon wafer 610 is etched for a predefined time to form two or more front side alignment marks. - If a wet etchant is used, the resulting structure is rinsed following the etch. After the rinse, the patterned photoresist layer is conventionally removed, such as with an ash plus a solvent clean. Following the removal of the patterned photoresist layer, the resulting structure is cleaned to remove organics, such as with a Piranha etch (e.g., using a solution of 50H2SO4:1H2O2 @ 120° C. removes approximately 240 nm/minute).
- Next, the method continues by forming a post structure on the
top surface 614 ofsilicon wafer 610. As illustrated inFIG. 6A , the post structure, which is non-conductive, is first formed by growing athick oxide layer 616 on thetop surface 614 ofsilicon wafer 610 using high-pressure oxidization (HIPOX). In addition, athick oxide layer 617 is simultaneously grown on thebottom surface 612 ofsilicon wafer 610. - For example,
thick oxide layers thick oxide layers photoresist layer 618 is formed onthick oxide layer 616 in a conventional manner. - Following the formation of patterned
photoresist layer 618, as further shown inFIG. 6B , the exposed region ofthick oxide layer 616 is etched to form anopening 620 approximately 1.12 mm wide that exposes acell region 622 of thetop surface 614 ofsilicon wafer 610, and form apost structure 624. - For example, a non-polymerizing plasma etch can be used to etch an opening through approximately 4.65 μm of the approximately 5.15 μm
thick oxide layer 616. In this example, the slope of the side wall at the end of the non-polymerizing etch is approximately 80° (i.e., the opening is slightly larger at the top than at the bottom), and results from the natural erosion of patternedphotoresist layer 618. - Following this, the remaining approximately 0.5 μm of
thick oxide layer 616 is removed without damaging thecell region 622 of thetop surface 614 ofsilicon wafer 610 using, for example, a wet etchant that is highly or completely selective to silicon. After this, the resulting structure is rinsed, and patternedphotoresist layer 618 is conventionally removed, such as with an ash plus a solvent clean. The resulting structure is then subjected to a conventional pre-oxidization clean. - The top surface of
thick oxide layer 616, and thereby the top surface ofpost structure 624, are substantially planar. In addition, the surface roughness ofthick oxide layer 616, and thereby the surface roughness ofpost structure 624, must be controlled to provide a good bonding surface. In the present example, the surface roughness is less than 3 Å RMS. - Following this, as shown in
FIG. 6C , acell oxide layer 634 is grown on thecell region 622 of thetop surface 614 ofsilicon wafer 610 in a conventional manner to have a thickness of, for example, 0.3 μm. Aftercell oxide layer 634 has been formed, as shown inFIG. 6D , a silicon-on-oxide (SOI)wafer 640 is bonded to the top surface ofpost structure 624 to form acavity 642. - In the present example,
SOI wafer 640 is vacuum fusion bonded to poststructure 624 ofsilicon wafer 610 in a conventional manner so thatcavity 624 has a vacuum, followed by an anneal to ensure reliable bonding strength. The anneal can be performed with a temperature in the range of 400° C. to 1050° C. In the present example, the anneal is performed at 1050° C. immediately after the bonding for approximately four hours. Alternately, other bonding approaches can also be used. -
SOI wafer 640 has ahandle wafer 644, aninsulation layer 646 that toucheshandle wafer 644, and a single-crystalsilicon substrate structure 648.Substrate structure 648, in turn, has a first substantially-planar surface that touchesinsulation layer 646, and a second substantially-planar surface that touchespost structure 624. In the present example,insulation layer 646 has a thickness of 1.1 μm, andsubstrate structure 648 has a thickness of 14 μm. - As shown in
FIG. 6E , aftersubstrate structure 648 has been bonded to poststructure 624, handlewafer 644 is removed in a conventional manner. For example, handlewafer 644 can be removed by first grindinghandle wafer 644 down to a thickness of approximately 150 μm. In the present example, a four hour anneal at 1050° C. is next performed, followed by a wet etch, such as with a solution of KOH or TMAH, to remove the remainder ofhandle wafer 644. - After
handle wafer 644 has been removed,insulation layer 646 is removed in a conventional manner. For example,insulation layer 646 can be removed using a wet HF etchant that is highly selective to silicon, or chemical mechanical polishing. The wet etch ofinsulation layer 646 could be performed using a single-sided wet etch, such as a SEZ etch by SEZ Austria GmbH, Draubodenweg 29, A-9500 Villach, Austria. - Once
insulation layer 646 has been removed, the center region ofsubstrate structure 648 is pulled towards the bottom surface ofcavity 642 by approximately 4 μm due to the vacuum incavity 642 and the effects of atmospheric pressure. To avoid the possibility thatsubstrate structure 648 could be bonded to the top surface ofnon-conductive structure 634 during the second four hour anneal, the second four hour anneal is performed prior to the wet etch of the final 150 μm Si substrate remaining after the initial back grind process step, and the subsequent wet etch ofinsulation layer 646. - Following the removal of
insulation layer 646, a patterned photoresist layer is formed on the first surface ofsubstrate structure 648 in a conventional manner. Once the patterned photoresist layer has been formed, the exposed regions ofsubstrate structure 648 are etched, such as with a plasma etch, to expose the alignment marks. - Alternately, a conventional Bosch etch can be used to expose the alignment marks. Since post structure 624 (which is approximately 5.15 μm thick and lies over the alignment marks) is transparent,
only substrate structure 648, which is approximately 14 μm thick, needs to be removed. After the etch, the patterned photoresist layer is conventionally removed, such as with an ash plus a solvent. Following the removal of the patterned photoresist layer, the resulting structure is cleaned to remove organics, such as with a Piranha etch. - As shown in
FIG. 6F , after cleaning following the removal of the patterned photoresist layer used to expose the alignment marks, a patternedphotoresist layer 660 is formed on the first surface ofsubstrate structure 648 in a conventional manner. Once patternedphotoresist layer 660 has been formed, as shown inFIG. 6G , the exposed regions ofsubstrate structure 648 are etched to form aCMUT membrane 662 that lies directly vertically over thecell region 622 of thetop surface 414 ofsilicon wafer 610. - For example, a conventional Bosch etch with a short Bosch cycle to minimize side wall scalloping can be used to
pattern CMUT membrane 662 without damagingCMUT membrane 662. After the etch, patternedphotoresist layer 660 is conventionally removed, such as with an ash plus a solvent clean. Following the removal of patternedphotoresist layer 660, the resulting structure is cleaned to remove organics, such as with a Piranha etch. - As shown in
FIG. 6H , after cleaning following the removal of patternedphotoresist layer 660, ametal layer 674, such as a layer of aluminum copper, is deposited to touchpost structure 624 andCMUT membrane 662. In the present example,metal layer 674 is formed to have a thickness of 1 μm. Next, a patternedphotoresist layer 680 is formed onmetal layer 674 in a conventional manner. - As shown in
FIG. 6I , after patternedphotoresist layer 680 has been formed, the exposed region ofmetal layer 674 is wet etched to form ametal plate 684 that touches the top surface ofCMUT membrane 662. In the present example,metal plate 684 has a minimum width of approximately 50 μm. Following the etch, the resulting structure is rinsed. After the rinse, patternedphotoresist layer 680 is conventionally removed, such as with an ash plus a solvent clean. - After cleaning following the removal of patterned
photoresist layer 680, as shown inFIG. 6J , apassivation layer 686, such as a layer of plasma oxide approximately 0.6 μm thick and an overlying layer of plasma nitride approximately 0.6 μm thick, is deposited onpost structure 624,CMUT membrane 662, andmetal plate 684. Next, a patternedphotoresist layer 690 is formed onpassivation layer 686 in a conventional manner. - After patterned
photoresist layer 690 has been formed, the exposed region ofpassivation layer 686 is wet etched to form an opening, like opening 446 shown inFIG. 4A , that exposes a bond pad region onmetal plate 684. Following the etch, the resulting structure is rinsed. After the rinse, patternedphotoresist layer 690 is conventionally removed, such as with an ash plus a solvent clean. In the present example, after the removal of patternedphotoresist layer 690, the resulting structure is alloyed at, for example, 400° C. in an ambient of N2+H2. - Next, as shown in
FIG. 6K , the resulting structure is flipped over for processing, andthick oxide layer 617 is removed in a conventional manner. For example,thick oxide layer 617 can be removed using chemical mechanical polishing. Alternately,thick oxide layer 617 can be removed using a single-sided wet etch, such as a SEZ etch. - Following the removal of
thick oxide layer 617, ametal layer 692, such as 100 Å of titanium and 1 μm of aluminum copper, is deposited onto thebottom surface 612 ofsilicon wafer 610 to form aCMUT 694.Metal layer 692 can also be implemented with other common back side metallization stacks, such as TiNiAg, TiNiAu, CRAu, or TiAu.Silicon wafer 610 is then diced to form a number of individual die that each has one ormore CMUTS 694. - In an alternate method, as shown in
FIG. 6L , after the removal ofinsulation layer 646 and prior to the formation of patternedphotoresist layer 660, ametal layer 695, such as a layer of aluminum copper, is deposited to touch the top surface ofsubstrate structure 648. In the present example,metal layer 695 is formed to have a thickness of 1 μm. Next, a patternedphotoresist layer 696 is formed onmetal layer 695 in a conventional manner. - As shown in
FIG. 6M , after patternedphotoresist layer 696 has been formed, the exposed region ofmetal layer 695 is wet etched to form ametal plate 697 that touches the top surface ofsubstrate structure 648. In the present example,metal plate 697 has a minimum width of approximately 50 μm. Following the etch, the resulting structure is rinsed. - In a first variation, as shown in
FIG. 6N , after the rinse, the exposed regions ofsubstrate structure 648 are next etched to formCMUT membrane 662. After the etch has been completed, patternedphotoresist layer 696 is conventionally removed, such as with an ash plus a solvent clean. - As shown in
FIG. 6O , following the removal of patternedphotoresist layer 696, the method continues as described above with the formation ofpassivation layer 686, except thatpassivation layer 686 is formed onmetal plate 697 rather thanmetal plate 684. One advantage of the first variation is that the first variation eliminates one masking step. However, a dedicated silicon etch tool may be required to etch silicon with the exposed aluminum copper ofmetal plate 697. - In a second variation, as shown in
FIG. 6P , following the formation ofmetal plate 697, the resulting structure is rinsed. After the rinse, patternedphotoresist layer 696 is conventionally removed, such as with an ash plus a solvent clean. Following the removal of patternedphotoresist layer 696, a patternedphotoresist layer 698 is formed onsubstrate structure 648 andmetal plate 697 in a conventional manner. - As shown in
FIG. 6Q , after patternedphotoresist layer 698 has been formed, the exposed region ofsubstrate structure 648 is etched to formCMUT membrane 662. Following the etch, the resulting structure is rinsed. After the rinse, patternedphotoresist layer 698 is conventionally removed, such as with an ash plus a solvent clean. - As shown in
FIG. 6R , following the removal of patternedphotoresist layer 698, the method continues as described above with the formation ofpassivation layer 686, except thatpassivation layer 686 is formed onmetal plate 697 rather thanmetal plate 684. One advantage of the second variation is that step coverage issues associated with depositing aluminum copper and a patterned photoresist layer over the 14 μm step of patternedCMUT membrane 662 are eliminated. -
FIGS. 7A-7B show views that illustrate an example of aCMUT 700 in accordance with an alternate embodiment of the present invention.FIG. 7A shows a plan view ofCMUT 700.FIG. 7B shows a cross-sectional view taken alongline 7B-7B ofFIG. 7A .CMUT 700 is similar toCMUT 400 and, as a result, utilizes the same reference numerals to designate the elements which are common to both CMUTS. - As shown in
FIGS. 7A-7B ,CMUT 700 differs fromCMUT 400 in thatpost structure 420 ofCMUT 700 includessubstrate contact openings 710 that extend completely throughpost structure 420 to exposesemiconductor substrate 410. In addition,CMUT 700 includessubstrate bond pads 712 that lie within thesubstrate contact openings 710 to make electrical connections tosemiconductor substrate 410. Further,passivation layer 442 ofCMUT 700 hasopenings 714 that expose thesubstrate bond pads 712. - In addition,
CMUT 700 includes abackside structure 714 that touches thebottom side 412 ofsemiconductor substrate 410.Backside oxide structure 710, which is non-conductive and can optionally be removed in the same manner thatthick oxide layer 617 is removed, is formed automatically at the same time that poststructure 420 is formed. -
FIGS. 8A-8D are cross-sectional views illustrating an example of a method of forming a CMUT in accordance with an alternate embodiment of the present invention. The present method is the same as the method illustrated inFIGS. 6A-6G , up through the removal of patternedphotoresist layer 660. As shown inFIG. 8A , after the cleaning following the removal of patternedphotoresist layer 660, a patternedphotoresist layer 810 is formed onpost structure 624 andCMUT membrate 662 in a conventional manner. - Once patterned
photoresist layer 810 has been formed, as shown inFIG. 8B , the exposed regions ofpost structure 624 are etched to formsubstrate contact openings 812 that exposesilicon wafer 610. In the present example, thesubstrate contact openings 812 each has a diameter of 50 μm. If a wet etchant is used, the resulting structure is rinsed following the etch. After the rinse, patternedphotoresist layer 810 is conventionally removed, such as with acetone. Following the removal of patternedphotoresist layer 810, the resulting structure is cleaned to remove organics, such as with a Piranha etch. - As shown in
FIG. 8C , after cleaning following the removal of patternedphotoresist layer 810,metal layer 674 is deposited as before to touchpost structure 624 andCMUT membrane 662, and now also lines theopenings 812 to touch thetop surface 614 ofsilicon wafer 610. Next, a patternedphotoresist layer 814 is formed onmetal layer 674 in lieu of patternedphotoresist layer 680. - As shown in
FIG. 8D , after patternedphotoresist layer 814 has been formed, the exposed region ofmetal layer 674 is wet etched to formmetal plate 684 as before, and also formsubstrate bond pads 816 that lie within thesubstrate contact openings 812 to make electrical connections tosilicon substrate 610. - Following the etch, the resulting structure is rinsed. After the rinse, patterned
photoresist layer 814 is conventionally removed, such as with acetone. After the removal of patternedphotoresist layer 814, the method continues as before with the formation ofpassivation layer 686, except that openings are also formed inpassivation layer 686 to expose thesubstrate bond pads 816 as the same time that the opening, like opening 446 inFIG. 4A , is formed to expose the bond pad region onmetal plate 684. In addition, the formation ofbond pad structure 692 is omitted, and the removal ofthick oxide layer 617 is optionally omitted. - It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.
Claims (20)
1. (canceled)
2. (canceled)
3. (canceled)
4. (canceled)
5. (canceled)
6. (canceled)
7. (canceled)
8. (canceled)
9. (canceled)
10. (canceled)
11. A method of forming a semiconductor transducer comprising:
providing semiconductor substrate having top and bottom surfaces wherein the top surface lies in a plane;
growing approximately a 5.15 micrometer thick oxide layer on both the top and bottom surfaces of the semiconductor wafer using a high-pressure oxidation (HIPOX) process;
wherein the 5.15 micrometer thick oxide layer is grown at a temperature in range of 900° C. to 1200° C. with an operating pressure of 10 to 20 atmospheres;
forming a patterned photoresist layer on the thick oxide layer on the top surface of the semiconductor substrate;
etching the thick oxide layer, exposing the top surface of the semiconductor substrate and forming a post structure on the top surface of the semiconductor substrate from the thick oxide layer, wherein the post structure having a top surface, being non-conductive, and laterally surrounding a cell region of the top surface of the substrate has no portion of the post structure lying below the plane of the top surface of the semiconductor substrate;
wherein etching the thick oxide layer comprises:
etching approximately 4.65 micrometers of the approximately 5.15 micrometer thick layer utilizing a non-polymerizing plasma etch, wherein the slope of the side wall at the end of the non-polymerizing etch is approximately 80°, making the opening slightly larger at the top than at the bottom of the thick oxide layer; and
removing the remaining approximately 0.5 micrometers of the thick oxide layer with a wet etchant that is highly or completely selective to silicon, thus leaving the cell region on the top surface of the semiconductor substrate without damage;
forming a non-conductive structure that touches the cell region of the top surface of the semiconductor substrate; and
forming a conductive structure that touches the top surface of the post structure and lies directly vertically over the non-conductive structure to form a cavity that lies vertically between the non-conductive structure and the conductive structure.
12. The method of claim 11 wherein the post structure laterally surrounds and touches the non-conductive structure.
13. The method of claim 12 wherein the cavity is under a vacuum.
14. The method of claim 13 and further comprising forming a metal bond pad structure that touches the bottom surface of the substrate.
15. The method of claim 14 wherein no conductive structure extends through the post structure.
16. The method of claim 15 wherein the conductive structure includes:
a single-crystal silicon structure; and
a metal plate that touches the single-crystal silicon structure.
17. The method of claim 13 and further comprising forming a bond pad opening that extends completely through the post structure to expose the substrate.
18. The method of claim 17 and further comprising forming a conductive bond pad structure that lies in the bond pad opening to touch the substrate.
19. The method of claim 18 wherein the conductive structure includes:
a single-crystal silicon structure; and
a metal plate that touches the single-crystal silicon structure.
20. The method of claim 12 wherein no non-conductive structure lies directly vertically between the cell region of the top surface of the substrate and the bottom surface of the substrate.
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US20160340178A1 (en) * | 2015-05-20 | 2016-11-24 | uBeam Inc. | Membrane bonding with photoresist |
US10058892B2 (en) | 2015-05-20 | 2018-08-28 | uBeam Inc. | Membrane bonding |
US10315224B2 (en) | 2015-05-20 | 2019-06-11 | uBeam Inc. | Ultrasonic transducer |
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US20130331705A1 (en) * | 2011-03-22 | 2013-12-12 | Koninklijke Philips Electronics N.V. | Ultrasonic cmut with suppressed acoustic coupling to the substrate |
US9219044B2 (en) * | 2013-11-18 | 2015-12-22 | Applied Materials, Inc. | Patterned photoresist to attach a carrier wafer to a silicon device wafer |
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US4837176A (en) * | 1987-01-30 | 1989-06-06 | Motorola Inc. | Integrated circuit structures having polycrystalline electrode contacts and process |
US5894452A (en) * | 1994-10-21 | 1999-04-13 | The Board Of Trustees Of The Leland Stanford Junior University | Microfabricated ultrasonic immersion transducer |
US5706565A (en) * | 1996-09-03 | 1998-01-13 | Delco Electronics Corporation | Method for making an all-silicon capacitive pressure sensor |
JP4398126B2 (en) * | 2001-12-06 | 2010-01-13 | ケイ・エス・ティ・ワ−ルド株式会社 | Method for producing silicon dioxide film |
US6958255B2 (en) * | 2002-08-08 | 2005-10-25 | The Board Of Trustees Of The Leland Stanford Junior University | Micromachined ultrasonic transducers and method of fabrication |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20160340178A1 (en) * | 2015-05-20 | 2016-11-24 | uBeam Inc. | Membrane bonding with photoresist |
US10058892B2 (en) | 2015-05-20 | 2018-08-28 | uBeam Inc. | Membrane bonding |
US10065854B2 (en) * | 2015-05-20 | 2018-09-04 | uBeam Inc. | Membrane bonding with photoresist |
US10252908B2 (en) | 2015-05-20 | 2019-04-09 | uBeam Inc. | Membrane bonding with photoresist |
US10315224B2 (en) | 2015-05-20 | 2019-06-11 | uBeam Inc. | Ultrasonic transducer |
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