US20130126949A1 - Mos device and method for fabricating the same - Google Patents

Mos device and method for fabricating the same Download PDF

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US20130126949A1
US20130126949A1 US13/299,044 US201113299044A US2013126949A1 US 20130126949 A1 US20130126949 A1 US 20130126949A1 US 201113299044 A US201113299044 A US 201113299044A US 2013126949 A1 US2013126949 A1 US 2013126949A1
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semiconductor compound
compound layers
layers
substrate
layer
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Chin-I Liao
I-Ming Lai
Chin-Cheng Chien
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Marlin Semiconductor Ltd
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United Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the present invention relates to a metal oxide semiconductor (MOS) device and a method for fabricating the same.
  • MOS metal oxide semiconductor
  • MOS transistor is one of the most common elements used in many different semiconductor devices, such as memories, image sensors or displays.
  • a typical MOS includes a silicon oxide dielectric layer, a gate conductive layer, and heavily doped source/drain contact regions. Along with decrease in linewidth of semiconductor devices, dimensions thereof are reduced. Due to the reduction in the gate width of the typical MOS, the channel length of the MOS is consequentially reduced.
  • an epitaxial growth rate of silicon germanium (SiGe), however, varies in accordance with different density of surrounding patterns of the device to be formed. Accordingly, the thickness of the resultant silicon germanium (SiGe) is non-uniform (i.e. so-called loading effects), and issues regarding mismatches of the device performance arise therefrom.
  • the present invention is directed to a MOS device, capable of enhancing turn-on currents and lessening turn-off currents, so that the mismatches of the device performance can be ameliorated.
  • the present invention is directed to a method for fabricating a MOS device, wherein alterations in the fabrication process can achieve enhancement of the turn-on currents, decrease in the turn-off currents, and improvement in the mismatches of the device performance.
  • a method for fabricating a MOS device of the present invention is described as follows. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers.
  • Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate.
  • the first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element.
  • the content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.
  • an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
  • the second semiconductor compound layers have a (311) facet.
  • the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
  • the epitaxial temperature of the second epitaxy growth process ranges between 650° C. and 680° C.
  • an epitaxial temperature of the first epitaxy growth process ranges between 630° C. and 660° C.
  • the method further includes performing a third epitaxy growth process before performing the first epitaxy growth process, so as to form a buffer layer in each of the recesses.
  • Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
  • the first epitaxy growth process finishes when a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 ⁇ to 100 ⁇ .
  • Another method for fabricating a MOS device of the present invention is described as follows. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed, so as to form a second semiconductor compound layer on each of the first semiconductor compound layers. The second semiconductor compound layers protrude from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.
  • the second epitaxy growth process includes a first growth stage and a second growth stage, wherein a growth rate of the second growth stage is less than a growth rate of the first growth stage.
  • the growth rate of the second epitaxy growth process is less than 80 ⁇ /100 sec.
  • the growth rate of the first growth stage is at least 2 times of the growth rate of the second growth stage in the second epitaxy growth process.
  • an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
  • the second semiconductor compound layers have a (311) facet.
  • the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
  • the method further includes performing a third epitaxy growth process before performing the first epitaxy growth process, so as to form a buffer layer in each of the recesses.
  • Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
  • the first epitaxy growth process finishes when a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 ⁇ to 100 ⁇ .
  • a MOS device of the present invention including a substrate, first semiconductor compound layers, and cap layers.
  • the substrate has two recesses therein.
  • the first semiconductor compound layers are disposed in the recesses.
  • Each of the cap layers includes a second semiconductor compound layer that is disposed on each of the first semiconductor compound layers and protrudes from a surface of the substrate.
  • An included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
  • the second semiconductor compound layers have a (311) facet.
  • the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
  • the MOS device further includes buffer layers, respectively disposed in the recesses and intervening between the substrate and the first semiconductor compound layers.
  • Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
  • a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 ⁇ to 100 ⁇ .
  • a thickness of the cap layers is 1/X to 1/Y times of a thickness of the first semiconductor compound layers.
  • the MOS device in this invention can enhance the turn-on currents and lessen the turn-off currents, thereby improving the mismatches of the device performance.
  • the fabricating method of the MOS device in this invention is capable of enhancing the turn-on currents, lessening the turn-off currents, and improving the mismatches of the device performance through modifications in the fabrication process.
  • FIGS. 1-7 depict, in a cross-sectional view, a method for fabricating a MOS device according to an embodiment of the present invention.
  • FIG. 8 illustrates a second epitaxy growth process for formation of cap layers according to an embodiment of the present invention.
  • FIGS. 1-7 depict, in a cross-sectional view, a method for fabricating a MOS device according to an embodiment of the present invention.
  • isolation structures 12 are formed in a substrate 10 , so as to define a first active area 14 a and a second active area 14 b.
  • the material of the substrate 10 includes semiconductor, such as silicon.
  • the material of the isolation structures 12 includes insulating material, such as silicon oxide.
  • the isolation structures 12 are, for example, formed by a shallow trench isolation (STI) method.
  • STI shallow trench isolation
  • Each stack structure 16 includes an insulating layer 18 , a conductor layer 20 and a hard mask layer 22 .
  • a width of the stack structures 16 is, for example, about 24 nm.
  • the insulating layers 18 may include a dielectric layer, a high-dielectric constant (K value greater than 4) material, a barrier layer, or combination thereof.
  • the dielectric layer is, for example, made of silicon oxide.
  • the high-K dielectric material is, for example, hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), or hafnium zirconium oxide (HfZrO).
  • the barrier layer is, for example, made of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or combination thereof.
  • the material of the conductor layers 20 can be monocrystalline silicon, undoped polysilicon, doped polysilicon, amorphous silicon, silicon germanium material, or combination thereof with a thickness of, for example, about 650 ⁇ .
  • the material of the hard mask layers 22 can be silicon oxide, silicon nitride, silicon carbide or silicon oxynitride with, for example, hundreds of angstroms in thickness.
  • the formation of the stack structures 16 can be carried out by forming an insulating material layer, a conductor material layer and a hard mask material layer, and then patterning the foregoing layers through lithography and etching processes.
  • first spacers 24 are formed on respective sidewalls of each stack structure 16 .
  • the material of the first spacers 24 are, for example, silicon nitride.
  • ion implantation processes are conducted individually, so that a lightly doped drain (LDD) 25 a and an LDD 25 b are formed respectively in the first active area 14 a and in the second active area 14 b.
  • LDD lightly doped drain
  • dopants implanted into the LDD 25 a may be P-type
  • an NMOS is to be formed on the second active area 14 b
  • dopants implanted into the LDD 25 b may be N-type.
  • dopants implanted into the LDD 25 a may be N-type; when the PMOS device is to be formed on the second active area 14 b, dopants implanted into the LDD 25 b may be P-type.
  • the P-type dopants can be boron or BF 2 + , while the N-type dopants can be phosphorous or arsenic.
  • a block layer 26 is formed on the substrate 10 .
  • the block layer 26 is, for example, made of silicon nitride.
  • a mask layer 28 is then formed on the first active area 14 a.
  • the mask layer 28 is, for example, made of photoresist, and the formation thereof can be implemented by the lithography process.
  • an anisotropic etching process is performed using the mask layer 28 as an etching mask, and thus, a portion of the block layer 26 is removed, so as to form second spacers 30 a on the respective sidewalls of the stack structure 16 on the first active area 14 a.
  • a portion of the substrate 10 in the first active area 14 a is removed by dry or wet etching or combination thereof, so that two recesses 32 are formed in the substrate 10 at both sides of the second spacers 30 a.
  • a depth of each recess 32 is, for example, about hundreds of angstroms.
  • the recesses 32 can have diamond-shaped profiles or rectangle-shaped profiles, and are not particularly limited by the present invention.
  • the mask layer 28 is removed, so that the block layer 26 on the second active area 14 b is exposed.
  • a semiconductor compound layer 33 is then formed in each of the recesses 32 .
  • the fabricating method of the semiconductor compound layers 33 includes performing a first epitaxy growth process to form a first semiconductor compound layer 34 in each recess 32 , and then performing a second epitaxy growth process to form a cap layer 36 on each first semiconductor compound layer 34 .
  • Each cap layer 36 includes a second semiconductor compound layer that may protrude from the surface of the substrate 10 .
  • thermal annealing can be optionally performed in a hydrogen ambience.
  • the first and the second semiconductor compounds described herein are, for example, IV-IV semiconductor compounds.
  • the IV-IV semiconductor compounds can be composed of a first Group N element and a second Group IV element.
  • the first Group IV element is, for example, silicon (Si).
  • the second Group N element is, for example, a nonsilicon element, such as germanium (Ge) or carbon (C).
  • the IV-IV semiconductor compounds can be silicon germanium (SiGe) or silicon carbide (SiC).
  • the material of the first semiconductor compound layers 34 and the second semiconductor compound layers may be silicon germanium (SiGe); in the NMOS device, the material of the first semiconductor compound layers 34 and the second semiconductor compound layers may be silicon carbide (SiC).
  • the content of the second Group IV element (e.g. germanium content or carbon content) in the second semiconductor compound layers is less than that of the second Group N element (e.g. germanium content or carbon content) in the first semiconductor compound layers 34 .
  • the first semiconductor compound layers 34 and the second semiconductor compound layers of the cap layers 36 have dopants contained therein, and the dopant concentration in the second semiconductor compound layers of the cap layers 36 is equal to or lower than that in the first semiconductor compound layer 34 .
  • the first semiconductor compound layers 34 and the second semiconductor compound layers are doped with the P-type dopants, e.g. boron or BF 2 + ; in the NMOS device, the first semiconductor compound layers 34 and the second semiconductor compound layers are doped with the N-type dopants, e.g. phosphorous or arsenic.
  • reactant gas utilized in the epitaxy growth processes includes a silicon source and a germanium source.
  • the epitaxial temperatures of the first epitaxy growth process and the second epitaxy growth process are lower than 700° C. Owing to the relatively low epitaxial temperatures of the first and the second epitaxy growth processes, outward diffusion of the dopants in the first semiconductor compound layers 34 and in the second semiconductor compound layers can be significantly mitigated.
  • the epitaxial temperature of the second epitaxy growth process may range between 650° C. and 680° C.
  • the epitaxial temperature of the first epitaxy growth process may range between 630° C. and 660° C.
  • the epitaxial temperature of the second epitaxy growth process is slightly higher than that of the first epitaxy growth process by about 10° C. to tens of degrees Celsius, but the epitaxial temperature of the second epitaxy growth process is still lower than 700° C.
  • the second epitaxy growth process for the formation of the cap layers 36 includes a first growth stage 100 and a second growth stage 200 .
  • the first growth stage 100 has a faster growth rate, while the second growth stage 200 has a slower growth rate.
  • the growth rate of the first growth stage 100 is, for example, about 80 ⁇ /100 sec.
  • the growth rate of the second growth stage 200 is, for example, less than 80 ⁇ /100 sec, possibly about 38 ⁇ /100 sec to 40 ⁇ /100 sec.
  • the growth rate of the first growth stage 100 is at least 2 times of that of the second growth stage 200 .
  • the cap layers 36 grow at the faster rate until the cap layers 36 arrive at a given thickness.
  • the second growth stage 200 is performed with the slower growth rate. Therefore, in case a wafer has a first area and a second area, wherein the semiconductor compound grows at the faster rate in the first area, and the semiconductor compound grows at the slower rate in the second area. After the semiconductor compound in the first area of the wafer grows at the faster growth rate during the first growth stage and then reaches the given thickness, the second growth stage is performed with the slower growth rate. As the semiconductor compound in the first area grows at the slower growth rate during the second growth stage, the second area of the wafer, in which the semiconductor compound grows at the slower rate, still undergoes the first growth stage with the faster rate. After the cap layers 36 in the second area reach the given thickness, the second growth stage is performed.
  • the thickness of the semiconductor compound formed in the first area is relatively thin during the second growth stage, which has a tiny difference from the thickness of the semiconductor compound formed in the second area. Accordingly, the loading effects of the first and the second areas can be alleviated in the present invention, thereby improving the mismatches of the device performance. It is substantiated by experiments that the mismatches of the device performance can be better improved by at least 6%.
  • the top of the resultant first semiconductor compound layers 34 may protrude from the surface of the substrate 10 by 50 ⁇ to 100 ⁇ .
  • the second semiconductor compound layers of the resultant cap layers 36 reach tens of angstroms to hundreds of angstroms in thickness.
  • an included angle between the second semiconductor compound layer of the cap layers 36 and the surface of the substrate 10 is less than 40°, for example about 25°.
  • the semiconductor compound is silicon germanium (SiGe)
  • the second semiconductor compound layers in the lateral of the cap layers 36 may have a (311) facet
  • the second semiconductor compound layers in the upper surface of the cap layers may have a (100) facet.
  • the formation of the semiconductor compound layers 33 further includes performing a third epitaxy growth process before the first epitaxy growth process is performed, so as to form a buffer layer 38 in each recess 32 .
  • Each buffer layer 38 includes a third semiconductor compound layer, and a dopant concentration therein equal to 0 or lower than that in the first semiconductor compound layers 34 .
  • the buffer layers 38 are doped with the P-type dopants, such as boron or BF 2 + .
  • the buffer layers 38 are doped with the N-type dopants, such as phosphorous or arsenic.
  • the semiconductor compound layers of the first semiconductor compound layers 34 , the second semiconductor compound layers 36 and the buffer layers 38 are silicon germanium (SiGe).
  • the germanium content in the semiconductor compound layers of the buffer layers 38 is, for example, about 22-25%; the germanium content in the first semiconductor compound layers 34 is, for example, about 28%; and the germanium content in the second semiconductor compound layers of the cap layers 36 is, for example, about 8%.
  • a boron-doped content in the semiconductor compound layers of the buffer layers 38 is, for example, about 0%; a boron-doped content in the first semiconductor compound layers 34 is, for example, about 2 ⁇ 10 20 /cm 2 ; and a boron-doped content in the second semiconductor compound layers of the cap layers 36 is, for example, about 7 ⁇ 10 19 /cm 2 to 2 ⁇ 10 20 /cm 2 . It is verified, in this invention, by experiments that the turn-on currents (Ion) can be enhanced by 2%, and the turn-off currents (Ioff) can be diminished, thereby the mismatches of the device performance can be ameliorated by 6% or above.
  • the foregoing first semiconductor compound layers 34 , the foregoing cap layers (the second semiconductor compound layers) 36 and the foregoing buffer layers 38 can be formed by conducting the epitaxy growth processes in the same reaction chamber, wherein the silicon germanium (SiGe) (or silicon carbide (SiC)) with various germanium content (or carbon content) is formed by adjusting the ratio of the silicon source and the germanium source in the reactant gas (or the ratio of the silicon source and the carbon source in the reactant gas). In addition, in-situ doping is conducted during the epitaxy growth processes.
  • SiGe silicon germanium
  • SiC silicon carbide
  • another mask layer 39 is formed on the first active area 14 a.
  • the block layer 26 on the second active area 14 b is anisotropically etched, so as to form second spacers 30 b on the second active area 14 b.
  • the mask layer 39 is removed.
  • a spacer material layer 40 and a spacer material layer 42 are then formed on the substrate 10 .
  • the material of the spacer material layer 40 is different from that of the spacer material layers 42 .
  • the material of the spacer material layer 40 may be silicon oxide, while the material of the spacer material layers 42 may be silicon nitride.
  • the spacer material layers 40 and 42 are etched in an anisotropic manner, so that third spacers 44 and fourth spacers 46 are respectively formed. Thereafter, ion implantation processes are performed to implant dopants respectively into the semiconductor compound layers 33 of the first active area 14 a and into the substrate 10 of the second active area 14 b, such that source and drain regions 50 a and source and drain regions 50 b are respectively formed.
  • the source and drain regions 50 a are implanted with the P-type dopants; when the NMOS device is to be formed on the second active area 14 b, the source and drain regions 50 b are implanted with the N-type dopants.
  • the source and drain regions 50 a when the NMOS device is to be formed on the first active area 14 a, the source and drain regions 50 a are implanted with the N-type dopants; when the PMOS device is to be formed on the second active area 14 b, the source and drain regions 50 b are implanted with the P-type dopants.
  • the P-type dopants can be boron or BF 2 +
  • the N-type dopants can be phosphorous or arsenic.
  • a metal layer 52 is then formed on the substrate 10 .
  • the material of the metal layer 52 includes refractory metal, e.g. nickel (Ni), titanium (Ti), tungsten (W), cobalt (Co), platinum (Pt) or palladium (Pd).
  • metal silicide layers 54 can be made of nickel silicide, titanium silicide, tungsten silicide, cobalt silicide, platinum silicide or palladium silicide.
  • the present invention is carried out by growing the semiconductor compounds of the source and drain regions through the first and the second epitaxy growth processes with the relatively low epitaxial temperatures, and the outward diffusion of the dopants in the resultant first and second semiconductor compound layers can be alleviated.
  • the second semiconductor compound layers formed by this fabrication process have an included angle with the surface of the substrate less than 40°, which can enhance the turn-on currents and lessen the turn-off currents of the MOS device, so that the improvement in the mismatches of the device performance can be achieved.

Abstract

A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a metal oxide semiconductor (MOS) device and a method for fabricating the same.
  • 2. Description of Related Art
  • Metal oxide semiconductor (MOS) transistor is one of the most common elements used in many different semiconductor devices, such as memories, image sensors or displays. A typical MOS includes a silicon oxide dielectric layer, a gate conductive layer, and heavily doped source/drain contact regions. Along with decrease in linewidth of semiconductor devices, dimensions thereof are reduced. Due to the reduction in the gate width of the typical MOS, the channel length of the MOS is consequentially reduced.
  • As the channel length reduces, applying mechanical stress to the channel is proposed to effectively change mobility of electrons and holes in the channel, thereby increasing operating speed of the transistor. A conventional technique has been provided with using silicon germanium (SiGe) epitaxy material as a major component of the source/drain contact regions in the transistor. As compared with characteristics of silicon material, germanium has larger atomic volume and can apply a compressive stress toward the channel. Thus, the mobility of the holes can be enhanced in the source/drain contact regions majorly made of silicon germanium (SiGe), and thereby device performance can be improved.
  • In the fabrication process of the device, an epitaxial growth rate of silicon germanium (SiGe), however, varies in accordance with different density of surrounding patterns of the device to be formed. Accordingly, the thickness of the resultant silicon germanium (SiGe) is non-uniform (i.e. so-called loading effects), and issues regarding mismatches of the device performance arise therefrom.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to a MOS device, capable of enhancing turn-on currents and lessening turn-off currents, so that the mismatches of the device performance can be ameliorated.
  • The present invention is directed to a method for fabricating a MOS device, wherein alterations in the fabrication process can achieve enhancement of the turn-on currents, decrease in the turn-off currents, and improvement in the mismatches of the device performance.
  • A method for fabricating a MOS device of the present invention is described as follows. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers.
  • Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.
  • According to an embodiment of the present invention, an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
  • According to an embodiment of the present invention, the second semiconductor compound layers have a (311) facet.
  • According to an embodiment of the present invention, the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
  • According to an embodiment of the present invention, the epitaxial temperature of the second epitaxy growth process ranges between 650° C. and 680° C.
  • According to an embodiment of the present invention, an epitaxial temperature of the first epitaxy growth process ranges between 630° C. and 660° C.
  • According to an embodiment of the present invention, the method further includes performing a third epitaxy growth process before performing the first epitaxy growth process, so as to form a buffer layer in each of the recesses. Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
  • According to an embodiment of the present invention, the first epitaxy growth process finishes when a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
  • Another method for fabricating a MOS device of the present invention is described as follows. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed, so as to form a second semiconductor compound layer on each of the first semiconductor compound layers. The second semiconductor compound layers protrude from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers. The second epitaxy growth process includes a first growth stage and a second growth stage, wherein a growth rate of the second growth stage is less than a growth rate of the first growth stage.
  • According to an embodiment of the present invention, the growth rate of the second epitaxy growth process is less than 80 Å/100 sec.
  • According to an embodiment of the present invention, the growth rate of the first growth stage is at least 2 times of the growth rate of the second growth stage in the second epitaxy growth process.
  • According to an embodiment of the present invention, an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
  • According to an embodiment of the present invention, the second semiconductor compound layers have a (311) facet.
  • According to an embodiment of the present invention, the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
  • According to an embodiment of the present invention, the method further includes performing a third epitaxy growth process before performing the first epitaxy growth process, so as to form a buffer layer in each of the recesses. Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
  • According to an embodiment of the present invention, the first epitaxy growth process finishes when a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
  • A MOS device of the present invention is provided, including a substrate, first semiconductor compound layers, and cap layers. The substrate has two recesses therein. The first semiconductor compound layers are disposed in the recesses. Each of the cap layers includes a second semiconductor compound layer that is disposed on each of the first semiconductor compound layers and protrudes from a surface of the substrate. An included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
  • According to an embodiment of the present invention, the second semiconductor compound layers have a (311) facet.
  • According to an embodiment of the present invention, the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
  • According to an embodiment of the present invention, the MOS device further includes buffer layers, respectively disposed in the recesses and intervening between the substrate and the first semiconductor compound layers. Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
  • According to an embodiment of the present invention, a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
  • According to an embodiment of the present invention, a thickness of the cap layers is 1/X to 1/Y times of a thickness of the first semiconductor compound layers.
  • As mentioned above, the MOS device in this invention can enhance the turn-on currents and lessen the turn-off currents, thereby improving the mismatches of the device performance. Moreover, the fabricating method of the MOS device in this invention is capable of enhancing the turn-on currents, lessening the turn-off currents, and improving the mismatches of the device performance through modifications in the fabrication process.
  • In order to make the aforementioned and other features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawings will be provided by the Office upon request and payment of the necessary fee. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIGS. 1-7 depict, in a cross-sectional view, a method for fabricating a MOS device according to an embodiment of the present invention.
  • FIG. 8 illustrates a second epitaxy growth process for formation of cap layers according to an embodiment of the present invention.
    •  DESCRIPTION OF THE EMBODIMENTS
  • Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
  • FIGS. 1-7 depict, in a cross-sectional view, a method for fabricating a MOS device according to an embodiment of the present invention.
  • Referring to FIG. 1, isolation structures 12 are formed in a substrate 10, so as to define a first active area 14 a and a second active area 14 b. The material of the substrate 10 includes semiconductor, such as silicon. The material of the isolation structures 12 includes insulating material, such as silicon oxide. The isolation structures 12 are, for example, formed by a shallow trench isolation (STI) method.
  • Stack structures are then formed on the first and the second active areas 14 a, 14 b of the substrate 10, respectively. Each stack structure 16 includes an insulating layer 18, a conductor layer 20 and a hard mask layer 22. In an embodiment, a width of the stack structures 16 is, for example, about 24 nm. The insulating layers 18 may include a dielectric layer, a high-dielectric constant (K value greater than 4) material, a barrier layer, or combination thereof. The dielectric layer is, for example, made of silicon oxide. The high-K dielectric material is, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), or hafnium zirconium oxide (HfZrO). The barrier layer is, for example, made of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or combination thereof. The material of the conductor layers 20 can be monocrystalline silicon, undoped polysilicon, doped polysilicon, amorphous silicon, silicon germanium material, or combination thereof with a thickness of, for example, about 650 Å. The material of the hard mask layers 22 can be silicon oxide, silicon nitride, silicon carbide or silicon oxynitride with, for example, hundreds of angstroms in thickness. The formation of the stack structures 16 can be carried out by forming an insulating material layer, a conductor material layer and a hard mask material layer, and then patterning the foregoing layers through lithography and etching processes.
  • Afterwards, first spacers 24 are formed on respective sidewalls of each stack structure 16. The material of the first spacers 24 are, for example, silicon nitride. Then, ion implantation processes are conducted individually, so that a lightly doped drain (LDD) 25 a and an LDD 25 b are formed respectively in the first active area 14 a and in the second active area 14 b. In an embodiment, when a PMOS device is to be formed on the first active area 14 a, dopants implanted into the LDD 25 a may be P-type; when an NMOS is to be formed on the second active area 14 b, dopants implanted into the LDD 25 b may be N-type. In another embodiment, when the NMOS device is to be formed on the first active area 14 a, dopants implanted into the LDD 25 a may be N-type; when the PMOS device is to be formed on the second active area 14 b, dopants implanted into the LDD 25 b may be P-type. The P-type dopants can be boron or BF2 +, while the N-type dopants can be phosphorous or arsenic.
  • Subsequently, a block layer 26 is formed on the substrate 10. The block layer 26 is, for example, made of silicon nitride. A mask layer 28 is then formed on the first active area 14 a. The mask layer 28 is, for example, made of photoresist, and the formation thereof can be implemented by the lithography process.
  • Referring to FIG. 2, an anisotropic etching process is performed using the mask layer 28 as an etching mask, and thus, a portion of the block layer 26 is removed, so as to form second spacers 30 a on the respective sidewalls of the stack structure 16 on the first active area 14 a.
  • Afterwards, a portion of the substrate 10 in the first active area 14 a is removed by dry or wet etching or combination thereof, so that two recesses 32 are formed in the substrate 10 at both sides of the second spacers 30 a. In an embodiment, a depth of each recess 32 is, for example, about hundreds of angstroms. The recesses 32 can have diamond-shaped profiles or rectangle-shaped profiles, and are not particularly limited by the present invention.
  • Referring to FIG. 3, the mask layer 28 is removed, so that the block layer 26 on the second active area 14 b is exposed.
  • A semiconductor compound layer 33 is then formed in each of the recesses 32. The fabricating method of the semiconductor compound layers 33 includes performing a first epitaxy growth process to form a first semiconductor compound layer 34 in each recess 32, and then performing a second epitaxy growth process to form a cap layer 36 on each first semiconductor compound layer 34. Each cap layer 36 includes a second semiconductor compound layer that may protrude from the surface of the substrate 10. Before conducting the first epitaxy growth process, thermal annealing can be optionally performed in a hydrogen ambiance.
  • The first and the second semiconductor compounds described herein are, for example, IV-IV semiconductor compounds. The IV-IV semiconductor compounds can be composed of a first Group N element and a second Group IV element. The first Group IV element is, for example, silicon (Si). The second Group N element is, for example, a nonsilicon element, such as germanium (Ge) or carbon (C). In other words, the IV-IV semiconductor compounds can be silicon germanium (SiGe) or silicon carbide (SiC). In the PMOS device, the material of the first semiconductor compound layers 34 and the second semiconductor compound layers may be silicon germanium (SiGe); in the NMOS device, the material of the first semiconductor compound layers 34 and the second semiconductor compound layers may be silicon carbide (SiC).
  • The content of the second Group IV element (e.g. germanium content or carbon content) in the second semiconductor compound layers is less than that of the second Group N element (e.g. germanium content or carbon content) in the first semiconductor compound layers 34. The first semiconductor compound layers 34 and the second semiconductor compound layers of the cap layers 36 have dopants contained therein, and the dopant concentration in the second semiconductor compound layers of the cap layers 36 is equal to or lower than that in the first semiconductor compound layer 34. In the PMOS device, the first semiconductor compound layers 34 and the second semiconductor compound layers are doped with the P-type dopants, e.g. boron or BF2 +; in the NMOS device, the first semiconductor compound layers 34 and the second semiconductor compound layers are doped with the N-type dopants, e.g. phosphorous or arsenic.
  • In an embodiment, when the semiconductor compound is silicon germanium (SiGe), reactant gas utilized in the epitaxy growth processes includes a silicon source and a germanium source. The epitaxial temperatures of the first epitaxy growth process and the second epitaxy growth process are lower than 700° C. Owing to the relatively low epitaxial temperatures of the first and the second epitaxy growth processes, outward diffusion of the dopants in the first semiconductor compound layers 34 and in the second semiconductor compound layers can be significantly mitigated.
  • In an embodiment, the epitaxial temperature of the second epitaxy growth process may range between 650° C. and 680° C., and the epitaxial temperature of the first epitaxy growth process may range between 630° C. and 660° C. In other words, the epitaxial temperature of the second epitaxy growth process is slightly higher than that of the first epitaxy growth process by about 10° C. to tens of degrees Celsius, but the epitaxial temperature of the second epitaxy growth process is still lower than 700° C.
  • Referring to FIG. 8, the second epitaxy growth process for the formation of the cap layers 36 includes a first growth stage 100 and a second growth stage 200. The first growth stage 100 has a faster growth rate, while the second growth stage 200 has a slower growth rate. The growth rate of the first growth stage 100 is, for example, about 80 Å/100 sec. The growth rate of the second growth stage 200 is, for example, less than 80 Å/100 sec, possibly about 38 Å/100 sec to 40 Å/100 sec. The growth rate of the first growth stage 100 is at least 2 times of that of the second growth stage 200. During the first growth stage 100, the cap layers 36 grow at the faster rate until the cap layers 36 arrive at a given thickness. Thereafter, the second growth stage 200 is performed with the slower growth rate. Therefore, in case a wafer has a first area and a second area, wherein the semiconductor compound grows at the faster rate in the first area, and the semiconductor compound grows at the slower rate in the second area. After the semiconductor compound in the first area of the wafer grows at the faster growth rate during the first growth stage and then reaches the given thickness, the second growth stage is performed with the slower growth rate. As the semiconductor compound in the first area grows at the slower growth rate during the second growth stage, the second area of the wafer, in which the semiconductor compound grows at the slower rate, still undergoes the first growth stage with the faster rate. After the cap layers 36 in the second area reach the given thickness, the second growth stage is performed. Due to the slow growth rate of the second growth stage, the thickness of the semiconductor compound formed in the first area is relatively thin during the second growth stage, which has a tiny difference from the thickness of the semiconductor compound formed in the second area. Accordingly, the loading effects of the first and the second areas can be alleviated in the present invention, thereby improving the mismatches of the device performance. It is substantiated by experiments that the mismatches of the device performance can be better improved by at least 6%.
  • When the first epitaxy growth process finishes, the top of the resultant first semiconductor compound layers 34 may protrude from the surface of the substrate 10 by 50 Å to 100 Å. When the second epitaxy growth process finishes, the second semiconductor compound layers of the resultant cap layers 36 reach tens of angstroms to hundreds of angstroms in thickness.
  • In an embodiment, as the semiconductor compound is silicon germanium (SiGe), an included angle between the second semiconductor compound layer of the cap layers 36 and the surface of the substrate 10 is less than 40°, for example about 25°. In an embodiment, as the semiconductor compound is silicon germanium (SiGe), the second semiconductor compound layers in the lateral of the cap layers 36 may have a (311) facet, and the second semiconductor compound layers in the upper surface of the cap layers may have a (100) facet.
  • In another embodiment, the formation of the semiconductor compound layers 33 further includes performing a third epitaxy growth process before the first epitaxy growth process is performed, so as to form a buffer layer 38 in each recess 32. Each buffer layer 38 includes a third semiconductor compound layer, and a dopant concentration therein equal to 0 or lower than that in the first semiconductor compound layers 34. In the PMOS device, the buffer layers 38 are doped with the P-type dopants, such as boron or BF2 +. In the NMOS device, the buffer layers 38 are doped with the N-type dopants, such as phosphorous or arsenic.
  • In the PMOS device at 40 nm process node, the semiconductor compound layers of the first semiconductor compound layers 34, the second semiconductor compound layers 36 and the buffer layers 38 are silicon germanium (SiGe). The germanium content in the semiconductor compound layers of the buffer layers 38 is, for example, about 22-25%; the germanium content in the first semiconductor compound layers 34 is, for example, about 28%; and the germanium content in the second semiconductor compound layers of the cap layers 36 is, for example, about 8%. A boron-doped content in the semiconductor compound layers of the buffer layers 38 is, for example, about 0%; a boron-doped content in the first semiconductor compound layers 34 is, for example, about 2×1020/cm2; and a boron-doped content in the second semiconductor compound layers of the cap layers 36 is, for example, about 7×1019/cm2 to 2×1020/cm2. It is verified, in this invention, by experiments that the turn-on currents (Ion) can be enhanced by 2%, and the turn-off currents (Ioff) can be diminished, thereby the mismatches of the device performance can be ameliorated by 6% or above.
  • The foregoing first semiconductor compound layers 34, the foregoing cap layers (the second semiconductor compound layers) 36 and the foregoing buffer layers 38 can be formed by conducting the epitaxy growth processes in the same reaction chamber, wherein the silicon germanium (SiGe) (or silicon carbide (SiC)) with various germanium content (or carbon content) is formed by adjusting the ratio of the silicon source and the germanium source in the reactant gas (or the ratio of the silicon source and the carbon source in the reactant gas). In addition, in-situ doping is conducted during the epitaxy growth processes.
  • Referring to FIG. 4, another mask layer 39 is formed on the first active area 14 a. Afterwards, the block layer 26 on the second active area 14 b is anisotropically etched, so as to form second spacers 30 b on the second active area 14 b.
  • Referring to FIG. 5, the mask layer 39 is removed. A spacer material layer 40 and a spacer material layer 42 are then formed on the substrate 10. The material of the spacer material layer 40 is different from that of the spacer material layers 42. In an embodiment, the material of the spacer material layer 40 may be silicon oxide, while the material of the spacer material layers 42 may be silicon nitride.
  • Referring to FIG. 6, the spacer material layers 40 and 42 are etched in an anisotropic manner, so that third spacers 44 and fourth spacers 46 are respectively formed. Thereafter, ion implantation processes are performed to implant dopants respectively into the semiconductor compound layers 33 of the first active area 14 a and into the substrate 10 of the second active area 14 b, such that source and drain regions 50 a and source and drain regions 50 b are respectively formed. In an embodiment, when the PMOS device is to be formed on the first active area 14 a, the source and drain regions 50 a are implanted with the P-type dopants; when the NMOS device is to be formed on the second active area 14 b, the source and drain regions 50 b are implanted with the N-type dopants. In another embodiment, when the NMOS device is to be formed on the first active area 14 a, the source and drain regions 50 a are implanted with the N-type dopants; when the PMOS device is to be formed on the second active area 14 b, the source and drain regions 50 b are implanted with the P-type dopants. The P-type dopants can be boron or BF2 +, and the N-type dopants can be phosphorous or arsenic.
  • A metal layer 52 is then formed on the substrate 10. The material of the metal layer 52 includes refractory metal, e.g. nickel (Ni), titanium (Ti), tungsten (W), cobalt (Co), platinum (Pt) or palladium (Pd).
  • Referring to FIG. 7, a thermal process is performed, such that the metal layer 52 may react with silicon in the substrate 10 to form metal silicide layers 54. The metal silicide layers 54 can be made of nickel silicide, titanium silicide, tungsten silicide, cobalt silicide, platinum silicide or palladium silicide.
  • In view of the above, the present invention is carried out by growing the semiconductor compounds of the source and drain regions through the first and the second epitaxy growth processes with the relatively low epitaxial temperatures, and the outward diffusion of the dopants in the resultant first and second semiconductor compound layers can be alleviated. In addition, the second semiconductor compound layers formed by this fabrication process have an included angle with the surface of the substrate less than 40°, which can enhance the turn-on currents and lessen the turn-off currents of the MOS device, so that the improvement in the mismatches of the device performance can be achieved.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (21)

What is claimed is:
1. A method for fabricating a metal oxide semiconductor (MOS) device, comprising:
forming two recesses in a substrate;
performing a first epitaxy growth process, so as to form a first semiconductor compound layer in each of the recesses; and
performing a second epitaxy growth process with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers, each of the cap layers comprising a second semiconductor compound layer that protrudes from a surface of the substrate, wherein the first semiconductor compound layers and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element that is a nonsilicon element, and a content of the second Group IV element in the second semiconductor compound layers is less than a content of the second Group IV element in the first semiconductor compound layers.
2. The method according to claim 1, wherein an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
3. The method according to claim 1, wherein the second semiconductor compound layers have a (311) facet.
4. The method according to claim 1, wherein the first semiconductor compound layers and the second semiconductor compound layers comprise dopants, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
5. The method according to claim 1, wherein the epitaxial temperature of the second epitaxy growth process ranges between 650° C. and 680° C.
6. The method according to claim 5, wherein an epitaxial temperature of the first epitaxy growth process ranges between 630° C. and 660° C.
7. The method according to claim 1, further comprising performing a third epitaxy growth process before performing the first epitaxy growth process, so as to form a buffer layer in each of the recesses, wherein each of the buffer layers comprises a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
8. The method according to claim 1, wherein the first epitaxy growth process finishes when a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
9. A method for fabricating a metal oxide semiconductor (MOS) device, comprising:
forming two recesses in a substrate;
performing a first epitaxy growth process, so as to form a first semiconductor compound layer in each of the recesses; and
performing a second epitaxy growth process, so that a second semiconductor compound layer is formed on each of the first semiconductor compound layers, and the second semiconductor compound layers protrude from a surface of the substrate, wherein the first semiconductor compound layers and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element that is a nonsilicon element, and a content of the second Group IV element in the second semiconductor compound layers is less than a content of the second Group IV element in the first semiconductor compound layers, the second epitaxy growth process comprising:
a first growth stage; and
a second growth stage, wherein a growth rate of the second growth stage is less than a growth rate of the first growth stage.
10. The method according to claim 9, wherein the growth rate of the second epitaxy growth process is less than 80 Å/100 sec.
11. The method according to claim 9, wherein the growth rate of the first growth stage is at least 2 times of the growth rate of the second growth stage.
12. The method according to claim 9, wherein an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
13. The method according to claim 9, wherein the second semiconductor compound layers have a (311) facet.
14. The method according to claim 9, wherein the first semiconductor compound layers and the second semiconductor compound layers comprise dopants, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
15. The method according to claim 9, further comprising performing a third epitaxy growth process before performing the first epitaxy growth process, so as to form a buffer layer in each of the recesses, wherein each of the buffer layers comprises a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
16. The method according to claim 9, wherein the first epitaxy growth process finishes when a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
17. A metal oxide semiconductor (MOS) device, comprising:
a substrate, having two recesses therein;
a first semiconductor compound layer, disposed in each of the recesses; and
a cap layer comprising a second semiconductor compound layer, disposed on each of the first semiconductor compound layers and protruding from a surface of the substrate, wherein an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
18. The MOS device according to claim 17, wherein the second semiconductor compound layers have a (311) facet.
19. The MOS device according to claim 17, wherein the first semiconductor compound layers and the second semiconductor compound layers comprise dopants, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
20. The MOS device according to claim 17, further comprising a buffer layer, disposed in each of the recesses and intervening between the substrate and the first semiconductor compound layers, wherein each of the buffer layers comprises a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
21. The MOS device according to claim 17, wherein a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
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