US20130037954A1 - Metallization and Its Use In, In Particular, an IGBT or a Diode - Google Patents
Metallization and Its Use In, In Particular, an IGBT or a Diode Download PDFInfo
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- US20130037954A1 US20130037954A1 US13/655,239 US201213655239A US2013037954A1 US 20130037954 A1 US20130037954 A1 US 20130037954A1 US 201213655239 A US201213655239 A US 201213655239A US 2013037954 A1 US2013037954 A1 US 2013037954A1
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- 238000001465 metallisation Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 94
- 229910052802 copper Inorganic materials 0.000 claims description 39
- 239000010949 copper Substances 0.000 claims description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 15
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- 238000009792 diffusion process Methods 0.000 claims description 10
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
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- 239000004332 silver Substances 0.000 claims description 5
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- 238000002513 implantation Methods 0.000 description 32
- 229910000679 solder Inorganic materials 0.000 description 17
- 239000000463 material Substances 0.000 description 14
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- 239000011733 molybdenum Substances 0.000 description 12
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Definitions
- the present invention relates to a method for fabricating a power semiconductor component that has a metallization.
- IGBT insulated gate bipolar transistor
- DCB direct copper bonding
- the solder connecting technique is therefore occasionally replaced by the thermally better suited low-temperature connecting technique (LTC).
- LTC low-temperature connecting technique
- LTC is still not suitable for a modular production of IGBTs.
- soldering a lamina composed of molybdenum onto the front side of the chip boosts the dissipation of heat from the semiconductor chip, its effectiveness is limited owing to the poor thermal properties of the solder that is once again used in this case.
- a proton irradiation may be performed in order that deep dopant profiles or profiles with charge carriers having a reduced lifetime are incorporated into a semiconductor chip in a targeted manner.
- the fabrication of a field stop zone at a depth of 10 ⁇ m, for example, from the rear side of the chip by means of a proton irradiation shall be mentioned as an example. If, in this example, the proton irradiation is carried out from the rear side of the chip, then a strongly localized excessive increase in doping arises in the so-called “end-of-range region” of the proton implantation.
- FIG. 2 of the accompanying drawings show such a profile of the doping concentration as a function of the depth from the rear side of the chip using a solid line, working with an energy of 750 keV in silicon and with an effective proton dose of 1e12 cm.sup. ⁇ 2 in this case.
- This relief of loading is actually realized by means of a masked cathode implantation into the rear side of the chip below the active chip region, but not below the edge region. In other words, an injection of charge carriers below the edge region scarcely takes place as a result of this. What is disadvantageous about such a procedure, however, is the need for a phototechnology on the rear side of the chip as well in order thus to be able to perform the masked cathode implantation below the active region but not below the edge.
- the invention is based on the object of specifying a metallization for power semiconductor components, in particular IGBTs and diodes, which—as far as IGBTs are concerned—improves the short circuit strength thereof with regard to destruction after a turn-off and which—as far as diodes are concerned—increases the surge current strength thereof; moreover, the intention is to readily enable a targeted widening of field stop profiles during fabrication by means of a proton irradiation; finally, the intention is also to ensure targeted relief of the loading of the edge region during dynamic switching and to specify a method for fabricating such a metallization.
- This object is achieved according to the invention by means of a metallization for power semiconductor components as described herein.
- the object is further achieved by a method of fabricating a power semiconductor component having a semiconductor body having at least two main surfaces.
- the method includes applying a layer of a metallization on at least one of the main surfaces, the layer having a thickness of at least 15 ⁇ m, the layer serving as a heat sink.
- the method also includes producing a field stop zone in the semiconductor body by implantation of protons or helium through the layer.
- the layer thickness of the at least one layer is at least 15 ⁇ m. It is preferably at least 20 ⁇ m.
- the metallization according to the invention can be used to produce a field stop layer by proton irradiation from the rear side of the chip or wafer or for masking a proton or helium implantation from the front side of a semiconductor chip.
- patent claims 10 to 15 Patent claim 16 specifies an advantageous method for fabricating the metallization.
- a material whose specific heat capacity is at least a factor of 1.3 higher than the specific heat capacity of the semiconductor chip is used for the at least one layer, that is to say for the emitter contact and/or the collector contact in the case of an IGBT, for example.
- the specific heat capacity of the material of said layer is preferably a factor of 2 greater than the specific heat capacity of the semiconductor chip.
- the specific thermal conductivity of the material of said layer should be greater than the specific thermal conductivity of the semiconductor chip. If the semiconductor chip is composed of silicon, by way of example, then the latter has a specific heat capacity of 1.63 J/(° K cm 3 ). Copper, which has a specific heat capacity of 3.43 J/(° K cm 3 ) is then preferably suitable as material for the at least one layer. Other materials that are likewise suitable are aluminum, silver and gold.
- the absolute thermal capacity of the at least one layer is preferably equal to at least 10% of the thermal capacity of the semiconductor chip.
- depositing a layer having a high thermal conductivity and specific heat capacity reduces the so-called thermal impedance “Zth” (Zth is a time-dependent impedance) of the semiconductor chip for short timescales.
- Zth is a time-dependent impedance
- the implantation profile of the field stop zone is widened during implantation of protons through the layer on the rear side of the chip, by way of example. This in turn brings about a more favorable switching behavior of IGBTs and diodes.
- the layer is deposited selectively onto metallizations that are already present on the front side of the chip, by way of example, then it can be utilized as masking for subsequent proton or helium implantations. In other words, a relief of the loading of the diode edge in a manner similar to the HDR concept can be achieved thereby.
- the layer can be electrodeposited or deposited by vapor deposition onto the rear side and/or front. side of the semiconductor chip.
- a significant advantage of at least some embodiments of the invention thus resides in the simultaneous reduction of Zth and the widening or masking of proton or helium implantations by means of a single measure, namely the application of the at least one layer to the at least one main surface.
- FIG. 1 shows a schematic sectional illustration through an IGBT according to the teaching of the invention
- FIG. 2 shows a diagram revealing the widening of a field stop profile during a proton implantation through a copper layer having a thickness of approximately 50 ⁇ m
- FIG. 3 shows a bar chart with results from electrothermal component simulations for short circuit destruction of an IGBT for 1200 V after turn-off of a current pulse, showing various mounting variants (cf. upper half) and relative destruction energies (cf. lower half), in relation to the prior art (cf. variant 1 ).
- FIG. 1 shows a section through an IGBT having a semiconductor body or chip 1 made preferably of silicon or another suitable semiconductor material (e.g. SiC or A III B v ).
- a p-conducting base zone 3 is introduced into an n ⁇ -conducting base zone 2 , an n- or n + -conducting source or emitter zone 4 being situated in said base zone 3 .
- the semiconductor body 1 has an n- or n + -conducting field stop zone 5 and also a p-conducting collector zone 6 . It goes without saying that the conduction types specified may also be respectively reversed.
- An insulating layer 8 made, for example, of silicon dioxide and/or silicon nitride is situated on a first main surface 7 of the semiconductor body 1 .
- a gate electrode 9 made, in particular, of polycrystalline silicon is introduced into said insulating layer 8 .
- a diode does not have such a gate electrode.
- the emitter zone 4 and the p-type base zone 3 are contact-connected via a first contact (emitter contact) 10 .
- a second main surface 11 of the semiconductor body 1 opposite to the first main surface 7 is provided with a second contact (collector contact) 12 .
- a diffusion barrier layer 13 made, for example, of Ti, TiN, Ta, TaN or combinations thereof may also be provided between the collector zone 6 , that is to say the second main surface 11 of the semiconductor body 1 , and the second contact 12 .
- the combinations Ti/TiN and Ta/TaN are particularly preferred.
- Said diffusion barrier layer 13 protects the silicon of the semiconductor body 1 against indiffusion of atoms from the contact 12 .
- the diffusion barrier layer 13 may, if appropriate, also be provided with an aluminum layer 14 , which further limits said indiffusion.
- the layer 14 may—as illustrated—be situated between the layers 12 and 13 , or else between the main surface 11 and the layer 13 .
- the layers 13 , 14 may also be fitted for the first contact 10 .
- the first contact 10 may be applied to a metallization already present, which is generally very thin and thus exhibits good thermal conduction.
- a suitable material for these conditions for specific heat capacity and specific thermal conductivity is preferably copper, aluminum, silver or gold.
- these metals may also be “mixed” or used in alloys.
- the layers of the contacts 10 , 12 are applied to the semiconductor body 1 or to the insulating layer 8 as far as possible directly and if need be via the diffusion barrier layer 13 and the aluminum layer 14 or a metallization that is already present.
- the layer thickness of the contacts 10 , 12 is at least 15 ⁇ m and preferably at least 20 ⁇ m.
- the thermal capacity of said layer 12 should have a magnitude at least equal to the thermal capacity of the semiconductor chip with the semiconductor body 1 .
- the layers for the contacts 10 , 12 may be applied by electrodeposition or by vapor deposition onto the front side of the chip, that is to say the main surface 7 , or in particular the rear side of the chip, that is to say the main surface 11 .
- An additional heat sink preferably made of molybdenum can then be soldered onto the layer for the contact 10 at the front side by means of solder, by way of example. This is done after a proton irradiation that may be provided has been performed through the layer for the contact 12 (cf. variant 5 in FIG. 3 explained further below).
- the copper layer for the contact 12 is deposited up to a thickness of 50 ⁇ m, for example.
- the proton irradiation is then effected through this layer.
- a further reinforcement of the copper layer is then possible by means of a further galvanic process (cf. variant 10 in FIG. 3 ). That is to say that the deposition of the copper layer is stopped in a targeted manner at a thickness such as is necessary for widening the proton profile, and after the irradiation.
- the high thermal conductivity of the layers for the corresponding contacts 10 and 12 has the effect that the thermal energy dissipated during a turn-off or a surge current loading of the component, from the semiconductor chip 1 , can be rapidly transferred into the thermal capacities of said layers.
- the layers for the contacts 10 , 12 have a layer thickness such that the above condition for the thermal capacity (thermal capacity of the layers or the layer is greater than half the thermal capacity of the semiconductor chip) is fulfilled. It has been shown that preferred layer thicknesses lie between 20 and 60 ⁇ m, preferably between 40 and 60 ⁇ m, and, in particular, a layer thickness of 50 ⁇ m is chosen. These dimensions hold true in particular for copper as material for the contacts 10 , 12 and a thickness of the semiconductor body 1 composed of silicon of approximately 120 ⁇ m.
- the copper of the contacts 10 , 12 may, if: appropriate, also be provided with a customary covering layer, for example by means of deposition, in order thus to avoid corrosion of the copper.
- a customary covering layer for example by means of deposition, in order thus to avoid corrosion of the copper.
- Suitable materials for such a covering layer are NiP—Pd—Au, for example.
- a proton implantation is effected from the rear side of the chip (or else the front side of the chip), that is to say via the main surface 11 (or respectively 7 ) of the semiconductor body 1 for the purpose of forming the field stop zone 5 , then the implantation profile is greatly widened—as has been shown—by virtue of the copper layer of the contact 12 .
- a heat treatment in the range of approximately 350° C. to 450° C. subsequent to the implantation then leads to the doping effect of the proton implantation, thus giving rise to the layer 5 effecting the field stop.
- Such a field stop layer 5 is preferably used for IGBTs and diodes.
- FIG. 2 uses a dashed line to show this widening effect for an effective proton dose of 1e12 cm.sup. ⁇ 2 at an implantation energy of 3.9 MeV through a 50 ⁇ m thick copper layer in a silicon body. If the profile of this curve is compared with the profile of the curve for an implantation at 750 keV without a copper layer in a silicon body, then the considerable widening of the implantation profile is immediately apparent. Strongly localized excessive increases in doping are thus avoided, thereby considerably improving the switching behavior of IGBTs and diodes in the case of an implantation for the field stop layer through a copper layer having a thickness of approximately 50 ⁇ m. With the gentle doping profile, the electric field is not braked abruptly, with the result that great increases in the voltage rise dU/dt do not occur in this case.
- the implantation of protons through the copper layer having a thickness of 20 to 60 ⁇ m and preferably approximately 50 ⁇ m thus effects a field stop profile that runs up gently in the semiconductor chip, which could otherwise only be achieved by means of a plurality of stacked implantations with different energies in conventional proton implantation technology.
- the active chip area that is to say the area in the region of the zone 3 , is covered by the copper layer of the contact 10 .
- said copper layer of the contact 10 acts as masking which stops a proton implantation which, without masking, would penetrate up to 100 ⁇ m into the silicon of the semiconductor 1 .
- the material, in particular copper, of the layer forming the contact 10 achieves a masking of the implantation and thus a reduced plasma flooding in the edge. Said additional phototechnology is not necessary since the material for the layer forming the contact 10 can be applied to the front side of the semiconductor body in a self-aligned manner by means of selective deposition.
- FIG. 3 which has already been discussed a number of times above, illustrates the advantages of the invention specifically with regard to the relative destruction energy (cf. the lower half of FIG. 3 ).
- variant 1 shows the present-day prior art: A chip CH is applied over a solder layer and a copper layer on ceramic.
- Variants 2 and 4 presuppose the novel connecting technique LTC, which has already been mentioned in the introduction.
- the copper layer of the substrate ceramic is connected to the semiconductor chip CH via an LTC layer.
- the semiconductor chip CH has an LTC layer on both sides, which is connected to a molybdenum lamina on the front side of the chip and to the DCB ceramic on the rear side of the chip.
- Variant 3 shows a case in which—as explained in the introduction—the rear side of the chip is contact-connected in accordance with variant 1 , while the front side of the chip is connected to a molybdenum lamina via a solder layer.
- Variants 5 to 10 in each case use the metallization according to the invention.
- a copper layer having a thickness of approximately 50 ⁇ m is applied to the semiconductor chip CH on both sides, which copper layer is provided with a molybdenum lamina via a solder layer on the front side of the chip and with a further copper layer likewise via a solder layer on the rear side of the chip.
- Variant 6 differs from variant 5 in that the solder layer and the molybdenum lamina are omitted on the front side of the chip.
- the copper layer is also absent on the front side of the chip.
- Variant 8 corresponds to variant 6 with regard to the front side of the chip.
- Variants 9 and 10 have a very thick copper layer having a layer thickness of more than 200 ⁇ m on the front side of the chip.
- the rear side of the chip is configured in a conventional manner in variant 9 with a DCB ceramic connected by a solder layer, while in variant 10 it has a copper layer which is applied directly to the rear side of the chip and is again provided with the DCB ceramic via a solder layer.
- Variant 6 constitutes a particularly preferred variant according to the invention: This is because it is possible in this case to retain the conventional connecting technique that only a pure optimization is performed at the chip level.
- the copper layers having a thickness of approximately 50 ⁇ m that are provided on both sides in this variant act as short-term heat sinks and are distinctly superior to soldering on a molybdenum lamina, for instance according to variant 3 .
- variant 6 is compared with the prior art in accordance with variant 1 , then an increase in the relative destruction energy from 100% (prior art) to approximately 175% (invention) is apparent. That is to say that the semiconductor component provided with the metallization according to the invention is not destroyed until at a dissipated energy amplified by a factor of 1.75. In other words, components configured in accordance with the present invention can be loaded to a significantly greater extent during operation.
- Additional heat sinks for instance in accordance with variant 5 , may provide for a further significant improvement by soldering on the molybdenum lamina.
- a subsequent reinforcement of the copper, as in variant 10 is likewise possible.
- the efficacy for variant 10 which has not yet been definitively determined, should lie between variants 4 and 5 , that is to say in the region of approximately 250%.
- At least some embodiments of the invention provide a metallization which carries away dissipated thermal energy in an outstanding manner from a component in the event of a turn-off or surge loading thereof.
- This metallization may additionally be utilized, on the rear side of the chip, for the proton implantation for widening the field stop profile and, on the front side of the chip, as masking for a proton or helium implantation for the targeted incorporation of recombination centers below the edge region specifically of diodes.
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Abstract
A vertical power semiconductor component includes a semiconductor chip and at least one layer serving as a heat sink. The semiconductor chip has a top main surface at a front side of the semiconductor chip, wherein the top main surface is in a heat exchanging relationship with the at least one layer serving as the heat sink. This layer has a layer thickness of at least 15 μm and has a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip. The component further includes metallizations between the at least one layer and the top main surface.
Description
- This application is a continuation application of U.S. patent application Ser. No. 13/206,257, filed Aug. 9, 2011, which is a divisional application of U.S. patent application Ser. No. 11/082,192, filed Mar. 16, 2005, which in turn claims priority to German Patent Application No. 10 2004 012 818.9, filed Mar. 16, 2004.
- The present invention relates to a method for fabricating a power semiconductor component that has a metallization.
- As is known, the short circuit strength of an IGBT (insulated gate bipolar transistor) is thermally limited with regard to its destruction after a turn-off. This can be attributed to the fact that a very high energy is liberated during a short circuit situation in the IGBT, which energy has to be dissipated rapidly by cooling if destruction of the IGBT is to be prevented.
- At the present time, IGBTs are soldered on one side by means of solder by their chip rear side onto a so-called DCB ceramic (DCB=direct copper bonding). This involves a ceramic plate which is coated with copper on both sides and is used in modular technology as a mechanical carrier of the chips and for making electrical contact with the chips. It is the case, however, that solder has a relatively weak thermal conductivity. On account of this unfavorable thermal property, it thus represents a “brake” for the cooling of the IGBT.
- On account of the low thermal conductivity of solder, the solder connecting technique is therefore occasionally replaced by the thermally better suited low-temperature connecting technique (LTC). The latter enables an increased dissipation of heat from a semiconductor chip.
- Finally, it is also possible to cool a semiconductor chip from its front side in addition to its rear side. For this purpose, a further thermal capacity, which is made available by a relatively thick molybdenum lamina, for example, is applied to the front side of the chip.
- To summarize, the following proposals have thus been made heretofore for improving the dissipation of heat from a semiconductor chip of an IGBT:
- (a) replacing the customary solder on the rear side of the chip by LTC,
- (b) soldering a lamina composed of molybdenum, in particular, onto the front side of the chip, and
- (c) replacing the solder at the rear side of the chip by LTC as in proposal (a) and connecting a lamina composed of molybdenum, in particular, onto the front side of the chip by means of LTC.
- However, at the present time, LTC is still not suitable for a modular production of IGBTs. Although soldering a lamina composed of molybdenum onto the front side of the chip boosts the dissipation of heat from the semiconductor chip, its effectiveness is limited owing to the poor thermal properties of the solder that is once again used in this case. There is not yet any practical experience for connecting a lamina composed of molybdenum by means of LTC.
- For these reasons, none of the above proposals (a) to (c) has gained acceptance in practice heretofore.
- The problem of rapidly dissipating heat from a semiconductor chip occurs not only in the case of IGBTs but also, in principle, in the case of diodes in surge current operation. The semiconductor chip is destroyed in this case, too, if the energy generated in surge current operation cannot be dissipated fast enough from the semiconductor chip. The above considerations for IGBTs therefore hold true in the same way for diodes.
- During the fabrication of, in particular, IGBTs and diodes, a proton irradiation may be performed in order that deep dopant profiles or profiles with charge carriers having a reduced lifetime are incorporated into a semiconductor chip in a targeted manner. The fabrication of a field stop zone at a depth of 10 μm, for example, from the rear side of the chip by means of a proton irradiation shall be mentioned as an example. If, in this example, the proton irradiation is carried out from the rear side of the chip, then a strongly localized excessive increase in doping arises in the so-called “end-of-range region” of the proton implantation. This excessive increase in doping is then situated approximately at a distance of 10 μm from the rear side of the chip.
FIG. 2 of the accompanying drawings show such a profile of the doping concentration as a function of the depth from the rear side of the chip using a solid line, working with an energy of 750 keV in silicon and with an effective proton dose of 1e12 cm.sup.−2 in this case. - The strongly localized excessive increase in doping is unfavorable for the switching behavior of IGBTs and diodes, however, since an electric field that penetrates into the field stop zone, that is to say into the region with the strongly localized excessive increase in doping, is abruptly braked, which leads to a great increase in the voltage rise dU/dt. This great increase in dU/dt poses considerable difficulties in applications of IGBTs and diodes.
- For the switching behavior of IGBTs and diodes, it would therefore be significantly more favorable if the profile of the field stop zone, the so-called field stop profile, trailed off gently into the semiconductor chip. With a conventional proton implantation from the rear side of the chip, however, this is possible only when a plurality of implantations with different energies and thus different penetration depths are performed in a staggered manner. However, this constitutes a considerable outlay.
- As an alternative, thought has already been given to carrying out a proton implantation from the front side of the chip. The “end-of-range region” would be greatly widened in this case. However, it is then necessary to radiate through the entire drift zone of the semiconductor component. As a result of this radiating-through process, however, on the one hand, the doping in the drift zone is determined by the so-called “tail region” of the proton irradiation precisely in the case of semiconductor substrates having a very high resistance. On the other hand, the position of the proton peaks relative to the rear side of the chip becomes dependent on fluctuations in the thickness of the semiconductor substrate. Moreover, properties of oxide layers on the front side of the semiconductor chip may also be altered by the irradiation.
- Overall, then, proton irradiation both from the rear side of the chip and from the front side of the chip poses considerable problems that have not been solved heretofore.
- For targeted relief of the loading of the edge of diodes or IBGTs during dynamic switching, the HDR concept (HDR=high dynamic robustness) employed at the present time seeks to reduce the plasma flooding in the edge region of diodes, in particular. This reduction of the plasma flooding in the edge region relieves the loading of the latter during dynamic switching operations. This relief of loading is actually realized by means of a masked cathode implantation into the rear side of the chip below the active chip region, but not below the edge region. In other words, an injection of charge carriers below the edge region scarcely takes place as a result of this. What is disadvantageous about such a procedure, however, is the need for a phototechnology on the rear side of the chip as well in order thus to be able to perform the masked cathode implantation below the active region but not below the edge.
- If an irradiation technique is used for reducing the lifetime of the charge carriers in the edge region of a diode, then it is necessary, if a plurality of chips are present on a semiconductor wafer, also to apply a plurality of thick metal masks, the accurate alignment of which is very complicated.
- Proceeding from the above considerations, the invention is based on the object of specifying a metallization for power semiconductor components, in particular IGBTs and diodes, which—as far as IGBTs are concerned—improves the short circuit strength thereof with regard to destruction after a turn-off and which—as far as diodes are concerned—increases the surge current strength thereof; moreover, the intention is to readily enable a targeted widening of field stop profiles during fabrication by means of a proton irradiation; finally, the intention is also to ensure targeted relief of the loading of the edge region during dynamic switching and to specify a method for fabricating such a metallization.
- This object is achieved according to the invention by means of a metallization for power semiconductor components as described herein. The object is further achieved by a method of fabricating a power semiconductor component having a semiconductor body having at least two main surfaces. The method includes applying a layer of a metallization on at least one of the main surfaces, the layer having a thickness of at least 15 μm, the layer serving as a heat sink. The method also includes producing a field stop zone in the semiconductor body by implantation of protons or helium through the layer.
- The layer thickness of the at least one layer is at least 15 μm. It is preferably at least 20 μm.
- At least some embodiments of the invention are particularly advantageously applied to IGBTs and to diodes. In this case, the metallization according to the invention can be used to produce a field stop layer by proton irradiation from the rear side of the chip or wafer or for masking a proton or helium implantation from the front side of a semiconductor chip. In this respect, reference is made to
patent claims 10 to 15. Patent claim 16 specifies an advantageous method for fabricating the metallization. - In the case of the embodiments described herein, then, a material whose specific heat capacity is at least a factor of 1.3 higher than the specific heat capacity of the semiconductor chip is used for the at least one layer, that is to say for the emitter contact and/or the collector contact in the case of an IGBT, for example. The specific heat capacity of the material of said layer is preferably a factor of 2 greater than the specific heat capacity of the semiconductor chip. In any event, however, the specific thermal conductivity of the material of said layer should be greater than the specific thermal conductivity of the semiconductor chip. If the semiconductor chip is composed of silicon, by way of example, then the latter has a specific heat capacity of 1.63 J/(° K cm3). Copper, which has a specific heat capacity of 3.43 J/(° K cm3) is then preferably suitable as material for the at least one layer. Other materials that are likewise suitable are aluminum, silver and gold.
- The absolute thermal capacity of the at least one layer is preferably equal to at least 10% of the thermal capacity of the semiconductor chip.
- In the case of some embodiments of the invention, depositing a layer having a high thermal conductivity and specific heat capacity reduces the so-called thermal impedance “Zth” (Zth is a time-dependent impedance) of the semiconductor chip for short timescales. This results in an increased short circuit robustness of an IGBT and an enhanced surge current strength of a diode, which are otherwise both thermally limited per se. The implantation profile of the field stop zone is widened during implantation of protons through the layer on the rear side of the chip, by way of example. This in turn brings about a more favorable switching behavior of IGBTs and diodes.
- If the layer is deposited selectively onto metallizations that are already present on the front side of the chip, by way of example, then it can be utilized as masking for subsequent proton or helium implantations. In other words, a relief of the loading of the diode edge in a manner similar to the HDR concept can be achieved thereby. The layer can be electrodeposited or deposited by vapor deposition onto the rear side and/or front. side of the semiconductor chip.
- A significant advantage of at least some embodiments of the invention thus resides in the simultaneous reduction of Zth and the widening or masking of proton or helium implantations by means of a single measure, namely the application of the at least one layer to the at least one main surface.
- The invention is explained in more detail below with reference to the drawings, in which:
-
FIG. 1 shows a schematic sectional illustration through an IGBT according to the teaching of the invention, -
FIG. 2 shows a diagram revealing the widening of a field stop profile during a proton implantation through a copper layer having a thickness of approximately 50 μm, and -
FIG. 3 shows a bar chart with results from electrothermal component simulations for short circuit destruction of an IGBT for 1200 V after turn-off of a current pulse, showing various mounting variants (cf. upper half) and relative destruction energies (cf. lower half), in relation to the prior art (cf. variant 1). -
FIG. 1 shows a section through an IGBT having a semiconductor body orchip 1 made preferably of silicon or another suitable semiconductor material (e.g. SiC or AIIIBv). In thissemiconductor body 1, a p-conductingbase zone 3 is introduced into an n−-conductingbase zone 2, an n- or n+-conducting source oremitter zone 4 being situated in saidbase zone 3. Furthermore, thesemiconductor body 1 has an n- or n+-conductingfield stop zone 5 and also a p-conductingcollector zone 6. It goes without saying that the conduction types specified may also be respectively reversed. - If only the zones 3 (p-conducting), 2 (n−-conducting) and, if appropriate, 5 (n-conducting) are provided, then a diode is present. The
emitter zone 4 and thecollector zone 6 are therefore omitted in this case. The following considerations for an IGBT hold true in the same way for a diode having a construction of this type or a similar construction. - An insulating
layer 8 made, for example, of silicon dioxide and/or silicon nitride is situated on a firstmain surface 7 of thesemiconductor body 1. Agate electrode 9 made, in particular, of polycrystalline silicon is introduced into said insulatinglayer 8. A diode, of course, does not have such a gate electrode. - In the first
main surface 7, theemitter zone 4 and the p-type base zone 3 are contact-connected via a first contact (emitter contact) 10. - A second
main surface 11 of thesemiconductor body 1 opposite to the firstmain surface 7 is provided with a second contact (collector contact) 12. - A
diffusion barrier layer 13 made, for example, of Ti, TiN, Ta, TaN or combinations thereof may also be provided between thecollector zone 6, that is to say the secondmain surface 11 of thesemiconductor body 1, and thesecond contact 12. The combinations Ti/TiN and Ta/TaN are particularly preferred. Saiddiffusion barrier layer 13 protects the silicon of thesemiconductor body 1 against indiffusion of atoms from thecontact 12. - The
diffusion barrier layer 13 may, if appropriate, also be provided with analuminum layer 14, which further limits said indiffusion. Thelayer 14 may—as illustrated—be situated between thelayers main surface 11 and thelayer 13. - If appropriate, the
layers first contact 10. Moreover, thefirst contact 10 may be applied to a metallization already present, which is generally very thin and thus exhibits good thermal conduction. - In the case of an IGBT and also in the case of a diode, rapid dissipation of heat from the
semiconductor body 1 or the semiconductor chip is crucially accelerated according to the invention by virtue of the fact that sufficiently thick layers, namely thecontacts contacts semiconductor body 1 and their (absolute) thermal capacity should have a magnitude at least equal to half the thermal capacity of the semiconductor chip comprising thesemiconductor body 1. The specific thermal conductivity of the contacts should be greater than the specific thermal conductivity of thesemiconductor body 1. - A suitable material for these conditions for specific heat capacity and specific thermal conductivity is preferably copper, aluminum, silver or gold.
- If appropriate, these metals may also be “mixed” or used in alloys. In other words, in the case of the present invention, the layers of the
contacts semiconductor body 1 or to the insulatinglayer 8 as far as possible directly and if need be via thediffusion barrier layer 13 and thealuminum layer 14 or a metallization that is already present. - The layer thickness of the
contacts - It goes without saying that it is also possible to provide, instead of two copper layers for the
contacts contact 12, and thus to construct the contact in a customary manner. In this case, the thermal capacity of saidlayer 12 should have a magnitude at least equal to the thermal capacity of the semiconductor chip with thesemiconductor body 1. - The layers for the
contacts main surface 7, or in particular the rear side of the chip, that is to say themain surface 11. An additional heat sink preferably made of molybdenum can then be soldered onto the layer for thecontact 10 at the front side by means of solder, by way of example. This is done after a proton irradiation that may be provided has been performed through the layer for the contact 12 (cf.variant 5 inFIG. 3 explained further below). - As an alternative, the copper layer for the
contact 12 is deposited up to a thickness of 50 μm, for example. The proton irradiation is then effected through this layer. A further reinforcement of the copper layer is then possible by means of a further galvanic process (cf.variant 10 inFIG. 3 ). That is to say that the deposition of the copper layer is stopped in a targeted manner at a thickness such as is necessary for widening the proton profile, and after the irradiation. - In the case of an IGBT constructed according to the invention or a diode provided according to the invention and, if appropriate, also in the case of a transistor having the metallization according to the invention, the high thermal conductivity of the layers for the
corresponding contacts semiconductor chip 1, can be rapidly transferred into the thermal capacities of said layers. For subsequent heat sinks in accordance withvariants 5 to 7 and 10, it is then possible to employ the thermally non-optimum connecting technique by means of solder. - The layers for the
contacts contacts semiconductor body 1 composed of silicon of approximately 120 μm. - It should be noted that, instead of copper, aluminum, silver or gold, it is also possible, if appropriate, to choose a different material having similar properties to these materials. The invention is therefore not restricted to the use of these materials.
- The copper of the
contacts - If a proton implantation is effected from the rear side of the chip (or else the front side of the chip), that is to say via the main surface 11 (or respectively 7) of the
semiconductor body 1 for the purpose of forming thefield stop zone 5, then the implantation profile is greatly widened—as has been shown—by virtue of the copper layer of thecontact 12. A heat treatment in the range of approximately 350° C. to 450° C. subsequent to the implantation then leads to the doping effect of the proton implantation, thus giving rise to thelayer 5 effecting the field stop. Such afield stop layer 5 is preferably used for IGBTs and diodes. -
FIG. 2 uses a dashed line to show this widening effect for an effective proton dose of 1e12 cm.sup.−2 at an implantation energy of 3.9 MeV through a 50 μm thick copper layer in a silicon body. If the profile of this curve is compared with the profile of the curve for an implantation at 750 keV without a copper layer in a silicon body, then the considerable widening of the implantation profile is immediately apparent. Strongly localized excessive increases in doping are thus avoided, thereby considerably improving the switching behavior of IGBTs and diodes in the case of an implantation for the field stop layer through a copper layer having a thickness of approximately 50 μm. With the gentle doping profile, the electric field is not braked abruptly, with the result that great increases in the voltage rise dU/dt do not occur in this case. - The implantation of protons through the copper layer having a thickness of 20 to 60 μm and preferably approximately 50 μm thus effects a field stop profile that runs up gently in the semiconductor chip, which could otherwise only be achieved by means of a plurality of stacked implantations with different energies in conventional proton implantation technology.
- The use of the copper layers for the contacts thus affords a considerable advantage besides the good dissipation of heat for the implantation: multiple implantations can be avoided in a surprisingly simple manner.
- In the fabrication of diodes, on the front side of the chip, that is to say on the
main surface 7 of thesemiconductor 1, the active chip area, that is to say the area in the region of thezone 3, is covered by the copper layer of thecontact 10. - If a proton or helium implantation is then carried out from the front side of the chip, then said copper layer of the
contact 10 acts as masking which stops a proton implantation which, without masking, would penetrate up to 100 μm into the silicon of thesemiconductor 1. - If such an implantation and a subsequent heat treatment for a number of hours are performed at temperatures lying between 220° C. and 350° C., then a charge carrier lifetime reduction is achieved in the edge region of the semiconductor chip, that is to say in the region outside the
contact 10. As a consequence, the plasma concentration is thus reduced below the edge of the diode as a result of recombination, which means a dynamic relief of the loading of the edge. - In other words without additional phototechnology as in the case of HDR (cf. above), the material, in particular copper, of the layer forming the
contact 10 achieves a masking of the implantation and thus a reduced plasma flooding in the edge. Said additional phototechnology is not necessary since the material for the layer forming thecontact 10 can be applied to the front side of the semiconductor body in a self-aligned manner by means of selective deposition. -
FIG. 3 which has already been discussed a number of times above, illustrates the advantages of the invention specifically with regard to the relative destruction energy (cf. the lower half ofFIG. 3 ). - In detail,
variant 1 shows the present-day prior art: A chip CH is applied over a solder layer and a copper layer on ceramic.Variants variant 2, the copper layer of the substrate ceramic is connected to the semiconductor chip CH via an LTC layer. Invariant 4, the semiconductor chip CH has an LTC layer on both sides, which is connected to a molybdenum lamina on the front side of the chip and to the DCB ceramic on the rear side of the chip. -
Variant 3 shows a case in which—as explained in the introduction—the rear side of the chip is contact-connected in accordance withvariant 1, while the front side of the chip is connected to a molybdenum lamina via a solder layer. -
Variants 5 to 10 in each case use the metallization according to the invention. Invariant 5, a copper layer having a thickness of approximately 50 μm is applied to the semiconductor chip CH on both sides, which copper layer is provided with a molybdenum lamina via a solder layer on the front side of the chip and with a further copper layer likewise via a solder layer on the rear side of the chip.Variant 6 differs fromvariant 5 in that the solder layer and the molybdenum lamina are omitted on the front side of the chip. Invariant 7, the copper layer is also absent on the front side of the chip.Variant 8 corresponds tovariant 6 with regard to the front side of the chip. On the rear side of the chip in the case ofvariant 8, however, the copper layer is connected to the semiconductor chip CH via a solder layer in a conventional manner.Variants variant 9 with a DCB ceramic connected by a solder layer, while invariant 10 it has a copper layer which is applied directly to the rear side of the chip and is again provided with the DCB ceramic via a solder layer. -
Variant 6 constitutes a particularly preferred variant according to the invention: This is because it is possible in this case to retain the conventional connecting technique that only a pure optimization is performed at the chip level. The copper layers having a thickness of approximately 50 μm that are provided on both sides in this variant act as short-term heat sinks and are distinctly superior to soldering on a molybdenum lamina, for instance according tovariant 3. - If
variant 6 is compared with the prior art in accordance withvariant 1, then an increase in the relative destruction energy from 100% (prior art) to approximately 175% (invention) is apparent. That is to say that the semiconductor component provided with the metallization according to the invention is not destroyed until at a dissipated energy amplified by a factor of 1.75. In other words, components configured in accordance with the present invention can be loaded to a significantly greater extent during operation. - Additional heat sinks, for instance in accordance with
variant 5, may provide for a further significant improvement by soldering on the molybdenum lamina. A subsequent reinforcement of the copper, as invariant 10, is likewise possible. The efficacy forvariant 10, which has not yet been definitively determined, should lie betweenvariants - To summarize, at least some embodiments of the invention provide a metallization which carries away dissipated thermal energy in an outstanding manner from a component in the event of a turn-off or surge loading thereof. This metallization may additionally be utilized, on the rear side of the chip, for the proton implantation for widening the field stop profile and, on the front side of the chip, as masking for a proton or helium implantation for the targeted incorporation of recombination centers below the edge region specifically of diodes.
- It will be appreciated that the above-described embodiments are merely illustrative, and that those of ordinary skill in the art may readily devise their own implementations and modifications that incorporate the principles of the present invention and fall within the spirit and scope thereof.
Claims (18)
1. A vertical power semiconductor component comprising:
a semiconductor chip having a top main surface at a front side of the semiconductor chip, wherein the top main surface is in a heat exchanging relationship with at least one layer serving as a heat sink, said at least one layer having a layer thickness of at least 15 μm and having a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip, and further comprising metallizations between the at least one layer and the top main surface.
2. The vertical power semiconductor component of claim 1 , wherein the at least one layer serving as the heat sink is electrically coupled to the semiconductor chip.
3. The vertical power semiconductor component of claim 2 , wherein the at least one layer serving as the heat sink forms an electrical contact for the vertical power semiconductor component.
4. The vertical power semiconductor component of claim 2 , wherein the at least one layer serving as the heat sink either directly contacts the top main surface or indirectly contacts the top main surface via a diffusion barrier layer.
5. The vertical power semiconductor component of claim 4 , wherein the diffusion barrier layer is formed from at least one of the group consisting of Ti, TiN, Ta, TaN and Al.
6. The vertical power semiconductor component of claim 5 , wherein the diffusion barrier layer is formed by a first sublayer composed of Ti/TiN or Ta/TaN, and a second sublayer composed of Al.
7. The vertical power semiconductor component of claim. claim 1 , wherein at least one layer serving as the heat sink is formed from at least one of the group consisting of copper, aluminum, silver and gold.
8. The vertical power semiconductor component of claim 1 , wherein at least one layer serving as the heat sink has a layer thickness of 20 to 60 μm.
9. A vertical power semiconductor component comprising:
a semiconductor chip having a bottom main surface at a rear side of the semiconductor chip, wherein the bottom main surface is in a heat exchanging relationship with at least one layer serving as a heat sink, said at least one layer having a layer thickness of at least 15 μm and having a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip.
10. The vertical power semiconductor component of claim 9 , wherein the at least one layer serving as the heat sink forms is electrically coupled to the semiconductor chip.
11. The vertical power semiconductor component of claim 10 , wherein the at least one layer serving as the heat sink forms an electrical contact for the vertical power semiconductor component.
12. The vertical power semiconductor component of claim 10 , wherein the at least one layer serving as the heat sink either directly contacts the bottom main surface or indirectly contacts the bottom main surface via a diffusion barrier layer.
13. The vertical power semiconductor component of claim 12 , wherein the diffusion barrier layer is formed from at least one of the group consisting of Ti, TiN, Ta, TaN and Al.
14. The vertical power semiconductor component of claim 13 , wherein the diffusion barrier layer is formed by a first sublayer composed of Ti/TiN or Ta/TaN, and a second sublayer composed of Al.
15. The vertical power semiconductor component of claim 9 , wherein at least one layer serving as the heat sink is formed from at least one of the group consisting of copper, aluminum, silver and gold.
16. The vertical power semiconductor component of claim 9 , wherein at least one layer serving as the heat sink has a layer thickness of 20 to 60 μm.
17. A power semiconductor component, comprising:
a chip;
a substrate ceramic including a copper layer; and wherein the copper layer of the substrate ceramic is connected to the semiconductor chip via a low-temperature connecting technique (LTC) layer.
18. The power semiconductor component of claim 17 , wherein the chip includes metallizations.
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Also Published As
Publication number | Publication date |
---|---|
US20180047815A1 (en) | 2018-02-15 |
US8314019B2 (en) | 2012-11-20 |
US10535743B2 (en) | 2020-01-14 |
DE102004012818B3 (en) | 2005-10-27 |
US20110300707A1 (en) | 2011-12-08 |
US8008712B2 (en) | 2011-08-30 |
US20050215042A1 (en) | 2005-09-29 |
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