US20120198145A1 - Memory access apparatus and display using the same - Google Patents

Memory access apparatus and display using the same Download PDF

Info

Publication number
US20120198145A1
US20120198145A1 US13/442,868 US201213442868A US2012198145A1 US 20120198145 A1 US20120198145 A1 US 20120198145A1 US 201213442868 A US201213442868 A US 201213442868A US 2012198145 A1 US2012198145 A1 US 2012198145A1
Authority
US
United States
Prior art keywords
memory
clients
buffer area
management unit
dynamic memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/442,868
Inventor
Chung-wen Hung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novatek Microelectronics Corp
Original Assignee
Novatek Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Novatek Microelectronics Corp filed Critical Novatek Microelectronics Corp
Priority to US13/442,868 priority Critical patent/US20120198145A1/en
Publication of US20120198145A1 publication Critical patent/US20120198145A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663Access to shared memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1673Details of memory controller using buffers

Definitions

  • the present invention generally relates to a memory access apparatus, in particular, to a memory access apparatus and a display using the same.
  • DRAM dynamic random access memory
  • FIG. 1 is a schematic view of a conventional memory access apparatus 100 .
  • clients 130 , 140 in the memory access apparatus 100 intend to perform a writing action for a dynamic memory 110 . Since two writing actions cannot be performed on the same dynamic memory 110 at the same time, the clients 130 , 140 respectively write the data in corresponding buffers 131 , 141 .
  • a memory management unit 120 detects whether the dynamic memory 110 is idle or not. Once the dynamic memory 110 is found to be idle, the data temporarily stored in the buffers 131 , 141 is sequentially written in the dynamic memory 110 .
  • clients 150 - 180 intend to read data from the dynamic memory 110 .
  • the dynamic memory 110 does not support reading data by so many clients simultaneously, and thus, the memory management unit 120 pre-fetches the data to be read by the clients 150 - 180 when the dynamic memory 110 is idle, and stores the data in buffers 151 - 181 . Once the clients 150 - 180 need to read the data, they simply read the data in the corresponding buffers 151 - 181 .
  • the memory access apparatus 100 should dispose buffers corresponding to the number of clients, and as a result, the conventional memory access apparatus 100 is always disposed with a large amount of buffers. Moreover, the resources of the buffers cannot be shared among each other, such that the buffers have a low efficiency, thereby severely increasing the manufacturing cost.
  • the present invention is directed to a memory access apparatus, which enables a plurality of clients to effectively access a dynamic memory, and to increase an available bandwidth thereof.
  • the present invention is also directed to a memory access apparatus used for a display, which enables a plurality of clients in the display to access a dynamic memory at a maximum bandwidth.
  • the present invention provides a memory access apparatus, which includes a dynamic memory and a memory management unit.
  • the dynamic memory is used to store a plurality of memory data
  • the memory management unit is coupled to the dynamic memory.
  • the memory management unit has a plurality of connection ports and each connection port is connected to a corresponding client.
  • the memory management unit stores a priority as a sequence for the clients to access the dynamic memory.
  • at least one buffer area is built in the memory management unit, so as to temporarily store a plurality of buffer data generated while the access action is performed.
  • the present invention provides a display using a memory access apparatus.
  • the memory access apparatus includes a dynamic memory and a memory management unit.
  • the dynamic memory is used to store a plurality of memory data, and the memory management unit is coupled to the dynamic memory.
  • the memory management unit has a plurality of connection ports and each connection port is connected to a corresponding client.
  • the memory management unit stores a priority as a sequence for the clients to access the dynamic memory.
  • at least one buffer area is built in the memory management unit, so as to temporarily store a plurality of buffer data generated while the access action is performed.
  • buffer areas are built in the memory management unit, such that the data required by a plurality of clients to access the same dynamic memory can be stored in the buffer areas in advance, and then allocated according to the bandwidths and priorities of the clients, thereby achieving the purpose of enabling a plurality of clients to access the same dynamic memory simultaneously, without disposing an exclusive buffer for each client, thereby effectively reducing the circuit area.
  • FIG. 1 is a schematic view of a conventional memory access apparatus 100 .
  • FIG. 2 shows an embodiment of a memory access apparatus of the present invention.
  • FIG. 3 shows a buffer area configuration according to an embodiment of the present invention.
  • FIG. 4 is a schematic view of adjusting the buffer area.
  • FIG. 5 shows a memory access apparatus used in a display according to an embodiment of the present invention.
  • FIG. 2 shows a memory access apparatus according to an embodiment of the present invention.
  • the memory access apparatus 200 includes a dynamic memory 210 , a memory management unit 220 , clients 231 - 236 , and a control unit 240 .
  • the dynamic memory 210 is used for the clients 231 - 236 to store data, and it is the memory management unit 220 that performs actual access actions for the dynamic memory 210 .
  • the memory management unit 220 has a plurality of connection ports, and each connection port is respectively connected to a corresponding client 231 - 236 .
  • the memory management unit 220 further includes a buffer area 221 built therein, and the buffer area 221 is used to store buffer data generated while the clients 231 - 236 perform reading or writing operation for the dynamic memory 210 .
  • the buffer area 221 is used to store buffer data generated while the clients 231 - 236 perform reading or writing operation for the dynamic memory 210 .
  • the data to be written by the clients 231 and 232 is temporarily stored in the buffer area 221 .
  • the memory management unit 220 writes the data temporarily stored in the buffer area 221 to the dynamic memory 210 until the dynamic memory 210 is idle.
  • the memory management unit 220 pre-fetches the data to be read by the clients 233 , 234 , 235 , and 236 from the dynamic memory 210 to the buffer area 221 when the dynamic memory 210 is idle. Once the clients 233 , 234 , 235 , and 236 need to read the data in the dynamic memory 210 , they may simply read the data from the buffer area 221 .
  • the memory management unit 220 arranges to perform the above actions according to a priority stored therein.
  • the priority is determined according to the importance of the clients 231 - 236 .
  • the access action required by the client with a higher priority should be performed first. For example, when both the client 231 and the client 232 intend to write data to the dynamic memory 210 , the data to be written is then stored in the buffer area 221 .
  • the memory management unit 220 finds that the dynamic memory 210 is idle, it writes the data of the client 231 with a higher priority (assuming the client 231 has a higher priority than the client 232 ) temporarily stored in the buffer area 221 to the dynamic memory 210 first, and then writes the data of the client 232 temporarily stored in the buffer area 221 to the dynamic memory 210 .
  • the memory management unit 220 may include more than one buffer area. Two or more buffer areas may be partitioned in usage according to the demand of different clients requiring reading and writing actions.
  • the buffer area 221 is generally partitioned into a plurality of sub-buffer areas (not shown in FIG. 2 ) corresponding to the clients 231 - 236 .
  • the control unit 240 coupled to the clients 231 - 236 and the memory management unit 220 , is used to adjust the sizes of the sub-buffer areas. The detailed operations are described herein below.
  • FIG. 3 shows a buffer area configuration according to an embodiment of the present invention.
  • the buffer area 321 is partitioned into six sub-buffer areas 3211 , 3212 , 3213 , 3214 , 3215 , and 3216 corresponding to the clients 331 , 332 , 333 , 334 , 335 , and 336 .
  • the embodiment in FIG. 3 corresponds to the description about the embodiment in FIG.
  • the client 331 when the client 331 intends to perform a writing action for the dynamic memory, it temporarily stores the data to be written in the buffer area, that is, temporarily stores the data to be written in the corresponding sub-buffer area 3211 (similarly, when the client 332 intends to perform a writing action for the dynamic memory, it temporarily stores the data to be written in the corresponding sub-buffer area 3212 ).
  • the clients 331 - 336 have different requirements on data in the dynamic memory 310 , so that the capacities of the sub-buffer areas 3211 - 3216 corresponding to the clients should be adjusted dynamically.
  • the control unit 340 is used for dynamically adjusting the capacities of the sub-buffer areas 3211 - 3216 .
  • the control unit 340 determines the size of the sub-buffer area correspondingly required by the client according to the priority of the client and according to the frequency for the client to perform reading and writing actions for the dynamic memory 310 .
  • the memory management unit 320 always processes the data of the client with a higher priority first. Therefore, the sub-buffer area corresponding to the client with a higher priority generally has less data under process stored therein. In other words, the client with a higher priority does not need a large sub-buffer area. In contrast, the client with a lower priority requires a larger sub-buffer area (the priority is inversely proportional to the capacity of the sub-buffer area). In addition, the frequency for the client to perform reading and writing actions for the dynamic memory 310 is also an important factor for determining the size of the sub-buffer area. It is obvious that the client with a higher read/write frequency requires a larger sub-buffer area. Alternatively, the client with a lower read/write frequency merely needs a smaller sub-buffer area.
  • the dynamic adjustment of the buffer area is illustrated through an example below, which aims at demonstrating the dynamic adjustment of the size of the sub-buffer area in detail.
  • FIG. 4 is a schematic view of adjusting the buffer area.
  • the buffer area of the memory management unit 420 is respectively partitioned into sub-buffer areas 4311 , 4312 , 4313 , 4314 , 4315 , and 4316 according to the clients 431 , 432 , 433 , 434 , 435 , and 436 .
  • the priority of the client 431 is higher than that of the client 432 , so that the capacity of the sub-buffer area 4311 is smaller than that of the sub-buffer area 4312 .
  • the client 433 has the highest priority, followed by the client 434 and the client 435 , and the client 436 has the lowest priority.
  • the sub-buffer area 4316 has the largest capacity, followed by the sub-buffer area 4315 and the sub-buffer area 4314 , and the sub-buffer area 4313 has the smallest capacity.
  • the capacities of the sub-buffer areas can also be adjusted according to the frequencies for the clients to access the dynamic memory during the actual operation of the memory access apparatus.
  • the priorities of the clients can also be adjusted during the operation of the memory access apparatus, that is to say, the sub-buffer areas can be adjusted dynamically and flexibly, so as to make full use of the buffer area.
  • FIG. 5 shows a memory access apparatus used in a display according to an embodiment of the present invention.
  • the memory access apparatus 500 used in a display includes a dynamic memory 510 , a memory management unit 520 , a control unit 540 , and a plurality of clients.
  • the memory management unit 520 has a buffer area 521 .
  • the clients include a 3D comb filter 531 , a display 532 , a direct memory access 533 , an over-driver 534 , and a de-interleaver 535 respectively performing a writing action for the dynamic memory.
  • the clients further include a display 536 , a direct memory access 537 , an over-driver 538 , and a de-interleaver 539 respectively performing a reading action for the dynamic memory (in this embodiment, the same electronic device is considered as two different clients when respectively performing a writing action and a reading action for the dynamic memory, for example, the display 532 and the display 536 ).
  • the operations of the memory access apparatus 500 used in a display are similar to that of the above memory access apparatus 200 , which can be understood by those ordinarily skilled in the art through derivation, and will not be repeatedly described herein.
  • the data-accessing frequency required by the 3 clients is 200 million bits/second (Mb/s), and they need to wait for 0.5 seconds to access the dynamic memory.
  • Three independent buffer areas each having a capacity of 1500 Mb are designed in the prior art, when another application occurs (for example, two input ends are both 720 p, and the output end is 1440 p panel), the data-accessing frequencies required by the 3 clients are 100 Mb/s, 100 Mb/s, and 400 Mb/s respectively.
  • the buffer areas are managed integrally, and the resources are allocated dynamically according to requirements.
  • the present invention enables a plurality of clients to access the same dynamic memory through utilizing the buffer area built in the memory management unit, and dynamically adjusts the capacity of each sub-buffer area in the buffer area to improve the utilization performance of the buffer area, thereby more effectively accessing the memory. Moreover, no external buffers corresponding to the clients are required, and the production cost is thus reduced.

Abstract

A memory access apparatus and a display using the same are provided. The memory access apparatus includes a dynamic memory, a plurality of clients and a memory management unit. The dynamic memory is used to store a plurality of memory data. The clients access the dynamic memory and each client has a priority. The memory management unit executes an access action of the clients for the dynamic memory respectively according to the priorities thereof. Besides, the memory management unit has at least one buffer area built therein. The buffer area is used to temporarily store a plurality of buffer data generated while the access action is performed.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 12/369,755, filed on Feb. 12, 2009, now pending. The prior application Ser. No. 12/369,755 claims the priority benefit of Taiwan application serial no. 97113616, filed on Apr. 15, 2008. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of specification.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a memory access apparatus, in particular, to a memory access apparatus and a display using the same.
  • 2. Description of Related Art
  • Current electronic systems all need memories to store data, and thus dynamic memories with a large capacity, such as dynamic random access memory (DRAM), are frequently used. However, such dynamic memories have a complicated accessing action, and generally, more than one electronic device (referred to as client hereinafter) in the same electronic system requires accessing the dynamic memory. Therefore, when a plurality of clients needs to access the dynamic memory simultaneously, a buffer must be disposed corresponding to each client for assisting the access action.
  • FIG. 1 is a schematic view of a conventional memory access apparatus 100. Referring to FIG. 1, clients 130, 140 in the memory access apparatus 100 intend to perform a writing action for a dynamic memory 110. Since two writing actions cannot be performed on the same dynamic memory 110 at the same time, the clients 130, 140 respectively write the data in corresponding buffers 131, 141. A memory management unit 120 detects whether the dynamic memory 110 is idle or not. Once the dynamic memory 110 is found to be idle, the data temporarily stored in the buffers 131, 141 is sequentially written in the dynamic memory 110.
  • In addition, clients 150-180 intend to read data from the dynamic memory 110. Similarly, the dynamic memory 110 does not support reading data by so many clients simultaneously, and thus, the memory management unit 120 pre-fetches the data to be read by the clients 150-180 when the dynamic memory 110 is idle, and stores the data in buffers 151-181. Once the clients 150-180 need to read the data, they simply read the data in the corresponding buffers 151-181.
  • As can be known from the above that, the memory access apparatus 100 should dispose buffers corresponding to the number of clients, and as a result, the conventional memory access apparatus 100 is always disposed with a large amount of buffers. Moreover, the resources of the buffers cannot be shared among each other, such that the buffers have a low efficiency, thereby severely increasing the manufacturing cost.
  • SUMMARY OF THE INVENTION
  • Accordingly, the present invention is directed to a memory access apparatus, which enables a plurality of clients to effectively access a dynamic memory, and to increase an available bandwidth thereof.
  • The present invention is also directed to a memory access apparatus used for a display, which enables a plurality of clients in the display to access a dynamic memory at a maximum bandwidth.
  • The present invention provides a memory access apparatus, which includes a dynamic memory and a memory management unit. The dynamic memory is used to store a plurality of memory data, and the memory management unit is coupled to the dynamic memory. The memory management unit has a plurality of connection ports and each connection port is connected to a corresponding client. The memory management unit stores a priority as a sequence for the clients to access the dynamic memory. When the client accesses the dynamic memory, at least one buffer area is built in the memory management unit, so as to temporarily store a plurality of buffer data generated while the access action is performed.
  • In addition, the present invention provides a display using a memory access apparatus. The memory access apparatus includes a dynamic memory and a memory management unit. The dynamic memory is used to store a plurality of memory data, and the memory management unit is coupled to the dynamic memory. The memory management unit has a plurality of connection ports and each connection port is connected to a corresponding client. The memory management unit stores a priority as a sequence for the clients to access the dynamic memory. When the client accesses the dynamic memory, at least one buffer area is built in the memory management unit, so as to temporarily store a plurality of buffer data generated while the access action is performed.
  • According to the present invention, buffer areas are built in the memory management unit, such that the data required by a plurality of clients to access the same dynamic memory can be stored in the buffer areas in advance, and then allocated according to the bandwidths and priorities of the clients, thereby achieving the purpose of enabling a plurality of clients to access the same dynamic memory simultaneously, without disposing an exclusive buffer for each client, thereby effectively reducing the circuit area.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 is a schematic view of a conventional memory access apparatus 100.
  • FIG. 2 shows an embodiment of a memory access apparatus of the present invention.
  • FIG. 3 shows a buffer area configuration according to an embodiment of the present invention.
  • FIG. 4 is a schematic view of adjusting the buffer area.
  • FIG. 5 shows a memory access apparatus used in a display according to an embodiment of the present invention.
  • DESCRIPTION OF THE EMBODIMENTS
  • Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
  • FIG. 2 shows a memory access apparatus according to an embodiment of the present invention. Referring to FIG. 2, the memory access apparatus 200 includes a dynamic memory 210, a memory management unit 220, clients 231-236, and a control unit 240. The dynamic memory 210 is used for the clients 231-236 to store data, and it is the memory management unit 220 that performs actual access actions for the dynamic memory 210.
  • The memory management unit 220 has a plurality of connection ports, and each connection port is respectively connected to a corresponding client 231-236. The memory management unit 220 further includes a buffer area 221 built therein, and the buffer area 221 is used to store buffer data generated while the clients 231-236 perform reading or writing operation for the dynamic memory 210. Taking the clients 231 and 232 performing a writing action for the dynamic memory 210 as an example, if the dynamic memory 210 is busy when the writing action is performed, the writing action of the clients 231 and 232 cannot be performed immediately. Therefore, the data to be written by the clients 231 and 232 is temporarily stored in the buffer area 221. The memory management unit 220 writes the data temporarily stored in the buffer area 221 to the dynamic memory 210 until the dynamic memory 210 is idle.
  • Moreover, the memory management unit 220 pre-fetches the data to be read by the clients 233, 234, 235, and 236 from the dynamic memory 210 to the buffer area 221 when the dynamic memory 210 is idle. Once the clients 233, 234, 235, and 236 need to read the data in the dynamic memory 210, they may simply read the data from the buffer area 221.
  • It should be noted that, the memory management unit 220 arranges to perform the above actions according to a priority stored therein. Herein, the priority is determined according to the importance of the clients 231-236. Definitely, in terms of the priority, the access action required by the client with a higher priority should be performed first. For example, when both the client 231 and the client 232 intend to write data to the dynamic memory 210, the data to be written is then stored in the buffer area 221. Once the memory management unit 220 finds that the dynamic memory 210 is idle, it writes the data of the client 231 with a higher priority (assuming the client 231 has a higher priority than the client 232) temporarily stored in the buffer area 221 to the dynamic memory 210 first, and then writes the data of the client 232 temporarily stored in the buffer area 221 to the dynamic memory 210.
  • Moreover, the memory management unit 220 may include more than one buffer area. Two or more buffer areas may be partitioned in usage according to the demand of different clients requiring reading and writing actions.
  • In order to process the data temporarily stored in the buffer area 221 more efficiently and orderly, the buffer area 221 is generally partitioned into a plurality of sub-buffer areas (not shown in FIG. 2) corresponding to the clients 231-236. The control unit 240, coupled to the clients 231-236 and the memory management unit 220, is used to adjust the sizes of the sub-buffer areas. The detailed operations are described herein below.
  • FIG. 3 shows a buffer area configuration according to an embodiment of the present invention. Referring to FIG. 3, the buffer area 321 is partitioned into six sub-buffer areas 3211, 3212, 3213, 3214, 3215, and 3216 corresponding to the clients 331, 332, 333, 334, 335, and 336. Corresponding to the description about the embodiment in FIG. 2, when the client 331 intends to perform a writing action for the dynamic memory, it temporarily stores the data to be written in the buffer area, that is, temporarily stores the data to be written in the corresponding sub-buffer area 3211 (similarly, when the client 332 intends to perform a writing action for the dynamic memory, it temporarily stores the data to be written in the corresponding sub-buffer area 3212).
  • The clients 331-336 have different requirements on data in the dynamic memory 310, so that the capacities of the sub-buffer areas 3211-3216 corresponding to the clients should be adjusted dynamically. The control unit 340 is used for dynamically adjusting the capacities of the sub-buffer areas 3211-3216. The control unit 340 determines the size of the sub-buffer area correspondingly required by the client according to the priority of the client and according to the frequency for the client to perform reading and writing actions for the dynamic memory 310.
  • The memory management unit 320 always processes the data of the client with a higher priority first. Therefore, the sub-buffer area corresponding to the client with a higher priority generally has less data under process stored therein. In other words, the client with a higher priority does not need a large sub-buffer area. In contrast, the client with a lower priority requires a larger sub-buffer area (the priority is inversely proportional to the capacity of the sub-buffer area). In addition, the frequency for the client to perform reading and writing actions for the dynamic memory 310 is also an important factor for determining the size of the sub-buffer area. It is obvious that the client with a higher read/write frequency requires a larger sub-buffer area. Definitely, the client with a lower read/write frequency merely needs a smaller sub-buffer area.
  • The dynamic adjustment of the buffer area is illustrated through an example below, which aims at demonstrating the dynamic adjustment of the size of the sub-buffer area in detail.
  • FIG. 4 is a schematic view of adjusting the buffer area. Referring to FIG. 4, the buffer area of the memory management unit 420 is respectively partitioned into sub-buffer areas 4311, 4312, 4313, 4314, 4315, and 4316 according to the clients 431, 432, 433, 434, 435, and 436. In this embodiment, the priority of the client 431 is higher than that of the client 432, so that the capacity of the sub-buffer area 4311 is smaller than that of the sub-buffer area 4312. In addition, among the clients 433-436, the client 433 has the highest priority, followed by the client 434 and the client 435, and the client 436 has the lowest priority. Thus, among the sub-buffer areas 4313-4316, the sub-buffer area 4316 has the largest capacity, followed by the sub-buffer area 4315 and the sub-buffer area 4314, and the sub-buffer area 4313 has the smallest capacity.
  • Definitely, the capacities of the sub-buffer areas can also be adjusted according to the frequencies for the clients to access the dynamic memory during the actual operation of the memory access apparatus. The priorities of the clients can also be adjusted during the operation of the memory access apparatus, that is to say, the sub-buffer areas can be adjusted dynamically and flexibly, so as to make full use of the buffer area.
  • FIG. 5 shows a memory access apparatus used in a display according to an embodiment of the present invention. Referring to FIG. 5, the memory access apparatus 500 used in a display includes a dynamic memory 510, a memory management unit 520, a control unit 540, and a plurality of clients. The memory management unit 520 has a buffer area 521. In this embodiment, the clients include a 3D comb filter 531, a display 532, a direct memory access 533, an over-driver 534, and a de-interleaver 535 respectively performing a writing action for the dynamic memory. The clients further include a display 536, a direct memory access 537, an over-driver 538, and a de-interleaver 539 respectively performing a reading action for the dynamic memory (in this embodiment, the same electronic device is considered as two different clients when respectively performing a writing action and a reading action for the dynamic memory, for example, the display 532 and the display 536).
  • The operations of the memory access apparatus 500 used in a display are similar to that of the above memory access apparatus 200, which can be understood by those ordinarily skilled in the art through derivation, and will not be repeatedly described herein.
  • In terms of the architecture of the above memory access apparatus used for a display, taking a high definition television (HDTV) as an example, 3 clients are assumed to be existed, in a certain application (for example, two input ends are both the 1080 p signal source and the output end is a 1080 p panel), the data-accessing frequency required by the 3 clients is 200 million bits/second (Mb/s), and they need to wait for 0.5 seconds to access the dynamic memory. When the memory access apparatus used for a display is operated stably, and the bandwidth of the dynamic memory is assumed to be 750 Mb/s, the sub-buffer area required by each of the 3 clients is 1500 Mb. Therefore, the size of the required buffer area is three times of 1500 Mb, that is, 4500 Mb, and at this time, the utilization efficiency of the dynamic memory is 600/750*100%=80%.
  • Three independent buffer areas each having a capacity of 1500 Mb are designed in the prior art, when another application occurs (for example, two input ends are both 720 p, and the output end is 1440 p panel), the data-accessing frequencies required by the 3 clients are 100 Mb/s, 100 Mb/s, and 400 Mb/s respectively. However, under the limit of the hardware (three independent buffer areas each having a capacity of 1500 Mb), the operation can be performed correctly only after the bandwidth of the dynamic memory reaches 794 Mb/s (at this time, each of the 720 p clients requires 1228 Mb, and the 1440 p client requires 1500 Mb). At this time, the bandwidth utilization of the dynamic memory is reduced to 600/794*100%=75.6%.
  • Through the present invention, the buffer areas are managed integrally, and the resources are allocated dynamically according to requirements. When being applied to the above example (two input ends are both 720 p, and the output end is 1440 p panel), the bandwidth utilization of the dynamic memory of 600/750*100%=80% can still be achieved, and at this time, the buffer area required by each 720 p client is 1000 Mb, the buffer area required by the 1440 p client is 2000 Mb, and they are all together 4000 Mb, which is much less than that of the prior art (two input ends are both 1080 p signal sources, and the output end is 1080 p panel).
  • In view of the above, the present invention enables a plurality of clients to access the same dynamic memory through utilizing the buffer area built in the memory management unit, and dynamically adjusts the capacity of each sub-buffer area in the buffer area to improve the utilization performance of the buffer area, thereby more effectively accessing the memory. Moreover, no external buffers corresponding to the clients are required, and the production cost is thus reduced.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (42)

1. A memory access apparatus, comprising:
a dynamic memory, for storing a plurality of memory data; and
a memory management unit, coupled to the dynamic memory, wherein the memory management unit has a plurality of connection ports, and each of the connection ports is directly connected between a corresponding client and at least one buffer area, the connection ports are used for providing the clients to access the buffer directly; the memory management unit stores a priority as a sequence for the clients to access the dynamic memory; and when the clients access the dynamic memory, the buffer area is built in the memory management unit to store temporarily a plurality of buffer data generated while an access action is performed.
wherein the memory management unit partitions the buffer area into a plurality of sub-buffer areas corresponding to the clients, and a capacity of each sub-buffer area depends on the priority corresponding to each client.
2. The memory access apparatus according to claim 1, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the buffer area.
3. The memory access apparatus according to claim 1, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the buffer area by the memory management unit.
4. The memory access apparatus according to claim 1, further comprising a control unit, coupled to the clients and the memory management unit, for dynamically adjusting the capacity of each sub-buffer area corresponding to each client according to the priority for the client to access the dynamic memory.
5. The memory access apparatus according to claim 1, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the corresponding sub-buffer area.
6. The memory access apparatus according to claim 1, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the sub-buffer area corresponding to the client by the memory management unit.
7. A memory access apparatus, comprising:
a dynamic memory, for storing a plurality of memory data; and
a memory management unit, coupled to the dynamic memory, wherein the memory management unit has a plurality of connection ports, and each of the connection ports is directly connected between a corresponding client and at least one buffer area, the connection ports are used for providing the clients to access the buffer directly; the memory management unit stores a priority as a sequence for the clients to access the dynamic memory; and when the clients access the dynamic memory, the buffer area is built in the memory management unit to store temporarily a plurality of buffer data generated while an access action is performed,
wherein the memory management unit partitions the buffer area into a plurality of sub-buffer areas corresponding to the clients, and a capacity of each sub-buffer area depends on the frequency of using the dynamic memory corresponding to each client.
8. The memory access apparatus according to claim 7, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the buffer area.
9. The memory access apparatus according to claim 7, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the buffer area by the memory management unit.
10. The memory access apparatus according to claim 7, further comprising a control unit, coupled to the clients and the memory management unit, for dynamically adjusting the capacity of each sub-buffer area depends on the frequency of using the dynamic memory corresponding to each client.
11. The memory access apparatus according to claim 7, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the corresponding sub-buffer area.
12. The memory access apparatus according to claim 7, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the sub-buffer area corresponding to the client by the memory management unit.
13. A memory access apparatus, comprising:
a dynamic memory, for storing a plurality of memory data; and
a memory management unit, coupled to the dynamic memory, wherein the memory management unit has a plurality of connection ports, and each of the connection ports is directly connected between a corresponding client and at least one buffer area, the connection ports are used for providing the clients to access the buffer directly; the memory management unit stores a priority as a sequence for the clients to access the dynamic memory; and when the clients access the dynamic memory, the buffer area is built in the memory management unit to store temporarily a plurality of buffer data generated while an access action is performed,
wherein the memory management unit partitions the buffer area into a plurality of sub-buffer areas corresponding to the clients, or a capacity of each sub-buffer area depends on the priority and the frequency of using the dynamic memory corresponding to each client.
14. The memory access apparatus according to claim 13, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the buffer area.
15. The memory access apparatus according to claim 13, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the buffer area by the memory management unit.
16. The memory access apparatus according to claim 13, further comprising a control unit, coupled to the clients and the memory management unit, for dynamically adjusting the capacity of each sub-buffer area depends on the priority and the frequency of using the dynamic memory corresponding to each client.
17. The memory access apparatus according to claim 13, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the corresponding sub-buffer area.
18. The memory access apparatus according to claim 13, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the sub-buffer area corresponding to the client by the memory management unit.
19. A display, using a memory access apparatus to store display data, wherein the memory access apparatus comprises:
a dynamic memory, for storing a plurality of memory data; and
a memory management unit, coupled to the dynamic memory, wherein the memory management unit has a plurality of connection ports, and each of the connection ports is directly connected between a corresponding client and at least one buffer area, the connection ports are used for providing the clients to access the buffer directly; the memory management unit stores a priority as a sequence for the clients to access the dynamic memory; and when the clients access the dynamic memory, the buffer area is built in the memory management unit to temporarily store a plurality of buffer data generated while the access action is performed,
wherein the memory management unit partitions the buffer area into a plurality of sub-buffer areas corresponding to the clients, and a capacity of each sub-buffer area depends on the priority corresponding to each client.
20. The display according to claim 19, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the buffer area.
21. The display according to claim 19, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the buffer area by the memory management unit.
22. The display according to claim 19, further comprising a control unit, for dynamically adjusting a capacity of each sub-buffer area corresponding to each client according to the priority for the client to access the dynamic memory.
23. The display according to claim 19, wherein the capacity of each sub-buffer area is inversely proportional to the priority corresponding to each client.
24. The display according to claim 19, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the corresponding sub-buffer area.
25. The display according to claim 19, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the sub-buffer area corresponding to the client by the memory management unit.
26. The display according to claim 19, wherein the clients comprise a display, an image grabber, a direct memory access, a 3-dimensional (3D) comb filter, a de-interleaver, and an over-driver.
27. A display, using a memory access apparatus to store display data, wherein the memory access apparatus comprises:
a dynamic memory, for storing a plurality of memory data; and
a memory management unit, coupled to the dynamic memory, wherein the memory management unit has a plurality of connection ports, and each of the connection ports is directly connected between a corresponding client and at least one buffer area, the connection ports are used for providing the clients to access the buffer directly; the memory management unit stores a priority as a sequence for the clients to access the dynamic memory; and when the clients access the dynamic memory, the buffer area is built in the memory management unit to temporarily store a plurality of buffer data generated while the access action is performed,
wherein the memory management unit partitions the buffer area into a plurality of sub-buffer areas corresponding to the clients, and a capacity of each sub-buffer area depends on the frequency of using the dynamic memory corresponding to each client.
28. The display according to claim 27, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the buffer area.
29. The display according to claim 27, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the buffer area by the memory management unit.
30. The display according to claim 27, further comprising a control unit, for dynamically adjusting a capacity of each sub-buffer area corresponding to each client according to the frequency for the client to access the dynamic memory.
31. The display according to claim 27, wherein the capacity of each sub-buffer area is inversely proportional to the priority corresponding to each client.
32. The display according to claim 27, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the corresponding sub-buffer area.
33. The display according to claim 27, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the sub-buffer area corresponding to the client by the memory management unit.
34. The display according to claim 27, wherein the clients comprise a display, an image grabber, a direct memory access, a 3-dimensional (3D) comb filter, a de-interleaver, and an over-driver.
35. A display, using a memory access apparatus to store display data, wherein the memory access apparatus comprises:
a dynamic memory, for storing a plurality of memory data; and
a memory management unit, coupled to the dynamic memory, wherein the memory management unit has a plurality of connection ports, and each of the connection ports is directly connected between a corresponding client and at least one buffer area, the connection ports are used for providing the clients to access the buffer directly; the memory management unit stores a priority as a sequence for the clients to access the dynamic memory; and when the clients access the dynamic memory, the buffer area is built in the memory management unit to temporarily store a plurality of buffer data generated while the access action is performed,
wherein the memory management unit partitions the buffer area into a plurality of sub-buffer areas corresponding to the clients, and a capacity of each sub-buffer area depends on the priority and the frequency of using the dynamic memory corresponding to each client.
36. The display according to claim 35, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the buffer area.
37. The display according to claim 35, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the buffer area by the memory management unit.
38. The display according to claim 35, further comprising a control unit, for dynamically adjusting the capacity of each sub-buffer area depends on the priority and the frequency of using the dynamic memory corresponding to each client.
39. The display according to claim 35, wherein the capacity of each sub-buffer area is inversely proportional to the priority corresponding to each client.
40. The display according to claim 35, wherein when performing a writing action for the dynamic memory, each of the clients temporarily stores data to be written in the corresponding sub-buffer area.
41. The display according to claim 35, wherein when performing a reading action for the dynamic memory, each of the clients reads data that is pre-fetched and stored in the sub-buffer area corresponding to the client by the memory management unit.
42. The display according to claim 35, wherein the clients comprise a display, an image grabber, a direct memory access, a 3-dimensional (3D) comb filter, a de-interleaver, and an over-driver.
US13/442,868 2008-04-15 2012-04-10 Memory access apparatus and display using the same Abandoned US20120198145A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/442,868 US20120198145A1 (en) 2008-04-15 2012-04-10 Memory access apparatus and display using the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW097113616A TWI391911B (en) 2008-04-15 2008-04-15 Memory access apparatus and display using the same
TW97113616 2008-04-15
US12/369,755 US8190814B2 (en) 2008-04-15 2009-02-12 Memory access apparatus and display using the same
US13/442,868 US20120198145A1 (en) 2008-04-15 2012-04-10 Memory access apparatus and display using the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/369,755 Continuation US8190814B2 (en) 2008-04-15 2009-02-12 Memory access apparatus and display using the same

Publications (1)

Publication Number Publication Date
US20120198145A1 true US20120198145A1 (en) 2012-08-02

Family

ID=41164930

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/369,755 Active 2030-08-04 US8190814B2 (en) 2008-04-15 2009-02-12 Memory access apparatus and display using the same
US13/442,868 Abandoned US20120198145A1 (en) 2008-04-15 2012-04-10 Memory access apparatus and display using the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/369,755 Active 2030-08-04 US8190814B2 (en) 2008-04-15 2009-02-12 Memory access apparatus and display using the same

Country Status (2)

Country Link
US (2) US8190814B2 (en)
TW (1) TWI391911B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102196252B (en) * 2010-03-12 2013-05-08 联咏科技股份有限公司 Memory control system and method
US8521902B2 (en) * 2010-12-02 2013-08-27 Microsoft Corporation Shared buffer for connectionless transfer protocols
US9049175B2 (en) 2010-12-02 2015-06-02 Microsoft Technology Licensing, Llc Client-adjustable window size for connectionless transfer protocols
WO2016082115A1 (en) * 2014-11-26 2016-06-02 华为技术有限公司 Service scheduling method and device
US11221971B2 (en) * 2016-04-08 2022-01-11 Qualcomm Incorporated QoS-class based servicing of requests for a shared resource

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040103245A1 (en) * 2002-11-21 2004-05-27 Hitachi Global Storage Technologies Nertherlands B.V. Data storage apparatus and method for managing buffer memory

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5689825A (en) * 1995-07-28 1997-11-18 Motorola, Inc. Method and apparatus for downloading updated software to portable wireless communication units
US6321295B1 (en) * 1998-03-19 2001-11-20 Insilicon Corporation System and method for selective transfer of application data between storage devices of a computer system through utilization of dynamic memory allocation
US6433786B1 (en) * 1999-06-10 2002-08-13 Intel Corporation Memory architecture for video graphics environment
US6853382B1 (en) * 2000-10-13 2005-02-08 Nvidia Corporation Controller for a memory system having multiple partitions
US7412492B1 (en) * 2001-09-12 2008-08-12 Vmware, Inc. Proportional share resource allocation with reduction of unproductive resource consumption
WO2004059499A2 (en) * 2002-12-30 2004-07-15 Koninklijke Philips Electronics N.V. Memory controller and method for writing to a memory
WO2004082197A2 (en) * 2003-03-12 2004-09-23 Bader David M System for simultaneously transmitting multiple rf signals using a composite waveform
KR100604660B1 (en) * 2004-04-30 2006-07-26 주식회사 하이닉스반도체 Semiconductor memory device controlled drivability of over-driver
US7770200B2 (en) * 2007-07-24 2010-08-03 Time Warner Cable Inc. Methods and apparatus for format selection for network optimization

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040103245A1 (en) * 2002-11-21 2004-05-27 Hitachi Global Storage Technologies Nertherlands B.V. Data storage apparatus and method for managing buffer memory

Also Published As

Publication number Publication date
TWI391911B (en) 2013-04-01
TW200943275A (en) 2009-10-16
US8190814B2 (en) 2012-05-29
US20090259809A1 (en) 2009-10-15

Similar Documents

Publication Publication Date Title
US7120723B2 (en) System and method for memory hub-based expansion bus
US8982658B2 (en) Scalable multi-bank memory architecture
JP5351145B2 (en) Memory control device, memory system, semiconductor integrated circuit, and memory control method
US20120198145A1 (en) Memory access apparatus and display using the same
CN102055973B (en) Memory address mapping method and memory address mapping circuit thereof
US7554874B2 (en) Method and apparatus for mapping memory
US20140344512A1 (en) Data Processing Apparatus and Memory Apparatus
US9696941B1 (en) Memory system including memory buffer
US7434023B2 (en) Memory device
US7139849B2 (en) Semiconductor integrated circuit device
US7865632B2 (en) Memory allocation and access method and device using the same
US7996601B2 (en) Apparatus and method of partially accessing dynamic random access memory
JP2005209206A (en) Data transfer method for multiprocessor system, multiprocessor system, and processor for executing the method
EP1604286B1 (en) Data processing system with cache optimised for processing dataflow applications
US6738840B1 (en) Arrangement with a plurality of processors having an interface for a collective memory
CN101566926B (en) Memory access device and display using same
US8244929B2 (en) Data processing apparatus
US20110153923A1 (en) High speed memory system
IL150149A (en) Specialized memory device
US8923405B1 (en) Memory access ordering for a transformation
US20080229030A1 (en) Efficient Use of Memory Ports in Microcomputer Systems
KR20060132147A (en) Processor of distribute storage structure
JP2006252584A (en) Semiconductor integrated circuit device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION