CN102196252B - Memory control system and method - Google Patents
Memory control system and method Download PDFInfo
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- CN102196252B CN102196252B CN 201010144168 CN201010144168A CN102196252B CN 102196252 B CN102196252 B CN 102196252B CN 201010144168 CN201010144168 CN 201010144168 CN 201010144168 A CN201010144168 A CN 201010144168A CN 102196252 B CN102196252 B CN 102196252B
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Abstract
The invention discloses a memory control system, which comprises a first queue unit, a second queue unit, a first conversion unit, a second conversion unit, an arbitrator and a control unit, wherein the first queue unit temporarily stores a plurality of first request instructions; the second queue unit temporarily stores a plurality of second request instructions; the first conversion unit selectively reassigns memory addresses corresponding to the first request instructions; the second conversion unit selectively reassigns the memory addresses corresponding to the second request instructions; the arbitrator executes the real-time scheduling of the first and second request instructions for a memory; and the control unit compares the bandwidths of the first request instructions with the bandwidths of the second request instructions, and controls the first and second conversion units to execute or not to execute the reassignment according to comparison results.
Description
Technical field
The invention relates to a kind of memory control system and method, and particularly relevant for a kind of memory control system and method that can the optimizing memory effective utilization.
Background technology
, must sequentially carry out and comprise activation (activate), write/step such as reading command and precharge when carrying out the writing/read of data when memory, can access data.The request instruction of separate sources is different to the access mode of memory.Display controller in the television system is as example, and display controller is in order to the show image picture frame, and it shows request instruction as shown in Figure 1, memory is carried out the action of data access in the mode of (line) access line by line.Due to the data of the demonstration request instruction institute access of adopting access line by line be in memory continuous, therefore the access of data can be adopted the mode of pipeline (pipeline), to reach best storage device frequency range utilance.
In addition, take video decoder as example, its decoding request instruction carries out the action of data access in the mode of block (block) access as shown in Figure 2 to memory.Yet page (page) address may occur and not hit but the phenomenon that hits address, storehouse (bank) in the decoding request instruction of exploiting field block access when the switchable memory address, so can't adopt the mode of pipeline to hide the step of activation instruction, cause usefulness to reduce, can't reach best storage device frequency range utilance.Hereat, piecemeal (tiling) mechanism is suggested, it is by mapping storage address again, although make video decoder take block as the unit access memory, but the data of access are continuous in the address of memory, can significantly reduce the situation that page address is not hit, promote the memory band width utilance.
Yet, usually all include display controller and video decoder on the market television system now, that is have access line by line and two kinds of memory access modes of block access in triangular web.Thus, if adopt access line by line, the usefulness variation of video decoder access memory; If adopt piecemeal mechanism with mapping storage address again, the usefulness variation of display controller access memory.That is, under traditional memory access technique, comprise that the system of two kinds of memory access modes can't reach optimized memory band width utilance.
Summary of the invention
The present invention utilizes classification queue to collect request instruction of the same type relevant for a kind of memory control system and method, and looks demand and correspond to and independently change the mechanism, to reach the purpose of optimization total system usefulness.
According to a first aspect of the invention, propose a kind of memory control system, comprise a first team column unit, one second queue unit, one first converting unit, one second converting unit, a moderator and a control unit.The first team column unit is in order to temporary a plurality of the first request instructions, and these a little first request instructions are access line by line for the access mode of a memory.The second queue unit is in order to temporary a plurality of the second request instructions, and these a little second request instructions are the block access for the access mode of memory.The first converting unit is in order to optionally again to assign storage address corresponding to these a little the first request instructions.The second converting unit is in order to optionally again to assign storage address corresponding to these a little the second request instructions.Moderator is coupled to the first converting unit and the second converting unit, in order to carry out these a little first request instructions and this a little the second request instructions for the real time scheduling of memory.Control unit is in order to the frequency range of these a little the first request instructions relatively frequency range of a little the second request instructions therewith, and whether carries out the action of again assigning according to output control the first converting unit relatively and the second converting unit.
According to a second aspect of the invention, propose a kind of memory control methods, comprise the following steps.Utilize a first team column unit to keep in a plurality of the first request instructions, these a little first request instructions are access line by line for the access mode of a memory.Utilize one second queue unit to keep in a plurality of the second request instructions, these a little second request instructions are the block access for the access mode of memory.Utilize a moderator to carry out these a little first request instructions and this a little the second request instructions for the real time scheduling of memory.Utilize the relatively frequency range frequency range of a little the second request instructions therewith of these a little the first request instructions of a control unit, and optionally again assign storage address corresponding to these a little the first request instructions according to output control one first converting unit relatively, and control one second converting unit and optionally again assign storage address corresponding to these a little the second request instructions.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperation accompanying drawing are described in detail below:
Description of drawings
Fig. 1 illustrates traditional display controller and memory is carried out the schematic diagram of access line by line.
Fig. 2 illustrates traditional video decoder and memory is carried out the schematic diagram of block access.
Fig. 3 illustrates the calcspar according to the memory control system of preferred embodiment of the present invention.
[primary clustering symbol description]
30: central processing unit
40: Audio Controller
50: peripheral controller
60: memory
100: memory control system
110: the first team column unit
115: the first converting units
120: the second queue unit
125: the second converting units
130: the three queue unit
140: moderator
150: control unit
152: buffer
154: microcontroller
L
1～L
m, B
1～B
n: the claimer
Embodiment
The present invention proposes a kind of memory system and method processed, utilize classification queue with dissimilar request instruction classification, and make it have separately independently address transition mechanism, then look demand and the Dynamic Selection address transition mechanism, to reach the purpose of optimization total system usefulness.
Please refer to Fig. 3, it illustrates the calcspar according to the memory control system of preferred embodiment of the present invention.Memory control system 100 comprises that one first formation (queue) unit 110, one second queue unit 120, one the 3rd formation are according to unit 130, one first converting unit 115, one second converting unit 125, a moderator (arbiter) 140 and a control unit 150.First team column unit 110 is in order to temporary a plurality of first request (request) instructions, and these a little first request instructions are access line by line for the access mode of a memory 60.The second queue unit 120 is in order to temporary a plurality of the second request instructions, and these a little second request instructions are the block access for the access mode of memory 60.Wherein, the first request instruction is for example for showing request instruction, in order to the show image picture frame; The second request instruction for example is the decoding request instruction, in order to carry out data decoding, does not so limit.The 3rd queue unit 130 is in order to the request instruction of temporary other type, such as the request instruction from other types such as central processing unit 30, Audio Controller 40 or peripheral controllers 50.That is dissimilar request instruction is classified and is temporary in different queue unit.
The first converting unit 115 is coupled to first team column unit 110, be controlled by control unit 150 optionally again to assign storage address corresponding to a plurality of the first request instructions, make these a little first request instructions be converted to the block access for the access mode of memory 60 by access line by line.The second converting unit 125 is coupled to the second queue unit 120, be controlled by control unit 150 optionally again to assign storage address corresponding to a plurality of the second request instructions, make these a little second request instructions be converted to access line by line to the access mode of memory 60 by the block access.That is these a little second request instructions are being continuous by the data of institute's access after instruction memory address again in the address of memory 60.
Moderator 140 is coupled to the first converting unit 115, the second converting unit 125 and the 3rd queue unit 130, and other request instruction of a plurality of first request instructions of execution first team column unit 110, a plurality of second request instructions of the second queue unit 120 and the 3rd queue unit 130 is for the real time scheduling of memory 60.The frequency range of control unit 150 these a little the first request instructions of comparison is the frequency range of a little the second request instructions therewith, and whether carries out the action of again assigning storage address according to output control the first converting unit 115 and the second converting unit 125 relatively.
Suppose that memory control system 100 corresponds to m the claimer L of access line by line
1～L
m, and correspond to the claimer B of n block access
1～B
n, m and n are positive integer.In addition, suppose in order to being f (x) from memory 60 accesses for the mechanism of appointment again of the first/the second request instruction of the data that show purposes, in order to being g (x) from memory 60 accesses for the mechanism of appointment again of the second request instruction of decoding purposes.If L (X) and B (X) represent respectively the claimer's of access line by line and block access frequency range, the claimer L of access line by line
1～L
mFrequency range be respectively L (L
1)～L (L
m), the claimer B of block access
1～B
nFrequency range be respectively B (B
1)～B (B
n).
The frequency range that surpasses these a little the second request instructions when the frequency range of these a little the first request instructions of microcontroller 154 judgement reaches one first critical value, that is line by line the frequency range demand of these a little the first request instructions of access higher than the frequency range demand of these a little the second request instructions of block access, microcontroller 154 output the first control commands and the second control command are to buffer 152, with difference anergy the first converting unit 115 and the second converting unit 125.At this moment, to calculate whole frequency range BW be L (L to microcontroller 154
1)+L (L
2)+... + L (L
m)+B (B
1)+B (B
2)+... + B (B
n), need in the frequency range scope that 60 of memories can provide.Wherein, the first request instruction is for example for showing request instruction, the second request instruction for example is the decoding request instruction, represent the frequency range demand high (for example showing the high image quality image) that is used for showing, microcontroller 154 meeting anergy the first converting units 115 and the second converting unit 125 are assigned machine-processed f (x) and g (x) again to close, to reach best storage device frequency range utilance.
The frequency range that surpasses these a little the first request instructions when the frequency range of these a little the second request instructions of microcontroller 154 judgement reaches one second critical value, that is the frequency range demand of these a little the second request instructions of block access is higher than the frequency range demand of these a little the first request instructions of access line by line, microcontroller 154 output the first control commands and the second control command are to buffer 152, to enable respectively the first converting unit 115 and the second converting unit 125.At this moment, microcontroller 154 calculates dynamic adjustment frequency range BW
dBe L2B (L
1)+L2B (L
2)+... + L2B (L
m)+B2L (B
1)+B2L (B
2)+... + B2L (B
n), need in the frequency range scope that 60 of memories can provide.Wherein, the first request instruction is for example for showing request instruction, the second request instruction for example is the decoding request instruction, represent that the frequency range demand that is used for showing is low, microcontroller 154 can enable the first converting unit 115 and the second converting unit 125 is assigned machine-processed f (x) and g (x) again to activate, to reach best storage device frequency range utilance.
When microcontroller 154 judges that a upper limit frequency range of memory control systems 100 is lower than one the 3rd critical value, that is 60 frequency ranges that can provide of memory are limited, microcontroller 154 is exported the first control commands with anergy the first converting unit 115, and exports the second control command again to assign non-storage address corresponding to other the second request instruction corresponding to showing the purposes data.Wherein, if the first request instruction is for example for showing request instruction, the second request instruction for example is the decoding request instruction, and r represents non-claimer's corresponding to showing the purposes data number, and microcontroller 154 calculates dynamic adjustment frequency range BW
dBe L (L
1)+L (L
2)+... + L (L
m)+B2L (B
1)+B2L (B
2)+... + B2L (B
r)+B (B
r+1)+... + B (B
n), need in the frequency range scope that 60 of memories can provide.At this moment, microcontroller 154 cuts out and again assigns machine-processed f (x), and activates and again assign machine-processed g (x), to reach best storage device frequency range utilance.
In addition, microcontroller 154 more can calculate part the first request instruction and part the second request instruction again assigned corresponding storage address after, the frequency range that memory 60 is carried out access.Suppose that p represents to be converted to by access line by line the claimer's of block access number, q represents to be converted to by the block access claimer's of access line by line number, and microcontroller 154 calculates dynamic adjustment frequency range BW
dBe L2B (L
1)+L2B (L
2)+... + L2B (L
p)+L (L
p+1)+L (L
p+2)+... + L (L
m)+B2L (B
1)+B2L (B
2)+... + B2L (B
q)+B (B
q+1)+B (B
q+2)+... + B (B
n).That is, the dynamic adjustment frequency range BW in the time of can obtaining different set by the value of adjusting p and q
dHereat, can look different in product application, the frequency range demand of different memory is adjusted the value of p and q so that suitable dynamic adjustment frequency range BW to be provided
dSo, not only can reach best storage device frequency range utilance, the advantage of product optimization and minimization of cost can also be provided.
In addition, the present invention more provides a kind of memory control methods, comprises the following steps.Utilize a first team column unit to keep in a plurality of the first request instructions, these a little first request instructions are access line by line for the access mode of a memory.Utilize one second queue unit to keep in a plurality of the second request instructions, these a little second request instructions are the block access for the access mode of memory.Utilize a moderator to carry out these a little first request instructions and this a little the second request instructions for the real time scheduling of memory.Utilize the relatively frequency range frequency range of a little the second request instructions therewith of these a little the first request instructions of a control unit, and optionally again assign storage address corresponding to these a little the first request instructions according to output control one first converting unit relatively, and control one second converting unit and optionally again assign storage address corresponding to these a little the second request instructions.
Above-mentioned memory control methods, its operating principle has been specified in the associated description of memory control system 100, therefore no longer repeat in this.
The disclosed memory control system of the above embodiment of the present invention and method have multiple advantages, below only enumerate the part advantage and are described as follows:
Memory control system of the present invention and method, utilize classification queue with dissimilar request instruction classification, and make it have separately independently address transition mechanism, look again demand that product uses and the Dynamic Selection address transition mechanism, so that suitable dynamic adjustment frequency range to be provided, therefore not only can reach the purpose of optimization total system usefulness, the advantage of product optimization and minimization of cost can also be provided.
In sum, although the present invention discloses as above with a preferred embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is worked as with being as the criterion that claim was defined.
Claims (20)
1. memory control system comprises:
One first team column unit, in order to temporary a plurality of the first request instructions, those first request instructions are access line by line for the access mode of a memory;
One second queue unit, in order to temporary a plurality of the second request instructions, those second request instructions are the block access for the access mode of this memory;
One first converting unit in order to optionally again to assign storage address corresponding to those the first request instructions, makes those first request instructions be converted to the block access for the access mode of this memory by access line by line;
One second converting unit in order to optionally again to assign storage address corresponding to those the second request instructions, makes those second request instructions be converted to the block access for the access mode of this memory by access line by line;
One moderator is coupled to this first converting unit and this second converting unit, in order to carry out those first request instructions and those the second request instructions for the real time scheduling of this memory; And
Whether one control unit in order to the frequency range of those the first request instructions of comparison and the frequency range of those the second request instructions, and carries out the action of again assigning according to this first converting unit of output control relatively and this second converting unit.
2. memory control system as claimed in claim 1, is characterized in that, those first request instructions are a plurality of demonstration request instructions.
3. memory control system as claimed in claim 1, is characterized in that, those second request instructions are a plurality of decoding request instructions.
4. memory control system as claimed in claim 1, is characterized in that, this first converting unit is controlled by this control unit, optionally again to assign storage address corresponding to those the first request instructions.
5. memory control system as claimed in claim 1, is characterized in that, this second converting unit is controlled by this control unit, optionally again to assign storage address corresponding to those the second request instructions.
6. memory control system as claimed in claim 1, is characterized in that, this control unit comprises:
One buffer is in order to be coupled to this first converting unit and this second converting unit; And
One microcontroller, in order to the frequency range that calculates those the first request instructions and the frequency range of those the second request instructions, and according to result output one first control command of calculating to this buffer enabling or this first converting unit of anergy, and export one second control command to this buffer to enable or this second converting unit of anergy.
7. memory control system as claimed in claim 6, is characterized in that, this microcontroller is more in order to after calculating those first request instructions and those the second request instructions and again being assigned corresponding storage address, the frequency range that this memory is carried out access.
8. memory control system as claimed in claim 6, it is characterized in that, reach one first critical value when this microcontroller judges the frequency range that the frequency range of those the first request instructions surpasses those the second request instructions, this microcontroller is exported this first control command and this second control command with this first converting unit of anergy and this second converting unit respectively.
9. memory control system as claimed in claim 6, it is characterized in that, reach one second critical value when this microcontroller judges the frequency range that the frequency range of those the second request instructions surpasses those the first request instructions, this microcontroller is exported this first control command and this second control command to enable respectively this first converting unit and this second converting unit.
10. memory control system as claimed in claim 6, it is characterized in that, those second request instructions of part are the demonstration purposes from the data of this memory access, when a upper limit frequency range of this memory control system lower than one the 3rd critical value, this microcontroller is exported this first control command with this first converting unit of anergy, and exports this second control command again to assign non-other those storage address corresponding to the second request instruction corresponding to showing the purposes data.
11. a memory control methods comprises:
Utilize a first team column unit to keep in a plurality of the first request instructions, those first request instructions are access line by line for the access mode of a memory;
Utilize one second queue unit to keep in a plurality of the second request instructions, those second request instructions are the block access for the access mode of this memory;
Utilize a moderator to carry out those first request instructions and those the second request instructions for the real time scheduling of this memory; And
utilize a control unit to compare the frequency range of those the first request instructions and the frequency range of those the second request instructions, and optionally again assign storage address corresponding to those the first request instructions according to output control one first converting unit relatively, make those first request instructions be converted to the block access for the access mode of this memory by access line by line, and control one second converting unit and optionally again assign storage address corresponding to those the second request instructions, make those second request instructions be converted to the block access for the access mode of this memory by access line by line.
12. memory control methods as claimed in claim 11 is characterized in that, those first request instructions are a plurality of demonstration request instructions.
13. memory control methods as claimed in claim 11 is characterized in that, those second request instructions are a plurality of decoding request instructions.
14. memory control methods as claimed in claim 11 is characterized in that, more comprises:
Utilize this control unit to control this first converting unit and optionally will again assign storage address corresponding to those the first request instructions.
15. memory control methods as claimed in claim 11 is characterized in that, more comprises:
Utilize this control unit to control this second converting unit and optionally again assign storage address corresponding to those the second request instructions.
16. memory control methods as claimed in claim 11 is characterized in that, this control unit comprises a buffer and a microcontroller, and this memory control methods more comprises:
Utilize this microcontroller to calculate the frequency range of those the first request instructions and the frequency range of those the second request instructions, and according to result output one first control command of calculating to this buffer enabling or this first converting unit of anergy, and export one second control command to this buffer to enable or this second converting unit of anergy.
17. memory control methods as claimed in claim 16 is characterized in that, more comprises:
After utilizing this microcontroller to calculate those first request instructions and those the second request instructions again to be assigned corresponding storage address, the frequency range that this memory is carried out access.
18. memory control methods as claimed in claim 16 is characterized in that, more comprises:
The frequency range that surpasses those the second request instructions when the frequency range of those the first request instructions reaches one first critical value, utilizes this microcontroller to export this first control command and this second control command with this first converting unit of anergy and this second converting unit respectively.
19. memory control methods as claimed in claim 16 is characterized in that, more comprises:
The frequency range that surpasses those the first request instructions when the frequency range of those the second request instructions reaches one second critical value, utilizes this microcontroller to export this first control command and this second control command to enable respectively this first converting unit and this second converting unit.
20. memory control methods as claimed in claim 16 is characterized in that, those second request instructions of part are the demonstration purposes from the data of this memory access, and this memory control methods more comprises:
When a upper limit frequency range of this memory control system lower than one the 3rd critical value, utilize this microcontroller to export this first control command with this first converting unit of anergy, and export this second control command again to assign non-other those storage address corresponding to the second request instruction corresponding to showing the purposes data.
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| CN 201010144168 CN102196252B (en) | 2010-03-12 | 2010-03-12 | Memory control system and method |
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| CN102196252B true CN102196252B (en) | 2013-05-08 |
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| US6892281B2 (en) * | 2002-10-03 | 2005-05-10 | Intel Corporation | Apparatus, method, and system for reducing latency of memory devices |
| KR100606812B1 (en) * | 2004-03-08 | 2006-08-01 | 엘지전자 주식회사 | Video decoding system |
| CN100417203C (en) * | 2004-05-11 | 2008-09-03 | 联咏科技股份有限公司 | Sensing device and method for sampling image signal |
| US7277982B2 (en) * | 2004-07-27 | 2007-10-02 | International Business Machines Corporation | DRAM access command queuing structure |
| TWI343525B (en) * | 2007-10-04 | 2011-06-11 | Novatek Microelectronics Corp | Method for data storage and access of memory and memory using the same |
| TWI391911B (en) * | 2008-04-15 | 2013-04-01 | Novatek Microelectronics Corp | Memory access apparatus and display using the same |
| CN101566926B (en) * | 2008-04-24 | 2011-06-22 | 联咏科技股份有限公司 | Memory access device and display using same |
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