US20120160551A1 - Embedded structure of circuit board - Google Patents
Embedded structure of circuit board Download PDFInfo
- Publication number
- US20120160551A1 US20120160551A1 US13/413,666 US201213413666A US2012160551A1 US 20120160551 A1 US20120160551 A1 US 20120160551A1 US 201213413666 A US201213413666 A US 201213413666A US 2012160551 A1 US2012160551 A1 US 2012160551A1
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- United States
- Prior art keywords
- embedded structure
- dielectric layer
- roughness
- pad opening
- resin
- Prior art date
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0236—Plating catalyst as filler in insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1377—Protective layers
- H05K2203/1388—Temporary protective conductive layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to an embedded structure and the fabrication method thereof.
- the present invention relates to an embedded structure of the circuit board with a smoother surface on the inner wall.
- Circuit boards are essential elements in electronic devices.
- the function of the circuit boards is to define the pre-determined circuit patterns on a solid surface.
- the line width and the line space of the conductive wires on the circuit boards are narrower and narrower.
- the first one is to transfer-print patterned wires into a dielectric layer.
- the other one is to pattern a substrate by laser to define a damascene structure, then use a conductive material to fill the recesses on the substrate to complete an embedded structure.
- the surface of the substrate is required to be activated in advance to allow the conductive material to successfully fill the recesses on the substrate, frequently by electroless plating methods.
- a material is proposed to allow the conductive material to be disposed on the recesses on the substrate without a prior activation procedure for the electroless plating.
- FIGS. 1-4 illustrate a conventional method to form an embedded structure.
- a substrate 101 is provided.
- a first patterned copper layer 110 is disposed on the substrate 101 and partially exposes the substrate 101 .
- a first dielectric layer 120 covers the first patterned copper layer 110 and the substrate 101 .
- the first dielectric layer 120 is patterned to form a pad opening 122 , a via 121 integrally formed with the pad opening 122 , and a trench 123 adjacent to the pad opening 122 .
- the via 121 exposes a portion of the first patterned copper layer 110 . Because residues may remain on the exposed surface of the first patterned copper layer 110 and would hinder the following electric connection, a desmearing procedure is carried out, as shown in FIG. 3 to remove the residues on the exposed surface of the first patterned copper layer 110 and to facilitate the following electric connection.
- the desmearing procedure may be carried out by employing plasma or an oxidizing agent, such as permanganate.
- the desmearing procedure In addition to removing all the residues on the exposed surface of the first patterned copper layer 110 , the desmearing procedure also etches the surface of the first dielectric layer 120 , including sidewalls of the pad opening 122 , the via 122 as well as the trench 123 , thereby forming a rugged surface on the first dielectric layer 120 . If such rugged surface further undergoes a copper deposition, as shown in FIG. 4 , undesirable lumps 131 occur everywhere in the copper layer 130 and deteriorate the quality of the copper layer 130 , or the rugged surface limits the design of circuit of high density. Even more, the rugged surface of the trench 123 results in rugged circuits and causes signal loss.
- the present invention therefore proposes a novel embedded structure with a smoother surface on the inner wall as well as a method for making such embedded structure to overcome the aforesaid problems. Because the inner wall of the embedded structure of the present invention has a much smoother surface, the number of copper lumps is minimized and a conductive layer of better quality can be obtained when a layer of copper is deposited on the inner wall of the embedded structure of the present invention, which enhances the reliability of the embedded circuit structure of the present invention.
- the embedded structure of the present invention may further have a substantially even outer surface.
- the present invention first provides an embedded structure.
- the embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the dielectric layer and in the pad opening, wherein the via and the pad opening together define the embedded structure, and further the inner wall of the via has a roughness C, the inner wall of the pad opening has a roughness B, and the outer surface of the dielectric layer has a substantially even surface with a roughness A.
- A, B, C are mutually different.
- the present invention still provides a method for defining an embedded structure.
- a dielectric layer is provided.
- an organic film layer is formed to cover the dielectric layer.
- a via is formed in the dielectric layer and in the organic film layer.
- a cleaning step is performed to roughen the inner wall of the via.
- the dielectric layer and the organic film layer are patterned to form a pad opening overlapping with the via in the dielectric layer.
- the via and the pad opening together define the embedded structure.
- the outer surface of the dielectric layer has a roughness A
- the inner wall of the pad opening has a roughness B
- the inner wall of the via has a roughness C.
- A, B, C are mutually different.
- the inner wall of the embedded structure of the present invention may have a smoother surface and avoid the attack of the cleaning step.
- the cleaning step on one hand lets the interconnection, i.e. the internal electrical connection, in the via have better affinity to the inner wall of the via.
- the embedded structure of the present invention may further have a substantially even outer surface due to the protection of the organic film layer.
- FIGS. 1-4 illustrate a conventional method to form an embedded structure in the prior art.
- FIG. 5 illustrates an embodiment of the embedded structure of the present invention.
- FIGS. 6-12 illustrate an embodiment of the method for defining an embedded structure of the present invention.
- FIG. 13 illustrates various embodiments of the trench of the present invention.
- the present invention provides a novel embedded structure as well as a method for making an embedded structure. Because the embedded structure of the present invention has gone through a patterning step after the cleaning step, the inner wall of the embedded structure of the present invention has a smoother surface. Moreover, less copper lumps will be formed and a conductive layer of better quality can be obtained when a layer of copper is later deposited on the inner wall of the embedded structure of the present invention due to the smoother surface, which enhances the reliability of the embedded circuit structure of the present invention. Moreover, the embedded structure of the present invention may further have a substantially even outer surface because of the protection of the organic film layer during the manufacturing process.
- FIG. 5 illustrates an embodiment of the embedded structure of the present invention.
- the embedded structure 200 of the present invention includes a dielectric layer 220 , a via 221 , and a pad opening 222 .
- the outer surface 224 of the dielectric layer 220 is supposed to have a substantially even surface.
- the outer surface 224 of the dielectric layer 220 has a roughness A.
- the roughness A may be expressed by the parameters Ra. Please refer to JIS B 0601-1982 for the details of the parameters Ra. If expressed by Ra, the roughness A is ⁇ 0.5 ⁇ m.
- the dielectric layer 220 may further include a metallic complex, such as Mn, Cr, Pd or Pt. Once activated, such as by laser, the dielectric layer 220 helps another conductive layer to deposit with the help of the metallic complex.
- a metallic complex such as Mn, Cr, Pd or Pt.
- the pad opening 222 is formed in the dielectric layer 220 .
- the via 221 is formed inside the pad opening 222 and in the dielectric layer 220 as well so that the pad opening 222 encircles the via 221 from a top view (not shown).
- the via 221 and the pad opening 222 together define the circuit of the embedded structure of the present invention.
- Each via 221 may have at least one pad opening 222 .
- a via 221 may optionally have one pad opening 222 or two pad openings 222 , as shown in FIG. 5 .
- the dielectric layer 220 may include a trench 223 which does not encircle the via 221 but may be connected to the via 221 , as shown in FIG. 5 .
- the trench 223 may have various shapes, as illustrated in FIG. 13 .
- the inner wall of the trench has a roughness B
- the inner wall of the pad opening has a roughness B
- the inner wall of the via has a roughness C.
- the roughness B is between 0.2 ⁇ m and 1.5 ⁇ m.
- the roughness C is between 0.5 ⁇ m and 5.0 ⁇ m.
- A, B and C are mutually different.
- the roughness A, B and C have relative relations, C>B>A.
- a conductive layer 230 may fill the via 221 , the pad opening 222 and the optional trench 223 to form the embedded circuit structure of the present invention.
- the conductive layer 230 usually includes a metal, such as Cu or Al, which may be formed by an electroless plating procedure. If the dielectric layer 220 includes the metallic complex, the dielectric layer acts as a seed layer for the conductive layer 230 .
- the embedded structure of the present invention may include an organic film layer 250 covering the dielectric layer 220 and selectively exposing the via 221 , the pad opening 222 and the optional trench 223 to protect the outer surface 224 of the dielectric layer 220 .
- the organic film layer 250 may optionally cover one outer surface 224 of the dielectric layer 220 or both sides of the outer surface 224 of the dielectric layer 220 .
- the organic film layer 250 may include a hydrophilic polymer to be optionally removed by water.
- the hydrophilic polymer may include functional groups such as hydroxyl group (—OH), amide group (—CONH2), sulfonic group (—SO3H) and/or carboxylic group (—COOH).
- the organic film layer 250 may include a hydrophobic polymer.
- the hydrophobic polymer may be methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamide resin, or polysiloxane resin.
- the present invention continues to provide a method for defining an embedded structure and further for forming the embedded structure.
- FIGS. 6-12 illustrating an embodiment of the method for defining an embedded structure of the present invention.
- the dielectric layer 220 may further include a metallic complex, such as Mn, Cr, Pd or Pt. Once activated, such as by laser, the dielectric layer 220 helps another conductive layer to deposit with the help of the metallic complex.
- an organic film layer 250 is formed to cover the dielectric layer 220 . Accordingly, the organic film layer 250 is capable of protecting the outer surface 224 of the dielectric layer 220 from any undesirable damages.
- the organic film layer 250 may optionally cover one outer surface 224 of the dielectric layer 220 or both sides of the outer surface 224 of the dielectric layer 220 .
- the organic film layer 250 may include a hydrophilic polymer to be optionally removed by water or a hydrophobic polymer.
- the hydrophilic polymer may include functional groups such as hydroxyl group (—OH), amide group (—CONH2), sulfonic group (—SO3H) and /or carboxylic group (—COOH).
- the organic film layer 250 may include a hydrophobic polymer.
- the hydrophobic polymer may be methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamide resin, or polysiloxane resin.
- the outer surface 224 of the dielectric layer 220 have an original roughness A, for example substantially even.
- the roughness may be expressed by either one of the parameters Ra. If expressed by Ra, the roughness A is ⁇ 0.5 ⁇ m.
- At least one via 221 is formed in the dielectric layer 220 and in the organic film layer 250 .
- the via 221 penetrates the dielectric layer 220 and the organic film layer 250 to form a through hole.
- the via 221 may be formed by using laser to remove part of the dielectric layer 220 and part of the organic film layer 250 .
- Each via 221 may have at least one pad opening 222 .
- a via 221 may optionally have one pad opening 222 or two pad openings 222 .
- a cleaning step is performed to etch the inner surface of the dielectric layer 220 as well as the organic film layer 250 , and leaves both the inner surface of the dielectric layer 220 and of the organic film layer 250 attacked, i.e. a rugged surface, as shown in FIG. 9 .
- the outer surface 224 of the dielectric layer 220 is kept from the attacks of the cleaning step and retains its original roughness A, for example a substantially even surface.
- the cleaning step may include the use of energy particles, such as plasma, or of an oxidizing agent, such as permanganate.
- the organic film layer 250 is capable of protecting the outer surface 224 of the dielectric layer 220 from any undesirable attacks.
- the organic film layer 250 may include a hydrophilic polymer to be optionally removed by water.
- the hydrophilic polymer may include functional groups such as hydroxyl group (—OH), amide group (—CONH2), sulfonic group (—SO3H) and/or carboxylic group (—COOH).
- the organic film layer 250 may include a hydrophobic polymer.
- the hydrophobic polymer may be methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamide resin, or polysiloxane resin.
- the dielectric layer 210 and the organic film layer 250 are patterned to form pad openings 222 , optional trenches 223 and simultaneously to reinforce the vias 221 .
- the pad opening 222 encircles, or in other words, overlaps with the via 221 , and the via 221 and the pad opening 222 together define the embedded structure of the present invention.
- the trench 223 does not encircle the via 221 but may be connected to the via 221 .
- the pad opening 222 , and the optional trench 223 may be formed by using laser to remove part of the dielectric layer 220 and part of the organic film layer 250 .
- the inner wall of the trench 223 has a roughness B and the inner wall of the pad opening 222 has a roughness B. If expressed by Ra, the roughness B is between 0.2 ⁇ m and 1.5 ⁇ m.
- the formation of the pad opening 222 and the optional trench 223 also reinforces the via 221 , so the inner wall of the via 221 may have a different roughness, namely roughness C.
- the roughness C is between 0.5 ⁇ m and 5.0 ⁇ m.
- A, B and C are mutually different.
- the roughness A, B and C have relative relations, C>B>A.
- the formation of the pad opening 222 and the optional trench 223 also activates the metallic complex. Once activated, such as by laser, the dielectric layer 220 helps another conductive layer to deposit with the help of the metallic complex.
- a first deposition step is performed to form a conductive layer 230 in the via 221 , the pad opening 222 and the trench 223 .
- the first deposition step is an electroless plating procedure. If the dielectric layer 220 includes the metallic complex and is activated by the formation of the pad opening 222 and the optional trench 223 , the dielectric layer acts as a seed layer for the electroless plating.
- the conductive layer 230 usually includes a metal, such as Cu or Al.
- a second deposition step, such as electroplating is optionally performed so that the conductive layer 230 fills the via 221 , the pad opening 222 and the trench 223 . Because the inner wall of the via, the pad opening and the trench are formed or reinforced after the cleaning step, less copper lumps will be formed and a conductive layer of better quality can be obtained due to a smoother surface.
- the organic film layer 250 may remain on the dielectric layer 220 or not. If not, the organic film layer 250 is removed, so as to leave the dielectric layer 220 a substantially even surface, as shown in FIG. 12 .
- the organic film layer 250 may be washed off by water.
- the inner wall of the via, the pad opening and the trench of the present invention may have a smoother surface. Moreover, less copper lumps will be formed and a conductive layer of better quality can be obtained when a layer of copper is later deposited on the inner wall of the embedded structure of the present invention due to the smoother surface.
- the smoother surface is able to raise the reliability of the embedded structure of the present invention.
- the embedded structure of the present invention may further have a substantially even outer surface because of the protection of the organic film layer during the manufacturing process.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
An embedded structure of circuit board is provided. The embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the pad opening and in the dielectric layer, wherein the outer surface of the dielectric layer has a substantially even surface.
Description
- This application is a division of U.S. application Ser. No. 12/211,816 filed Sep. 17, 2008.
- 1. Field of the Invention
- The present invention relates to an embedded structure and the fabrication method thereof. In particular, the present invention relates to an embedded structure of the circuit board with a smoother surface on the inner wall.
- 2. Description of the Prior Art
- Circuit boards are essential elements in electronic devices. The function of the circuit boards is to define the pre-determined circuit patterns on a solid surface. For the trend of miniaturization of the electronic devices, the line width and the line space of the conductive wires on the circuit boards are narrower and narrower.
- Currently, there are two methods available to form the circuit boards to meet the demand. The first one is to transfer-print patterned wires into a dielectric layer. The other one is to pattern a substrate by laser to define a damascene structure, then use a conductive material to fill the recesses on the substrate to complete an embedded structure. Generally speaking, the surface of the substrate is required to be activated in advance to allow the conductive material to successfully fill the recesses on the substrate, frequently by electroless plating methods. Even more, a material is proposed to allow the conductive material to be disposed on the recesses on the substrate without a prior activation procedure for the electroless plating.
-
FIGS. 1-4 illustrate a conventional method to form an embedded structure. As shown inFIG. 1 , first, asubstrate 101 is provided. A first patternedcopper layer 110 is disposed on thesubstrate 101 and partially exposes thesubstrate 101. A firstdielectric layer 120 covers the first patternedcopper layer 110 and thesubstrate 101. - As shown in
FIG. 2 , the firstdielectric layer 120 is patterned to form a pad opening 122, avia 121 integrally formed with the pad opening 122, and atrench 123 adjacent to the pad opening 122. Thevia 121 exposes a portion of the first patternedcopper layer 110. Because residues may remain on the exposed surface of the first patternedcopper layer 110 and would hinder the following electric connection, a desmearing procedure is carried out, as shown inFIG. 3 to remove the residues on the exposed surface of the first patternedcopper layer 110 and to facilitate the following electric connection. The desmearing procedure may be carried out by employing plasma or an oxidizing agent, such as permanganate. In addition to removing all the residues on the exposed surface of the first patternedcopper layer 110, the desmearing procedure also etches the surface of the firstdielectric layer 120, including sidewalls of the pad opening 122, thevia 122 as well as thetrench 123, thereby forming a rugged surface on the firstdielectric layer 120. If such rugged surface further undergoes a copper deposition, as shown inFIG. 4 ,undesirable lumps 131 occur everywhere in thecopper layer 130 and deteriorate the quality of thecopper layer 130, or the rugged surface limits the design of circuit of high density. Even more, the rugged surface of thetrench 123 results in rugged circuits and causes signal loss. Thecopper layer 130 of bad quality jeopardizes the reliability of the embeddedstructure 100, of the circuit board and of the electric device made thereof. It is a disadvantage to be overcome. - Therefore, an embedded structure of better surface evenness as well as a novel manufacturing process is needed to provide a circuit board with good reliability.
- The present invention therefore proposes a novel embedded structure with a smoother surface on the inner wall as well as a method for making such embedded structure to overcome the aforesaid problems. Because the inner wall of the embedded structure of the present invention has a much smoother surface, the number of copper lumps is minimized and a conductive layer of better quality can be obtained when a layer of copper is deposited on the inner wall of the embedded structure of the present invention, which enhances the reliability of the embedded circuit structure of the present invention. In addition, in one embodiment of the present invention, the embedded structure of the present invention may further have a substantially even outer surface.
- The present invention first provides an embedded structure. The embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the dielectric layer and in the pad opening, wherein the via and the pad opening together define the embedded structure, and further the inner wall of the via has a roughness C, the inner wall of the pad opening has a roughness B, and the outer surface of the dielectric layer has a substantially even surface with a roughness A. A, B, C are mutually different.
- The present invention still provides a method for defining an embedded structure. In the method for defining an embedded structure of the present invention, first a dielectric layer is provided. Second, an organic film layer is formed to cover the dielectric layer. Then, a via is formed in the dielectric layer and in the organic film layer. Afterwards, a cleaning step is performed to roughen the inner wall of the via. Later, the dielectric layer and the organic film layer are patterned to form a pad opening overlapping with the via in the dielectric layer. The via and the pad opening together define the embedded structure. The outer surface of the dielectric layer has a roughness A, the inner wall of the pad opening has a roughness B, and the inner wall of the via has a roughness C. A, B, C are mutually different.
- Because the novel embedded structure of the present invention goes through a patterning step to define the pad opening, or the optional trench after the cleaning step, the inner wall of the embedded structure of the present invention may have a smoother surface and avoid the attack of the cleaning step. The cleaning step on one hand lets the interconnection, i.e. the internal electrical connection, in the via have better affinity to the inner wall of the via.
- Moreover, less copper lumps will be formed and a conductive layer of better quality can be obtained when a layer of copper is later deposited on the inner wall of the embedded structure of the present invention, which raises the reliability of the embedded circuit structure of the present invention. In addition, the embedded structure of the present invention may further have a substantially even outer surface due to the protection of the organic film layer.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-4 illustrate a conventional method to form an embedded structure in the prior art. -
FIG. 5 illustrates an embodiment of the embedded structure of the present invention. -
FIGS. 6-12 illustrate an embodiment of the method for defining an embedded structure of the present invention. -
FIG. 13 illustrates various embodiments of the trench of the present invention. - The present invention provides a novel embedded structure as well as a method for making an embedded structure. Because the embedded structure of the present invention has gone through a patterning step after the cleaning step, the inner wall of the embedded structure of the present invention has a smoother surface. Moreover, less copper lumps will be formed and a conductive layer of better quality can be obtained when a layer of copper is later deposited on the inner wall of the embedded structure of the present invention due to the smoother surface, which enhances the reliability of the embedded circuit structure of the present invention. Moreover, the embedded structure of the present invention may further have a substantially even outer surface because of the protection of the organic film layer during the manufacturing process.
- The present invention first provides an embedded structure.
FIG. 5 illustrates an embodiment of the embedded structure of the present invention. As shown inFIG. 5 , the embeddedstructure 200 of the present invention includes adielectric layer 220, avia 221, and a pad opening 222. - The
outer surface 224 of thedielectric layer 220 is supposed to have a substantially even surface. For example, theouter surface 224 of thedielectric layer 220 has a roughness A. The roughness A may be expressed by the parameters Ra. Please refer to JIS B 0601-1982 for the details of the parameters Ra. If expressed by Ra, the roughness A is <0.5 μm. - In one embodiment of the present invention, the
dielectric layer 220 may further include a metallic complex, such as Mn, Cr, Pd or Pt. Once activated, such as by laser, thedielectric layer 220 helps another conductive layer to deposit with the help of the metallic complex. - The
pad opening 222 is formed in thedielectric layer 220. Besides, the via 221 is formed inside thepad opening 222 and in thedielectric layer 220 as well so that thepad opening 222 encircles the via 221 from a top view (not shown). The via 221 and thepad opening 222 together define the circuit of the embedded structure of the present invention. Each via 221 may have at least onepad opening 222. In other words, a via 221 may optionally have onepad opening 222 or twopad openings 222, as shown inFIG. 5 . - Additionally, the
dielectric layer 220 may include atrench 223 which does not encircle the via 221 but may be connected to the via 221, as shown inFIG. 5 . Thetrench 223 may have various shapes, as illustrated inFIG. 13 . - Similarly, the inner wall of the trench has a roughness B, the inner wall of the pad opening has a roughness B and the inner wall of the via has a roughness C. If expressed by Ra, the roughness B is between 0.2 μm and 1.5 μm. Again, if expressed by Ra, the roughness C is between 0.5 μm and 5.0 μm. A, B and C are mutually different. For example, the roughness A, B and C have relative relations, C>B>A.
- In one embodiment of the present invention, a
conductive layer 230 may fill the via 221, thepad opening 222 and theoptional trench 223 to form the embedded circuit structure of the present invention. Theconductive layer 230 usually includes a metal, such as Cu or Al, which may be formed by an electroless plating procedure. If thedielectric layer 220 includes the metallic complex, the dielectric layer acts as a seed layer for theconductive layer 230. - In order to achieve a substantially even surface for the
outer surface 224 of thedielectric layer 220, in another embodiment of the present invention, the embedded structure of the present invention may include anorganic film layer 250 covering thedielectric layer 220 and selectively exposing the via 221, thepad opening 222 and theoptional trench 223 to protect theouter surface 224 of thedielectric layer 220. Theorganic film layer 250 may optionally cover oneouter surface 224 of thedielectric layer 220 or both sides of theouter surface 224 of thedielectric layer 220. - The
organic film layer 250 may include a hydrophilic polymer to be optionally removed by water. For instance, the hydrophilic polymer may include functional groups such as hydroxyl group (—OH), amide group (—CONH2), sulfonic group (—SO3H) and/or carboxylic group (—COOH). - Alternatively, the
organic film layer 250 may include a hydrophobic polymer. For instance, the hydrophobic polymer may be methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamide resin, or polysiloxane resin. - The present invention continues to provide a method for defining an embedded structure and further for forming the embedded structure. Please refer to
FIGS. 6-12 , illustrating an embodiment of the method for defining an embedded structure of the present invention. As shown inFIG. 6 , first adielectric layer 220 is provided. In one embodiment of the present invention, thedielectric layer 220 may further include a metallic complex, such as Mn, Cr, Pd or Pt. Once activated, such as by laser, thedielectric layer 220 helps another conductive layer to deposit with the help of the metallic complex. - Second, as shown in
FIG. 7 , anorganic film layer 250 is formed to cover thedielectric layer 220. Accordingly, theorganic film layer 250 is capable of protecting theouter surface 224 of thedielectric layer 220 from any undesirable damages. Theorganic film layer 250 may optionally cover oneouter surface 224 of thedielectric layer 220 or both sides of theouter surface 224 of thedielectric layer 220. - The
organic film layer 250 may include a hydrophilic polymer to be optionally removed by water or a hydrophobic polymer. For instance, the hydrophilic polymer may include functional groups such as hydroxyl group (—OH), amide group (—CONH2), sulfonic group (—SO3H) and /or carboxylic group (—COOH). - Alternatively, the
organic film layer 250 may include a hydrophobic polymer. For instance, the hydrophobic polymer may be methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamide resin, or polysiloxane resin. - The
outer surface 224 of thedielectric layer 220 have an original roughness A, for example substantially even. The roughness may be expressed by either one of the parameters Ra. If expressed by Ra, the roughness A is <0.5 μm. - Then, as shown in
FIG. 8 , at least one via 221 is formed in thedielectric layer 220 and in theorganic film layer 250. The via 221 penetrates thedielectric layer 220 and theorganic film layer 250 to form a through hole. The via 221 may be formed by using laser to remove part of thedielectric layer 220 and part of theorganic film layer 250. Each via 221 may have at least onepad opening 222. In other words, a via 221 may optionally have onepad opening 222 or twopad openings 222. - Afterwards, a cleaning step is performed to etch the inner surface of the
dielectric layer 220 as well as theorganic film layer 250, and leaves both the inner surface of thedielectric layer 220 and of theorganic film layer 250 attacked, i.e. a rugged surface, as shown inFIG. 9 . However, thanks to the protection of theorganic film layer 250, theouter surface 224 of thedielectric layer 220 is kept from the attacks of the cleaning step and retains its original roughness A, for example a substantially even surface. The cleaning step may include the use of energy particles, such as plasma, or of an oxidizing agent, such as permanganate. - The
organic film layer 250 is capable of protecting theouter surface 224 of thedielectric layer 220 from any undesirable attacks. Theorganic film layer 250 may include a hydrophilic polymer to be optionally removed by water. For instance, the hydrophilic polymer may include functional groups such as hydroxyl group (—OH), amide group (—CONH2), sulfonic group (—SO3H) and/or carboxylic group (—COOH). - Alternatively, the
organic film layer 250 may include a hydrophobic polymer. For instance, the hydrophobic polymer may be methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamide resin, or polysiloxane resin. - As shown in
FIG. 10 , afterwards, the dielectric layer 210 and theorganic film layer 250 are patterned to formpad openings 222,optional trenches 223 and simultaneously to reinforce thevias 221. Thepad opening 222 encircles, or in other words, overlaps with the via 221, and the via 221 and thepad opening 222 together define the embedded structure of the present invention. - By contrast with the
pad opening 222, thetrench 223 does not encircle the via 221 but may be connected to thevia 221. Similarly, thepad opening 222, and theoptional trench 223 may be formed by using laser to remove part of thedielectric layer 220 and part of theorganic film layer 250. When thepad opening 222 and theoptional trench 223 are formed, the inner wall of thetrench 223 has a roughness B and the inner wall of thepad opening 222 has a roughness B. If expressed by Ra, the roughness B is between 0.2 μm and 1.5 μm. - The formation of the
pad opening 222 and theoptional trench 223 also reinforces the via 221, so the inner wall of the via 221 may have a different roughness, namely roughness C. Again, if expressed by Ra, the roughness C is between 0.5 μm and 5.0 μm. A, B and C are mutually different. For example, the roughness A, B and C have relative relations, C>B>A. - If the
dielectric layer 220 includes the metallic complex, the formation of thepad opening 222 and theoptional trench 223 also activates the metallic complex. Once activated, such as by laser, thedielectric layer 220 helps another conductive layer to deposit with the help of the metallic complex. - In order to form the embedded circuit structure of the present invention, as shown in
FIG. 11 , a first deposition step is performed to form aconductive layer 230 in the via 221, thepad opening 222 and thetrench 223. Preferably, the first deposition step is an electroless plating procedure. If thedielectric layer 220 includes the metallic complex and is activated by the formation of thepad opening 222 and theoptional trench 223, the dielectric layer acts as a seed layer for the electroless plating. Theconductive layer 230 usually includes a metal, such as Cu or Al. If necessary, a second deposition step, such as electroplating, is optionally performed so that theconductive layer 230 fills the via 221, thepad opening 222 and thetrench 223. Because the inner wall of the via, the pad opening and the trench are formed or reinforced after the cleaning step, less copper lumps will be formed and a conductive layer of better quality can be obtained due to a smoother surface. - Optionally, the
organic film layer 250 may remain on thedielectric layer 220 or not. If not, theorganic film layer 250 is removed, so as to leave the dielectric layer 220 a substantially even surface, as shown inFIG. 12 . When theorganic film layer 250 includes a hydrophilic polymer, theorganic film layer 250 may be washed off by water. - Because the embedded structure of the present invention has gone through a patterning step after the cleaning step, the inner wall of the via, the pad opening and the trench of the present invention may have a smoother surface. Moreover, less copper lumps will be formed and a conductive layer of better quality can be obtained when a layer of copper is later deposited on the inner wall of the embedded structure of the present invention due to the smoother surface. The smoother surface is able to raise the reliability of the embedded structure of the present invention. In addition, the embedded structure of the present invention may further have a substantially even outer surface because of the protection of the organic film layer during the manufacturing process.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (13)
1. An embedded structure, comprising:
a dielectric layer, wherein the outer surface of said dielectric layer has a substantially even surface with a roughness A;
a pad opening disposed in said dielectric layer, wherein the inner wall of said pad opening has a roughness B; and
a via disposed in said pad opening and in said dielectric layer, wherein said via and said pad opening together define said embedded structure, the inner wall of said via has a roughness C and A, B, C are mutually different.
2. The embedded structure of claim 1 , further comprising:
a trench disposed in said dielectric layer, wherein the inner wall of said trench has said roughness B.
3. The embedded structure of claim 1 , wherein C>B>A.
4. The embedded structure of claim 1 , further comprising:
a conductive layer filling said via and said pad opening to form an embedded circuit structure.
5. The embedded structure of claim 4 , wherein said dielectric layer acts as a seed layer for said conductive layer.
6. The embedded structure of claim 1 , wherein said dielectric layer comprises a metallic complex.
7. The embedded structure of claim 6 , wherein said metallic complex comprises a metal selected from a group consisting of Mn, Cr, Pd and Pt.
8. The embedded structure of claim 1 , wherein said roughness A is expressed by Ra<0.5 μm.
9. The embedded structure of claim 1 , wherein said roughness B is expressed by 0.2 μm<Ra<0.5 μm.
10. The embedded structure of claim 1 , wherein said roughness C is expressed by 0.5 μm<Ra<5.0 μm.
11. The embedded structure of claim 1 , further comprising:
an organic film layer covering said dielectric layer and selectively exposing said via and said pad opening.
12. The embedded structure of claim 11 , wherein said organic film layer comprises a hydrophilic polymer, wherein said hydrophilic polymer comprises a functional group selected form a group consisting of hydroxyl group (—OH), amide group (—CONH2), sulfonic group (—SO3H) and carboxylic group (—COOH).
13. The embedded structure of claim 11 , wherein said organic film layer comprises a hydrophobic polymer, wherein said hydrophobic polymer is selected form a group consisting of methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamide resin, and polysiloxane resin.
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US12/211,816 US8191248B2 (en) | 2008-09-17 | 2008-09-17 | Method for making an embedded structure |
US13/413,666 US20120160551A1 (en) | 2008-09-17 | 2012-03-07 | Embedded structure of circuit board |
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Also Published As
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CN101677491A (en) | 2010-03-24 |
CN101677491B (en) | 2011-07-06 |
US20100065324A1 (en) | 2010-03-18 |
US8191248B2 (en) | 2012-06-05 |
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