KR100452040B1 - Method of forming a metal wiring in a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, wherein silicided surfaces in order to reduce reactivity or diffusivity of metal components included in lower metal wirings or junctions exposed through via holes. Modification of the interlayer insulating film from Hydrophobic to Less Hydrophobic, followed by redepositing the metal silicide on the sidewall of the via hole while removing the silicide layer on the surface of the metal wiring by a sputter etching method. Disclosed is a method of forming a metal wiring of a semiconductor device capable of preventing the film quality of a via hole sidewall from being degraded due to the penetration of the film and improving the adhesion properties of the interlayer insulating film, thereby improving the reliability of the process and the electrical characteristics of the device. .

Description

Method of forming a metal wiring in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of preventing film quality from deteriorating on the sidewalls of via holes and improving adhesion properties of an interlayer insulating film.

Until now, the contact precleaning process has been performed by sputter etching in the process of forming metal wires. However, this method has been performed by contacting the metal material from the contact bottom region to the via hole sidewalls. Deposition may occur to deteriorate an insulating property of the interlayer insulating layer. As a result, it is difficult to form the interlayer insulating layer with a low-k material in order to increase the operation speed of the device. In particular, since the interlayer insulating film formed of the low dielectric material is less dense than the general interlayer insulating film, it is not only susceptible to metal diffusion (especially copper diffusion) acting as a fast diffuser, but also has a hydrophobic surface property. Since there are many, the surface roughness of the sidewalls when the metal is redeposited may be rougher than that of the existing insulating film. As a result, a step coverage characteristic or an adhesion characteristic of the films formed thereon may be deteriorated in a subsequent process, and a problem may occur in that voids are formed by a subsequent thermal process.

Therefore, in order to solve the above problem, the present invention provides an interlayer insulating film with silicided surfaces in order to reduce reactivity or diffusivity of metal components included in the lower metal wirings or junctions exposed through the via holes. Infiltration of metal components by changing the hydrophobicity from hydrophobic to less hydrophobic and then redepositing the metal silicide on the sidewall of the via hole while removing the silicide layer on the surface of the metal wiring by a sputtering etching process. The present invention provides a method for forming a metal wiring of a semiconductor device which can prevent the film quality of the via hole sidewalls from deteriorating and improve the adhesion properties of the interlayer insulating film, thereby improving the reliability of the process and the electrical characteristics of the device. There is this.

1A to 1G are cross-sectional views of devices for describing names according to embodiments of the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 102 first interlayer insulating film

103: first hard mask 104: first diffusion barrier film

105: lower metal wiring 106: second interlayer insulating film

107: second hard mask 108a: via hole

108b: trench 108: dual damascene pattern

109: silicide layer 110: second diffusion barrier film

111: metal seed layer 112: upper metal wiring, via plug

According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, including providing a semiconductor substrate in which a dual damascene pattern formed of a via hole and a trench is formed in an interlayer insulating layer to expose a portion of the lower metal wiring through the via hole; Forming a silicide layer in an exposed region of the lower metal wiring by a silicide treatment process, performing a sputter etching so that the silicide layer is redeposited on the sidewall of the via hole while removing the silicide layer from the lower metal wiring, and the dual damascene pattern Filling the conductive metal with the conductive material to form the upper metal wiring and the via plug.

In the above, the silicide treatment process may be performed in a SiH ₄ surface treatment method to form a silicide layer on the exposed surface of the lower metal interconnection, and change the interlayer insulating film from hydrophobicity to less hydrophobicity, thereby simultaneously improving the adhesive property.

In addition, the silicide treatment process proceeds with a time delay such that the desorbed H ₂ O can be sufficiently discharged after the gas is discharged without a time delay when the preceding process is completed, and the particles are reacted by the reaction of SiH ₄ and H ₂ O. This can minimize the occurrence.

The silicide treatment process may be performed at a temperature of 150 to 350 ° C. to form the silicide layer in a thickness of 100 to 150 kPa.

Meanwhile, in the silicide treatment process, when the interlayer insulating film is sensitive to hydrogen, the surface treatment may be performed only by heat without the aid of plasma, and when the interlayer insulating film is not sensitive to hydrogen, plasma may be generated to increase the surface treatment effect. In this case, in the case of generating the plasma, low-frequency power in the range of 500 to 800W and high-frequency power in the range of 0 to 50W may be applied to increase the activation efficiency of SiH ₄ .

After the silicide treatment process and before the sputter etching, the surface temperature of the sidewalls and the bottom of the dual damascene pattern can be improved by cooling the temperature of the semiconductor substrate elevated during the silicide treatment process to a temperature below room temperature by in-situ. have.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

1A to 1G are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a first interlayer insulating film 102 and a first hard mask 103 are formed on a semiconductor substrate 101 on which various elements (not shown), such as a transistor or a flash memory cell, are formed to form a semiconductor device. Form. Subsequently, a trench and a via hole (not shown) are formed in a predetermined region of the interlayer insulating layer 102, and a first diffusion barrier layer 103 is formed on the sidewalls of the trench and the via hole (not shown). The metal wiring 104 is formed. Subsequently, the second interlayer insulating film 106 and the second hard mask 107 are sequentially formed on the whole.

Referring to FIG. 1B, a via hole 108a is formed to expose a predetermined region of the lower metal interconnection 104 by a dual damascene process, and a trench 108b is formed on the second interlayer insulating layer 106. As a result, a dual damascene pattern 108 including a via hole 108a and a trench 108b is formed.

Referring to FIG. 1C, in order to prevent the surface of the lower metal interconnection 105 exposed through the via hole 108a from being oxidized, a silicide treatment process may be performed without a time delay to prevent the surface of the lower metal interconnection 105 from being oxidized. The silicide layer 109 is formed on the exposed surface. Here, when the lower metal wiring is formed of copper, a copper silicide layer is formed.

On the other hand, the silicide treatment process for forming the silicide layer 109 on the surface of the lower metal wiring 105 proceeds to the SiH ₄ surface treatment method to form the silicide layer 109 on the exposed surface of the lower metal wiring 105. In addition, the second interlayer insulating layer 106 may be modified from hydrophobic to less hydrophobic to improve adhesion properties. The SiH ₄ surface treatment process is performed immediately after the gas is discharged (Degas) and without a time delay when the preceding process is completed. do. At this time, it is important to proceed with the SiH ₄ surface treatment with a time delay enough to allow the degassed H ₂ O to be sufficiently discharged after degassing without any time delay when the preceding process is completed. . This is to minimize the generation of particles by the reaction of SiH ₄ and H ₂ O (or O). In addition, the SiH ₄ surface treatment may be applied differently according to the kind of low dielectric material of the second interlayer insulating layer 106 to prevent the dielectric constant from increasing during the SiH ₄ surface treatment. For example, in the case of an interlayer insulating film sensitive to hydrogen, surface treatment is performed only by thermal without plasma assist, and in the case of an interlayer insulating film not sensitive to hydrogen, plasma is generated. To increase the surface treatment effect. In the case of generating the plasma, low frequency power in the range of 500 to 800 W and high frequency power in the range of 0 to 50 W are applied to increase the activation efficiency of SiH ₄ .

Subsequently, in the SiH ₄ surface treatment process, the elevated temperature of the semiconductor substrate 101 is cooled to a temperature below room temperature by In-Situ to improve the surface roughness of the sidewall and the bottom of the dual damascene pattern 108. Let's do it.

1D and 1E, sputter etching is performed. In this case, the stuffer etching may be performed using argon. When the sputter etching is performed, the silicide layer 109 formed on the lower metal wiring 105 is etched and redeposited on the sidewall of the via hole 108a. When all of the silicide layer 109 is removed from the surface of the lower metal wiring 105, an oxide film (not shown) formed on the surface of the lower metal wiring 105 is removed. At this time, the dual damascene pattern 108 in a state in which the silicide component having a reduced chemical activity during the sputter etching process is separated from the surface of the lower metal interconnection 105 and redeposited first on the sidewall of the via hole 108a. The conductive material is embedded in the to ensure thermal stability in subsequent processes. In addition, since the surface energy can be changed, the adhesion characteristics and the step coverage characteristics can be improved.

Referring to FIG. 1F, after the second diffusion barrier layer 110 is formed on the entire structure including the sidewalls and the bottom of the dual damascene pattern 108 in a conventional process, the sidewalls and the bottom of the dual damascene pattern 108 are formed. Only the metal seed layer 111 is formed.

Referring to FIG. 1G, the inside of the dual damascene pattern 108 of FIG. 1F is filled with a conductive material 112 to form a metal interconnect 112 in a trench (108b of FIG. 1F) and a via hole (108a of FIG. 1F). The via plug 112 is formed therein.

As described above, in the present invention, the silicide layer on the surface of the metal wiring surface is sputtered after modifying the interlayer insulating film from hydrophobic to less hydrophobic while silicifying the surface of the lower metal wiring or the junction. By re-depositing the metal silicide on the sidewall of the via hole while removing it by the etching process, the film quality of the via hole sidewall is prevented from being degraded by the penetration of metal components, and the adhesion property of the interlayer insulating film is improved to improve the reliability of the process. The electrical characteristics of the device can be improved.

In addition, the SiH ₄ surface treatment process can increase the surface energy of the interlayer insulating film in the via hole region, thereby improving the wettability of the metal silicide layer redeposited on the via hole side, thereby improving the step coverage characteristics of the subsequent barrier process. Can be.

On the other hand, since there is a redeposited silicide layer between the diffusion barrier and the interlayer insulating film, if a redeposited metal layer is present instead of the silicide layer, voids may be generated due to a problem of adhesion between the insulating film and the redeposited metal layer during the subsequent thermal process. You can prevent it.

If necessary, plasma is generated during the SiH ₄ surface treatment process to simultaneously remove the metal oxide film formed on the surface of the metal wiring under the via hole with hydrogen radicals, thereby preventing the silicide layer from being formed unevenly or increasing the via resistance. can do.

Claims (7)

Providing a semiconductor substrate having a dual damascene pattern formed of a via hole and a trench in an interlayer insulating layer to expose a portion of the lower metal wiring through the via hole; Forming a silicide layer in an exposed region of the lower metal wiring by a silicide treatment process; Performing a sputter etching to remove the silicide layer from the lower metal wires and to re-deposit the silicide layer on the sidewall of the via hole; And Filling the dual damascene pattern with a conductive material to form an upper metal wiring and a via plug. The method of claim 1, The silicide treatment process proceeds by SiH ₄ surface treatment to form the silicide layer on the exposed surface of the lower metal interconnection, while changing the interlayer insulating film from hydrophobicity to less hydrophobicity, thereby simultaneously improving adhesive properties. A metal wiring formation method of a semiconductor element. The method of claim 1, When the silicide treatment process is completed, the gas is discharged without a time delay after the preceding process is completed, and a time delay is sufficient to allow sufficient removal of the desorbed H ₂ O by the reaction between the SiH ₄ and the H ₂ O. A method for forming metal wirings in a semiconductor device, characterized by minimizing the generation of particles. The method according to any one of claims 1 to 3, The silicide treatment step is performed at a temperature of 150 to 350 ° C. to form the silicide layer to a thickness of 100 to 150 kPa. The method of claim 1, In the silicide treatment process, when the interlayer insulating film is sensitive to hydrogen, the surface treatment is performed only by heat without the aid of plasma, and when the interlayer insulating film is not sensitive to hydrogen, plasma is generated to increase the surface treatment effect. Metal wiring formation method of a semiconductor element. The method of claim 5, wherein In the case of generating the plasma, a metal wiring forming method of a semiconductor device, characterized in that the activation efficiency of SiH ₄ is increased by applying a low frequency power in a range of 500 to 800W and a high frequency power in a range of 0 to 50W. The method of claim 1, wherein after performing the silicide treatment process, before performing the sputter etching, Cooling the temperature of the semiconductor substrate elevated during the silicide treatment process to a temperature below room temperature by in-situ to improve surface roughness of sidewalls and bottom surfaces of the dual damascene pattern. .