US20120126901A1 - Programmable electro-magnetic-interference (emi) reduction with enhanced noise immunity and process tolerance - Google Patents
Programmable electro-magnetic-interference (emi) reduction with enhanced noise immunity and process tolerance Download PDFInfo
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- US20120126901A1 US20120126901A1 US12/948,896 US94889610A US2012126901A1 US 20120126901 A1 US20120126901 A1 US 20120126901A1 US 94889610 A US94889610 A US 94889610A US 2012126901 A1 US2012126901 A1 US 2012126901A1
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
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Definitions
- This invention relates to Electro-Magnetic Interference (EMI) reduction, and more particularly to circuits with frequency dithering for reduced EMI.
- EMI Electro-Magnetic Interference
- Power converters may include a large transistor that is rapidly switched on and off. This rapid switching can cause noise on the resulting power-supply voltage, and upon other nearly signals. Downstream and upstream devices from the power converter can generate emissions that create disturbances in other electronic equipment. For example, a noisy switching power supply driving a portable computer may emit radiation that interferes with a television receiver. Intentional receivers, such as televisions, cellular phones, pagers, and wireless devices, are often affected by unintentional transmitters that emit electromagnetic radiation. As both types of electronic equipment become more common, interference becomes more noticeable to the consumer.
- Electromagnetic interference is a measure of the amount of interference that an electronic device (the unintentional transmitter) disturbs an intentional receiver. Government agencies such as the Federal Communication Commission (FCC) strictly regulate the amount of radiation or EMI that an electronic device can generate.
- FCC Federal Communication Commission
- Coax wires and shielded cables are effective at containing radiation, but are expensive, heavy, bulky, and inflexible. The weight and bulk of shielded cables make them undesirable for portable devices.
- Metal chassis with sealed seams are effective for reducing EMI of desktop equipment, but portable devices are kept light by using plastic.
- FIG. 1 shows a graph of radiation intensity as a function of frequency for an un-modulated clock signal.
- a sharp spike occurs at a harmonic of the clock's frequency, 40 MHz. Since the clock constantly operates at the rated frequency, all of the energy of the radiation appears in a narrow spike, which has a large amplitude. The spike has an amplitude over the EMI limit set by the FCC. The high intensity of the spike can cause interference in a receiver.
- FIG. 2 is a graph of radiation intensity as a function of frequency generated by a modulated clock.
- the clock's frequency is not constant, but is varied with time over a range of +5% to ⁇ 5% of the rated frequency.
- the clock operates at 40 MHz for a period of time, but also operates at other frequencies between 38 MHz and at 42 MHz at other times.
- Such a clock can be generated by slowly changing the frequency from 38 MHz to 42 MHz and then slowly reducing the frequency back to 38 MHz.
- a voltage-controlled oscillator (VCO) can be used with the input voltage being slewed back and forth between voltages that generate 38 MHz and 42 MHz oscillations.
- VCO voltage-controlled oscillator
- the modulated clock spends only part of the time at 40 MHz, the intensity of the radiation, averaged over a relatively long time, is reduced.
- the total energy of the radiation at all frequencies is about the same as for the un-modulated clock of FIG. 1 , but the intensity at any particular frequency is greatly reduced. Interference at any one frequency is reduced since receivers generally are tuned to a particular frequency (even FM receivers are tuned to a relatively small range of frequencies).
- modulating the clock's frequency reduces the maximum intensity of radiation at any one frequency, although the energy radiated at all frequencies is not reduced. This has the practical effect of reducing interference for receivers tuned to a fixed frequency.
- FIG. 3 is a graph of a modulated clock's frequency as a function of time over a few sweep periods.
- the clock's nominal frequency is 40 MHz.
- the clock is modulated by +/ ⁇ 5%, from 38 MHz to 42 MHz.
- the clock's frequency is swept from minimum to maximum frequencies over one or two thousand clock periods so that adjacent clock pulses have a very small variation.
- a 40 MHz clock with a 25 nanosecond (ns) period is varied from 26.25 ns to 23.75 ns over a sweep period, a variation of +/ ⁇ 1.25 ns.
- a 37 KHz sweep rate has a sweep period of 27 micro-seconds ( ⁇ s).
- a sweep period is 27 ⁇ s/25 ns or 1081 clock periods.
- the cycle-to-cycle period variation for two adjacent clock periods is thus 5 ns/1081 or 4.62 pico-seconds (ps).
- the sweep frequency is typically 15 to 50 KHz.
- Such spread spectrum using frequency dithering is effective in reducing EMI.
- Bulky filter components such as large capacitors and inductors are not needed.
- frequency dithering requires switching precise components such as precision capacitors to generate small steps or adjustments in frequency. Matching of these precision capacitors or resistors is difficult.
- Very large capacitors or very small currents or resistors must be used. Such small currents are themselves subject to noise interference and leakages and are thus undesirable.
- a frequency dithering circuit for reducing EMI for a switched power supply.
- a dithering circuit that does not need bulky filters or precision components is desirable.
- a dithering circuit that can be integrated with other circuits for a small form factor is desirable.
- a dithering circuit that can be tuned or programmed for the degree of frequency dithering is desirable.
- a dithering circuit that can be used with an oscillator for a switched power supply is desirable.
- a dithering circuit that can be used as a module for a clock generator is also desired.
- FIG. 1 shows a graph of radiation intensity as a function of frequency for an un-modulated clock signal.
- FIG. 2 is a graph of radiation intensity as a function of frequency generated by a modulated clock.
- FIG. 3 is a graph of a modulated clock's frequency as a function of time over a few sweep periods.
- FIG. 4 is a schematic of a frequency dithering circuit for modulating oscillating of a clock.
- FIG. 5 is a diagram of the control circuit.
- FIG. 6 shows a simple DAC.
- FIG. 7 is a waveform graph of sawtooth voltages for controlling frequency dithering.
- FIG. 8 is an expansion of the time scale of the waveform of FIG. 7 .
- FIG. 9 is a spectrum diagram of an oscillator without frequency dithering.
- FIG. 10 is a spectrum diagram of a clock with frequency dithering, such as the circuit of FIG. 4 .
- FIG. 11 is a programmable dithering circuit.
- FIGS. 12A-C are waveforms showing the effects on emissions of different programmable values of feedback resistance.
- the present invention relates to an improvement in EMI reduction circuits.
- the following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements.
- Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
- DAC digital-to-analog converter
- the inventors further realize that matching of precision resistors and capacitors for the DAC can be relaxed if the resolution requirement of the DAC is relaxed.
- the DAC resolution can be reduced by scaling and subtraction of the DAC output.
- the inventors further realize that programming the subtractor after the DAC can allow for the degree of dithering to be programmed.
- FIG. 4 is a schematic of a frequency dithering circuit for modulating oscillating of a clock.
- Clock CLK may be used to switch a large field-effect transistor (FET) in a switching power supply, or may be used for some other purpose.
- SR latch 24 toggles to cause its outputs CLK and CLKB to pulse.
- the CLK signal is fed back to control circuit 22 .
- control circuit 22 is a counter, such as a binary counter.
- the count value from control circuit 22 is input to digital-to-analog converter (DAC) 20 , and DAC 20 converts the digital count value to an analog voltage VDAC that is a fraction of analog input voltage Vref, with the fraction depending on the digital input value from control circuit 22 .
- DAC digital-to-analog converter
- Voltage divider 26 generates a lower voltage Vref 2 from Vref, and this lower reference voltage Vref 2 is input to subtractor 31 .
- the other input to subtractor 31 is the converted analog voltage VDAC from DAC 20 .
- Subtractor 31 includes op amp 30 , which receives Vref 2 on its non-inverting (+) input.
- Input resistor 36 is in series between VDAC from DAC 20 and the inverting ( ⁇ ) input to op amp 30 .
- Feedback resistor 18 is connected between the output and inverting input of op amp 30 . The ratio of resistances of input resistor 36 and feedback resistor 18 determines the amount of scaling of VDAC, which also determines the degree of frequency dithering.
- Subtractor 31 scales down the analog output from DAC 20 .
- the output of subtractor 31 is ramp voltage Vrmp_max, which is a scaled-down reproduction of the VDAC voltage from DAC 20 .
- Scaling down the DAC output also reduces the effect of errors from DAC 20 on the frequency of clock CLK.
- the dithering circuit is less sensitive to errors from DAC 20 due to subtractor 31 .
- a larger step size or difference between voltage levels of DAC 20 can be tolerated.
- resistors, capacitors, or other components inside DAC 20 do not have to be matched as precisely.
- the binary count value from control circuit 22 counts up and then counts down.
- the resulting converted analog voltage VDAC from DAC 20 is a sawtooth wave that slowly rises and then slowly falls.
- Subtractor 31 reduces the amplitude of the sawtooth wave from DAC 20 , so that ramp voltage Vrmp_max is also a sawtooth wave, but with a smaller voltage swing.
- switch 46 When CLK is high and CLKB low, switch 46 is closed, and switch 47 is open. Switch 46 allows current source 42 to drive current from the power supply to node Vrmp, charging capacitor 48 . Voltage Vrmp rises. Once Vrmp rises above ramp voltage Vrmp_max, comparator 32 is triggered, since its + input is Vrmp and its ⁇ input is Vrmp_max. Comparator 32 triggers a pulse to the reset input of SR latch 24 causing CLK to go low and CLKB to go high.
- Ramp voltage Vrmp_max acts as a maximum voltage limit
- limit voltage VP acts as a minimum voltage limit. While the minimum voltage limit is fixed, the maximum voltage limit varies with the sawtooth wave from DAC 20 .
- control circuit 22 Once control circuit 22 has reached the maximum count value, it reverses direction and counts down.
- the decreasing digital values applied to DAC 20 produce a series of decreasing steps down in voltage VDAC. These large steps in VDAC are scaled down by subtractor 31 to smaller steps downward in voltage Vrmp_max. As Vrmp_max drops, charging and discharging require less time, and the clock frequency increases.
- Vrmp_max Vrmp_peak
- VDAC the series resistance Rs of input resistor 36
- Rf of feedback resistor 18 The peak value of Vrmp_max, Vrmp_peak, is related to Vref 2 , VDAC, the series resistance Rs of input resistor 36 and the feedback resistance Rf of feedback resistor 18 as follows:
- Vrmp_peak Vref2 ⁇ (Rf/Rs)*VDAC.
- adjusting the ratio of resistors 18 , 36 adjusts the peak limit voltage, the maximum charging time, and thus the period of the clock.
- Rf/Rs adjusts a degree or maximum amount of frequency dithering.
- FIG. 5 is a diagram of the control circuit.
- Control circuit 22 of FIG. 4 is a binary up/down counter in some embodiments.
- An (N+1)-bit binary count value CBO:CBN is generated from input clock CLK, CLKB.
- the inverse count value is CBOB:CBNB. This count value CBO:CBN is input to DAC 20 .
- An intermediate count value BO:BN and its inverse bits BOB:BNB are generated by flip-flops 62 .
- CLK is applied to the first of flip-flops 62 , and each flip-flop 62 acts as a toggle flip-flop with its QB output fed back to its D input.
- the Q output of one flip-flop 62 is input as the clock to the next flip-flop 62 .
- Flip-flops 62 act as a ripple counter producing a binary count value.
- a final count value is generated from the intermediate count value by logic including AND gates 64 , 66 , OR gates 68 , and flip-flops 70 .
- AND gates 64 and 66 act as gate logic to pass either signal BO:B(N ⁇ 1) or BOB:B(N ⁇ 1)B to the D input of D-flip-flops 70 depending the logic signal of BN and BNB.
- CLKB is rising from 0 to 1
- flip-flop 70 clocks the input signal at D to its output Q and QB. The result is that the count value counts up in binary to FF, then counts down from FF to 00.
- FIG. 6 shows a simple DAC.
- Analog input voltage Vref is applied to a voltage divider of resistors 72 to ground, producing a series of voltages between Vref and ground. When resistors 72 all have about the same value, a series of intermediate voltages are produced.
- Mux logic 80 selects one of these intermediate voltages for output as VDAC.
- the select for mux logic 80 is the binary count value CBO:CBN and its inverse CBOB:CBNB from control logic 22 .
- DAC 20 can be a simplified DAC since subtractor 31 reduces the value of the voltage steps, so that errors produce a smaller effect on the frequency of CLK. Thus frequency dithering is more tolerant of errors.
- Resistors 72 do not have to be precisely matched, since some error is tolerable. Smaller currents may be used, reducing power. For example, resistors 72 may be matched in resistance values to within 5% of each other when errors are tolerated.
- FIG. 7 is a waveform graph of sawtooth voltages for controlling frequency dithering.
- VDAC is a sawtooth wave that slowly swings between ground and 2.5 volts.
- Subtractor 31 scales this down to a swing of only about 300 mV, from 1.1 to 1.4 volts on Vrmp_max.
- FIG. 8 is an expansion of the time scale of the waveform of FIG. 7 .
- VDAC slowly steps down each time clock CLK pulses, as the count value from control circuit 22 is reduced.
- Vrmp_max slows steps upward, but by smaller increments due to the attenuation by subtractor 31 .
- the reverse behavior occurs for the other half of the sawtooth wave, when VDAC is stepping upward. and Vrmp_max is stepping downward.
- FIG. 9 is a spectrum diagram of an oscillator without frequency dithering.
- noise and emissions vary with frequency.
- the maximum emission occurs at about 80 kHz.
- the maximum emission is greater than 0 dBV. This may exceed emission limits.
- FIG. 10 is a spectrum diagram of a clock with frequency dithering, such as the circuit of FIG. 4 .
- noise and emissions vary with frequency.
- the maximum emissions occurs in a broad range of about 75-90 kHz.
- the maximum emission is about 15 dBV less than 0 dBV. This may meet emission limits.
- frequency dithering spread out the peak emission over a wider range of frequencies, producing a broader and lower peak.
- FIG. 11 is a programmable dithering circuit.
- the circuit is similar to that of FIG. 4 , except that feedback resistor 18 is replaced by digitally-controlled resistor 50 .
- the value Rf of the feedback resistance is controlled by digital select value SEL, which selects one or more parallel resistors using switches. Thus the value of Rf may be programmed.
- FIGS. 12A-C are waveforms showing the effects on emissions of different programmable values of feedback resistance.
- digitally-controlled resistor 50 FIG. 11
- the ratio of feedback resistor 18 to input resistor 36 , Rf/Rs can be adjusted. This varies the contribution of feedback.
- the amount of frequency dithering is also varied as Vrmp_max swings over a wider voltage range for higher values of Rf/Rs.
- Rf/Rs is 0.03.
- a narrow peak emission of about ⁇ 15 dBV occurs around 77 kHz.
- Rf/Rs is 0.06.
- the peak emission is lowered to about ⁇ 20 dBV but is spread over a wider range of frequencies.
- Rf/Rs is 0.09.
- the peak emission is lowered to less than ⁇ 20 dBV but over a wider range of frequency.
- the dithering circuit may also be used in other power converters, or in more general applications such as a clock generator module or other clock generators.
- the charge pumps may be implemented as transistors as approximations.
- a square wave, a sine wave, or other kinds of waveforms for modulation can be generated instead of the sawtooth wave described.
- the entire circuit may be integrated onto a single integrated circuit. Polarities of signals can be reversed. Other counting and encoding schemes other than binary may be used.
- the control logic can be implemented as a binary counter using synchronous rather than ripple logic, and can be implemented in a variety of ways.
- the DAC can be implemented in a variety of ways. Voltages and other data shown in the waveforms are examples and can vary with different embodiments and conditions. Reset inputs (not shown) can be added to each flip-flop 62 , 70 in FIG. 5 . Other kinds of bistables may be substituted for the SR latch, such as JK flip-flops, toggle flip-flops, D-type flip-flops, etc.
- the background of the invention section may contain background information about the problem or environment of the invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant.
- Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result.
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Description
- This invention relates to Electro-Magnetic Interference (EMI) reduction, and more particularly to circuits with frequency dithering for reduced EMI.
- Power converters may include a large transistor that is rapidly switched on and off. This rapid switching can cause noise on the resulting power-supply voltage, and upon other nearly signals. Downstream and upstream devices from the power converter can generate emissions that create disturbances in other electronic equipment. For example, a noisy switching power supply driving a portable computer may emit radiation that interferes with a television receiver. Intentional receivers, such as televisions, cellular phones, pagers, and wireless devices, are often affected by unintentional transmitters that emit electromagnetic radiation. As both types of electronic equipment become more common, interference becomes more noticeable to the consumer.
- Electromagnetic interference (EMI) is a measure of the amount of interference that an electronic device (the unintentional transmitter) disturbs an intentional receiver. Government agencies such as the Federal Communication Commission (FCC) strictly regulate the amount of radiation or EMI that an electronic device can generate.
- Improving technology also worsens the EMI problem. Faster clock rates of higher-speed equipment generate more radiation. Higher resolution monitors and displays require that more pixels be transferred to the screen for each screen refresh period; thus a higher clock rate and more interference results.
- Traditional techniques to reduce EMI attempt to contain radiation or to reduce the amount of radiation generated. Coax wires and shielded cables are effective at containing radiation, but are expensive, heavy, bulky, and inflexible. The weight and bulk of shielded cables make them undesirable for portable devices. Metal chassis with sealed seams are effective for reducing EMI of desktop equipment, but portable devices are kept light by using plastic.
- Lower voltages reduce the intensity of the radiation generated, and the new 3-volt standard has helped reduce EMI at all harmonics. Proper impedance matching and termination of signals reduces ringing and harmonics, and shorter signal traces further reduce radiation. Ground planes on PCB's or ground lines running parallel with signal lines effectively shield signals on boards. Filtering can reduce sharp rise and fall times and reduce radiation by wave shaping since more sinusoidal waves have fewer harmonics than square waves. Of course, filters require additional capacitors, resistors, or inductors, raising the cost. All of these techniques are useful to varying extents.
- Large physical components are often needed as filters to reduce noise and EMI. For example, a large inductor coil may be added to a power converter, along with high-value capacitors that also are bulky. Precision capacitors or resistors may be needed. These bulky components are undesirable and costly and defeat integration.
- A newer technique to reduce EMI is to vary or modulate the frequency of clocks. This technique known as spread spectrum, since the frequency spectrum of the clock is spread out over a wider range of frequencies.
FIG. 1 shows a graph of radiation intensity as a function of frequency for an un-modulated clock signal. A sharp spike occurs at a harmonic of the clock's frequency, 40 MHz. Since the clock constantly operates at the rated frequency, all of the energy of the radiation appears in a narrow spike, which has a large amplitude. The spike has an amplitude over the EMI limit set by the FCC. The high intensity of the spike can cause interference in a receiver. -
FIG. 2 is a graph of radiation intensity as a function of frequency generated by a modulated clock. The clock's frequency is not constant, but is varied with time over a range of +5% to −5% of the rated frequency. Thus the clock operates at 40 MHz for a period of time, but also operates at other frequencies between 38 MHz and at 42 MHz at other times. Such a clock can be generated by slowly changing the frequency from 38 MHz to 42 MHz and then slowly reducing the frequency back to 38 MHz. A voltage-controlled oscillator (VCO) can be used with the input voltage being slewed back and forth between voltages that generate 38 MHz and 42 MHz oscillations. - Since the modulated clock spends only part of the time at 40 MHz, the intensity of the radiation, averaged over a relatively long time, is reduced. The total energy of the radiation at all frequencies is about the same as for the un-modulated clock of
FIG. 1 , but the intensity at any particular frequency is greatly reduced. Interference at any one frequency is reduced since receivers generally are tuned to a particular frequency (even FM receivers are tuned to a relatively small range of frequencies). - Thus modulating the clock's frequency reduces the maximum intensity of radiation at any one frequency, although the energy radiated at all frequencies is not reduced. This has the practical effect of reducing interference for receivers tuned to a fixed frequency.
- Long Sweep Period of Modulation—
FIG. 3 -
FIG. 3 is a graph of a modulated clock's frequency as a function of time over a few sweep periods. The clock's nominal frequency is 40 MHz. The clock is modulated by +/−5%, from 38 MHz to 42 MHz. The clock's frequency is swept from minimum to maximum frequencies over one or two thousand clock periods so that adjacent clock pulses have a very small variation. A 40 MHz clock with a 25 nanosecond (ns) period is varied from 26.25 ns to 23.75 ns over a sweep period, a variation of +/−1.25 ns. A 37 KHz sweep rate has a sweep period of 27 micro-seconds (μs). A sweep period is 27 μs/25 ns or 1081 clock periods. The cycle-to-cycle period variation for two adjacent clock periods is thus 5 ns/1081 or 4.62 pico-seconds (ps). The sweep frequency is typically 15 to 50 KHz. - Such spread spectrum using frequency dithering is effective in reducing EMI. Bulky filter components such as large capacitors and inductors are not needed. However, often such frequency dithering requires switching precise components such as precision capacitors to generate small steps or adjustments in frequency. Matching of these precision capacitors or resistors is difficult. Very large capacitors or very small currents or resistors must be used. Such small currents are themselves subject to noise interference and leakages and are thus undesirable.
- What is desired is a frequency dithering circuit for reducing EMI for a switched power supply. A dithering circuit that does not need bulky filters or precision components is desirable. A dithering circuit that can be integrated with other circuits for a small form factor is desirable. A dithering circuit that can be tuned or programmed for the degree of frequency dithering is desirable. A dithering circuit that can be used with an oscillator for a switched power supply is desirable. A dithering circuit that can be used as a module for a clock generator is also desired.
-
FIG. 1 shows a graph of radiation intensity as a function of frequency for an un-modulated clock signal. -
FIG. 2 is a graph of radiation intensity as a function of frequency generated by a modulated clock. -
FIG. 3 is a graph of a modulated clock's frequency as a function of time over a few sweep periods. -
FIG. 4 is a schematic of a frequency dithering circuit for modulating oscillating of a clock. -
FIG. 5 is a diagram of the control circuit. -
FIG. 6 shows a simple DAC. -
FIG. 7 is a waveform graph of sawtooth voltages for controlling frequency dithering. -
FIG. 8 is an expansion of the time scale of the waveform ofFIG. 7 . -
FIG. 9 is a spectrum diagram of an oscillator without frequency dithering. -
FIG. 10 is a spectrum diagram of a clock with frequency dithering, such as the circuit ofFIG. 4 . -
FIG. 11 is a programmable dithering circuit. -
FIGS. 12A-C are waveforms showing the effects on emissions of different programmable values of feedback resistance. - The present invention relates to an improvement in EMI reduction circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
- The inventors have realized that a digital-to-analog converter (DAC) can be used to adjust the frequency of an oscillator or other clock generator. This frequency dithering can reduce or eliminate bulky filter components and allow for integration and small form factor devices.
- The inventors further realize that matching of precision resistors and capacitors for the DAC can be relaxed if the resolution requirement of the DAC is relaxed. The DAC resolution can be reduced by scaling and subtraction of the DAC output. The inventors further realize that programming the subtractor after the DAC can allow for the degree of dithering to be programmed.
-
FIG. 4 is a schematic of a frequency dithering circuit for modulating oscillating of a clock. Clock CLK may be used to switch a large field-effect transistor (FET) in a switching power supply, or may be used for some other purpose.SR latch 24 toggles to cause its outputs CLK and CLKB to pulse. The CLK signal is fed back tocontrol circuit 22. In some embodiments,control circuit 22 is a counter, such as a binary counter. The count value fromcontrol circuit 22 is input to digital-to-analog converter (DAC) 20, andDAC 20 converts the digital count value to an analog voltage VDAC that is a fraction of analog input voltage Vref, with the fraction depending on the digital input value fromcontrol circuit 22. -
Voltage divider 26 generates a lower voltage Vref2 from Vref, and this lower reference voltage Vref2 is input tosubtractor 31. The other input tosubtractor 31 is the converted analog voltage VDAC fromDAC 20. -
Subtractor 31 includesop amp 30, which receives Vref2 on its non-inverting (+) input.Input resistor 36 is in series between VDAC fromDAC 20 and the inverting (−) input toop amp 30.Feedback resistor 18 is connected between the output and inverting input ofop amp 30. The ratio of resistances ofinput resistor 36 andfeedback resistor 18 determines the amount of scaling of VDAC, which also determines the degree of frequency dithering. -
Subtractor 31 scales down the analog output fromDAC 20. The output ofsubtractor 31 is ramp voltage Vrmp_max, which is a scaled-down reproduction of the VDAC voltage fromDAC 20. Scaling down the DAC output also reduces the effect of errors fromDAC 20 on the frequency of clock CLK. Thus the dithering circuit is less sensitive to errors fromDAC 20 due tosubtractor 31. A larger step size or difference between voltage levels ofDAC 20 can be tolerated. Thus resistors, capacitors, or other components insideDAC 20 do not have to be matched as precisely. - The binary count value from
control circuit 22 counts up and then counts down. The resulting converted analog voltage VDAC fromDAC 20 is a sawtooth wave that slowly rises and then slowly falls.Subtractor 31 reduces the amplitude of the sawtooth wave fromDAC 20, so that ramp voltage Vrmp_max is also a sawtooth wave, but with a smaller voltage swing. - When CLK is high and CLKB low,
switch 46 is closed, and switch 47 is open.Switch 46 allowscurrent source 42 to drive current from the power supply to node Vrmp, chargingcapacitor 48. Voltage Vrmp rises. Once Vrmp rises above ramp voltage Vrmp_max,comparator 32 is triggered, since its + input is Vrmp and its − input is Vrmp_max.Comparator 32 triggers a pulse to the reset input ofSR latch 24 causing CLK to go low and CLKB to go high. - When CLK is low and CLKB is high,
switch 46 is open, and switch 47 is closed.Switch 47 allowscurrent sink 44 to sink current to ground from node Vrmp, dischargingcapacitor 48. Voltage Vrmp falls. Limit voltage VP is generated byvoltage source 28. Once Vrmp falls below limit voltage VP,comparator 34 is triggered, since its + input is VP and its − input is Vrmp.Comparator 34 triggers a pulse to the set input ofSR latch 24 causing CLK to go high and CLKB to go low. - Ramp voltage Vrmp_max acts as a maximum voltage limit, while limit voltage VP acts as a minimum voltage limit. While the minimum voltage limit is fixed, the maximum voltage limit varies with the sawtooth wave from
DAC 20. - As Vrmp slowly rises as the count value input to
DAC 20 increases, the upper limit rises. Sincecurrent source 42 delivers a fixed current, it takes a longer period of time to chargecapacitor 48 up to the new higher limit of Vrmp. This longer time required to chargecapacitor 48 to the higher Vrmp_max delays the next falling transition of CLK, thus increasing the clock period and decreasing the frequency. Likewise, the increased charge oncapacitor 48 at the higher Vrmp that matches Vrmp_max takes a longer time to discharge, so the rising transitions of CLK are also delayed. Thus both clock edges are delayed as Vrmp_max rises, and frequency drops. - Once
control circuit 22 has reached the maximum count value, it reverses direction and counts down. The decreasing digital values applied toDAC 20 produce a series of decreasing steps down in voltage VDAC. These large steps in VDAC are scaled down bysubtractor 31 to smaller steps downward in voltage Vrmp_max. As Vrmp_max drops, charging and discharging require less time, and the clock frequency increases. - The peak value of Vrmp_max, Vrmp_peak, is related to Vref2, VDAC, the series resistance Rs of
input resistor 36 and the feedback resistance Rf offeedback resistor 18 as follows: -
Vrmp_peak=Vref2−(Rf/Rs)*VDAC. - Thus adjusting the ratio of
resistors -
FIG. 5 is a diagram of the control circuit.Control circuit 22 ofFIG. 4 is a binary up/down counter in some embodiments. An (N+1)-bit binary count value CBO:CBN is generated from input clock CLK, CLKB. The inverse count value is CBOB:CBNB. This count value CBO:CBN is input toDAC 20. - An intermediate count value BO:BN and its inverse bits BOB:BNB are generated by flip-
flops 62. CLK is applied to the first of flip-flops 62, and each flip-flop 62 acts as a toggle flip-flop with its QB output fed back to its D input. The Q output of one flip-flop 62 is input as the clock to the next flip-flop 62. Flip-flops 62 act as a ripple counter producing a binary count value. - A final count value is generated from the intermediate count value by logic including AND
gates gates 68, and flip-flops 70. ANDgates flops 70 depending the logic signal of BN and BNB. When CLKB is rising from 0 to 1, flip-flop 70 clocks the input signal at D to its output Q and QB. The result is that the count value counts up in binary to FF, then counts down from FF to 00. -
FIG. 6 shows a simple DAC. Analog input voltage Vref is applied to a voltage divider ofresistors 72 to ground, producing a series of voltages between Vref and ground. Whenresistors 72 all have about the same value, a series of intermediate voltages are produced.Mux logic 80 selects one of these intermediate voltages for output as VDAC. The select formux logic 80 is the binary count value CBO:CBN and its inverse CBOB:CBNB fromcontrol logic 22. -
DAC 20 can be a simplified DAC sincesubtractor 31 reduces the value of the voltage steps, so that errors produce a smaller effect on the frequency of CLK. Thus frequency dithering is more tolerant of errors.Resistors 72 do not have to be precisely matched, since some error is tolerable. Smaller currents may be used, reducing power. For example,resistors 72 may be matched in resistance values to within 5% of each other when errors are tolerated. -
FIG. 7 is a waveform graph of sawtooth voltages for controlling frequency dithering. VDAC is a sawtooth wave that slowly swings between ground and 2.5 volts.Subtractor 31 scales this down to a swing of only about 300 mV, from 1.1 to 1.4 volts on Vrmp_max. -
FIG. 8 is an expansion of the time scale of the waveform ofFIG. 7 . VDAC slowly steps down each time clock CLK pulses, as the count value fromcontrol circuit 22 is reduced. Vrmp_max slows steps upward, but by smaller increments due to the attenuation bysubtractor 31. The reverse behavior occurs for the other half of the sawtooth wave, when VDAC is stepping upward. and Vrmp_max is stepping downward. -
FIG. 9 is a spectrum diagram of an oscillator without frequency dithering. In this idealized example, noise and emissions vary with frequency. The maximum emission occurs at about 80 kHz. The maximum emission is greater than 0 dBV. This may exceed emission limits. -
FIG. 10 is a spectrum diagram of a clock with frequency dithering, such as the circuit ofFIG. 4 . In this example, noise and emissions vary with frequency. The maximum emissions occurs in a broad range of about 75-90 kHz. The maximum emission is about 15 dBV less than 0 dBV. This may meet emission limits. Thus frequency dithering spread out the peak emission over a wider range of frequencies, producing a broader and lower peak. -
FIG. 11 is a programmable dithering circuit. The circuit is similar to that ofFIG. 4 , except thatfeedback resistor 18 is replaced by digitally-controlledresistor 50. The value Rf of the feedback resistance is controlled by digital select value SEL, which selects one or more parallel resistors using switches. Thus the value of Rf may be programmed. -
FIGS. 12A-C are waveforms showing the effects on emissions of different programmable values of feedback resistance. Using digitally-controlled resistor 50 (FIG. 11 ), the ratio offeedback resistor 18 to inputresistor 36, Rf/Rs, can be adjusted. This varies the contribution of feedback. The amount of frequency dithering is also varied as Vrmp_max swings over a wider voltage range for higher values of Rf/Rs. - In
FIG. 12A , Rf/Rs is 0.03. A narrow peak emission of about −15 dBV occurs around 77 kHz. InFIG. 12B , Rf/Rs is 0.06. The peak emission is lowered to about −20 dBV but is spread over a wider range of frequencies. - In
FIG. 12C , Rf/Rs is 0.09. The peak emission is lowered to less than −20 dBV but over a wider range of frequency. - Several other embodiments are contemplated by the inventors. For example, while the use of the dithering circuit for a power supply has been described, the dithering circuit may also be used in other power converters, or in more general applications such as a clock generator module or other clock generators. The charge pumps may be implemented as transistors as approximations.
- A square wave, a sine wave, or other kinds of waveforms for modulation can be generated instead of the sawtooth wave described. The entire circuit may be integrated onto a single integrated circuit. Polarities of signals can be reversed. Other counting and encoding schemes other than binary may be used. The control logic can be implemented as a binary counter using synchronous rather than ripple logic, and can be implemented in a variety of ways. The DAC can be implemented in a variety of ways. Voltages and other data shown in the waveforms are examples and can vary with different embodiments and conditions. Reset inputs (not shown) can be added to each flip-
flop FIG. 5 . Other kinds of bistables may be substituted for the SR latch, such as JK flip-flops, toggle flip-flops, D-type flip-flops, etc. - The background of the invention section may contain background information about the problem or environment of the invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant.
- Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machine, computer, or other device and are not intended to be performed solely by humans without such machine assistance. Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result.
- Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC Sect. 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claim elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word “means” are not intended to fall under 35 USC Sect. 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line.
- The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
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