US20120099371A1 - Method of operating a phase-change memory device - Google Patents
Method of operating a phase-change memory device Download PDFInfo
- Publication number
- US20120099371A1 US20120099371A1 US13/343,383 US201213343383A US2012099371A1 US 20120099371 A1 US20120099371 A1 US 20120099371A1 US 201213343383 A US201213343383 A US 201213343383A US 2012099371 A1 US2012099371 A1 US 2012099371A1
- Authority
- US
- United States
- Prior art keywords
- resistance
- reset
- voltage
- change layer
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
Definitions
- the first resistance is higher than the second resistance.
- a first interval I 1 between the first pulse voltage V 1 and second pulse voltage V 2 and a second interval I 2 between the second pulse voltage V 2 and third pulse voltage V 3 may, or may not, be equal to each other.
- Each of the first interval I 1 and second interval I 2 may be less than 100 ns.
- Each of the first interval I 1 and second interval I 2 may range from 5 ns to 100 ns.
- the first, second and third regions a 1 , a 2 , a 3 of FIG. 3 are formed by the first, second and third pulse voltages V 1 , V 2 , V 3 (each of which is applied for a relatively short time) the first, second and third regions a 1 , a 2 , a 3 may be heated to a temperature less than the first temperature and cool such that the first, second and third regions a 1 , a 2 , a 3 become amorphous regions.
- the reset voltage V reset of FIG. 2 and the reset voltage V′ reset of FIG. 4 have the same energy, a temperature to which the phase-change layer 30 is heated by the reset voltage V reset of FIG. 2 may be lower than a temperature to which the phase-change layer 30 is heated by the reset voltage V′ reset of FIG. 4 .
Abstract
A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.
Description
- This U.S. nonprovisional application is a continuation under 35 U.S.C. §120 of U.S. application Ser. No. 12/081,451, filed on Apr. 16, 2008, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0122737, filed on Nov. 29, 2007 in the Korean Intellectual Property Office, the disclosure of each of which is hereby incorporated herein in their entirety by reference.
- 1. Field
- Example embodiments relate to a method of operating a memory device. Other example embodiments relate to a method of operating a phase-change memory device.
- 2. Description of the Related Art
- There are several types of non-volatile memory devices including a flash memory, a ferroelectric RAM (FeRAM), a magnetic RAM (MRAM) and phase-change random access memories (PRAMs). A storage node of a PRAM is structurally different than other non-volatile memory devices.
- A storage node of a PRAM includes a phase-change layer as a data storage layer. If a predetermined reset voltage is applied to the phase-change layer for a substantially short amount of time, a region of the phase-change layer changes to an amorphous region. If a predetermined set voltage is applied to the storage node for a substantially long amount of time, the amorphous region returns to a crystalline state.
- Assuming that a first resistance pertains to the phase-change layer having an amorphous region and a second resistance pertains to the phase-change layer having no amorphous region, the first resistance is higher than the second resistance.
- The PRAM is a memory device that writes and reads bit data using a phase-change layer having resistance characteristics that vary depending on the phase of the phase-change layer.
- A conventional method of operating the PRAM may have a substantially slow operation speed because a set amount of time for the amorphous region to return to the crystalline state is relatively long.
- In the conventional method of operating the PRAM, the characteristics of the phase-change layer may easily deteriorate by repeating the reset and set operations, shortening the durability (or endurance) of the PRAM.
- Example embodiments relate to a method of operating a memory device. Other example embodiments relate to a method of operating a phase-change memory device.
- Example embodiments provide a method of operating a phase-change memory device using a phase change layer having resistance characteristics that vary depending on a phase of the phase-change layer.
- According to example embodiments, there is provided a method of operating a phase-change memory device having a phase-change layer and a unit applying a voltage to the phase-change layer, the method including applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied. The pulse voltages may be substantially the same.
- A pulse width of each of the pulse voltages may be less than 20 ns. A pulse width of each of the pulse voltages may range from 5 ns to 20 ns. An interval between the pulse voltages may be less than 100 ns. The interval between the pulse voltages may be greater than 5 ns. The interval between the pulse voltages may range from 5 ns to 100 ns. The number of the pulse voltages may range 2 to 10.
- The method may include applying a set voltage to the phase-change layer, after the applying of the reset voltage to the phase-change layer.
- The reset voltage may be applied for an equal or less amount of time than the set voltage.
- Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
FIGS. 1-7 represent non-limiting, example embodiments as described herein. -
FIG. 1 is a diagram illustrating a cross-sectional view for explaining a method of operating a phase-change random access memory (PRAM) according to example embodiments; -
FIG. 2 is a graph illustrating a reset voltage usable in a method of operating a PRAM according to example embodiments; -
FIG. 3 is a diagram illustrating a cross-sectional view of a PRAM reset using the reset voltage ofFIG. 2 ; -
FIG. 4 is a graph illustrating a reset voltage used in a conventional method of operating a PRAM according to a comparative example; -
FIG. 5 is a diagram illustrating a cross-sectional view of a PRAM reset using the reset voltage ofFIG. 4 ; -
FIG. 6 is a graph illustrating reset resistances of a first cell of a PRAM reset in a method according to example embodiments and a method according to a comparative example; and -
FIG. 7 is a graph illustrating a resistance variation of a first cell of a PRAM and a set pulse width if the first cell reset is changed to a set state in a method according to example embodiments and a method according to a comparative example. - Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.
- Detailed illustrative embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. This invention may, however, may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.
- Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.
- It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
- It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of example embodiments.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation which is above as well as below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
- Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient (e.g., of implant concentration) at its edges rather than an abrupt change from an implanted region to a non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation may take place. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.
- It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
- In order to more specifically describe example embodiments, various aspects will be described in detail with reference to the attached drawings. However, the present invention is not limited to example embodiments described.
- Example embodiments relate to a method of operating a memory device. Other example embodiments relate to a method of operating a phase-change memory device.
-
FIG. 1 is a diagram illustrating a cross-sectional view of a method of operating a phase-change random access memory (PRAM) according to example embodiments. - Referring to
FIG. 1 , the PRAM may include alower electrode 10, a lowerelectrode contact layer 20, a phase-change layer 30 and anupper electrode 40, which are stacked sequentially (or in parallel). The lowerelectrode contact layer 20 may have a width less than that of thelower electrode 10. The lowerelectrode contact layer 20 may connect thelower electrode 10 and the phase-change layer 30. An interlayer insulatinglayer 15 surrounding the lowerelectrode contact layer 20 may be formed between thelower electrode 10 and the phase-change layer 30. Although not shown inFIG. 1 , one of thelower electrode 10 and theupper electrode 40 may be connected to a switching element. The switching element may be a transistor formed on a substrate (not shown) or other elements (e.g., a diode). - The phase of a region of the phase-
change layer 30 contacting the lowerelectrode contact layer 20 may be changed according to a voltage V applied between thelower electrode 10 and theupper electrode 40. The overall phase-change layer 30 shown inFIG. 1 is in a crystalline state. -
FIG. 2 is a graph illustrating a reset voltage Vreset applied between thelower electrode 10 and theupper electrode 40 in a method of operating a PRAM according to example embodiments. - Referring to
FIG. 2 , the reset voltage Vreset may include two or more pulse voltages (e.g., first, second and third pulse voltages V1, V2, V3), which are continuously applied at predetermined intervals. - Magnitudes of the first, second and third pulse voltages V1, V2, V3 may be the same. First, second and third pulse widths T1, T2, T3, for which the first, second and third pulse voltages V1, V2, V3, respectively, are applied may be the same. As such, the first, second and third pulse voltages V1, V2, V3 may be substantially the same. Each of the first, second and third pulse widths T1, T2, T3 may be less than 20 nanoseconds (ns). Each of the first, second and third pulse widths T1, T2, T3 may range from 5 ns to 20 ns. A first interval I1 between the first pulse voltage V1 and second pulse voltage V2 and a second interval I2 between the second pulse voltage V2 and third pulse voltage V3 may, or may not, be equal to each other. Each of the first interval I1 and second interval I2 may be less than 100 ns. Each of the first interval I1 and second interval I2 may range from 5 ns to 100 ns.
- If such short pulse voltages are continuously applied at predetermined intervals, the region of the phase-
change layer 30 contacting the lowerelectrode contact layer 20 may change to an amorphous region. For example, if the reset voltage Vreset ofFIG. 2 is applied between thelower electrode 10 and theupper electrode 40 ofFIG. 1 , the PRAM ofFIG. 1 may change as shown inFIG. 3 . -
FIG. 3 is a diagram illustrating a cross-sectional view of a PRAM reset using the reset voltage ofFIG. 2 . - Referring to
FIG. 3 , the region of the phase-change layer 30 contacting the lowerelectrode contact layer 20 may change, due to the reset voltage Vreset, into an amorphous region A. The amorphous region A may include first, second and third regions a1, a2, a3. At least one of the first, second and third regions a1, a2, a3 may become amorphous regions due to the first, second and third pulse voltages V1, V2, V3, respectively, ofFIG. 2 . - A local region of the phase-
change layer 30 may melt due to the first pulse voltage V1 and cool for a time corresponding to the first interval I1 to become an amorphous region. The amorphous local region may be one of the first, second or third regions a1, a2, a3. For example, the amorphous local region may be the second region a2. If the second region a2 is an amorphous region, the second region a2 has a resistivity higher than crystalline regions around the amorphous region a2. If the second pulse voltage V2 is applied between thelower electrode 10 and theupper electrode 40, current flows through the crystalline regions around the amorphous local region (e.g., second region a2), heating a portion of the crystalline regions. One (e.g., the first region a1) of the other two regions (e.g., the first region a1 and the third region a3) may be formed from the heated regions. The remaining region (e.g., third region a3) may be formed by the third pulse voltage V3. - Although the reset voltage Vreset includes the first, second and third pulse voltages V1, V2, V3 in
FIGS. 2 and 3 , the reset voltage Vreset may include two pulse voltages. The reset voltage Vreset may include four or more (e.g., 4 to 10) pulse voltages. The number of minute amorphous regions formed inFIG. 3 may vary depending on the number of pulse voltages constituting the reset voltage Vreset. -
FIG. 4 is a graph illustrating a reset voltage V′reset applied between thelower electrode 10 and theupper electrode 40 ofFIG. 1 in a conventional method of operating a PRAM according to a comparative example. - Referring to
FIG. 4 , the reset voltage V′reset is one pulse voltage. The reset voltage V′reset has a relatively long fourth pulse width T4 for which the reset voltage V′reset is applied. For example, the fourth pulse width T4 may be similar to the sum of the first, second and third pulse widths T1, T2, T3 ofFIG. 2 . A magnitude of the reset voltage V′reset ofFIG. 4 may be the same as that of each of the first, second and third pulse voltages V1, V2, V3 ofFIG. 2 . As such, the total energy of the reset voltage V′reset ofFIG. 4 may be the same as the total energy of the reset voltage Vreset ofFIG. 2 . - If the reset voltage V′reset of
FIG. 4 is applied between thelower electrode 10 and theupper electrode 40 ofFIG. 1 , the PRAM ofFIG. 1 may change as shown inFIG. 5 . -
FIG. 5 is a diagram illustrating a cross-sectional view of a PRAM reset using the reset voltage ofFIG. 4 . - Referring to
FIG. 5 , a region of the phase-change layer 30 contacting the lowerelectrode contact layer 20 changes, due to the reset voltage V′reset, into an amorphous region A′. The amorphous region A′ may have a volume similar to that of the amorphous region A ofFIG. 3 . - A region of the phase-
change layer 30 is heated by the reset voltage V′reset ofFIG. 5 . Because the reset voltage V′reset is applied for a relatively long amount of time, a portion of the heated region of the phase-change layer 30 may be heated to a substantially high temperature (hereinafter referred to as a “first temperature”). For example, if current excessively flows through a region along a grain boundary of the phase-change layer 30 due to the reset voltage V′reset, the region through which the current excessively flows may be heated to the first temperature. - Because the first, second and third regions a1, a2, a3 of
FIG. 3 are formed by the first, second and third pulse voltages V1, V2, V3 (each of which is applied for a relatively short time) the first, second and third regions a1, a2, a3 may be heated to a temperature less than the first temperature and cool such that the first, second and third regions a1, a2, a3 become amorphous regions. Although the reset voltage Vreset ofFIG. 2 and the reset voltage V′reset ofFIG. 4 have the same energy, a temperature to which the phase-change layer 30 is heated by the reset voltage Vreset ofFIG. 2 may be lower than a temperature to which the phase-change layer 30 is heated by the reset voltage V′reset ofFIG. 4 . - Because a method of operating a PRAM according to example embodiments may prevent (or reduce) the phase-change layer from being excessively heated during a reset operation, the durability of the PRAM may increase. If a region of a phase-change layer becomes an amorphous region by excessively heating and cooling, it may be difficult to return the amorphous region to a crystalline region, increasing the set time. In a method of operating a PRAM according to example embodiments, the PRAM has a shorter set time because the phase-change layer is not excessively heated during a reset operation.
- In a method of operating a PRAM according to example embodiments, because a resistance of the phase-change layer is not measured between the pulse voltages applied during the reset operation, time necessary for measuring the resistance decreases.
-
FIG. 6 is a graph illustrating reset resistances of a first cell of a PRAM reset by a method according to example embodiments and by a method according to the comparative example. InFIG. 6 , data marked by ▴ are resistances of the first cell reset by a first reset voltage in the method according to example embodiments, and data marked by * are resistances of the first cell reset by a second reset voltage in the method ofFIG. 4 according to the comparative example. The first reset voltage includes first, second, third, fourth and fifth pulse voltages, which are respectively applied for approximately 10 ns. The second reset voltage includes one pulse voltage having a pulse width of approximately 50 ns. Magnitudes of the first, second, third, fourth and fifth pulse voltages of the first reset voltage and the second reset voltage may be approximately 3.7 V. - Referring to
FIG. 6 , the data marked by * and the data marked ▴ are almost the same. Reset resistances if the first, second, third, fourth and fifth pulse voltages having a pulse width of 10 ns are applied at intervals of 10 ns and if the pulse voltage is applied once for 50 ns, the reset resistances are similar to each other. -
FIG. 7 is a graph illustrating a resistance variation of a first cell of a PRAM and a set pulse width if the first cell reset is changed to a set state by a method according to example embodiments and by a method according to a comparative example. InFIG. 7 , a first graph G1 shows a resistance variation of the first cell if the first cell reset is changed to a set state by the first reset voltage according to example embodiments, and a second graph G2 shows a resistance variation of the first cell if the first cell reset is changed to a set state by the second reset voltage according to the comparative example. A set voltage having a magnitude of approximately 1.8 V is used. - Referring to
FIG. 7 , the first graph G1 is located below the second graph G2 because if set voltages are applied for the same time, a resistance value of the first graph G1 is lower than a resistance value of the second graph G2. As such, a time to set the PRAM reset by the method according to example embodiments is shorter than a time taken to set the PRAM reset by the method according to the comparative example. ΔRs denotes a reference resistance range usable to measure a set resistance. A difference in set pulse width between the first graph G1 and the second graph G2 is approximately 40 ns on a first reference resistance line Rs1 within the reference resistance range. A set time in the method according to example embodiments is approximately 30% shorter than a set time in the method according to the comparative example. - A set time of a PRAM according to example embodiments is more than 100 ns, which is longer than a reset time. A programming time is determined by the set time that is longer than the reset time. Even though a reset time T1+I1+T2+I2+T3 of
FIG. 2 is slightly longer than a conventional reset time, a programming time in the method according to example embodiments may be shorter. If a total applying time of the reset voltage Vreset ofFIG. 2 is shorter than or equal to a set time, because a programming time is determined by the set time, a programming time in the method according to example embodiments is shorter than a programming time in a conventional method of operating a PRAM. A total reset pulse width used in the method according to example embodiments may be equal to or less than a set pulse width. A set pulse width for which a set pulse is applied to the phase-change layer 30 to change the amorphous region A ofFIG. 3 into a crystalline region may be equal to or larger than a total reset pulse width. - The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
Claims (16)
1. A method of programming a memory device having a resistance-change layer, a first electrode contact layer, and a unit applying a voltage to the resistance-change layer, the programming method comprising:
applying a reset voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a resistance-change is initiated at a surface of the resistance-change layer contacting the first electrode contact layer,
wherein the reset voltage includes at least two pulse voltages.
2. The method of claim 1 , wherein the at least two pulse voltages are sequentially applied.
3. The method of claim 1 , wherein the at least two pulse voltages are continuously applied.
4. The method of claim 1 , wherein the at least two pulse voltages are applied with a time interval therebetween.
5. The method of claim 1 , wherein the at least two pulse voltages are applied with identical magnitude.
6. The method of claim 1 , wherein a pulse width of the at least two pulse voltages are equal.
7. The method of claim 1 , further comprising:
applying a set voltage to the resistance-change layer,
wherein the set voltage includes one pulse voltage.
8. A method of programming a memory device having a resistance-change layer, a first electrode contact layer, and a unit applying a voltage to the resistance-change layer, the programming method comprising:
applying a reset voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a resistance-change is initiated at a surface of the resistance-change layer contacting the first electrode contact layer, wherein the reset voltage includes at least two pulse voltages; and
applying a set voltage to the resistance-change layer.
9. The method of claim 8 , wherein the reset voltage is applied for an equal or shorter amount of time than the set voltage.
10. The method of claim 8 , wherein the set voltage includes one pulse voltage.
11. The method of claim 8 , wherein the applying a reset voltage to the resistance-change layer includes,
applying a first pulse voltage to the resistance-change layer via the first electrode contact layer in a programming step for data writing such that a first resistance-change is initiated at a first surface of the resistance-change layer contacting the first electrode contact layer; and
applying a second pulse voltage to the resistance-change layer via the first electrode contact layer in the programming step for data writing such that a second resistance-change is initiated at a second surface of the resistance-change layer contacting the first electrode contact layer, wherein the second surface is disposed adjacent to the first surface.
12. The method of claim 8 , wherein the at least two pulse voltages are sequentially applied in a same programming step.
13. The method of claim 8 , wherein the at least two pulse voltages are continuously applied in a same programming step.
14. The method of claim 8 , wherein the at least two pulse voltages are applied with a time interval therebetween in a same programming step.
15. The method of claim 8 , wherein the at least two pulse voltages are applied with identical magnitude.
16. The method of claim 8 , wherein a pulse width of the at least two pulse voltages are equal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/343,383 US20120099371A1 (en) | 2007-11-29 | 2012-01-04 | Method of operating a phase-change memory device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070122737A KR101291222B1 (en) | 2007-11-29 | 2007-11-29 | Method of operating phase change memory device |
KR10-2007-0122737 | 2007-11-29 | ||
US12/081,451 US8116125B2 (en) | 2007-11-29 | 2008-04-16 | Method of operating a phase-change memory device |
US13/343,383 US20120099371A1 (en) | 2007-11-29 | 2012-01-04 | Method of operating a phase-change memory device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/081,451 Continuation US8116125B2 (en) | 2007-11-29 | 2008-04-16 | Method of operating a phase-change memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20120099371A1 true US20120099371A1 (en) | 2012-04-26 |
Family
ID=40675539
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/081,451 Active 2028-12-10 US8116125B2 (en) | 2007-11-29 | 2008-04-16 | Method of operating a phase-change memory device |
US13/343,383 Abandoned US20120099371A1 (en) | 2007-11-29 | 2012-01-04 | Method of operating a phase-change memory device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/081,451 Active 2028-12-10 US8116125B2 (en) | 2007-11-29 | 2008-04-16 | Method of operating a phase-change memory device |
Country Status (4)
Country | Link |
---|---|
US (2) | US8116125B2 (en) |
JP (1) | JP2009135409A (en) |
KR (1) | KR101291222B1 (en) |
CN (1) | CN101447226B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9111640B2 (en) | 2011-10-18 | 2015-08-18 | Panasonic Intellectual Property Management Co., Ltd. | Nonvolatile memory element, nonvolatile memory device, and writing method for use in nonvolatile memory element |
CN107768517A (en) * | 2016-08-23 | 2018-03-06 | 三星电子株式会社 | Phase change memory device including two-dimensional material, the method and phase change layer for operating it |
US10083749B2 (en) | 2014-07-24 | 2018-09-25 | Huawei Technologies Co., Ltd | Data storage method and phase change memory |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101291222B1 (en) * | 2007-11-29 | 2013-07-31 | 삼성전자주식회사 | Method of operating phase change memory device |
CN101699562B (en) * | 2009-11-23 | 2012-10-10 | 中国科学院上海微系统与信息技术研究所 | Erasing method of phase change memory |
US9251897B2 (en) * | 2009-12-31 | 2016-02-02 | Micron Technology, Inc. | Methods for a phase-change memory array |
US8624217B2 (en) * | 2010-06-25 | 2014-01-07 | International Business Machines Corporation | Planar phase-change memory cell with parallel electrical paths |
US8575008B2 (en) | 2010-08-31 | 2013-11-05 | International Business Machines Corporation | Post-fabrication self-aligned initialization of integrated devices |
JP2012064254A (en) | 2010-09-14 | 2012-03-29 | Toshiba Corp | Nonvolatile semiconductor storage device |
JP5662237B2 (en) * | 2011-05-10 | 2015-01-28 | 株式会社日立製作所 | Semiconductor memory device |
JP5553797B2 (en) * | 2011-05-27 | 2014-07-16 | 株式会社日立製作所 | Data recording method for semiconductor memory device |
CN103714852B (en) * | 2013-12-18 | 2017-03-01 | 华中科技大学 | A kind of precise control micro-nano scale phase change material amorphous rate continually varying method |
CN105453182A (en) * | 2014-07-24 | 2016-03-30 | 华为技术有限公司 | Data storage method and control device for phase-change memory |
JP2016170848A (en) * | 2015-03-16 | 2016-09-23 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
KR20220050303A (en) | 2020-10-15 | 2022-04-25 | 삼성전자주식회사 | Memory device including phase change memory and operation method thereof |
US20230263078A1 (en) * | 2022-02-16 | 2023-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device, method for configuring memory cell in n-bit memory unit, and memory array |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6813177B2 (en) * | 2002-12-13 | 2004-11-02 | Ovoynx, Inc. | Method and system to store information |
US20050068804A1 (en) * | 2003-09-25 | 2005-03-31 | Samsung Electronics Co., Ltd. | Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range |
US20050169093A1 (en) * | 2004-02-04 | 2005-08-04 | Byung-Gil Choi | Phase-change memory device and method of writing a phase-change memory device |
US20050281073A1 (en) * | 2004-06-19 | 2005-12-22 | Woo-Yeong Cho | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement |
US20060007729A1 (en) * | 2004-07-09 | 2006-01-12 | Beak-Hyung Cho | Phase change memories and/or methods of programming phase change memories using sequential reset control |
US20060220071A1 (en) * | 2005-04-04 | 2006-10-05 | Kang Sang-Beom | Phase-change semiconductor memory device and method of programming the same |
US20060221679A1 (en) * | 2005-04-04 | 2006-10-05 | Kang Sang-Beom | Method of programming memory cell array |
US20070008769A1 (en) * | 2005-07-06 | 2007-01-11 | Samsung Electronics Co., Ltd. | Phase-changeable memory device and method of programming the same |
US20080055969A1 (en) * | 2006-08-30 | 2008-03-06 | Micron Technology, Inc. | Phase change memory |
US8116125B2 (en) * | 2007-11-29 | 2012-02-14 | Samsung Electronics Co., Ltd. | Method of operating a phase-change memory device |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3846767A (en) * | 1973-10-24 | 1974-11-05 | Energy Conversion Devices Inc | Method and means for resetting filament-forming memory semiconductor device |
US3922648A (en) * | 1974-08-19 | 1975-11-25 | Energy Conversion Devices Inc | Method and means for preventing degradation of threshold voltage of filament-forming memory semiconductor device |
US6844582B2 (en) * | 2002-05-10 | 2005-01-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and learning method thereof |
KR100498493B1 (en) * | 2003-04-04 | 2005-07-01 | 삼성전자주식회사 | Low current and high speed phase-change memory and operation method therefor |
WO2005031752A1 (en) * | 2003-09-26 | 2005-04-07 | Kanazawa University Technology Licensing Organization Ltd. | Multinary memory and method for recording to phase-change type recording medium for it |
DE102005004338B4 (en) * | 2004-02-04 | 2009-04-09 | Samsung Electronics Co., Ltd., Suwon | Phase change memory device and associated programming method |
KR100618824B1 (en) * | 2004-05-08 | 2006-08-31 | 삼성전자주식회사 | Driver circuit capable of controlling the width of writing pulse of Phase Change memory device and method thereof |
US7327602B2 (en) * | 2004-10-07 | 2008-02-05 | Ovonyx, Inc. | Methods of accelerated life testing of programmable resistance memory elements |
JP2006127583A (en) * | 2004-10-26 | 2006-05-18 | Elpida Memory Inc | Nonvolatile semiconductor memory device and phase changing memory |
KR100576369B1 (en) * | 2004-11-23 | 2006-05-03 | 삼성전자주식회사 | Method for programming a non-volatile memory device employing a transition metal oxide layer as a data storage material layer |
US7031181B1 (en) * | 2004-11-23 | 2006-04-18 | Infineon Technologies Ag | Multi-pulse reset write scheme for phase-change memories |
TW200633193A (en) * | 2004-12-02 | 2006-09-16 | Koninkl Philips Electronics Nv | Non-volatile memory |
JP4955218B2 (en) * | 2005-04-13 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US7525117B2 (en) * | 2005-08-09 | 2009-04-28 | Ovonyx, Inc. | Chalcogenide devices and materials having reduced germanium or telluruim content |
KR101501980B1 (en) * | 2005-12-12 | 2015-03-18 | 오보닉스, 아이엔씨. | Chalcogenide devices and materials having reduced germanium or telluruim content |
KR101213702B1 (en) * | 2006-04-21 | 2012-12-18 | 삼성전자주식회사 | Non-volatile memory device having a pair of fins between which a void is defined |
KR100763231B1 (en) | 2006-09-11 | 2007-10-04 | 삼성전자주식회사 | Phase change random access memory device |
US7679980B2 (en) * | 2006-11-21 | 2010-03-16 | Qimonda North America Corp. | Resistive memory including selective refresh operation |
US7898847B2 (en) * | 2007-03-08 | 2011-03-01 | Qimonda Ag | Method to prevent overreset |
US7577023B2 (en) * | 2007-05-04 | 2009-08-18 | Qimonda North America Corp. | Memory including write circuit for providing multiple reset pulses |
US7646625B2 (en) * | 2007-06-29 | 2010-01-12 | Qimonda Ag | Conditioning operations for memory cells |
-
2007
- 2007-11-29 KR KR1020070122737A patent/KR101291222B1/en active IP Right Grant
-
2008
- 2008-04-16 US US12/081,451 patent/US8116125B2/en active Active
- 2008-06-18 CN CN2008101102149A patent/CN101447226B/en active Active
- 2008-06-26 JP JP2008167497A patent/JP2009135409A/en active Pending
-
2012
- 2012-01-04 US US13/343,383 patent/US20120099371A1/en not_active Abandoned
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6813177B2 (en) * | 2002-12-13 | 2004-11-02 | Ovoynx, Inc. | Method and system to store information |
US20050068804A1 (en) * | 2003-09-25 | 2005-03-31 | Samsung Electronics Co., Ltd. | Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range |
US20050169093A1 (en) * | 2004-02-04 | 2005-08-04 | Byung-Gil Choi | Phase-change memory device and method of writing a phase-change memory device |
US20050281073A1 (en) * | 2004-06-19 | 2005-12-22 | Woo-Yeong Cho | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement |
US20060007729A1 (en) * | 2004-07-09 | 2006-01-12 | Beak-Hyung Cho | Phase change memories and/or methods of programming phase change memories using sequential reset control |
US20060220071A1 (en) * | 2005-04-04 | 2006-10-05 | Kang Sang-Beom | Phase-change semiconductor memory device and method of programming the same |
US20060221679A1 (en) * | 2005-04-04 | 2006-10-05 | Kang Sang-Beom | Method of programming memory cell array |
US20070008769A1 (en) * | 2005-07-06 | 2007-01-11 | Samsung Electronics Co., Ltd. | Phase-changeable memory device and method of programming the same |
US20080055969A1 (en) * | 2006-08-30 | 2008-03-06 | Micron Technology, Inc. | Phase change memory |
US8116125B2 (en) * | 2007-11-29 | 2012-02-14 | Samsung Electronics Co., Ltd. | Method of operating a phase-change memory device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9111640B2 (en) | 2011-10-18 | 2015-08-18 | Panasonic Intellectual Property Management Co., Ltd. | Nonvolatile memory element, nonvolatile memory device, and writing method for use in nonvolatile memory element |
US10083749B2 (en) | 2014-07-24 | 2018-09-25 | Huawei Technologies Co., Ltd | Data storage method and phase change memory |
CN107768517A (en) * | 2016-08-23 | 2018-03-06 | 三星电子株式会社 | Phase change memory device including two-dimensional material, the method and phase change layer for operating it |
US10217513B2 (en) * | 2016-08-23 | 2019-02-26 | Samsung Electronics Co., Ltd. | Phase change memory devices including two-dimensional material and methods of operating the same |
Also Published As
Publication number | Publication date |
---|---|
JP2009135409A (en) | 2009-06-18 |
KR20090055878A (en) | 2009-06-03 |
US8116125B2 (en) | 2012-02-14 |
US20090141546A1 (en) | 2009-06-04 |
CN101447226A (en) | 2009-06-03 |
CN101447226B (en) | 2013-05-01 |
KR101291222B1 (en) | 2013-07-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8116125B2 (en) | Method of operating a phase-change memory device | |
US7558100B2 (en) | Phase change memory devices including memory cells having different phase change materials and related methods and systems | |
US9019777B2 (en) | Nonvolatile semiconductor memory device and operating method of the same | |
US8203873B2 (en) | Rectifying element for a crosspoint based memory array architecture | |
KR100504700B1 (en) | Phase random access memory with high dencity | |
JP4869600B2 (en) | Memory and access device | |
USRE45817E1 (en) | Nonvolatile semiconductor memory device comprising memory cell array having multilayer structure | |
US9136468B2 (en) | Nonvolatile semiconductor memory device | |
US7733691B2 (en) | Memory device including thermal conductor located between programmable volumes | |
US7400027B2 (en) | Nonvolatile memory device having two or more resistance elements and methods of forming and using the same | |
US20060038221A1 (en) | Antiferromagnetic/paramagnetic resistive device, non-volatile memory and method for fabricating the same | |
US9570169B1 (en) | Resistive memory device | |
US8320170B2 (en) | Multi-bit phase change memory devices | |
US8493769B2 (en) | Memory devices including decoders having different transistor channel dimensions and related devices | |
EP1982335A1 (en) | Memory having nanotube transistor access device | |
US7977661B2 (en) | Memory having shared storage material | |
US20080303015A1 (en) | Memory having shared storage material | |
US8791448B2 (en) | Semiconductor memory devices having strapping contacts | |
US20090097306A1 (en) | Phase-change random access memory device, system having the same, and associated methods | |
US7636251B2 (en) | Methods of operating a non-volatile memory device | |
Ande et al. | A new approach to the design, fabrication, and testing of chalcogenide-based multi-state phase-change nonvolatile memory | |
US20220005869A1 (en) | Semiconductor memory device | |
US20130088910A1 (en) | Non-volatile semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |