US20120083119A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- US20120083119A1 US20120083119A1 US13/323,560 US201113323560A US2012083119A1 US 20120083119 A1 US20120083119 A1 US 20120083119A1 US 201113323560 A US201113323560 A US 201113323560A US 2012083119 A1 US2012083119 A1 US 2012083119A1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device having a through-electrode, and a method of manufacturing the same.
- one end of through-electrode on the top surface side of the substrate is positioned on the surface of the substrate or on the surface of a device isolation film.
- a viaplug connection plug
- the diameter of the viaplug formed in the lowermost insulating interlayer has extremely been shrunk, in an ongoing tendency of shrinkage of semiconductor devices. For this reason, contact failure between the through-electrode and the electro-conductive pattern has been becoming more likely to occur, when the through-electrode and the viaplug are misaligned with each other.
- a semiconductor device which includes:
- connection terminal provided over the other surface of the substrate
- a through-electrode extended through the substrate and the first insulating interlayer, so as to connect the electro-conductive pattern and the connection terminal.
- the through-electrode is provided through the substrate and the first insulating interlayer, and is directly connected to the electro-conductive pattern on the first insulating interlayer, so that it is no more necessary to provide any connection plug used for connecting the through-electrode with the electro-conductive pattern. Allowance for the misalignment may therefore increase, as compared with the case where the through-electrode and the electro-conductive pattern are connected via the connection plug. As a consequence, connection failure between the through-electrode and the electro-conductive pattern may be suppressed.
- a method of manufacturing a semiconductor device which includes:
- connection terminal connected to the other end of said through-electrode, on the other surface of said substrate.
- the through-electrode may directly be connected to elements (transistors which are disposed below the insulating interlayer) in some cases, and may indirectly be connected via any other interconnect or connection plug in some cases. In both cases, the through-electrode is electrically connected with the element.
- any connection failure between the through-electrode and the electro-conductive pattern may be suppressed.
- FIG. 1 is a sectional view illustrating a configuration of a semiconductor device according to an embodiment
- FIGS. 2A to 7B are sectional views sequentially illustrating the individual steps of manufacturing the semiconductor device illustrated in FIG. 1 .
- FIG. 1 is a sectional view illustrating a configuration of a semiconductor device of this embodiment.
- the semiconductor device has a substrate 100 , an insulating interlayer 260 , an interconnect 342 as one example of the electro-conductive pattern, a through-electrode 440 , and a bump 900 as one example of the connection terminal.
- the insulating interlayer 260 is positioned on one surface (top surface) of the substrate 100 .
- the interconnect 342 is formed over the insulating interlayer 260 .
- the bump 900 is provided on the opposite surface (back surface) of the substrate 100 .
- the through-electrode 440 extends through the substrate 100 and the insulating interlayer 260 , so as to connect the interconnect 342 with the bump 900 .
- one end of the through-electrode 440 is directly connected to the interconnect 342 . Accordingly, the connection failure between the through-electrode 440 and the interconnect 342 may be suppressed, even if the relative position between the through-electrode 440 and the interconnect 342 should be misaligned in the direction of extension of the interconnect 342 .
- the connection failure between the through-electrode 440 and the electro-conductive pattern may be suppressed also when the electro-conductive pattern is provided in place of the interconnect 342 , because the area of the electro-conductive pattern may be set larger than the area of the via or contact. The effect will be detailed below.
- the interconnect 342 or the electro-conductive pattern may be composed of, for example, an Al pattern formed on the insulating interlayer 260 , or may be a Cu pattern buried in the surficial portion of the insulating interlayer 260 by the damascene process.
- any interconnects positioned on the surface of the insulating interlayers may be Al patterns formed on the insulating interlayer, or may be Cu patterns buried into the insulating interlayers by the damascene process.
- the insulating interlayer 260 is a third insulating interlayer. Between the substrate 100 and the insulating interlayer 260 , a first insulating interlayer 200 , and second insulating interlayers 220 , 240 are disposed. The through-electrode 440 is directly connected to the interconnect 342 , after being extended through the substrate 100 and the insulating interlayers 200 , 220 , 240 , 260 .
- the transistors 120 , 140 and capacitor elements 160 there are disposed elements such as transistors 120 , 140 and capacitor elements 160 .
- the transistors 120 and the capacitor elements 160 compose a DRAM.
- the capacitor elements 160 are disposed over the second insulating interlayers 220 , 240 .
- the capacitor elements 160 are typically those having cylinder-type electrodes.
- the surface of the lower electrode may be treated to have HSG (hemispherical grains).
- the transistors 140 compose a logic circuit or a peripheral circuit of the DRAM.
- connection plugs 540 , 542 which extend through the insulating interlayer 260 .
- the connection plugs 540 , 542 are extended through the insulating interlayers 200 , 220 , 240 , 260 , and are directly connected to the transistors 140 .
- the diameter of the through-electrode 440 is larger than that of the connection plugs 540 , 542 .
- the diameter of the through-electrode 440 is preferably five times or more as large as the connection plugs 540 , 542 .
- the diameter of the through-electrode 440 is typically 5 ⁇ m or larger and 20 ⁇ m or smaller.
- the other end of the through-electrode 440 is projected out from the back surface of the substrate 100 .
- the portion of the other end of the through-electrode 440 , projected out from the back surface of the substrate 100 has an insulating film 800 formed on the side face thereof.
- the insulating film 800 is formed also around the circumference of the through-electrode 440 on the back surface of the substrate 100 .
- the through-electrode 440 may be shrunk in the diameter in a portion more closer to the back surface of the substrate 100 .
- FIG. 2A The individual drawings from FIG. 2A to FIG. 7B are sectional views explaining a method of manufacturing the semiconductor device illustrated in FIG. 1 .
- a first-conductivity-type (N-type, for example) deep well 102 a first-conductivity-type well 104 , a second-conductivity-type (P-type, for example) well 106 , a device isolation film, and the transistors 120 , 140 are formed in, or over the substrate 100 .
- the insulating interlayer 200 , an interconnect 300 positioned on the insulating interlayer 200 , the insulating interlayers 220 , 240 , the capacitor elements 160 , and an alignment mark 322 are formed.
- the alignment mark 322 is positioned on the surface of the insulating interlayer 240 , and formed typically in the same process with an interconnect (not illustrated) positioned on the surface of the insulating interlayer 240 and an upper electrode 164 of the capacitor elements 160 .
- the insulating interlayer 260 is formed over the insulating interlayer 240 , the capacitor elements 160 , and the alignment mark 322 .
- a resist pattern 50 is formed over the insulating interlayer 260 .
- the resist pattern 50 has an opening pattern over the region where the through-electrode 440 will be provided therein later.
- alignment is carried out on the basis of the alignment mark 322 .
- the insulating interlayers 260 , 240 , 220 , 200 , the device isolation film, and the substrate 100 are etched, using the resist pattern 50 as a mask.
- a first hole 400 is thus formed in the insulating interlayer 260 , 240 , 220 , 200 , the device isolation film, and the substrate 100 .
- the distance from the surface of the substrate to the bottom of the first hole 400 is typically 20 ⁇ m or larger and 100 ⁇ m or smaller.
- the first hole 400 is a hole to be filled with the through-electrode 440 , and extends from the surface of the insulating interlayer 260 to a midway of the substrate 100 .
- the region where the first hole 400 is formed may have no device isolation film formed therein.
- an inner wall insulating film 420 is formed.
- the inner wall insulating film 420 is formed also over the insulating interlayer 260 (not illustrated).
- the inner wall insulating film 420 is typically a silicon oxide film, or a stacked film of a silicon oxide film and a silicon nitride film, and is formed by CVD.
- the thickness of the inner wall insulating film 420 is typically 0.1 ⁇ m or larger and 1 ⁇ m or smaller.
- the barrier film is a film for preventing diffusion of metal, and is typically a single-layered film selected from the group consisting of Mo film, TiN film, TaN film, TiW film, Ti film, Ta film, and Cr film, or a stacked film obtained by stacking a plurality of films selected from the group.
- the through-electrode 440 is filled into the first hole 400 .
- the through-electrode 440 may be formed typically by repeating a step of forming an electro-conductive film and a step of planarizing it a plurality of times.
- the step of forming the electro-conductive film is typically a step of forming a tungsten film by CVD, wherein typically 1 ⁇ m or thinner film may be formed by a single cycle of film formation.
- the step of planarization is typically a step of carrying out an etchback process and CMP (Chemical Mechanical Polishing) in this order.
- a step of forming a film similar to the above-described barrier film may be provided between the CMP process and the step of forming the electro-conductive film in the next cycle.
- the inner wall insulating film 420 may be remained on the insulating interlayer 260 .
- a resist pattern 52 is formed over the insulating interlayer 260 and the through-electrode 440 .
- the resist pattern 52 has opening patterns over the regions where the connection plugs 540 , 542 are provided therein later. When the opening patterns of the resist pattern 52 are formed, alignment is carried on the basis of the alignment mark 322 .
- Second holes 500 , 502 are thus formed in the insulating interlayers 260 , 240 , 220 , 200 .
- the second holes 500 , 502 are holes to be filled with the connection plugs 540 , 542 , wherein the former is positioned on the source or drain region, and the latter is positioned on the gate electrode of the transistors 140 .
- connection plugs 540 , 542 may be formed typically by carrying out a step of forming an electro-conductive film and the CMP (Chemical Mechanical Polishing) process in this order.
- interconnects 342 , 344 , 346 are formed on the surface of the insulating interlayer 260 .
- the interconnect 342 is positioned on the through-electrode 440 , and the interconnect 344 connects the connection plugs 540 , 542 with each other.
- alignment is carried out on the basis of the alignment mark 322 .
- an insulating interlayer 270 is formed over the insulating interlayer 260 and over the interconnects 342 , 344 , 346 , and connection plugs 350 and interconnects 360 are formed.
- the interconnects 360 are positioned on the surface of the insulating interlayer 270 , and the connection plugs 350 which connect the interconnects 360 and the interconnects 342 , 344 , while being filled in the insulating interlayer 270 .
- protective films 280 , 290 are formed in this order over the insulating interlayer 270 and the interconnects 360 , and a resin layer 600 and bumps (not illustrated) are further formed over the protective film 290 .
- the bumps are electrically connected to any interconnects 360 .
- a pressure-sensitive adhesive layer 720 is formed on the top surface of the resin layer 600 , and the resin layer 600 is bonded to the support 700 while placing the pressure-sensitive adhesive layer 720 in between.
- the pressure-sensitive adhesive layer 720 is typically an adhesive tape.
- the adhesive tape is composed of a base, and pressure-sensitive adhesive layers formed on both surfaces thereof.
- the base composing the adhesive tape may typically be composed of polyolefin-base resin, polyester-base resin or the like.
- the pressure-sensitive adhesive composing the adhesive tape may typically be composed of acryl-base, emulsion-type, pressure-sensitive adhesive; acryl-base, solution-type, pressure-sensitive adhesive; urethane-base, pressure-sensitive adhesive, or the like.
- a material for composing the support 700 those durable against heat, chemicals, external force and so forth, possibly applied typically in the process of thinning of the substrate 100 by means of grinding and etching of the back surface described later, may be adoptable. Quartz and glasses such as Pyrex (registered trademark) may be adoptable. Also materials other than glass, such as acrylic resin or other plastics, may be adoptable.
- the back surface of the substrate 100 is ground.
- grinding is carried out so as not to expose the inner wall insulating film 420 and through-electrode 440 out onto the back surface of the substrate 100 .
- the thickness of the portion between the back surface of the substrate 100 after being ground to the inner wall insulating film 420 may be 0.1 ⁇ m or larger and 1 ⁇ m or smaller, for example.
- the back surface of the substrate 100 is etched.
- the inner wall insulating film 420 and the through-electrode 440 are projected out from the back surface of the substrate 100 , to as high as approximately 1 ⁇ m or higher and 5 ⁇ m or lower, for example.
- the insulating film 800 is formed over the back surface of the substrate 100 and the inner wall insulating film 420 .
- the insulating film 800 is typically a SiN film, and is formed typically by CVD.
- portions of the inner wall insulating film 420 and the insulating film 800 positioned on the end face of the through-electrode 440 are removed typically by CMP, to thereby expose the end face of the through-electrode 440 .
- the bump 900 is formed on the back surface side of the substrate 100 . Thereafter, the pressure-sensitive adhesive layer 720 and the support 700 are removed.
- one end of the through-electrode 440 is directly connected to the interconnect 342 , so that the connection failure between the through-electrode 440 and the interconnect 342 may be suppressed.
- the interconnect 342 is positioned above the capacitor elements 160 .
- the width of interconnect positioned in the upper layer of the capacitor element may generally be larger than that of the interconnect positioned in the lower layer of the capacitor elements. Accordingly, allowance for misalignment in the relative position between the through-electrode 440 and the interconnect 342 may be increased, so that the connection failure between the through-electrode 440 and the interconnect 312 may further reliably be suppressed.
- the insulating interlayer 260 is provided as an insulating interlayer in the third layer, while placing the insulating interlayer 200 in the first layer and the insulating interlayers 220 , 240 in the second layer, between the substrate 100 and the insulating interlayer 260 .
- the through-electrode 440 is directly connected to the interconnect 342 , while being formed so as to extend through the substrate 100 and the insulating interlayers 200 , 220 , 240 , 260 .
- the contact resistance between the through-electrode 440 and the interconnect 342 may be reduced, and pattern layout of the interconnects in the process of designing the semiconductor device may be simplified, as compared with the case where the through-electrode 440 is connected to the interconnect 342 through electro-conductive components respectively buried in the insulating interlayers 200 , 220 , 240 , 260 .
- This effect may be obtained from both cases where the electro-conductive component forms a part of interconnects respectively buried in the insulating interlayers 200 , 220 , 240 , 260 , and where the electro-conductive component forms an electro-conductive plug.
- This effect may be obtained also from the case where the insulating interlayer 260 forms an insulating interlayer in the second layer, unlike the exemplary case illustrated in this drawing.
- the through-electrode 440 and the interconnect 342 may necessarily be connected via connection plugs, unless otherwise the through-electrode 440 is formed so as to extend through the insulating interlayers 200 , 220 , 240 , 260 .
- the connection resistance will inevitably increase irrespective of at which hierarchy of layer the insulating interlayer 260 is positioned, as compared with the example illustrated in this drawing.
- the direct connection between the through-electrode 440 and the interconnect 342 as shown in this embodiment may successfully reduce the contact resistance between the through-electrode 440 and the interconnect 342 .
- This effect may be obtained also for the case where the insulating interlayer 260 composes an insulating interlayer in the first layer, unlike the exemplary case illustrated in the drawings.
- the diameter of the through-electrode 440 is larger than the diameter of the connection plugs 540 , 542 . Accordingly, the resistance between the bump 900 and the interconnect 342 may still further be reduced, as compared with the case where the interconnect layers are connected via the connection plugs.
- the diameter of the through-electrode 440 is larger than the diameter of the connection plugs 540 , 542 , so that the thickness of an electro-conductive film composing the through-electrode 440 is larger than that of the an electro-conductive film composing the connection plugs 540 , 542 .
- the etch-back process and the CMP process for forming the through-electrode 440 will consequently take a longer time than the etch-back process and the CMP process for forming the connection plugs 540 , 542 .
- formation of the connection plugs 540 , 542 prior to formation of the through-electrode 440 may damage the surfaces of the connection plugs 540 , 542 .
- the surfaces of the connection plugs 540 , 542 may be prevented from being damaged in this embodiment, because the connection plugs 540 , 542 are formed after the through-electrode 440 is formed.
- the other end of the through-electrode 440 is projected out from the back surface of the substrate 100 .
- the bump 900 is therefore kept away from the back surface of the substrate 100 .
- this configuration ensures a space between these semiconductor devices.
- the configuration also suppresses short-circuiting between the bump 900 and the substrate 100 .
- the insulating film 800 Around the through-electrode 440 on the back surface of the substrate 100 , there is formed the insulating film 800 . This configuration further reliably suppresses the short-circuiting between the bump 900 and the substrate 100 .
- the interconnect 342 is formed after the through-electrode 440 is formed, the interconnect 342 may be prevented from being damaged, unlike the case where the first hole 400 is formed and filled with the through-electrode 440 from the back surface side of the substrate 100 .
- Alignment of the first hole 400 to be filled with the through-electrode 440 , and alignment of the interconnect 342 are respectively carried out on the basis of the alignment mark 322 . Both alignment processes are carried out by detecting the alignment mark 322 through the insulating interlayer 260 . On the other hand, any attempts of forming the hole to be filled with the through-electrode from the back surface side of the substrate 100 , the alignment of the hole may necessarily be carried out by detecting the alignment mark 322 from the back surface side of the substrate 100 , or on the basis of any other alignment mark. These attempts may result in degraded accuracy in alignment, as compared with this embodiment.
- the through-electrode 440 and the interconnect 342 may therefore be suppressed from being misaligned, as compared with the case where the through-electrode is filled from the back surface side of the substrate 100 .
- the back surface of the substrate 100 is initially ground only to a degree the through-electrode 440 is not exposed, and the through-electrode 440 is then exposed by etching.
- the end portion of the through-electrode 440 may be prevented from being elongated, and the through-electrode 440 is prevented from re-adhesion of debris of grinding, as compared with the case where the through-electrode 440 is exposed only by grinding of the back surface of the substrate 100 .
- the through-electrode 440 may be formed after the connection plugs 540 , 542 are formed.
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Abstract
A method of manufacturing a semiconductor device includes forming a first insulating interlayer positioned above one surface of a substrate, forming a first hole extended from the surface of the first insulating interlayer to midway of the substrate, forming a through-electrode in the first hole, forming an electro-conductive pattern positioned on the surface of the first insulating interlayer, and connected to one end of the through-electrode, making the other end of the through-electrode expose, by removing the other surface of the substrate, and forming a connection terminal connected to the other end of the through-electrode, on the other surface of the substrate.
Description
- The present application is a Divisional Application of U.S. patent application Ser. No. 12/385,840 filed on Apr. 21, 2009, which is based is based on Japanese patent application No. 2008-125042 the content of which is incorporated hereinto by reference.
- 1. Technical Field
- The present invention relates to a semiconductor device having a through-electrode, and a method of manufacturing the same.
- 2. Related Art
- In recent years, there has been developed a technique of three-dimensionally integrating semiconductor devices, by bonding semiconductor devices having semiconductor elements formed therein. By this technique, a through-electrode is provided to a semiconductor substrate of the semiconductor device. The semiconductor element formed on the surface of the semiconductor substrate is connected to other semiconductor device, through the interconnect formed over the insulating interlayer and through-electrode (see Japanese Laid-Open Patent Publication Nos. 2001-339057 and 2006-41450, for example).
- In the semiconductor devices described in these patent documents, one end of through-electrode on the top surface side of the substrate is positioned on the surface of the substrate or on the surface of a device isolation film. For the purpose of connecting any electro-conductive pattern positioned on an insulating interlayer with the through-electrode, it may therefore be necessary to form a viaplug (connection plug), allowing therethrough connection of the electro-conductive pattern and the through-electrode, in the insulating interlayer. However, the diameter of the viaplug formed in the lowermost insulating interlayer has extremely been shrunk, in an ongoing tendency of shrinkage of semiconductor devices. For this reason, contact failure between the through-electrode and the electro-conductive pattern has been becoming more likely to occur, when the through-electrode and the viaplug are misaligned with each other.
- According to the present invention, there is provided a semiconductor device which includes:
- a substrate;
- a first insulating interlayer formed over one surface of the substrate;
- an electro-conductive pattern formed over the first insulating interlayer;
- a connection terminal provided over the other surface of the substrate; and
- a through-electrode extended through the substrate and the first insulating interlayer, so as to connect the electro-conductive pattern and the connection terminal.
- Since the through-electrode is provided through the substrate and the first insulating interlayer, and is directly connected to the electro-conductive pattern on the first insulating interlayer, so that it is no more necessary to provide any connection plug used for connecting the through-electrode with the electro-conductive pattern. Allowance for the misalignment may therefore increase, as compared with the case where the through-electrode and the electro-conductive pattern are connected via the connection plug. As a consequence, connection failure between the through-electrode and the electro-conductive pattern may be suppressed.
- According to the present invention, there is provided also a method of manufacturing a semiconductor device which includes:
- forming a first insulating interlayer positioned above one surface of a substrate;
- forming a first hole extended from the surface of said first insulating interlayer to midway of said substrate;
- forming a through-electrode in said first hole;
- forming an electro-conductive pattern positioned on the surface of said first insulating interlayer, and connected to one end of said through-electrode;
- making the other end of said through-electrode expose, by removing the other surface of said substrate; and
- forming a connection terminal connected to the other end of said through-electrode, on the other surface of said substrate.
- The through-electrode may directly be connected to elements (transistors which are disposed below the insulating interlayer) in some cases, and may indirectly be connected via any other interconnect or connection plug in some cases. In both cases, the through-electrode is electrically connected with the element.
- According to the present invention, any connection failure between the through-electrode and the electro-conductive pattern may be suppressed.
- The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a sectional view illustrating a configuration of a semiconductor device according to an embodiment, and -
FIGS. 2A to 7B are sectional views sequentially illustrating the individual steps of manufacturing the semiconductor device illustrated inFIG. 1 . - The invention will now be described herein with reference to an illustrative embodiment. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiment illustrated for explanatory purposes.
- Embodiments of the present invention will be explained below, referring to the attached drawings. Note that, in all drawings, any similar constituents may be given with similar reference numerals or symbols, and explanations therefor will not be repeated.
-
FIG. 1 is a sectional view illustrating a configuration of a semiconductor device of this embodiment. The semiconductor device has asubstrate 100, aninsulating interlayer 260, aninterconnect 342 as one example of the electro-conductive pattern, a through-electrode 440, and abump 900 as one example of the connection terminal. Theinsulating interlayer 260 is positioned on one surface (top surface) of thesubstrate 100. Theinterconnect 342 is formed over theinsulating interlayer 260. Thebump 900 is provided on the opposite surface (back surface) of thesubstrate 100. The through-electrode 440 extends through thesubstrate 100 and theinsulating interlayer 260, so as to connect theinterconnect 342 with thebump 900. - In the semiconductor device, one end of the through-
electrode 440 is directly connected to theinterconnect 342. Accordingly, the connection failure between the through-electrode 440 and theinterconnect 342 may be suppressed, even if the relative position between the through-electrode 440 and theinterconnect 342 should be misaligned in the direction of extension of theinterconnect 342. The connection failure between the through-electrode 440 and the electro-conductive pattern may be suppressed also when the electro-conductive pattern is provided in place of theinterconnect 342, because the area of the electro-conductive pattern may be set larger than the area of the via or contact. The effect will be detailed below. - The
interconnect 342 or the electro-conductive pattern may be composed of, for example, an Al pattern formed on theinsulating interlayer 260, or may be a Cu pattern buried in the surficial portion of theinsulating interlayer 260 by the damascene process. In the explanation below, any interconnects positioned on the surface of the insulating interlayers may be Al patterns formed on the insulating interlayer, or may be Cu patterns buried into the insulating interlayers by the damascene process. - In the example illustrated in this drawing, the
insulating interlayer 260 is a third insulating interlayer. Between thesubstrate 100 and theinsulating interlayer 260, a firstinsulating interlayer 200, and secondinsulating interlayers electrode 440 is directly connected to theinterconnect 342, after being extended through thesubstrate 100 and theinsulating interlayers - Below the
insulating interlayer 260, there are disposed elements such astransistors capacitor elements 160. Thetransistors 120 and thecapacitor elements 160 compose a DRAM. Thecapacitor elements 160 are disposed over the secondinsulating interlayers capacitor elements 160 are typically those having cylinder-type electrodes. For the case where the lower electrode is made of polysilicon, the surface of the lower electrode may be treated to have HSG (hemispherical grains). Thetransistors 140 compose a logic circuit or a peripheral circuit of the DRAM. - At least one of these elements (the
transistors 140 in the example illustrated in the drawing) is electrically connected to connection plugs 540, 542 which extend through the insulatinginterlayer 260. In the example illustrated in this drawing, the connection plugs 540, 542 are extended through the insulatinginterlayers transistors 140. - In the example illustrated in this drawing, the diameter of the through-
electrode 440 is larger than that of the connection plugs 540, 542. The diameter of the through-electrode 440 is preferably five times or more as large as the connection plugs 540, 542. The diameter of the through-electrode 440 is typically 5 μm or larger and 20 μm or smaller. - The other end of the through-
electrode 440 is projected out from the back surface of thesubstrate 100. The portion of the other end of the through-electrode 440, projected out from the back surface of thesubstrate 100, has an insulatingfilm 800 formed on the side face thereof. The insulatingfilm 800 is formed also around the circumference of the through-electrode 440 on the back surface of thesubstrate 100. - The through-
electrode 440 may be shrunk in the diameter in a portion more closer to the back surface of thesubstrate 100. - The individual drawings from
FIG. 2A toFIG. 7B are sectional views explaining a method of manufacturing the semiconductor device illustrated inFIG. 1 . First, as illustrated inFIG. 2A , a first-conductivity-type (N-type, for example)deep well 102, a first-conductivity-type well 104, a second-conductivity-type (P-type, for example) well 106, a device isolation film, and thetransistors substrate 100. Next, the insulatinginterlayer 200, aninterconnect 300 positioned on the insulatinginterlayer 200, the insulatinginterlayers capacitor elements 160, and analignment mark 322 are formed. Thealignment mark 322 is positioned on the surface of the insulatinginterlayer 240, and formed typically in the same process with an interconnect (not illustrated) positioned on the surface of the insulatinginterlayer 240 and anupper electrode 164 of thecapacitor elements 160. Next, the insulatinginterlayer 260 is formed over the insulatinginterlayer 240, thecapacitor elements 160, and thealignment mark 322. - Next, as illustrated in
FIG. 2B , a resistpattern 50 is formed over the insulatinginterlayer 260. The resistpattern 50 has an opening pattern over the region where the through-electrode 440 will be provided therein later. When the opening pattern of the resistpattern 50 is formed, alignment is carried out on the basis of thealignment mark 322. - Next, the insulating
interlayers substrate 100 are etched, using the resistpattern 50 as a mask. Afirst hole 400 is thus formed in the insulatinginterlayer substrate 100. The distance from the surface of the substrate to the bottom of thefirst hole 400 is typically 20 μm or larger and 100 μm or smaller. Thefirst hole 400 is a hole to be filled with the through-electrode 440, and extends from the surface of the insulatinginterlayer 260 to a midway of thesubstrate 100. Since a plurality of insulating interlayers are preliminarily formed when thefirst hole 400 is formed, so that charge-induced damage possibly applied to thetransistors first hole 400 may be reduced. The region where thefirst hole 400 is formed may have no device isolation film formed therein. - Thereafter, as illustrated in
FIG. 3A , the resistpattern 50 is removed. Next, on the side faces and the bottom of thefirst hole 400, an innerwall insulating film 420 is formed. In this process, the innerwall insulating film 420 is formed also over the insulating interlayer 260 (not illustrated). The innerwall insulating film 420 is typically a silicon oxide film, or a stacked film of a silicon oxide film and a silicon nitride film, and is formed by CVD. The thickness of the innerwall insulating film 420 is typically 0.1 μm or larger and 1 μm or smaller. - Next, a barrier film (not illustrated) is formed over the inner
wall insulating film 420. The barrier film is a film for preventing diffusion of metal, and is typically a single-layered film selected from the group consisting of Mo film, TiN film, TaN film, TiW film, Ti film, Ta film, and Cr film, or a stacked film obtained by stacking a plurality of films selected from the group. - Next, the through-
electrode 440 is filled into thefirst hole 400. The through-electrode 440 may be formed typically by repeating a step of forming an electro-conductive film and a step of planarizing it a plurality of times. The step of forming the electro-conductive film is typically a step of forming a tungsten film by CVD, wherein typically 1 μm or thinner film may be formed by a single cycle of film formation. The step of planarization is typically a step of carrying out an etchback process and CMP (Chemical Mechanical Polishing) in this order. A step of forming a film similar to the above-described barrier film may be provided between the CMP process and the step of forming the electro-conductive film in the next cycle. In some process, the innerwall insulating film 420 may be remained on the insulatinginterlayer 260. - Next, as illustrated in
FIG. 3B , a resistpattern 52 is formed over the insulatinginterlayer 260 and the through-electrode 440. The resistpattern 52 has opening patterns over the regions where the connection plugs 540, 542 are provided therein later. When the opening patterns of the resistpattern 52 are formed, alignment is carried on the basis of thealignment mark 322. - Next, the insulating
interlayers pattern 52 as a mask.Second holes interlayers second holes transistors 140. - The resist
pattern 52 is then removed as illustrated inFIG. 4A . Next, a barrier film (not illustrated) is formed over the side faces and bottom of thesecond holes second holes - Next, as illustrated in
FIG. 4B , interconnects 342, 344, 346 are formed on the surface of the insulatinginterlayer 260. Theinterconnect 342 is positioned on the through-electrode 440, and theinterconnect 344 connects the connection plugs 540, 542 with each other. When theinterconnects alignment mark 322. - Thereafter, as illustrated in
FIG. 5A , an insulatinginterlayer 270 is formed over the insulatinginterlayer 260 and over theinterconnects interconnects 360 are formed. Theinterconnects 360 are positioned on the surface of the insulatinginterlayer 270, and the connection plugs 350 which connect theinterconnects 360 and theinterconnects interlayer 270. Next,protective films interlayer 270 and theinterconnects 360, and aresin layer 600 and bumps (not illustrated) are further formed over theprotective film 290. The bumps are electrically connected to anyinterconnects 360. - Next, as illustrated in
FIG. 5B , a pressure-sensitive adhesive layer 720 is formed on the top surface of theresin layer 600, and theresin layer 600 is bonded to thesupport 700 while placing the pressure-sensitive adhesive layer 720 in between. The pressure-sensitive adhesive layer 720 is typically an adhesive tape. The adhesive tape is composed of a base, and pressure-sensitive adhesive layers formed on both surfaces thereof. The base composing the adhesive tape may typically be composed of polyolefin-base resin, polyester-base resin or the like. The pressure-sensitive adhesive composing the adhesive tape may typically be composed of acryl-base, emulsion-type, pressure-sensitive adhesive; acryl-base, solution-type, pressure-sensitive adhesive; urethane-base, pressure-sensitive adhesive, or the like. - As a material for composing the
support 700, those durable against heat, chemicals, external force and so forth, possibly applied typically in the process of thinning of thesubstrate 100 by means of grinding and etching of the back surface described later, may be adoptable. Quartz and glasses such as Pyrex (registered trademark) may be adoptable. Also materials other than glass, such as acrylic resin or other plastics, may be adoptable. - Next, as illustrated in,
FIG. 6A , the back surface of thesubstrate 100 is ground. In this process, grinding is carried out so as not to expose the innerwall insulating film 420 and through-electrode 440 out onto the back surface of thesubstrate 100. The thickness of the portion between the back surface of thesubstrate 100 after being ground to the innerwall insulating film 420 may be 0.1 μm or larger and 1 μm or smaller, for example. - Next, as illustrated in
FIG. 6B , the back surface of thesubstrate 100 is etched. By the etching, the innerwall insulating film 420 and the through-electrode 440 are projected out from the back surface of thesubstrate 100, to as high as approximately 1 μm or higher and 5 μm or lower, for example. - Next, as illustrated in
FIG. 7A , the insulatingfilm 800 is formed over the back surface of thesubstrate 100 and the innerwall insulating film 420. The insulatingfilm 800 is typically a SiN film, and is formed typically by CVD. Next, portions of the innerwall insulating film 420 and the insulatingfilm 800 positioned on the end face of the through-electrode 440 are removed typically by CMP, to thereby expose the end face of the through-electrode 440. - Next, as illustrated in
FIG. 7B , thebump 900 is formed on the back surface side of thesubstrate 100. Thereafter, the pressure-sensitive adhesive layer 720 and thesupport 700 are removed. - Effects expectable from this embodiment will be explained below. First, as has been described in the above, one end of the through-
electrode 440 is directly connected to theinterconnect 342, so that the connection failure between the through-electrode 440 and theinterconnect 342 may be suppressed. In particular in this embodiment, theinterconnect 342 is positioned above thecapacitor elements 160. The width of interconnect positioned in the upper layer of the capacitor element may generally be larger than that of the interconnect positioned in the lower layer of the capacitor elements. Accordingly, allowance for misalignment in the relative position between the through-electrode 440 and theinterconnect 342 may be increased, so that the connection failure between the through-electrode 440 and the interconnect 312 may further reliably be suppressed. - Moreover, the insulating
interlayer 260 is provided as an insulating interlayer in the third layer, while placing the insulatinginterlayer 200 in the first layer and the insulatinginterlayers substrate 100 and the insulatinginterlayer 260. The through-electrode 440 is directly connected to theinterconnect 342, while being formed so as to extend through thesubstrate 100 and the insulatinginterlayers electrode 440 and theinterconnect 342 may be reduced, and pattern layout of the interconnects in the process of designing the semiconductor device may be simplified, as compared with the case where the through-electrode 440 is connected to theinterconnect 342 through electro-conductive components respectively buried in the insulatinginterlayers interlayers interlayer 260 forms an insulating interlayer in the second layer, unlike the exemplary case illustrated in this drawing. - For the case where the interconnect layers are connected via the connection plugs as shown in this embodiment, the through-
electrode 440 and theinterconnect 342 may necessarily be connected via connection plugs, unless otherwise the through-electrode 440 is formed so as to extend through the insulatinginterlayers interlayer 260 is positioned, as compared with the example illustrated in this drawing. As a consequence, for the case where the interconnect layers are connected via the connection plugs, the direct connection between the through-electrode 440 and theinterconnect 342 as shown in this embodiment may successfully reduce the contact resistance between the through-electrode 440 and theinterconnect 342. This effect may be obtained also for the case where the insulatinginterlayer 260 composes an insulating interlayer in the first layer, unlike the exemplary case illustrated in the drawings. - The diameter of the through-
electrode 440 is larger than the diameter of the connection plugs 540, 542. Accordingly, the resistance between thebump 900 and theinterconnect 342 may still further be reduced, as compared with the case where the interconnect layers are connected via the connection plugs. - Since the diameter of the through-
electrode 440 is larger than the diameter of the connection plugs 540, 542, so that the thickness of an electro-conductive film composing the through-electrode 440 is larger than that of the an electro-conductive film composing the connection plugs 540, 542. The etch-back process and the CMP process for forming the through-electrode 440 will consequently take a longer time than the etch-back process and the CMP process for forming the connection plugs 540, 542. For this reason, formation of the connection plugs 540, 542 prior to formation of the through-electrode 440 may damage the surfaces of the connection plugs 540, 542. In contrast, the surfaces of the connection plugs 540, 542 may be prevented from being damaged in this embodiment, because the connection plugs 540, 542 are formed after the through-electrode 440 is formed. - The other end of the through-
electrode 440 is projected out from the back surface of thesubstrate 100. Thebump 900 is therefore kept away from the back surface of thesubstrate 100. In an stacked structure having one semiconductor device bonded to another semiconductor device, this configuration ensures a space between these semiconductor devices. The configuration also suppresses short-circuiting between thebump 900 and thesubstrate 100. - Around the through-
electrode 440 on the back surface of thesubstrate 100, there is formed the insulatingfilm 800. This configuration further reliably suppresses the short-circuiting between thebump 900 and thesubstrate 100. - Since the
interconnect 342 is formed after the through-electrode 440 is formed, theinterconnect 342 may be prevented from being damaged, unlike the case where thefirst hole 400 is formed and filled with the through-electrode 440 from the back surface side of thesubstrate 100. - Alignment of the
first hole 400 to be filled with the through-electrode 440, and alignment of theinterconnect 342 are respectively carried out on the basis of thealignment mark 322. Both alignment processes are carried out by detecting thealignment mark 322 through the insulatinginterlayer 260. On the other hand, any attempts of forming the hole to be filled with the through-electrode from the back surface side of thesubstrate 100, the alignment of the hole may necessarily be carried out by detecting thealignment mark 322 from the back surface side of thesubstrate 100, or on the basis of any other alignment mark. These attempts may result in degraded accuracy in alignment, as compared with this embodiment. According to this embodiment, the through-electrode 440 and theinterconnect 342 may therefore be suppressed from being misaligned, as compared with the case where the through-electrode is filled from the back surface side of thesubstrate 100. As a consequence, it is no more necessary to thicken theinterconnect 342 or the through-electrode 440, for the purpose of suppressing misalignment between the through-electrode 440 and theinterconnect 342. - In the process of exposing the through-
electrode 440 out from the back surface of thesubstrate 100, the back surface of thesubstrate 100 is initially ground only to a degree the through-electrode 440 is not exposed, and the through-electrode 440 is then exposed by etching. By virtue of this process, the end portion of the through-electrode 440 may be prevented from being elongated, and the through-electrode 440 is prevented from re-adhesion of debris of grinding, as compared with the case where the through-electrode 440 is exposed only by grinding of the back surface of thesubstrate 100. - The embodiments of the present invention, having been described referring to the attached drawings, are merely for exemplary purposes, allowing adoption of any other various configurations. For example, the through-
electrode 440 may be formed after the connection plugs 540, 542 are formed. - It is apparent that the present invention is not limited to the above embodiment, that may be modified and changed without departing from the scope and spirit of the invention.
Claims (5)
1. A method of manufacturing a semiconductor device comprising:
forming a first insulating interlayer positioned above one surface of a substrate;
forming a first hole extended from the surface of said first insulating interlayer to midway of said substrate;
forming a through-electrode in said first hole;
forming an electro-conductive pattern positioned on the surface of said first insulating interlayer, and connected to one end of said through-electrode;
making the other end of said through-electrode expose, by removing the other surface of said substrate; and
forming a connection terminal connected to the other end of said through-electrode, on the other surface of said substrate.
2. The method of manufacturing a semiconductor device as claimed in claim 1 , wherein said making the other end of said through-electrode expose comprises:
grinding the other surface of said substrate so as to not expose the other end of said through-electrode, and then by etching the other surface of said substrate, so as to expose the other end of said through-electrode.
3. The method of manufacturing a semiconductor device as claimed in claim 1 , further comprising, after forming said first insulating interlayer, and before forming said electro-conductive pattern:
forming a second hole so as to extend through said first insulating interlayer; and
forming a connection plug in said second hole.
4. The method of manufacturing a semiconductor device as claimed in claim 3 ,
wherein said forming said second hole, and said forming said connection plug, are conducted after said forming said through-electrode.
5. The method of manufacturing a semiconductor device as claimed in claim 1 , further comprising, before said forming said first insulating interlayer:
forming an alignment mark positioned between said substrate and said first insulating interlayer,
wherein in both of said forming said first hole, and said forming said electro-conductive pattern, alignment is carried out by detecting said alignment mark from the above through said first insulating interlayer.
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US13/323,560 US20120083119A1 (en) | 2008-05-12 | 2011-12-12 | Semiconductor device and method of manufacturing the same |
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JP2008125042A JP2009277719A (en) | 2008-05-12 | 2008-05-12 | Semiconductor device and method of manufacturing the same |
US12/385,840 US8089161B2 (en) | 2008-05-12 | 2009-04-21 | Semiconductor device and method of manufacturing the same |
US13/323,560 US20120083119A1 (en) | 2008-05-12 | 2011-12-12 | Semiconductor device and method of manufacturing the same |
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US13/323,560 Abandoned US20120083119A1 (en) | 2008-05-12 | 2011-12-12 | Semiconductor device and method of manufacturing the same |
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US20110042811A1 (en) * | 2009-08-21 | 2011-02-24 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US20120306084A1 (en) * | 2011-06-06 | 2012-12-06 | Micron Technology, Inc. | Semiconductor Constructions Having Through-Substrate Interconnects, and Methods of Forming Through-Substrate Interconnects |
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JP2006049557A (en) * | 2004-08-04 | 2006-02-16 | Seiko Epson Corp | Semiconductor device |
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2009
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- 2009-05-08 CN CN2009101381870A patent/CN101582408B/en active Active
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2011
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US20110042811A1 (en) * | 2009-08-21 | 2011-02-24 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US8618666B2 (en) * | 2009-08-21 | 2013-12-31 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US20140178680A1 (en) * | 2010-07-29 | 2014-06-26 | Nitto Denko Corporation | Film for flip chip type semiconductor back surface and its use |
US10211083B2 (en) * | 2010-07-29 | 2019-02-19 | Nitto Denko Corporation | Film for flip chip type semiconductor back surface and its use |
US20120306084A1 (en) * | 2011-06-06 | 2012-12-06 | Micron Technology, Inc. | Semiconductor Constructions Having Through-Substrate Interconnects, and Methods of Forming Through-Substrate Interconnects |
US8853072B2 (en) * | 2011-06-06 | 2014-10-07 | Micron Technology, Inc. | Methods of forming through-substrate interconnects |
Also Published As
Publication number | Publication date |
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CN101582408B (en) | 2012-02-08 |
US20090278230A1 (en) | 2009-11-12 |
US8089161B2 (en) | 2012-01-03 |
JP2009277719A (en) | 2009-11-26 |
CN101582408A (en) | 2009-11-18 |
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