US20120066444A1 - Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation - Google Patents

Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation Download PDF

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Publication number
US20120066444A1
US20120066444A1 US12/881,663 US88166310A US2012066444A1 US 20120066444 A1 US20120066444 A1 US 20120066444A1 US 88166310 A US88166310 A US 88166310A US 2012066444 A1 US2012066444 A1 US 2012066444A1
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Prior art keywords
memory
banks
buffer
channels
memory banks
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US12/881,663
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English (en)
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Greg Sadowski
Philip J. Rogers
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Priority to US12/881,663 priority Critical patent/US20120066444A1/en
Priority to EP11758654.5A priority patent/EP2616945B1/en
Priority to PCT/US2011/051156 priority patent/WO2012037002A1/en
Priority to JP2013529213A priority patent/JP5947302B2/ja
Priority to KR1020137008490A priority patent/KR101812300B1/ko
Priority to CN201180044281.5A priority patent/CN103109283B/zh
Assigned to ADVANCED MICRO DEVICES, INC. reassignment ADVANCED MICRO DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ROGERS, PHLIP J., SADOWSKI, GREG
Priority to US13/302,499 priority patent/US20120066471A1/en
Publication of US20120066444A1 publication Critical patent/US20120066444A1/en
Priority to US15/958,805 priority patent/US10795837B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present invention generally relate to allocating one or more memory buffers in a computing system with a plurality of memory channels.
  • a source of inefficiency in the system bus relates to a recovery time period of a memory device when the client devices request successive data transfers from the same memory bank of the memory device (also referred to herein as “memory bank contention”).
  • the recovery time period refers to a delay time exhibited by the memory device between a first access and an immediately subsequent second access to the memory device. While the memory device accesses data, no data can be transferred on the system bus during the recovery time period, thus leading to inefficiency in the system bus.
  • one approach to improve bus efficiency involves interleaving memory addresses within the multiple memory devices on the system bus.
  • successive memory storage locations e.g., memory locations having consecutive addresses
  • the effects from the recovery time period for a given memory device, and thus memory bank contention can be reduced.
  • the system bus typically enters an arbitration state to determine which of the client devices can access the system bus and interleaved memory addresses within the multiple memory devices. For instance, the arbitration state can allow a first client device to access the system bus and successive memory locations within the multiple memory devices prior to a second client device.
  • the arbitration state cannot guarantee that the second client device will immediately access the same successive memory locations as the first client device, thus compromising the benefits of the interleaved memory architecture (e.g., reduction of memory bank contention).
  • Methods and systems are needed to reduce, or eliminate, memory bank contention in computer systems with multiple client devices.
  • Embodiments of the present invention include a method for allocating one or more memory buffers in a computing system with a plurality of memory channels.
  • the method can include the following: allocating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels; allocating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels; associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively; and, accessing the first and second memory buffers based on the first and second sequence identifiers.
  • the method can also include executing a first memory operation associated with the first memory buffer at a first operating frequency. Similarly, the method can include executing a second memory operation associated with the second memory buffer at a second operating frequency, where the first operating frequency is different from the second operating frequency.
  • Embodiments of the present invention additionally include a computer program product that includes a computer-usable medium having computer program logic recorded thereon for enabling a processor to allocate one or more memory buffers in a computing system with a plurality of memory channels.
  • the computer program logic can include the following: first computer readable program code that enables a processor to allocate a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels; second computer readable program code that enables a processor to allocate a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels; third computer readable program code that enables a processor to associate a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively; and, fourth computer readable program code that enables a processor to access the first and second memory buffers based on the first and second sequence identifiers.
  • the computer program logic can also include the following: fifth computer readable program code that enables a processor to execute a first memory operation associated with the first memory buffer at a first operating frequency; and, sixth computer readable program code that enables a processor to execute a second memory operation associated with the second memory buffer at a second operating frequency, where the first operating frequency is different from the second operating frequency.
  • Embodiments of the present invention further include a computing system.
  • the computing system can include a first client device, a second client device, a plurality of memory channels, and a memory controller.
  • the plurality of memory channels can include a plurality of memory devices (e.g., Dynamic Random Access Memory (DRAM) devices).
  • the memory controller is configured to communicatively couple the first and second client devices to the plurality of memory channels.
  • DRAM Dynamic Random Access Memory
  • the memory controller is also configured to perform the following functions: allocate a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels; allocate a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels; associate a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively; and, access the first and second memory buffers based on the first and second sequence identifiers. Further, the memory controller is also configured to execute a first memory operation associated with the first memory buffer at a first operating frequency and to execute a second memory operation associated with the second memory buffer at a second operating frequency, where the first operating frequency is different from the second operating frequency.
  • FIG. 1 is an illustration of an exemplary system with multiple client devices in which embodiments of the present invention can be implemented.
  • FIG. 2 is an illustration of an embodiment of a plurality of memory buffers that spans over a plurality of memory channels.
  • FIG. 3 is an illustration of an embodiment of a memory controller.
  • FIG. 4 is an illustration of an example scenario in which an available memory space is smaller than a memory buffer requested from a computing device.
  • FIG. 5 is an illustration of an embodiment of a method for allocating one or more memory buffers in a computing system with a plurality of memory channels.
  • FIG. 6 is an illustration of an example computer system in which embodiments of the present invention can be implemented.
  • FIG. 1 is an illustration of an embodiment of a multi-client computing system 100 .
  • Multi-client computing system 100 includes a first computing device 110 , a second computing device 120 , a memory controller 130 , and memory devices 140 , 150 , 160 and 170 .
  • First and second computing devices 110 and 120 are communicatively coupled to memory controller 130 via a system bus 180 .
  • memory controller 130 is communicatively coupled to memory devices 140 , 150 , 160 , and 170 via data buses 141 , 151 , 161 , and 171 , respectively.
  • Memory devices 140 , 150 , 160 , and 170 are also referred to herein as memory channels 140 , 150 , 160 , and 170 .
  • multi-client computing system 100 can include more or less than two computing devices, more than one memory controller, more or less than four memory devices, or a combination thereof. These different configurations of multi-client computing system 100 are within the scope and spirit of the embodiments described herein. However, for ease of explanation, the embodiments contained herein will be described in the context of the system architecture depicted in FIG. 1 .
  • each of computing devices 110 and 120 can be, for example and without limitation, a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC) controller, other similar types of processing units, or a combination thereof.
  • Computing devices 110 and 120 are configured to execute instructions and to carry out operations associated with multi-client computing system 100 .
  • multi-client computing system 100 can be configured to render and display graphics.
  • Multi-client computing system 100 can include a CPU (e.g., computing device 110 ) and a GPU (e.g., computing device 120 ), where the GPU can be configured to render two- and three-dimensional graphics and the CPU can be configured to coordinate the display of the rendered graphics onto a display device (not shown in FIG. 1 ).
  • Computing devices 110 and 120 can be separate devices (e.g., separate semiconductor integrated circuits or separate “chips”), separate devices in the same package, combined devices on a single device (e.g., devices on a single semiconductor device), or variants thereof.
  • each of memory devices 140 , 150 , 160 , and 170 is a Dynamic Random Access Memory (DRAM) device with four memory banks (e.g., memory banks 0 - 3 in FIG. 2 below), according to an embodiment of the present invention.
  • DRAM Dynamic Random Access Memory
  • memory devices 140 , 150 , 160 , and 170 can be other types of memory devices such as, for example and without limitation, Static Random Access Memory devices (SRAMs), Static DRAMs, Flash memory devices, or a combination thereof.
  • one or more memory buffers are allocated to, or associated with, a plurality of memory banks, where the plurality of memory banks can span over one or more memory channels.
  • FIG. 2 is an illustration of an embodiment of a plurality of memory buffers 210 , 220 , 230 , 240 , and 250 that spans over a plurality of memory channels 140 , 150 , 160 , and 170 .
  • memory buffer 210 spans over memory banks 0 - 3 in memory channels 140 , 150 , 160 , and 170
  • memory buffer 220 spans over memory banks 0 - 3 in memory channel 170
  • memory buffers 230 and 240 span over memory banks 0 - 3 in memory channel 160
  • memory buffer 250 spans over memory banks 0 - 3 in memory channels 140 and 150 .
  • the plurality of memory buffers 210 - 250 is interleaved over one or more memory banks in memory channels 140 - 170 , according to an embodiment of the present invention. Methods and techniques for interleaving memory addresses over a plurality of memory banks are known to a person of ordinary skill in the relevant art.
  • FIG. 3 is an illustration of an embodiment of memory controller 130 .
  • Memory controller 130 includes a memory management unit 310 and a scheduler 320 .
  • a function of memory management unit 310 is to allocate, or associate, one or more memory buffers to operations associated with computing devices 110 and 120 .
  • memory management unit 310 allocates (or associates) memory buffers at a memory channel/memory bank granularity. This granularity refers to a number of memory channels and a number of memory banks (within the memory channels) that are allocated to the one or more memory buffers. In an embodiment, the granularity can be dictated by computing devices 110 and 120 , as described in further detail below.
  • memory management unit 310 is configured to allocate, or associate, a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels.
  • An example of the first memory buffer is memory buffer 220 of FIG. 2 .
  • Memory management unit 310 is also configured to allocate, or associate, a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels, according to an embodiment of the present invention.
  • An example of the second memory buffer is memory buffer 250 of FIG. 2 .
  • the second plurality of memory banks is different from the first plurality of memory banks.
  • memory buffer 220 occupies a different plurality of memory banks from memory buffer 250 .
  • the second plurality of memory banks is the same as the first plurality of memory banks.
  • memory buffer 230 occupies the same plurality of memory banks as memory buffer 240 of FIG. 2 .
  • memory buffers in computing systems are typically used when moving data between operations or processes executed by computing devices (e.g., computing devices 110 and 120 of FIG. 1 ).
  • computing device 110 is a CPU and the first plurality of memory banks is allocated to the first memory buffer (e.g., memory buffer 220 of FIG. 2 ).
  • Memory buffers required to execute latency-sensitive CPU instruction code can be mapped to the first memory buffer, according to an embodiment of the present invention.
  • a benefit, among others, of mapping latency-sensitive CPU instruction code to the first memory buffer is that memory bank contention issues can be reduced, or avoided, between computing devices 110 and 120 .
  • computing device 120 is a GPU and the second memory buffer (e.g., memory buffer 250 of FIG. 2 ) can be used in the execution of operations by computing device 120 .
  • the second memory buffer e.g., memory buffer 250 of FIG. 2
  • frame memory buffers required to execute graphics operations can be mapped to the second memory buffer. Since one or more memory banks are dedicated to GPU operations, a benefit, among others, of the second memory buffer is that memory bank contention issues can be reduced, or avoided, between computing devices 110 and 120 .
  • the first and second memory buffers can be used in the execution of operations by computing device 110 or computing device 120 .
  • computing device 110 is a GPU and the first and second memory buffers can be used in the execution of operations by computing device 110 .
  • memory buffer 210 of FIG. 2 can be allocated to GPU operations associated with frame buffering
  • memory buffers 220 , 230 , and 240 can be allocated to GPU operations associated with video decoding
  • memory buffer 250 can be allocated to GPU operations associated with a static screen state.
  • memory buffers 210 - 250 of FIG. 2 can be allocated to other GPU operations, which are within the scope and spirit of the embodiments described herein.
  • memory buffers 210 - 250 can be allocated to operations associated with other types of computing devices (e.g., CPUs and ASIC controllers), which are within the scope and spirit of the embodiments described herein.
  • a benefit, among others, in allocating memory buffers 210 - 250 across all of the memory channels in multi-computing system 100 of FIG. 1 is not only that memory bank contention issues can be reduced, or avoided, but also that the full bandwidth of the memory channels can be utilized. In using the full bandwidth of the memory channels in multi-client computing system 100 , both power and efficiency in multi-client computing system 100 are improved.
  • memory management unit 310 is configured to allocate one or more memory buffers to operations associated with computing devices 110 and 120 of FIG. 1 in such a manner as to minimize “holes” in the memory space.
  • a “hole” refers to a situation in which an available memory buffer is smaller than requested by computing device 110 or computing device 120 , and the requested memory buffer is allocated to a higher address space. This, as a result, leaves an available memory buffer space unused.
  • memory management unit 310 is configured to maintain an accounting and status of the memory buffers in order to minimize, or avoid, the occurrence of holes in the memory space.
  • FIG. 4 is an illustration of an example scenario in which an available memory space 410 is smaller than a memory buffer 420 requested from computing device 110 or 120 .
  • Memory management unit 310 of FIG. 3 is configured to track the allocation of memory space to memory buffers associated with the operations of computing devices 110 and 120 of FIG. 1 such that the tracking information can be used in memory space allocations for future operations, according to an embodiment of the present invention. For instance, in the example scenario illustrated in FIG.
  • the tracking information maintained by memory management unit 310 can be used to adjust the memory space allocation of memory buffers 210 , 230 , 240 , and 250 for future operations of the computing device such that memory buffer 420 can be allocated across memory banks 0 - 3 of memory channel 170 (e.g., similar to the memory buffer arrangement illustrated in FIG. 2 ).
  • memory buffer 420 can be allocated across memory banks 0 - 3 of memory channel 170 (e.g., similar to the memory buffer arrangement illustrated in FIG. 2 ).
  • the full bandwidth of the memory channels in multi-client computing system 100 of FIG. 1 can be utilized, thus leading to an improvement in power and efficiency in multi-client computing system 100 .
  • memory management unit 310 is also configured to allocate one or more memory buffers to operations associated with computing devices 110 and 120 of FIG. 1 based on a workload expectation of computing devices 110 and 120 .
  • computing device 110 is a GPU and requests one or more memory buffers to execute one or more GPU operations at a particular bandwidth or rate.
  • memory management unit 310 can allocate an appropriate amount of memory space and memory buffer for the GPU operations.
  • a video decode pipeline operation can be performed using memory buffers 220 , 230 , 240 , and 250 .
  • Memory buffer 250 can be used, for example, in a static screen state of the video decode pipeline.
  • Memory buffers 230 and 240 can be used for internal use by a video decoder in the pipeline.
  • memory buffer 220 can be used, for example, in write operations by the video decoder and read operations from one or more graphics blocks in the video decode pipeline.
  • Each of memory buffers 220 , 230 , 240 , and 250 can be assigned a sequence identifier, according to an embodiment of the present invention.
  • the sequence identifier provides a reference for memory controller 130 and memory devices 140 , 150 , 160 , and 170 of FIG. 1 , in which the reference is an indicator on an address/access sequence for the allocated memory buffers.
  • a sequence identifier of ‘1’ can be assigned to memory buffer 250 and the static screen state operation of the video decode pipeline.
  • a sequence identifier of ‘2’ can be assigned to memory buffer 240 and the video decoder's internal operation.
  • a sequence identifier of ‘3’ can be assigned to memory buffer 230 and the write operations by the video decoder and the read operations from the one or more graphics blocks. Further, a sequence identifier of ‘4’ can be assigned to memory buffer 220 and the video decoder's internal operation.
  • memory controller 130 and memory devices 140 - 170 may address/access memory buffers 220 , 230 , 240 , and 250 in a particular sequence, according to an embodiment of the present invention.
  • the sequence identifiers of memory buffers 220 , 230 , 240 , and 250 can be used as parameters for the particular sequence. For example, if the particular sequence is ‘1’, ‘2’, and ‘4’, memory buffer 250 will be addressed/accessed first, memory buffer 240 will be addressed/accessed second, and memory buffer 220 will be addressed/accessed last.
  • memory buffer 250 will be addressed/accessed first, memory buffer 230 will be addressed/accessed second, and memory buffer 220 will be addressed/accessed last.
  • the particular sequences do not have ‘2’ and ‘3’ occurring one after another.
  • memory bank contention issues are not only reduced, or avoided, in memory channel 160 , but the full bandwidth of the memory channels in multi-client computing system 100 can also be utilized.
  • a default memory buffer arrangement can be used for operations associated with computing devices 110 and 120 , according to an embodiment of the present invention.
  • the default memory buffer arrangement can span across all memory banks of and across all memory channels.
  • An example of this memory buffer arrangement is illustrated as memory buffer 210 of FIG. 2 , which spans across all memory banks 0 - 3 and across all memory channels 140 - 170 .
  • memory management unit 310 is configured to operate each of memory channels 140 , 150 , 160 , and 170 at a particular operating frequency.
  • the bandwidth per memory channel can be assessed based on the allocated memory buffers across one or more of the memory channels. For instance, based on a particular arrangement of memory buffers across memory channels 140 , 150 , 160 , and 170 (e.g., memory buffers 210 , 220 , 230 , 240 , and 250 of FIG. 2 ), the clock frequency of each of the memory channels can either be increased or decreased to assess whether the performance (e.g., throughput) of multi-client computing system 100 of FIG. 1 improves based on the arrangement of memory buffers.
  • an optimal clock frequency can be used for one or more memory channels associated with one or more memory buffers such that memory operations associated with the computing devices can be optimized.
  • the performance parameter portion of the tracking information includes the optimal clock frequency for each of memory channels 140 , 150 , 160 , and 170 .
  • scheduler 320 is configured to process memory requests from memory management unit 310 .
  • scheduler 320 processes the memory requests based on the tracking information provided by memory management unit 310 .
  • the tracking information can provide the following information: (1) whether an allocated memory buffer is in use, free, or reserved; (2) the memory channel/memory bank granularity of the allocated memory buffer; (3) a sequence identifier associated with the allocated memory buffer; and, (4) a performance parameter for the allocated memory buffer.
  • scheduler 320 Based on this tracking information, scheduler 320 generates an address, command, and control signals necessary to send read and write operations to memory channels 140 , 150 , 160 , and 170 via data buses 141 , 151 , 161 , and 171 , respectively, of FIG. 1 .
  • the generation of address, command, and control signals corresponding to read and write memory requests from computing devices 110 and 120 of FIG. 1 is known to a person skilled in the relevant art.
  • scheduler 320 operates in conjunction with memory management unit 310 to sort threads of arbitration between computing devices 110 and 120 of FIG. 1 .
  • memory controller 130 of FIG. 1 can manage two threads of arbitration—one thread of arbitration allocated to memory requests from computing device 110 and another thread of arbitration allocated to memory requests from computing device 120 .
  • Scheduler 320 can be optimized by processing the memory requests of one computing device before the other computing device. For instance, if computing device 110 is a CPU and computing device 120 is a GPU, scheduler 320 can process the CPU-related memory requests before GPU-related memory requests since CPU performance is typically more sensitive to memory delay than GPU performance.
  • scheduler 220 provides control of system bus 180 of FIG. 1 to computing device 110 such that the data transfer associated with the CPU-related memory request takes priority over the data transfer associated with the GPU-related memory request, according to an embodiment of the present invention.
  • memory management unit 310 of FIG. 3 de-allocates the one or more memory buffers associated with the operation from the memory space. At this point, memory management unit 310 can allocate the free memory space to other memory buffers associated with operations of computing devices 110 and 120 . Memory management unit 310 can allocate the free memory space to the other memory buffers in the same arrangement as (e.g., same number of banks and channels allocated to memory buffers associated with the previous operation) or in a different arrangement from (e.g., different number of banks and channels allocated to the other memory buffers associated with the previous operation) as the previous operation. Memory management unit 310 is configured to allocate the other memory buffers to the operations of computing devices 110 and 120 in the same manner described above with respect to FIG. 3 .
  • FIG. 5 is an illustration of an embodiment of a method 500 for allocating one or more memory buffers in a computing system with a plurality of memory channels.
  • Method 500 can occur using, for example and without limitation, multi-client computing system 100 of FIG. 1 .
  • a first memory buffer is allocated to, or associated with, a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels.
  • Memory management unit 310 of FIG. 3 can be used, for example, to perform step 510 .
  • a second memory buffer is allocated to, or associated with, a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels.
  • the second plurality of memory banks is different from the first plurality of memory banks (in step 510 ).
  • the second plurality of memory banks is the same as the first plurality of memory banks.
  • Memory management unit 310 of FIG. 3 can be used, for example, to perform step 520 .
  • a first sequence identifier and a second sequence identifier are associated with the first memory buffer and the second memory buffer, respectively.
  • Memory management unit 310 of FIG. 3 can be used, for example, to perform step 530 .
  • the first and second memory buffers are accessed based on the first and second sequence identifiers.
  • the first and second memory buffers are accessed in sequence to avoid memory bank contention and to utilize a full bandwidth of the plurality of memory channels.
  • Memory management unit 310 and scheduler 320 of FIG. 3 can be used, for example, to perform step 540 .
  • the first and second memory operations when executing a first memory operation associated with the first memory buffer and a second memory operation associated with the second memory buffer, are executed at a first operating frequency and a second operating frequency, respectively.
  • the first and second operating frequencies are different from one another, according to an embodiment of the present invention.
  • step 550 after the first and second memory operations associated with the first and second memory buffers, respectively, are executed, the first and second memory buffers are de-allocated from their respective memory spaces. With the de-allocation of the first and second memory buffers, memory buffers associated with other memory operations can be allocated to the free memory space.
  • FIG. 6 is an illustration of an example computer system 600 in which embodiments of the present invention, or portions thereof, can be implemented as computer-readable code.
  • the method illustrated by flowchart 500 of FIG. 5 can be implemented in system 600 .
  • Various embodiments of the present invention are described in terms of this example computer system 600 . After reading this description, it will become apparent to a person skilled in the relevant art how to implement embodiments of the present invention using other computer systems and/or computer architectures.
  • simulation, synthesis and/or manufacture of various embodiments of this invention may be accomplished, in part, through the use of computer readable code, including general programming languages (such as C or C++), hardware description languages (HDL) such as, for example, Verilog HDL, VHDL, Altera HDL (AHDL), or other available programming and/or schematic capture tools (such as circuit capture tools).
  • This computer readable code can be disposed in any known computer-usable medium including a semiconductor, magnetic disk, optical disk (such as CD-ROM, DVD-ROM). As such, the code can be transmitted over communication networks including the Internet.
  • the functions accomplished and/or structure provided by the systems and techniques described above can be represented in a core (such as a GPU core) that is embodied in program code and can be transformed to hardware as part of the production of integrated circuits.
  • Computer system 600 includes one or more processors, such as processor 604 .
  • Processor 604 may be a special purpose or a general purpose processor.
  • Processor 604 is connected to a communication infrastructure 606 (e.g., a bus or network).
  • Computer system 600 also includes a main memory 608 , preferably random access memory (RAM), and may also include a secondary memory 610 .
  • Secondary memory 610 can include, for example, a hard disk drive 612 , a removable storage drive 614 , and/or a memory stick.
  • Removable storage drive 614 can include a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash memory, or the like.
  • the removable storage drive 614 reads from and/or writes to a removable storage unit 618 in a well known manner.
  • Removable storage unit 618 can comprise a floppy disk, magnetic tape, optical disk, etc. which is read by and written to by removable storage drive 614 .
  • removable storage unit 618 includes a computer-usable storage medium having stored therein computer software and/or data.
  • secondary memory 610 can include other similar devices for allowing computer programs or other instructions to be loaded into computer system 600 .
  • Such devices can include, for example, a removable storage unit 622 and an interface 620 .
  • Examples of such devices can include a program cartridge and cartridge interface (such as those found in video game devices), a removable memory chip (e.g., EPROM or PROM) and associated socket, and other removable storage units 622 and interfaces 620 which allow software and data to be transferred from the removable storage unit 622 to computer system 600 .
  • Computer system 600 can also include a communications interface 624 .
  • Communications interface 624 allows software and data to be transferred between computer system 600 and external devices.
  • Communications interface 624 can include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, or the like.
  • Software and data transferred via communications interface 624 are in the form of signals which may be electronic, electromagnetic, optical, or other signals capable of being received by communications interface 624 . These signals are provided to communications interface 624 via a communications path 626 .
  • Communications path 626 carries signals and can be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a RF link or other communications channels.
  • Computer program medium and “computer-usable medium” are used to generally refer to media such as removable storage unit 618 , removable storage unit 622 , and a hard disk installed in hard disk drive 612 .
  • Computer program medium and computer-usable medium can also refer to memories, such as main memory 608 and secondary memory 610 , which can be memory semiconductors (e.g., DRAMs, etc.). These computer program products provide software to computer system 600 .
  • Computer programs are stored in main memory 608 and/or secondary memory 610 . Computer programs may also be received via communications interface 624 . Such computer programs, when executed, enable computer system 600 to implement embodiments of the present invention as discussed herein. In particular, the computer programs, when executed, enable processor 604 to implement processes of embodiments of the present invention, such as the steps in the methods illustrated by flowchart 500 of FIG. 5 , discussed above. Accordingly, such computer programs represent controllers of the computer system 600 . Where embodiments of the present invention are implemented using software, the software can be stored in a computer program product and loaded into computer system 600 using removable storage drive 614 , interface 620 , hard drive 612 , or communications interface 624 .
  • Embodiments of the present invention are also directed to computer program products including software stored on any computer-usable medium. Such software, when executed in one or more data processing device, causes a data processing device(s) to operate as described herein.
  • Embodiments of the present invention employ any computer-usable or -readable medium, known now or in the future.
  • Examples of computer-usable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, optical storage devices, MEMS, nanotechnological storage devices, etc.), and communication mediums (e.g., wired and wireless communications networks, local area networks, wide area networks, intranets, etc.).
  • primary storage devices e.g., any type of random access memory
  • secondary storage devices e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, optical storage devices, MEMS, nanotechnological storage devices, etc.
  • communication mediums e.g., wired and wireless communications networks, local area networks, wide area networks, intranets, etc.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
US12/881,663 2010-09-14 2010-09-14 Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation Abandoned US20120066444A1 (en)

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US12/881,663 US20120066444A1 (en) 2010-09-14 2010-09-14 Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation
EP11758654.5A EP2616945B1 (en) 2010-09-14 2011-09-12 Allocation of memory buffers in computing system with multiple memory channels
PCT/US2011/051156 WO2012037002A1 (en) 2010-09-14 2011-09-12 Allocation of memory buffers in computing system with multiple memory channels
JP2013529213A JP5947302B2 (ja) 2010-09-14 2011-09-12 複数のメモリチャネルを有するコンピューティングシステムにおけるメモリバッファの割り当て
KR1020137008490A KR101812300B1 (ko) 2010-09-14 2011-09-12 다수의 메모리 채널들을 가진 컴퓨팅 시스템에서의 메모리 버퍼들의 할당
CN201180044281.5A CN103109283B (zh) 2010-09-14 2011-09-12 在计算系统中以多个存储通道对存储缓冲器的分配
US13/302,499 US20120066471A1 (en) 2010-09-14 2011-11-22 Allocation of memory buffers based on preferred memory performance
US15/958,805 US10795837B2 (en) 2010-09-14 2018-04-20 Allocation of memory buffers in computing system with multiple memory channels

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WO2012037002A1 (en) 2012-03-22
US10795837B2 (en) 2020-10-06
CN103109283B (zh) 2018-12-18
KR101812300B1 (ko) 2017-12-26
US20180239722A1 (en) 2018-08-23
EP2616945B1 (en) 2017-08-16
CN103109283A (zh) 2013-05-15
JP5947302B2 (ja) 2016-07-06
KR20130106392A (ko) 2013-09-27
JP2013542493A (ja) 2013-11-21

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