US20110217823A1 - Storage capacitor having an increased aperture ratio and method of manufacturing the same - Google Patents
Storage capacitor having an increased aperture ratio and method of manufacturing the same Download PDFInfo
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- US20110217823A1 US20110217823A1 US13/110,556 US201113110556A US2011217823A1 US 20110217823 A1 US20110217823 A1 US 20110217823A1 US 201113110556 A US201113110556 A US 201113110556A US 2011217823 A1 US2011217823 A1 US 2011217823A1
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- storage capacitor
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- dielectric layer
- aperture ratio
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- 239000003990 capacitor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 14
- 239000011521 glass Substances 0.000 claims description 8
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
- G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/30—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 grating
- G02F2201/305—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 grating diffraction grating
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
Definitions
- the present invention relates to a technology for manufacturing an array substrate of a liquid crystal display, and in particular to a storage capacitor having an increased aperture ratio and method of manufacturing the same.
- each pixel is provided with a thin-film-transistor (TFT), wherein each TFT includes a gate electrode connected to a scanning line in a horizontal direction, a source electrode connected to a data line in a vertical direction, and a drain electrode connected to a liquid crystal capacitance.
- TFT thin-film-transistor
- the storage capacitor is obtained through a series of procedures that includes forming a metal layer, a first dielectric layer, a second dielectric layer and an electrode layer on a glass substrate, wherein the first dielectric layer, the second dielectric layer and the electrode layer are respectively shared a uniform thickness with other layers of the elements on a substrate.
- the application of the storage capacitor may reduce the voltage variations caused by leakage current of liquid crystal capacitance, hereby increasing the capacity of potential-holding.
- the application of a storage capacitor may reduce the coupling effects between capacitors as well.
- the storage capacitor should be designed as large as possible, however, the size of the storage capacitor may not be enlarged without any limits in practice. Since the storage capacitor is made by sandwiching an insulation layer between two metal electrodes, yet since the light can not be transmitted through the metal layer, therefore, once the storage capacitor is designed in a larger scale, the larger area of the light will be shielded by the enlarged area of the storage capacitor, so that the aperture ratio and light transmittance are reduced. However, on the other hand, if an increased aperture ratio is essentially required, the storage capacitor would have to be made smaller, which may further reduce its capability of potential-holding and capacitance coupling effects improvement.
- the present invention discloses a storage capacitor having an increased aperture ratio and a method of manufacturing the same, thus solving the contradiction of the prior art.
- the major objective of the present invention is to provide a storage capacitor having an increased aperture ratio and a method of manufacturing the same.
- a photoresist layer is coated on a dielectric layer and exposed to light by making use of patterns on a mask, then a developing process and an etching process are carried out in sequence to reduce the thickness of the dielectric layer.
- an electrode layer is formed on the dielectric layer, hereby providing a storage capacitor.
- the storage capacitor of the present invention may be able to maintain a sufficient capacitance while reducing the area of an electrode layer as required, and the aperture ratios of the respective pixels on a panel are further raised.
- the present invention provides a storage capacitor having an increased aperture ratio, including a substrate, a metal layer coating on the substrate, a first dielectric layer and a second dielectric layer sequentially forming on the metal layer, wherein the thickness of the second dielectric layer correspondingly disposed over the metal layer is less than that of the remaining areas of the second dielectric layer. Furthermore, an electrode layer is disposed on the second dielectric layer.
- the present invention also provides a method of manufacturing a storage capacitor having an increased aperture ratio, including the following steps: firstly, providing a substrate having a metal layer disposed thereon; next, forming in sequence a first dielectric layer and a second dielectric layer covering the metal layer; then, forming a photoresist layer with a uniform thickness to cover the second dielectric layer, and through performing a process of exposure-to-light to the photoresist layer correspondingly disposed over the metal layer by utilizing a mask at first and next performing a developing process, the original thickness of the photoresist layer is hereby reduced; subsequently, removing the photoresist layer and portions of second dielectric layer through etching, so that the thickness of the second dielectric layer correspondingly disposed over a metal layer is less than its original thickness, and the etching depth of the portion is greater than that of the other remaining portions of the second dielectric layer, and finally, forming an electrode layer on the second dielectric layer.
- FIG. 1 is a cross section view of a storage capacitor according to the present invention
- FIGS. 2( a ) to 2 ( f ) are cross section views of structures of a storage capacitor corresponding to various steps of the method of the present invention
- FIG. 3 is a schematic diagram of pattern layout of a mask according to the present invention.
- FIG. 4 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a first embodiment of the present invention
- FIG. 5 is a partial enlarged view of a storage capacitor in a circuit layout according to a first embodiment of the present invention
- FIG. 6 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a second embodiment of the present invention.
- FIG. 7 is a partial enlarged view of a storage capacitor in a circuit layout according to a second embodiment of the present invention.
- FIG. 8 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a third embodiment of the present invention.
- FIG. 9 is a partial enlarged view of a storage capacitor in a circuit layout according to a third embodiment of the present invention.
- a storage capacitor of the present invention includes a glass substrate 10 , a metal layer 12 coating on the glass substrate 10 as well as a first dielectric layer 14 made of silicon nitride and a second dielectric layer 16 , which are sequentially formed on the metal layer 12 .
- the thickness a of the portion of the second dielectric layer 16 correspondingly disposed over the metal layer 12 must be less than the thickness b of the remaining portions of the second dielectric layer 16 .
- a transparent and conductive electrode layer 18 made of indium-tin-oxide (ITO) is formed on the second dielectric layer 16 .
- FIGS. 2( a ) to 2 ( f ) show the cross section views of structures of a storage capacitor corresponding to various steps of the method of the present invention.
- FIG. 2( a ) shows, providing a glass substrate 10 having a metal layer 12 disposed thereon, and said metal layer 12 is covered correspondingly with a first dielectric layer 14 and a second dielectric layer 16 sequentially, wherein the second dielectric layer 16 has a thickness b.
- FIG. 2( b ) forming a photoresist layer 20 with a uniform thickness c on a second dielectric layer 16 .
- FIG. 2( b ) shows, providing a glass substrate 10 having a metal layer 12 disposed thereon, and said metal layer 12 is covered correspondingly with a first dielectric layer 14 and a second dielectric layer 16 sequentially, wherein the second dielectric layer 16 has a thickness b.
- FIG. 2( b ) shows, forming a photoresist layer 20 with a uniform thickness c on
- the portion of the photoresist layer 20 correspondingly disposed over the metal layer 12 is only partially etched, in other words, the portion of the photoresist layer 20 is not etched away in its entirety, such that the thickness d of photoresist layer 20 correspondingly disposed over the metal layer 12 is less than its original thickness c, meanwhile the thickness of the remaining portion of the photoresist layer 20 still remains unchanged as shown in FIG. 2( d ).
- FIG. 2( e ) for a cross section view of a structure of storage capacitor corresponding to a step of the method of the present invention.
- dry anisotropic etching is utilized to remove the photoresist layer 20 and a part of the second dielectric layer 16 . Since different portions of photoresist layer 20 are of different thicknesses, and dry anisotropic etching has the same etching speed for the same material in a specific direction, so that when the portion of photoresist layer 20 of thickness c is entirely etched away, the portion of the second dielectric layer 16 correspondingly disposed over the metal layer 12 is partially etched away.
- the thickness a of the portion of the second dielectric layer 16 correspondingly disposed over the metal layer 12 is less than the original thickness b, while the thickness of the remaining portions of the second dielectric layer 16 still remains unchanged as b.
- the etching depth of the portion of the second dielectric layer 16 correspondingly disposed over metal layer 12 is greater than the etching depth of the remaining portions of the second dielectric layer 16 .
- the capacitance of a storage capacitor can be maintained, while still achieving the purpose of reducing the area of a transparent conductive electrode layer 18 of a storage capacitor, hereby raising the aperture ratio of the respective pixel of a display panel.
- a mask 22 is provided with a transparent substrate 24 , a plurality of opaque first block patterns 26 , and a second block pattern 28 surrounding these first block patterns 26 .
- the first and second block patterns are made of chromium, so that they can be used to expose a specific portion of a photoresist layer to light, while without exposing other portions of a photoresist layer to light.
- FIG. 4 for a schematic diagram of a pixel electrode of an LCD panel utilizing a storage capacitor according to a first embodiment of the present invention
- the H-shaped slanted-line portion indicates a storage capacitor 30 , which is connected to a thin-film-transistor 32 .
- FIG. 5 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown in FIG. 4 .
- the solid line portion indicates the portion of a removed storage capacitor 34 upon the completion of a storage capacitor through utilizing the present invention
- the dotted line portion indicates the portion of a remaining storage capacitor 36 .
- FIG. 6 for a schematic diagram of a circuit layout used for pixel electrode of an LCD panel according to a second embodiment of the present invention
- the ⁇ -shaped slanted-line portion indicates a storage capacitor 38 , which is connected to a thin-film-transistor 40 .
- FIG. 7 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown in FIG. 6 .
- the solid line portion indicates the portion of a removed storage capacitor 42 upon the completion of a storage capacitor through utilizing the present invention
- the dotted line portion indicates the portion of a remaining storage capacitor 44 .
- FIG. 8 for a schematic diagram of a circuit layout used for pixel electrode of an LCD panel according to a third embodiment of the present invention, wherein, the ⁇ -shaped slanted-line portion indicates a storage capacitor 46 , which is connected to a thin-film-transistor 48 .
- FIG. 9 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown in FIG. 8 .
- the solid line portion indicates the portion of a removed storage capacitor 50 upon the completion of a storage capacitor through utilizing the present invention
- the dotted line portion indicates the portion of a remaining storage capacitor 52 .
- the exposure to light of photoresist layer is performed through a diffraction phenomenon created by the patterns of a mask, so as to produce a storage capacitor having thinner dielectric layer, thus being capable of reducing the area of an electrode layer, increasing aperture ratio of a storage capacitor, while maintaining sufficient capacitance.
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Abstract
Disclosed is a method of manufacturing a storage capacitor having increased aperture ratio: providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence; forming a photoresist layer with a uniform thickness to cover said second dielectric layer; performing a process of exposure-to-light and development to a portion of said photoresist layer that is correspondingly disposed over said metal layer sequentially, so that its thickness is less than its original thickness; removing said photoresist layer and etching said portion of said second dielectric layer, so that a thickness of said portion of said second dielectric layer is less than its original thickness, and the etching depth of said portion is greater than that of the other remaining portions of said second dielectric layer; and forming an electrode layer on said second dielectric layer.
Description
- This application is a Divisional of co-pending application Ser. No. 12/466,675, filed on 15 May 2009, and for which priority is claimed under 35 U.S.C. §120; and this application claims priority of Application No. 200910036561.6 filed in China on 9 Jan. 2009 under 35 U.S.C. §119; the entire contents of all of which are hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to a technology for manufacturing an array substrate of a liquid crystal display, and in particular to a storage capacitor having an increased aperture ratio and method of manufacturing the same.
- 2. The Prior Arts
- In an active matrix liquid crystal display (LCD), each pixel is provided with a thin-film-transistor (TFT), wherein each TFT includes a gate electrode connected to a scanning line in a horizontal direction, a source electrode connected to a data line in a vertical direction, and a drain electrode connected to a liquid crystal capacitance.
- When a thin-film-transistor is turned-on, there will be no current flow through the liquid crystal, and the liquid crystal will react to an electric field caused by the charges accumulated on both sides of liquid crystal, so that the voltage difference between these charges would hereby affect the gray level illuminance of pixels on a panel. Thus, it would be a matter of great importance in stressing the problem of how to reduce the leakage current of liquid crystal capacitance. In order to solve the above-mentioned problem, it is practicable to form a storage capacitor on a glass substrate, which is parallel-connected with the liquid crystal capacitance. In general, the storage capacitor is obtained through a series of procedures that includes forming a metal layer, a first dielectric layer, a second dielectric layer and an electrode layer on a glass substrate, wherein the first dielectric layer, the second dielectric layer and the electrode layer are respectively shared a uniform thickness with other layers of the elements on a substrate.
- The application of the storage capacitor may reduce the voltage variations caused by leakage current of liquid crystal capacitance, hereby increasing the capacity of potential-holding. In addition, the application of a storage capacitor may reduce the coupling effects between capacitors as well. From this point of view, the storage capacitor should be designed as large as possible, however, the size of the storage capacitor may not be enlarged without any limits in practice. Since the storage capacitor is made by sandwiching an insulation layer between two metal electrodes, yet since the light can not be transmitted through the metal layer, therefore, once the storage capacitor is designed in a larger scale, the larger area of the light will be shielded by the enlarged area of the storage capacitor, so that the aperture ratio and light transmittance are reduced. However, on the other hand, if an increased aperture ratio is essentially required, the storage capacitor would have to be made smaller, which may further reduce its capability of potential-holding and capacitance coupling effects improvement.
- Due to the above-mentioned shortcomings and drawbacks, the present invention discloses a storage capacitor having an increased aperture ratio and a method of manufacturing the same, thus solving the contradiction of the prior art.
- The major objective of the present invention is to provide a storage capacitor having an increased aperture ratio and a method of manufacturing the same. For this purpose, a photoresist layer is coated on a dielectric layer and exposed to light by making use of patterns on a mask, then a developing process and an etching process are carried out in sequence to reduce the thickness of the dielectric layer. Subsequently, an electrode layer is formed on the dielectric layer, hereby providing a storage capacitor. As such, the storage capacitor of the present invention may be able to maintain a sufficient capacitance while reducing the area of an electrode layer as required, and the aperture ratios of the respective pixels on a panel are further raised.
- To achieve the above-mentioned objective, the present invention provides a storage capacitor having an increased aperture ratio, including a substrate, a metal layer coating on the substrate, a first dielectric layer and a second dielectric layer sequentially forming on the metal layer, wherein the thickness of the second dielectric layer correspondingly disposed over the metal layer is less than that of the remaining areas of the second dielectric layer. Furthermore, an electrode layer is disposed on the second dielectric layer.
- In addition, the present invention also provides a method of manufacturing a storage capacitor having an increased aperture ratio, including the following steps: firstly, providing a substrate having a metal layer disposed thereon; next, forming in sequence a first dielectric layer and a second dielectric layer covering the metal layer; then, forming a photoresist layer with a uniform thickness to cover the second dielectric layer, and through performing a process of exposure-to-light to the photoresist layer correspondingly disposed over the metal layer by utilizing a mask at first and next performing a developing process, the original thickness of the photoresist layer is hereby reduced; subsequently, removing the photoresist layer and portions of second dielectric layer through etching, so that the thickness of the second dielectric layer correspondingly disposed over a metal layer is less than its original thickness, and the etching depth of the portion is greater than that of the other remaining portions of the second dielectric layer, and finally, forming an electrode layer on the second dielectric layer.
- Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the present invention will become apparent to those skilled in the art from this detailed description.
- The related drawings in connection with the detailed description of the present invention to be made later are described briefly as follows, in which:
-
FIG. 1 is a cross section view of a storage capacitor according to the present invention; -
FIGS. 2( a) to 2(f) are cross section views of structures of a storage capacitor corresponding to various steps of the method of the present invention; -
FIG. 3 is a schematic diagram of pattern layout of a mask according to the present invention; -
FIG. 4 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a first embodiment of the present invention; -
FIG. 5 is a partial enlarged view of a storage capacitor in a circuit layout according to a first embodiment of the present invention; -
FIG. 6 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a second embodiment of the present invention; -
FIG. 7 is a partial enlarged view of a storage capacitor in a circuit layout according to a second embodiment of the present invention; -
FIG. 8 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a third embodiment of the present invention; and -
FIG. 9 is a partial enlarged view of a storage capacitor in a circuit layout according to a third embodiment of the present invention. - The purpose, construction, features, functions and advantages of the present invention can be appreciated and understood more thoroughly through the following detailed description with reference to the attached drawings.
- In a method of manufacturing a display panel, a thin-film-transistor and a storage capacitor are produced simultaneously during certain specific processes, and a cross section view of the storage capacitor is shown in
FIG. 1 . AsFIG. 1 shows, a storage capacitor of the present invention includes aglass substrate 10, ametal layer 12 coating on theglass substrate 10 as well as a firstdielectric layer 14 made of silicon nitride and a seconddielectric layer 16, which are sequentially formed on themetal layer 12. In addition, since enough space must be provided for the remaining portions of the seconddielectric layer 16, which is other than the portion of the seconddielectric layer 16 correspondingly disposed over themetal layer 12, to accommodate the data lines and other components, thus the thicknesses of these remaining portions cannot be reduced too much at will, yet in order to achieve the purpose of reducing the electrode areas of a storage capacitor while still maintaining a sufficient capacitance, it must be aware that the thickness a of the portion of the seconddielectric layer 16 correspondingly disposed over themetal layer 12 must be less than the thickness b of the remaining portions of the seconddielectric layer 16. Furthermore, a transparent andconductive electrode layer 18 made of indium-tin-oxide (ITO) is formed on the seconddielectric layer 16. - Upon finishing reviewing the preliminary design perspective and the structure of a storage capacitor of the present invention, please continuingly refer to
FIGS. 2( a) to 2(f), which show the cross section views of structures of a storage capacitor corresponding to various steps of the method of the present invention. Firstly, asFIG. 2( a) shows, providing aglass substrate 10 having ametal layer 12 disposed thereon, and saidmetal layer 12 is covered correspondingly with a firstdielectric layer 14 and a seconddielectric layer 16 sequentially, wherein the seconddielectric layer 16 has a thickness b. Next, as shown inFIG. 2( b), forming aphotoresist layer 20 with a uniform thickness c on a seconddielectric layer 16. Then, as shown inFIG. 2( c), selecting and preparing amask 22 having atransparent substrate 24, a plurality of opaquefirst block patterns 26, and an opaquesecond block pattern 28 in a perimeter of thefirst block patterns 26, wherein the distance s between the respectivefirst block patterns 26 is ranged from 0 to 4 μm, and the distance p between thesecond block pattern 28 and the first block patterns nearest to thefirst block pattern 26 is less than 4 μm, so that thefirst block patterns 26 and thesecond block pattern 28 are both located on thetransparent substrate 24; then, upon aligning thefirst block patterns 26 of themask 22 on the portion of thephotoresist layer 20 correspondingly disposed over themetal layer 12, and aligning thesecond block pattern 28 on the remaining portions of thephotoresist layer 20, thus exposing thephotoresist layer 20 to light by making use of themask 22; however, in practical application of exposure-to-light process, thesecond block pattern 28 would block the light from irradiating the remaining areas of thephotoresist layer 20, so that only the portion of thephotoresist layer 20 correspondingly disposed over themetal layer 12 are exposed to light. Additionally, since a plurality of less than 4 μm gaps exist between the respectivefirst block patterns 26 and between thefirst block patterns 26 and thesecond block pattern 28, so that light may transmit through the above-mentioned gaps in proceeding with light exposure to the portion of thephotoresist layer 20 correspondingly disposed over themetal layer 12, meanwhile, when light passes through thses gaps less than 4 μm wide, a diffraction phenomenon will appear, so that the energy of the light will reduce after passing through these gaps. Finally, upon finishing exposing to light, proceeding with the development process ofphotoresist layer 20, and at this time, since the energy of this part of light is decreased, therefore while performing a development process, the portion of thephotoresist layer 20 correspondingly disposed over themetal layer 12 is only partially etched, in other words, the portion of thephotoresist layer 20 is not etched away in its entirety, such that the thickness d ofphotoresist layer 20 correspondingly disposed over themetal layer 12 is less than its original thickness c, meanwhile the thickness of the remaining portion of thephotoresist layer 20 still remains unchanged as shown inFIG. 2( d). - Subsequently, referring to
FIG. 2( e) for a cross section view of a structure of storage capacitor corresponding to a step of the method of the present invention. As shown inFIG. 2( e), dry anisotropic etching is utilized to remove thephotoresist layer 20 and a part of the seconddielectric layer 16. Since different portions ofphotoresist layer 20 are of different thicknesses, and dry anisotropic etching has the same etching speed for the same material in a specific direction, so that when the portion ofphotoresist layer 20 of thickness c is entirely etched away, the portion of the seconddielectric layer 16 correspondingly disposed over themetal layer 12 is partially etched away. In other words, at this moment, the thickness a of the portion of the seconddielectric layer 16 correspondingly disposed over themetal layer 12 is less than the original thickness b, while the thickness of the remaining portions of the seconddielectric layer 16 still remains unchanged as b. As a result, whether the etching will be further performed or not, the etching depth of the portion of the seconddielectric layer 16 correspondingly disposed overmetal layer 12 is greater than the etching depth of the remaining portions of the seconddielectric layer 16. Finally, as shown inFIG. 2( f), a transparentconductive electrode layer 18 is formed on the seconddielectric layer 16, hereby obtaining a storage capacitor on aglass substrate 10. - Since the second
dielectric layer 16 is shared with other layers of the elements onglass substrate 10, therefore, in the present invention, it is only the thickness of the portion of the seconddielectric layer 16 correspondingly disposed over themetal layer 12 that is reduced. From a well comprehensive equation C=(ε=A)/d (wherein, C is a value of capacitance, ε is a dielectric coefficient of a dielectric layer, A is an area of a transparentconductive electrode layer 18, and d is a distance between a transparentconductive electrode layer 18 and a metal layer 12), it is known that when d is reduced, then A is reduced correspondingly, such that C can keep a same capacitance value. As such, through the application of the method of the present invention, the capacitance of a storage capacitor can be maintained, while still achieving the purpose of reducing the area of a transparentconductive electrode layer 18 of a storage capacitor, hereby raising the aperture ratio of the respective pixel of a display panel. - Since in
FIG. 2( c) is shown a cross section of amask 22, yet its pattern layout can be seen more clearly as shown inFIG. 3 . As shown inFIG. 3 , amask 22 is provided with atransparent substrate 24, a plurality of opaquefirst block patterns 26, and asecond block pattern 28 surrounding thesefirst block patterns 26. The first and second block patterns are made of chromium, so that they can be used to expose a specific portion of a photoresist layer to light, while without exposing other portions of a photoresist layer to light. - Subsequently, referring to
FIG. 4 for a schematic diagram of a pixel electrode of an LCD panel utilizing a storage capacitor according to a first embodiment of the present invention, wherein, the H-shaped slanted-line portion indicates astorage capacitor 30, which is connected to a thin-film-transistor 32. Furthermore, referring toFIG. 5 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown inFIG. 4 . Wherein, the solid line portion indicates the portion of a removedstorage capacitor 34 upon the completion of a storage capacitor through utilizing the present invention, while the dotted line portion indicates the portion of a remainingstorage capacitor 36. - Furthermore, referring to
FIG. 6 for a schematic diagram of a circuit layout used for pixel electrode of an LCD panel according to a second embodiment of the present invention, wherein, the □-shaped slanted-line portion indicates astorage capacitor 38, which is connected to a thin-film-transistor 40. Furthermore, referring toFIG. 7 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown inFIG. 6 . Wherein, the solid line portion indicates the portion of a removedstorage capacitor 42 upon the completion of a storage capacitor through utilizing the present invention, while the dotted line portion indicates the portion of a remainingstorage capacitor 44. - Finally, referring to
FIG. 8 for a schematic diagram of a circuit layout used for pixel electrode of an LCD panel according to a third embodiment of the present invention, wherein, the π-shaped slanted-line portion indicates astorage capacitor 46, which is connected to a thin-film-transistor 48. Furthermore, referring toFIG. 9 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown inFIG. 8 . Wherein, the solid line portion indicates the portion of a removedstorage capacitor 50 upon the completion of a storage capacitor through utilizing the present invention, while the dotted line portion indicates the portion of a remainingstorage capacitor 52. - Summing up the above, in the present invention, the exposure to light of photoresist layer is performed through a diffraction phenomenon created by the patterns of a mask, so as to produce a storage capacitor having thinner dielectric layer, thus being capable of reducing the area of an electrode layer, increasing aperture ratio of a storage capacitor, while maintaining sufficient capacitance.
- The above detailed description of the preferred embodiment is intended to describe more clearly the characteristics and spirit of the present invention. However, the preferred embodiments disclosed above is not intended to be any restrictions to the scope of the present invention. Conversely, its purpose is to include the various changes and equivalent arrangements which are within the scope of the appended claims.
Claims (11)
1. A method of manufacturing a storage capacitor having an increased aperture ratio, which is formed simultaneously with a thin-film-transistor, comprising the following steps of:
providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence;
forming a photoresist layer with a uniform thickness to cover said second dielectric layer;
performing a process of exposure-to-light and development to said photoresist layer sequentially, so that said uniform thickness of said photoresist layer is less than its original thickness after said process;
removing said photoresist layer and etching a portion of said second dielectric layer that is correspondingly disposed over said metal layer, wherein said thickness of said portion of said second dielectric layer is less than its original thickness after etching, and an etching depth of said portion is greater than said etching depth of said other remaining portions of said second dielectric layer; and
forming an electrode layer on said second dielectric layer.
2. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1 , wherein
said exposure-to-light process further includes exposing said photoresist layer to light by means of a mask.
3. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 2 , wherein
said mask is composed of a plurality of opaque first block patterns and an opaque second block pattern in a perimeter of said first block patterns, wherein a distance between said respective first block patterns is ranged from 0 to 4 μm.
4. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 3 , wherein
said distance between said second block pattern and said first block patterns nearest to said second block pattern is less than 4 μm.
5. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 3 , wherein
said first block patterns of said mask are aligned to said portion of said photoresist layer that is correspondingly disposed over said metal layer in said process of exposure-to-light, and said second block pattern is aligned to said other remaining portions of said photoresist layer.
6. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1 , wherein
said etching process includes a dry anisotropic etching.
7. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 3 , wherein
said first block patterns and said second block pattern are made of chromium.
8. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1 , wherein
said first dielectric layer and said second dielectric layer are made of silicon nitride.
9. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1 , wherein
said electrode layer is a transparent metal electrode layer.
10. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 9 , wherein
said transparent metal electrode layer is made of indium-tin-oxide (ITO).
11. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1 , wherein
said substrate is a glass substrate.
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US13/110,556 US20110217823A1 (en) | 2009-01-09 | 2011-05-18 | Storage capacitor having an increased aperture ratio and method of manufacturing the same |
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CN2009100365616A CN101710586B (en) | 2009-01-09 | 2009-01-09 | Storage capacitor for improving aperture opening ratio and manufacturing method thereof |
CN200910036561.6 | 2009-01-09 | ||
US12/466,675 US8269310B2 (en) | 2009-01-09 | 2009-05-15 | Storage capacitor having an increased aperture ratio and method of manufacturing the same |
US13/110,556 US20110217823A1 (en) | 2009-01-09 | 2011-05-18 | Storage capacitor having an increased aperture ratio and method of manufacturing the same |
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US13/110,556 Abandoned US20110217823A1 (en) | 2009-01-09 | 2011-05-18 | Storage capacitor having an increased aperture ratio and method of manufacturing the same |
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CN102738171A (en) * | 2012-06-15 | 2012-10-17 | 深圳市华星光电技术有限公司 | Display panel and method manufacturing same |
CN105097826A (en) * | 2015-06-04 | 2015-11-25 | 京东方科技集团股份有限公司 | Gate driver on array (GOA) unit, fabrication method thereof, display substrate and display device |
TWI607562B (en) | 2016-07-11 | 2017-12-01 | 友達光電股份有限公司 | Display panel |
CN113345322A (en) * | 2020-03-02 | 2021-09-03 | 元太科技工业股份有限公司 | Wiring structure of display panel |
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Also Published As
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CN101710586B (en) | 2011-12-28 |
US20100176485A1 (en) | 2010-07-15 |
US8269310B2 (en) | 2012-09-18 |
CN101710586A (en) | 2010-05-19 |
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