US20110217823A1 - Storage capacitor having an increased aperture ratio and method of manufacturing the same - Google Patents

Storage capacitor having an increased aperture ratio and method of manufacturing the same Download PDF

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US20110217823A1
US20110217823A1 US13/110,556 US201113110556A US2011217823A1 US 20110217823 A1 US20110217823 A1 US 20110217823A1 US 201113110556 A US201113110556 A US 201113110556A US 2011217823 A1 US2011217823 A1 US 2011217823A1
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storage capacitor
layer
dielectric layer
aperture ratio
increased aperture
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US13/110,556
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Chiu-Chuan Chen
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Chiu-Chuan Chen
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Priority to CN 200910036561 priority Critical patent/CN101710586B/en
Priority to CN200910036561.6 priority
Priority to US12/466,675 priority patent/US8269310B2/en
Application filed by Chiu-Chuan Chen filed Critical Chiu-Chuan Chen
Priority to US13/110,556 priority patent/US20110217823A1/en
Publication of US20110217823A1 publication Critical patent/US20110217823A1/en
Abandoned legal-status Critical Current

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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F2001/136231Active matrix addressed cells for reducing the number of lithographic steps
    • G02F2001/136236Active matrix addressed cells for reducing the number of lithographic steps using a gray or half tone lithographic process
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F2001/136295Materials; Compositions; Methods of manufacturing
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/30Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 grating
    • G02F2201/305Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 grating diffraction grating
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40Arrangements for improving the aperture ratio

Abstract

Disclosed is a method of manufacturing a storage capacitor having increased aperture ratio: providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence; forming a photoresist layer with a uniform thickness to cover said second dielectric layer; performing a process of exposure-to-light and development to a portion of said photoresist layer that is correspondingly disposed over said metal layer sequentially, so that its thickness is less than its original thickness; removing said photoresist layer and etching said portion of said second dielectric layer, so that a thickness of said portion of said second dielectric layer is less than its original thickness, and the etching depth of said portion is greater than that of the other remaining portions of said second dielectric layer; and forming an electrode layer on said second dielectric layer.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a Divisional of co-pending application Ser. No. 12/466,675, filed on 15 May 2009, and for which priority is claimed under 35 U.S.C. §120; and this application claims priority of Application No. 200910036561.6 filed in China on 9 Jan. 2009 under 35 U.S.C. §119; the entire contents of all of which are hereby incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a technology for manufacturing an array substrate of a liquid crystal display, and in particular to a storage capacitor having an increased aperture ratio and method of manufacturing the same.
  • 2. The Prior Arts
  • In an active matrix liquid crystal display (LCD), each pixel is provided with a thin-film-transistor (TFT), wherein each TFT includes a gate electrode connected to a scanning line in a horizontal direction, a source electrode connected to a data line in a vertical direction, and a drain electrode connected to a liquid crystal capacitance.
  • When a thin-film-transistor is turned-on, there will be no current flow through the liquid crystal, and the liquid crystal will react to an electric field caused by the charges accumulated on both sides of liquid crystal, so that the voltage difference between these charges would hereby affect the gray level illuminance of pixels on a panel. Thus, it would be a matter of great importance in stressing the problem of how to reduce the leakage current of liquid crystal capacitance. In order to solve the above-mentioned problem, it is practicable to form a storage capacitor on a glass substrate, which is parallel-connected with the liquid crystal capacitance. In general, the storage capacitor is obtained through a series of procedures that includes forming a metal layer, a first dielectric layer, a second dielectric layer and an electrode layer on a glass substrate, wherein the first dielectric layer, the second dielectric layer and the electrode layer are respectively shared a uniform thickness with other layers of the elements on a substrate.
  • The application of the storage capacitor may reduce the voltage variations caused by leakage current of liquid crystal capacitance, hereby increasing the capacity of potential-holding. In addition, the application of a storage capacitor may reduce the coupling effects between capacitors as well. From this point of view, the storage capacitor should be designed as large as possible, however, the size of the storage capacitor may not be enlarged without any limits in practice. Since the storage capacitor is made by sandwiching an insulation layer between two metal electrodes, yet since the light can not be transmitted through the metal layer, therefore, once the storage capacitor is designed in a larger scale, the larger area of the light will be shielded by the enlarged area of the storage capacitor, so that the aperture ratio and light transmittance are reduced. However, on the other hand, if an increased aperture ratio is essentially required, the storage capacitor would have to be made smaller, which may further reduce its capability of potential-holding and capacitance coupling effects improvement.
  • Due to the above-mentioned shortcomings and drawbacks, the present invention discloses a storage capacitor having an increased aperture ratio and a method of manufacturing the same, thus solving the contradiction of the prior art.
  • SUMMARY OF THE INVENTION
  • The major objective of the present invention is to provide a storage capacitor having an increased aperture ratio and a method of manufacturing the same. For this purpose, a photoresist layer is coated on a dielectric layer and exposed to light by making use of patterns on a mask, then a developing process and an etching process are carried out in sequence to reduce the thickness of the dielectric layer. Subsequently, an electrode layer is formed on the dielectric layer, hereby providing a storage capacitor. As such, the storage capacitor of the present invention may be able to maintain a sufficient capacitance while reducing the area of an electrode layer as required, and the aperture ratios of the respective pixels on a panel are further raised.
  • To achieve the above-mentioned objective, the present invention provides a storage capacitor having an increased aperture ratio, including a substrate, a metal layer coating on the substrate, a first dielectric layer and a second dielectric layer sequentially forming on the metal layer, wherein the thickness of the second dielectric layer correspondingly disposed over the metal layer is less than that of the remaining areas of the second dielectric layer. Furthermore, an electrode layer is disposed on the second dielectric layer.
  • In addition, the present invention also provides a method of manufacturing a storage capacitor having an increased aperture ratio, including the following steps: firstly, providing a substrate having a metal layer disposed thereon; next, forming in sequence a first dielectric layer and a second dielectric layer covering the metal layer; then, forming a photoresist layer with a uniform thickness to cover the second dielectric layer, and through performing a process of exposure-to-light to the photoresist layer correspondingly disposed over the metal layer by utilizing a mask at first and next performing a developing process, the original thickness of the photoresist layer is hereby reduced; subsequently, removing the photoresist layer and portions of second dielectric layer through etching, so that the thickness of the second dielectric layer correspondingly disposed over a metal layer is less than its original thickness, and the etching depth of the portion is greater than that of the other remaining portions of the second dielectric layer, and finally, forming an electrode layer on the second dielectric layer.
  • Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the present invention will become apparent to those skilled in the art from this detailed description.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The related drawings in connection with the detailed description of the present invention to be made later are described briefly as follows, in which:
  • FIG. 1 is a cross section view of a storage capacitor according to the present invention;
  • FIGS. 2( a) to 2(f) are cross section views of structures of a storage capacitor corresponding to various steps of the method of the present invention;
  • FIG. 3 is a schematic diagram of pattern layout of a mask according to the present invention;
  • FIG. 4 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a first embodiment of the present invention;
  • FIG. 5 is a partial enlarged view of a storage capacitor in a circuit layout according to a first embodiment of the present invention;
  • FIG. 6 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a second embodiment of the present invention;
  • FIG. 7 is a partial enlarged view of a storage capacitor in a circuit layout according to a second embodiment of the present invention;
  • FIG. 8 is a schematic diagram of a circuit layout used for a pixel electrode of an LCD panel according to a third embodiment of the present invention; and
  • FIG. 9 is a partial enlarged view of a storage capacitor in a circuit layout according to a third embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • The purpose, construction, features, functions and advantages of the present invention can be appreciated and understood more thoroughly through the following detailed description with reference to the attached drawings.
  • In a method of manufacturing a display panel, a thin-film-transistor and a storage capacitor are produced simultaneously during certain specific processes, and a cross section view of the storage capacitor is shown in FIG. 1. As FIG. 1 shows, a storage capacitor of the present invention includes a glass substrate 10, a metal layer 12 coating on the glass substrate 10 as well as a first dielectric layer 14 made of silicon nitride and a second dielectric layer 16, which are sequentially formed on the metal layer 12. In addition, since enough space must be provided for the remaining portions of the second dielectric layer 16, which is other than the portion of the second dielectric layer 16 correspondingly disposed over the metal layer 12, to accommodate the data lines and other components, thus the thicknesses of these remaining portions cannot be reduced too much at will, yet in order to achieve the purpose of reducing the electrode areas of a storage capacitor while still maintaining a sufficient capacitance, it must be aware that the thickness a of the portion of the second dielectric layer 16 correspondingly disposed over the metal layer 12 must be less than the thickness b of the remaining portions of the second dielectric layer 16. Furthermore, a transparent and conductive electrode layer 18 made of indium-tin-oxide (ITO) is formed on the second dielectric layer 16.
  • Upon finishing reviewing the preliminary design perspective and the structure of a storage capacitor of the present invention, please continuingly refer to FIGS. 2( a) to 2(f), which show the cross section views of structures of a storage capacitor corresponding to various steps of the method of the present invention. Firstly, as FIG. 2( a) shows, providing a glass substrate 10 having a metal layer 12 disposed thereon, and said metal layer 12 is covered correspondingly with a first dielectric layer 14 and a second dielectric layer 16 sequentially, wherein the second dielectric layer 16 has a thickness b. Next, as shown in FIG. 2( b), forming a photoresist layer 20 with a uniform thickness c on a second dielectric layer 16. Then, as shown in FIG. 2( c), selecting and preparing a mask 22 having a transparent substrate 24, a plurality of opaque first block patterns 26, and an opaque second block pattern 28 in a perimeter of the first block patterns 26, wherein the distance s between the respective first block patterns 26 is ranged from 0 to 4 μm, and the distance p between the second block pattern 28 and the first block patterns nearest to the first block pattern 26 is less than 4 μm, so that the first block patterns 26 and the second block pattern 28 are both located on the transparent substrate 24; then, upon aligning the first block patterns 26 of the mask 22 on the portion of the photoresist layer 20 correspondingly disposed over the metal layer 12, and aligning the second block pattern 28 on the remaining portions of the photoresist layer 20, thus exposing the photoresist layer 20 to light by making use of the mask 22; however, in practical application of exposure-to-light process, the second block pattern 28 would block the light from irradiating the remaining areas of the photoresist layer 20, so that only the portion of the photoresist layer 20 correspondingly disposed over the metal layer 12 are exposed to light. Additionally, since a plurality of less than 4 μm gaps exist between the respective first block patterns 26 and between the first block patterns 26 and the second block pattern 28, so that light may transmit through the above-mentioned gaps in proceeding with light exposure to the portion of the photoresist layer 20 correspondingly disposed over the metal layer 12, meanwhile, when light passes through thses gaps less than 4 μm wide, a diffraction phenomenon will appear, so that the energy of the light will reduce after passing through these gaps. Finally, upon finishing exposing to light, proceeding with the development process of photoresist layer 20, and at this time, since the energy of this part of light is decreased, therefore while performing a development process, the portion of the photoresist layer 20 correspondingly disposed over the metal layer 12 is only partially etched, in other words, the portion of the photoresist layer 20 is not etched away in its entirety, such that the thickness d of photoresist layer 20 correspondingly disposed over the metal layer 12 is less than its original thickness c, meanwhile the thickness of the remaining portion of the photoresist layer 20 still remains unchanged as shown in FIG. 2( d).
  • Subsequently, referring to FIG. 2( e) for a cross section view of a structure of storage capacitor corresponding to a step of the method of the present invention. As shown in FIG. 2( e), dry anisotropic etching is utilized to remove the photoresist layer 20 and a part of the second dielectric layer 16. Since different portions of photoresist layer 20 are of different thicknesses, and dry anisotropic etching has the same etching speed for the same material in a specific direction, so that when the portion of photoresist layer 20 of thickness c is entirely etched away, the portion of the second dielectric layer 16 correspondingly disposed over the metal layer 12 is partially etched away. In other words, at this moment, the thickness a of the portion of the second dielectric layer 16 correspondingly disposed over the metal layer 12 is less than the original thickness b, while the thickness of the remaining portions of the second dielectric layer 16 still remains unchanged as b. As a result, whether the etching will be further performed or not, the etching depth of the portion of the second dielectric layer 16 correspondingly disposed over metal layer 12 is greater than the etching depth of the remaining portions of the second dielectric layer 16. Finally, as shown in FIG. 2( f), a transparent conductive electrode layer 18 is formed on the second dielectric layer 16, hereby obtaining a storage capacitor on a glass substrate 10.
  • Since the second dielectric layer 16 is shared with other layers of the elements on glass substrate 10, therefore, in the present invention, it is only the thickness of the portion of the second dielectric layer 16 correspondingly disposed over the metal layer 12 that is reduced. From a well comprehensive equation C=(ε=A)/d (wherein, C is a value of capacitance, ε is a dielectric coefficient of a dielectric layer, A is an area of a transparent conductive electrode layer 18, and d is a distance between a transparent conductive electrode layer 18 and a metal layer 12), it is known that when d is reduced, then A is reduced correspondingly, such that C can keep a same capacitance value. As such, through the application of the method of the present invention, the capacitance of a storage capacitor can be maintained, while still achieving the purpose of reducing the area of a transparent conductive electrode layer 18 of a storage capacitor, hereby raising the aperture ratio of the respective pixel of a display panel.
  • Since in FIG. 2( c) is shown a cross section of a mask 22, yet its pattern layout can be seen more clearly as shown in FIG. 3. As shown in FIG. 3, a mask 22 is provided with a transparent substrate 24, a plurality of opaque first block patterns 26, and a second block pattern 28 surrounding these first block patterns 26. The first and second block patterns are made of chromium, so that they can be used to expose a specific portion of a photoresist layer to light, while without exposing other portions of a photoresist layer to light.
  • Subsequently, referring to FIG. 4 for a schematic diagram of a pixel electrode of an LCD panel utilizing a storage capacitor according to a first embodiment of the present invention, wherein, the H-shaped slanted-line portion indicates a storage capacitor 30, which is connected to a thin-film-transistor 32. Furthermore, referring to FIG. 5 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown in FIG. 4. Wherein, the solid line portion indicates the portion of a removed storage capacitor 34 upon the completion of a storage capacitor through utilizing the present invention, while the dotted line portion indicates the portion of a remaining storage capacitor 36.
  • Furthermore, referring to FIG. 6 for a schematic diagram of a circuit layout used for pixel electrode of an LCD panel according to a second embodiment of the present invention, wherein, the □-shaped slanted-line portion indicates a storage capacitor 38, which is connected to a thin-film-transistor 40. Furthermore, referring to FIG. 7 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown in FIG. 6. Wherein, the solid line portion indicates the portion of a removed storage capacitor 42 upon the completion of a storage capacitor through utilizing the present invention, while the dotted line portion indicates the portion of a remaining storage capacitor 44.
  • Finally, referring to FIG. 8 for a schematic diagram of a circuit layout used for pixel electrode of an LCD panel according to a third embodiment of the present invention, wherein, the π-shaped slanted-line portion indicates a storage capacitor 46, which is connected to a thin-film-transistor 48. Furthermore, referring to FIG. 9 for a partial enlarged view of the dotted line circle portion of a storage capacitor as shown in FIG. 8. Wherein, the solid line portion indicates the portion of a removed storage capacitor 50 upon the completion of a storage capacitor through utilizing the present invention, while the dotted line portion indicates the portion of a remaining storage capacitor 52.
  • Summing up the above, in the present invention, the exposure to light of photoresist layer is performed through a diffraction phenomenon created by the patterns of a mask, so as to produce a storage capacitor having thinner dielectric layer, thus being capable of reducing the area of an electrode layer, increasing aperture ratio of a storage capacitor, while maintaining sufficient capacitance.
  • The above detailed description of the preferred embodiment is intended to describe more clearly the characteristics and spirit of the present invention. However, the preferred embodiments disclosed above is not intended to be any restrictions to the scope of the present invention. Conversely, its purpose is to include the various changes and equivalent arrangements which are within the scope of the appended claims.

Claims (11)

1. A method of manufacturing a storage capacitor having an increased aperture ratio, which is formed simultaneously with a thin-film-transistor, comprising the following steps of:
providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence;
forming a photoresist layer with a uniform thickness to cover said second dielectric layer;
performing a process of exposure-to-light and development to said photoresist layer sequentially, so that said uniform thickness of said photoresist layer is less than its original thickness after said process;
removing said photoresist layer and etching a portion of said second dielectric layer that is correspondingly disposed over said metal layer, wherein said thickness of said portion of said second dielectric layer is less than its original thickness after etching, and an etching depth of said portion is greater than said etching depth of said other remaining portions of said second dielectric layer; and
forming an electrode layer on said second dielectric layer.
2. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1, wherein
said exposure-to-light process further includes exposing said photoresist layer to light by means of a mask.
3. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 2, wherein
said mask is composed of a plurality of opaque first block patterns and an opaque second block pattern in a perimeter of said first block patterns, wherein a distance between said respective first block patterns is ranged from 0 to 4 μm.
4. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 3, wherein
said distance between said second block pattern and said first block patterns nearest to said second block pattern is less than 4 μm.
5. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 3, wherein
said first block patterns of said mask are aligned to said portion of said photoresist layer that is correspondingly disposed over said metal layer in said process of exposure-to-light, and said second block pattern is aligned to said other remaining portions of said photoresist layer.
6. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1, wherein
said etching process includes a dry anisotropic etching.
7. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 3, wherein
said first block patterns and said second block pattern are made of chromium.
8. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1, wherein
said first dielectric layer and said second dielectric layer are made of silicon nitride.
9. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1, wherein
said electrode layer is a transparent metal electrode layer.
10. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 9, wherein
said transparent metal electrode layer is made of indium-tin-oxide (ITO).
11. The method of manufacturing a storage capacitor having an increased aperture ratio according to claim 1, wherein
said substrate is a glass substrate.
US13/110,556 2009-01-09 2011-05-18 Storage capacitor having an increased aperture ratio and method of manufacturing the same Abandoned US20110217823A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN 200910036561 CN101710586B (en) 2009-01-09 2009-01-09 Storage capacitor for improving aperture opening ratio and manufacturing method thereof
CN200910036561.6 2009-01-09
US12/466,675 US8269310B2 (en) 2009-01-09 2009-05-15 Storage capacitor having an increased aperture ratio and method of manufacturing the same
US13/110,556 US20110217823A1 (en) 2009-01-09 2011-05-18 Storage capacitor having an increased aperture ratio and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/110,556 US20110217823A1 (en) 2009-01-09 2011-05-18 Storage capacitor having an increased aperture ratio and method of manufacturing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/466,675 Division US8269310B2 (en) 2009-01-09 2009-05-15 Storage capacitor having an increased aperture ratio and method of manufacturing the same

Publications (1)

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